1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_hw_headers.h" 21 #include "hal_api.h" 22 #include "hal_reo.h" 23 #include "target_type.h" 24 #include "qdf_module.h" 25 #include "wcss_version.h" 26 #include <qdf_tracepoint.h> 27 #include "qdf_ssr_driver_dump.h" 28 29 struct tcl_data_cmd gtcl_data_symbol __attribute__((used)); 30 31 #ifdef QCA_WIFI_QCA8074 32 void hal_qca6290_attach(struct hal_soc *hal); 33 #endif 34 #ifdef QCA_WIFI_QCA8074 35 void hal_qca8074_attach(struct hal_soc *hal); 36 #endif 37 #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) || \ 38 defined(QCA_WIFI_QCA9574) 39 void hal_qca8074v2_attach(struct hal_soc *hal); 40 #endif 41 #ifdef QCA_WIFI_QCA6390 42 void hal_qca6390_attach(struct hal_soc *hal); 43 #endif 44 #ifdef QCA_WIFI_QCA6490 45 void hal_qca6490_attach(struct hal_soc *hal); 46 #endif 47 #ifdef QCA_WIFI_QCN9000 48 void hal_qcn9000_attach(struct hal_soc *hal); 49 #endif 50 #ifdef QCA_WIFI_QCN9224 51 void hal_qcn9224v1_attach(struct hal_soc *hal); 52 void hal_qcn9224v2_attach(struct hal_soc *hal); 53 #endif 54 #if defined(QCA_WIFI_QCN6122) || defined(QCA_WIFI_QCN9160) 55 void hal_qcn6122_attach(struct hal_soc *hal); 56 #endif 57 #ifdef QCA_WIFI_QCA6750 58 void hal_qca6750_attach(struct hal_soc *hal); 59 #endif 60 #ifdef QCA_WIFI_QCA5018 61 void hal_qca5018_attach(struct hal_soc *hal); 62 #endif 63 #ifdef QCA_WIFI_QCA5332 64 void hal_qca5332_attach(struct hal_soc *hal); 65 #endif 66 #ifdef QCA_WIFI_KIWI 67 void hal_kiwi_attach(struct hal_soc *hal); 68 #endif 69 70 #ifdef ENABLE_VERBOSE_DEBUG 71 bool is_hal_verbose_debug_enabled; 72 #endif 73 74 #define HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4) 75 #define HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8) 76 #define HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) 77 #define HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) 78 79 #ifdef ENABLE_HAL_REG_WR_HISTORY 80 struct hal_reg_write_fail_history hal_reg_wr_hist; 81 82 void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc, 83 uint32_t offset, 84 uint32_t wr_val, uint32_t rd_val) 85 { 86 struct hal_reg_write_fail_entry *record; 87 int idx; 88 89 idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index, 90 HAL_REG_WRITE_HIST_SIZE); 91 92 record = &hal_soc->reg_wr_fail_hist->record[idx]; 93 94 record->timestamp = qdf_get_log_timestamp(); 95 record->reg_offset = offset; 96 record->write_val = wr_val; 97 record->read_val = rd_val; 98 } 99 100 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 101 { 102 hal->reg_wr_fail_hist = &hal_reg_wr_hist; 103 104 qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1); 105 } 106 #else 107 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 108 { 109 } 110 #endif 111 112 /** 113 * hal_get_srng_ring_id() - get the ring id of a described ring 114 * @hal: hal_soc data structure 115 * @ring_type: type enum describing the ring 116 * @ring_num: which ring of the ring type 117 * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings) 118 * 119 * Return: the ring id or -EINVAL if the ring does not exist. 120 */ 121 static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type, 122 int ring_num, int mac_id) 123 { 124 struct hal_hw_srng_config *ring_config = 125 HAL_SRNG_CONFIG(hal, ring_type); 126 int ring_id; 127 128 if (ring_num >= ring_config->max_rings) { 129 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO, 130 "%s: ring_num exceeded maximum no. of supported rings", 131 __func__); 132 /* TODO: This is a programming error. Assert if this happens */ 133 return -EINVAL; 134 } 135 136 /** 137 * Some DMAC rings share a common source ring, hence don't provide them 138 * with separate ring IDs per LMAC. 139 */ 140 if (ring_config->lmac_ring && !ring_config->dmac_cmn_ring) { 141 ring_id = (ring_config->start_ring_id + ring_num + 142 (mac_id * HAL_MAX_RINGS_PER_LMAC)); 143 } else { 144 ring_id = ring_config->start_ring_id + ring_num; 145 } 146 147 return ring_id; 148 } 149 150 static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id) 151 { 152 /* TODO: Should we allocate srng structures dynamically? */ 153 return &(hal->srng_list[ring_id]); 154 } 155 156 #ifndef SHADOW_REG_CONFIG_DISABLED 157 #define HP_OFFSET_IN_REG_START 1 158 #define OFFSET_FROM_HP_TO_TP 4 159 static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc, 160 int shadow_config_index, 161 int ring_type, 162 int ring_num) 163 { 164 struct hal_srng *srng; 165 int ring_id; 166 struct hal_hw_srng_config *ring_config = 167 HAL_SRNG_CONFIG(hal_soc, ring_type); 168 169 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0); 170 if (ring_id < 0) 171 return; 172 173 srng = hal_get_srng(hal_soc, ring_id); 174 175 if (ring_config->ring_dir == HAL_SRNG_DST_RING) { 176 srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index) 177 + hal_soc->dev_base_addr; 178 hal_debug("tp_addr=%pK dev base addr %pK index %u", 179 srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr, 180 shadow_config_index); 181 } else { 182 srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index) 183 + hal_soc->dev_base_addr; 184 hal_debug("hp_addr=%pK dev base addr %pK index %u", 185 srng->u.src_ring.hp_addr, 186 hal_soc->dev_base_addr, shadow_config_index); 187 } 188 189 } 190 #endif 191 192 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 193 void hal_set_one_target_reg_config(struct hal_soc *hal, 194 uint32_t target_reg_offset, 195 int list_index) 196 { 197 int i = list_index; 198 199 qdf_assert_always(i < MAX_GENERIC_SHADOW_REG); 200 hal->list_shadow_reg_config[i].target_register = 201 target_reg_offset; 202 hal->num_generic_shadow_regs_configured++; 203 } 204 205 qdf_export_symbol(hal_set_one_target_reg_config); 206 207 #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4 208 #define MAX_REO_REMAP_SHADOW_REGS 4 209 QDF_STATUS hal_set_shadow_regs(void *hal_soc) 210 { 211 uint32_t target_reg_offset; 212 struct hal_soc *hal = (struct hal_soc *)hal_soc; 213 int i; 214 struct hal_hw_srng_config *srng_config = 215 &hal->hw_srng_table[WBM2SW_RELEASE]; 216 uint32_t reo_reg_base; 217 218 reo_reg_base = hal_get_reo_reg_base_offset(hal_soc); 219 220 target_reg_offset = 221 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(reo_reg_base); 222 223 for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) { 224 hal_set_one_target_reg_config(hal, target_reg_offset, i); 225 target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET; 226 } 227 228 target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 229 target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 230 * HAL_IPA_TX_COMP_RING_IDX); 231 232 hal_set_one_target_reg_config(hal, target_reg_offset, i); 233 return QDF_STATUS_SUCCESS; 234 } 235 236 qdf_export_symbol(hal_set_shadow_regs); 237 238 QDF_STATUS hal_construct_shadow_regs(void *hal_soc) 239 { 240 struct hal_soc *hal = (struct hal_soc *)hal_soc; 241 int shadow_config_index = hal->num_shadow_registers_configured; 242 int i; 243 int num_regs = hal->num_generic_shadow_regs_configured; 244 245 for (i = 0; i < num_regs; i++) { 246 qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS); 247 hal->shadow_config[shadow_config_index].addr = 248 hal->list_shadow_reg_config[i].target_register; 249 hal->list_shadow_reg_config[i].shadow_config_index = 250 shadow_config_index; 251 hal->list_shadow_reg_config[i].va = 252 SHADOW_REGISTER(shadow_config_index) + 253 (uintptr_t)hal->dev_base_addr; 254 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x", 255 hal->shadow_config[shadow_config_index].addr, 256 SHADOW_REGISTER(shadow_config_index), 257 shadow_config_index); 258 shadow_config_index++; 259 hal->num_shadow_registers_configured++; 260 } 261 return QDF_STATUS_SUCCESS; 262 } 263 264 qdf_export_symbol(hal_construct_shadow_regs); 265 #endif 266 267 #ifndef SHADOW_REG_CONFIG_DISABLED 268 269 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, 270 int ring_type, 271 int ring_num) 272 { 273 uint32_t target_register; 274 struct hal_soc *hal = (struct hal_soc *)hal_soc; 275 struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type]; 276 int shadow_config_index = hal->num_shadow_registers_configured; 277 278 if (shadow_config_index >= MAX_SHADOW_REGISTERS) { 279 QDF_ASSERT(0); 280 return QDF_STATUS_E_RESOURCES; 281 } 282 283 hal->num_shadow_registers_configured++; 284 285 target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 286 target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 287 *ring_num); 288 289 /* if the ring is a dst ring, we need to shadow the tail pointer */ 290 if (srng_config->ring_dir == HAL_SRNG_DST_RING) 291 target_register += OFFSET_FROM_HP_TO_TP; 292 293 hal->shadow_config[shadow_config_index].addr = target_register; 294 295 /* update hp/tp addr in the hal_soc structure*/ 296 hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type, 297 ring_num); 298 299 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d", 300 target_register, 301 SHADOW_REGISTER(shadow_config_index), 302 shadow_config_index, 303 ring_type, ring_num); 304 305 return QDF_STATUS_SUCCESS; 306 } 307 308 qdf_export_symbol(hal_set_one_shadow_config); 309 310 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 311 { 312 int ring_type, ring_num; 313 struct hal_soc *hal = (struct hal_soc *)hal_soc; 314 315 for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) { 316 struct hal_hw_srng_config *srng_config = 317 &hal->hw_srng_table[ring_type]; 318 319 if (ring_type == CE_SRC || 320 ring_type == CE_DST || 321 ring_type == CE_DST_STATUS) 322 continue; 323 324 if (srng_config->lmac_ring) 325 continue; 326 327 for (ring_num = 0; ring_num < srng_config->max_rings; 328 ring_num++) 329 hal_set_one_shadow_config(hal_soc, ring_type, ring_num); 330 } 331 332 return QDF_STATUS_SUCCESS; 333 } 334 335 qdf_export_symbol(hal_construct_srng_shadow_regs); 336 #else 337 338 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 339 { 340 return QDF_STATUS_SUCCESS; 341 } 342 343 qdf_export_symbol(hal_construct_srng_shadow_regs); 344 345 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type, 346 int ring_num) 347 { 348 return QDF_STATUS_SUCCESS; 349 } 350 qdf_export_symbol(hal_set_one_shadow_config); 351 #endif 352 353 void hal_get_shadow_config(void *hal_soc, 354 struct pld_shadow_reg_v2_cfg **shadow_config, 355 int *num_shadow_registers_configured) 356 { 357 struct hal_soc *hal = (struct hal_soc *)hal_soc; 358 359 *shadow_config = &hal->shadow_config[0].v2; 360 *num_shadow_registers_configured = 361 hal->num_shadow_registers_configured; 362 } 363 qdf_export_symbol(hal_get_shadow_config); 364 365 #ifdef CONFIG_SHADOW_V3 366 void hal_get_shadow_v3_config(void *hal_soc, 367 struct pld_shadow_reg_v3_cfg **shadow_config, 368 int *num_shadow_registers_configured) 369 { 370 struct hal_soc *hal = (struct hal_soc *)hal_soc; 371 372 *shadow_config = &hal->shadow_config[0].v3; 373 *num_shadow_registers_configured = 374 hal->num_shadow_registers_configured; 375 } 376 qdf_export_symbol(hal_get_shadow_v3_config); 377 #endif 378 379 static bool hal_validate_shadow_register(struct hal_soc *hal, 380 uint32_t *destination, 381 uint32_t *shadow_address) 382 { 383 unsigned int index; 384 uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr; 385 int destination_ba_offset = 386 ((char *)destination) - (char *)hal->dev_base_addr; 387 388 index = shadow_address - shadow_0_offset; 389 390 if (index >= MAX_SHADOW_REGISTERS) { 391 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 392 "%s: index %x out of bounds", __func__, index); 393 goto error; 394 } else if (hal->shadow_config[index].addr != destination_ba_offset) { 395 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 396 "%s: sanity check failure, expected %x, found %x", 397 __func__, destination_ba_offset, 398 hal->shadow_config[index].addr); 399 goto error; 400 } 401 return true; 402 error: 403 qdf_print("baddr %pK, destination %pK, shadow_address %pK s0offset %pK index %x", 404 hal->dev_base_addr, destination, shadow_address, 405 shadow_0_offset, index); 406 QDF_BUG(0); 407 return false; 408 } 409 410 static void hal_target_based_configure(struct hal_soc *hal) 411 { 412 /** 413 * Indicate Initialization of srngs to avoid force wake 414 * as umac power collapse is not enabled yet 415 */ 416 hal->init_phase = true; 417 418 switch (hal->target_type) { 419 #ifdef QCA_WIFI_QCA6290 420 case TARGET_TYPE_QCA6290: 421 hal->use_register_windowing = true; 422 hal_qca6290_attach(hal); 423 break; 424 #endif 425 #ifdef QCA_WIFI_QCA6390 426 case TARGET_TYPE_QCA6390: 427 hal->use_register_windowing = true; 428 hal_qca6390_attach(hal); 429 break; 430 #endif 431 #ifdef QCA_WIFI_QCA6490 432 case TARGET_TYPE_QCA6490: 433 hal->use_register_windowing = true; 434 hal_qca6490_attach(hal); 435 break; 436 #endif 437 #ifdef QCA_WIFI_QCA6750 438 case TARGET_TYPE_QCA6750: 439 hal->use_register_windowing = true; 440 hal->static_window_map = true; 441 hal_qca6750_attach(hal); 442 break; 443 #endif 444 #ifdef QCA_WIFI_KIWI 445 case TARGET_TYPE_KIWI: 446 case TARGET_TYPE_MANGO: 447 case TARGET_TYPE_PEACH: 448 hal->use_register_windowing = true; 449 hal_kiwi_attach(hal); 450 break; 451 #endif 452 #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0) 453 case TARGET_TYPE_QCA8074: 454 hal_qca8074_attach(hal); 455 break; 456 #endif 457 458 #if defined(QCA_WIFI_QCA8074V2) 459 case TARGET_TYPE_QCA8074V2: 460 hal_qca8074v2_attach(hal); 461 break; 462 #endif 463 464 #if defined(QCA_WIFI_QCA6018) 465 case TARGET_TYPE_QCA6018: 466 hal_qca8074v2_attach(hal); 467 break; 468 #endif 469 470 #if defined(QCA_WIFI_QCA9574) 471 case TARGET_TYPE_QCA9574: 472 hal_qca8074v2_attach(hal); 473 break; 474 #endif 475 476 #if defined(QCA_WIFI_QCN6122) 477 case TARGET_TYPE_QCN6122: 478 hal->use_register_windowing = true; 479 /* 480 * Static window map is enabled for qcn9000 to use 2mb bar 481 * size and use multiple windows to write into registers. 482 */ 483 hal->static_window_map = true; 484 hal_qcn6122_attach(hal); 485 break; 486 #endif 487 488 #if defined(QCA_WIFI_QCN9160) 489 case TARGET_TYPE_QCN9160: 490 hal->use_register_windowing = true; 491 /* 492 * Static window map is enabled for qcn9160 to use 2mb bar 493 * size and use multiple windows to write into registers. 494 */ 495 hal->static_window_map = true; 496 hal_qcn6122_attach(hal); 497 break; 498 #endif 499 500 #ifdef QCA_WIFI_QCN9000 501 case TARGET_TYPE_QCN9000: 502 hal->use_register_windowing = true; 503 /* 504 * Static window map is enabled for qcn9000 to use 2mb bar 505 * size and use multiple windows to write into registers. 506 */ 507 hal->static_window_map = true; 508 hal_qcn9000_attach(hal); 509 break; 510 #endif 511 #ifdef QCA_WIFI_QCA5018 512 case TARGET_TYPE_QCA5018: 513 hal->use_register_windowing = true; 514 hal->static_window_map = true; 515 hal_qca5018_attach(hal); 516 break; 517 #endif 518 #ifdef QCA_WIFI_QCN9224 519 case TARGET_TYPE_QCN9224: 520 hal->use_register_windowing = true; 521 hal->static_window_map = true; 522 if (hal->version == 1) 523 hal_qcn9224v1_attach(hal); 524 else 525 hal_qcn9224v2_attach(hal); 526 break; 527 #endif 528 #ifdef QCA_WIFI_QCA5332 529 case TARGET_TYPE_QCA5332: 530 hal->use_register_windowing = true; 531 hal->static_window_map = true; 532 hal_qca5332_attach(hal); 533 break; 534 #endif 535 default: 536 break; 537 } 538 } 539 540 uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl) 541 { 542 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 543 struct hif_target_info *tgt_info = 544 hif_get_target_info_handle(hal_soc->hif_handle); 545 546 return tgt_info->target_type; 547 } 548 549 qdf_export_symbol(hal_get_target_type); 550 551 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 552 /** 553 * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes 554 * @hal: hal_soc pointer 555 * 556 * Return: true if throughput is high, else false. 557 */ 558 static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal) 559 { 560 int bw_level = hif_get_bandwidth_level(hal->hif_handle); 561 562 return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false; 563 } 564 565 static inline 566 char *hal_fill_reg_write_srng_stats(struct hal_srng *srng, 567 char *buf, qdf_size_t size) 568 { 569 qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u", 570 srng->wstats.enqueues, srng->wstats.dequeues, 571 srng->wstats.coalesces, srng->wstats.direct); 572 return buf; 573 } 574 575 /* bytes for local buffer */ 576 #define HAL_REG_WRITE_SRNG_STATS_LEN 100 577 578 void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl) 579 { 580 struct hal_srng *srng; 581 char buf[HAL_REG_WRITE_SRNG_STATS_LEN]; 582 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 583 584 srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1); 585 hal_debug("SW2TCL1: %s", 586 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 587 588 srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE); 589 hal_debug("WBM2SW0: %s", 590 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 591 592 srng = hal_get_srng(hal, HAL_SRNG_REO2SW1); 593 hal_debug("REO2SW1: %s", 594 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 595 596 srng = hal_get_srng(hal, HAL_SRNG_REO2SW2); 597 hal_debug("REO2SW2: %s", 598 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 599 600 srng = hal_get_srng(hal, HAL_SRNG_REO2SW3); 601 hal_debug("REO2SW3: %s", 602 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 603 } 604 605 void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl) 606 { 607 uint32_t *hist; 608 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 609 610 hist = hal->stats.wstats.sched_delay; 611 hal_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u", 612 qdf_atomic_read(&hal->stats.wstats.enqueues), 613 hal->stats.wstats.dequeues, 614 qdf_atomic_read(&hal->stats.wstats.coalesces), 615 qdf_atomic_read(&hal->stats.wstats.direct), 616 qdf_atomic_read(&hal->stats.wstats.q_depth), 617 hal->stats.wstats.max_q_depth, 618 hist[REG_WRITE_SCHED_DELAY_SUB_100us], 619 hist[REG_WRITE_SCHED_DELAY_SUB_1000us], 620 hist[REG_WRITE_SCHED_DELAY_SUB_5000us], 621 hist[REG_WRITE_SCHED_DELAY_GT_5000us]); 622 } 623 624 int hal_get_reg_write_pending_work(void *hal_soc) 625 { 626 struct hal_soc *hal = (struct hal_soc *)hal_soc; 627 628 return qdf_atomic_read(&hal->active_work_cnt); 629 } 630 631 #endif 632 633 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 634 #ifdef MEMORY_DEBUG 635 /* 636 * Length of the queue(array) used to hold delayed register writes. 637 * Must be a multiple of 2. 638 */ 639 #define HAL_REG_WRITE_QUEUE_LEN 128 640 #else 641 #define HAL_REG_WRITE_QUEUE_LEN 32 642 #endif 643 644 /** 645 * hal_process_reg_write_q_elem() - process a register write queue element 646 * @hal: hal_soc pointer 647 * @q_elem: pointer to hal register write queue element 648 * 649 * Return: The value which was written to the address 650 */ 651 static uint32_t 652 hal_process_reg_write_q_elem(struct hal_soc *hal, 653 struct hal_reg_write_q_elem *q_elem) 654 { 655 struct hal_srng *srng = q_elem->srng; 656 uint32_t write_val; 657 658 SRNG_LOCK(&srng->lock); 659 660 srng->reg_write_in_progress = false; 661 srng->wstats.dequeues++; 662 663 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 664 q_elem->dequeue_val = srng->u.src_ring.hp; 665 hal_write_address_32_mb(hal, 666 srng->u.src_ring.hp_addr, 667 srng->u.src_ring.hp, false); 668 write_val = srng->u.src_ring.hp; 669 } else { 670 q_elem->dequeue_val = srng->u.dst_ring.tp; 671 hal_write_address_32_mb(hal, 672 srng->u.dst_ring.tp_addr, 673 srng->u.dst_ring.tp, false); 674 write_val = srng->u.dst_ring.tp; 675 } 676 677 q_elem->valid = 0; 678 srng->last_dequeue_time = q_elem->dequeue_time; 679 SRNG_UNLOCK(&srng->lock); 680 681 return write_val; 682 } 683 684 /** 685 * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal 686 * @hal: hal_soc pointer 687 * @delay: delay in us 688 * 689 * Return: None 690 */ 691 static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal, 692 uint64_t delay_us) 693 { 694 uint32_t *hist; 695 696 hist = hal->stats.wstats.sched_delay; 697 698 if (delay_us < 100) 699 hist[REG_WRITE_SCHED_DELAY_SUB_100us]++; 700 else if (delay_us < 1000) 701 hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++; 702 else if (delay_us < 5000) 703 hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++; 704 else 705 hist[REG_WRITE_SCHED_DELAY_GT_5000us]++; 706 } 707 708 #ifdef SHADOW_WRITE_DELAY 709 710 #define SHADOW_WRITE_MIN_DELTA_US 5 711 #define SHADOW_WRITE_DELAY_US 50 712 713 /* 714 * Never add those srngs which are performance relate. 715 * The delay itself will hit performance heavily. 716 */ 717 #define IS_SRNG_MATCH(s) ((s)->ring_id == HAL_SRNG_CE_1_DST_STATUS || \ 718 (s)->ring_id == HAL_SRNG_CE_1_DST) 719 720 static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem) 721 { 722 struct hal_srng *srng = elem->srng; 723 struct hal_soc *hal; 724 qdf_time_t now; 725 qdf_iomem_t real_addr; 726 727 if (qdf_unlikely(!srng)) 728 return false; 729 730 hal = srng->hal_soc; 731 if (qdf_unlikely(!hal)) 732 return false; 733 734 /* Check if it is target srng, and valid shadow reg */ 735 if (qdf_likely(!IS_SRNG_MATCH(srng))) 736 return false; 737 738 if (srng->ring_dir == HAL_SRNG_SRC_RING) 739 real_addr = SRNG_SRC_ADDR(srng, HP); 740 else 741 real_addr = SRNG_DST_ADDR(srng, TP); 742 if (!hal_validate_shadow_register(hal, real_addr, elem->addr)) 743 return false; 744 745 /* Check the time delta from last write of same srng */ 746 now = qdf_get_log_timestamp(); 747 if (qdf_log_timestamp_to_usecs(now - srng->last_dequeue_time) > 748 SHADOW_WRITE_MIN_DELTA_US) 749 return false; 750 751 /* Delay dequeue, and record */ 752 qdf_udelay(SHADOW_WRITE_DELAY_US); 753 754 srng->wstats.dequeue_delay++; 755 hal->stats.wstats.dequeue_delay++; 756 757 return true; 758 } 759 #else 760 static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem) 761 { 762 return false; 763 } 764 #endif 765 766 /** 767 * hal_reg_write_work() - Worker to process delayed writes 768 * @arg: hal_soc pointer 769 * 770 * Return: None 771 */ 772 static void hal_reg_write_work(void *arg) 773 { 774 int32_t q_depth, write_val; 775 struct hal_soc *hal = arg; 776 struct hal_reg_write_q_elem *q_elem; 777 uint64_t delta_us; 778 uint8_t ring_id; 779 uint32_t *addr; 780 uint32_t num_processed = 0; 781 782 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 783 q_elem->work_scheduled_time = qdf_get_log_timestamp(); 784 q_elem->cpu_id = qdf_get_cpu(); 785 786 /* Make sure q_elem consistent in the memory for multi-cores */ 787 qdf_rmb(); 788 if (!q_elem->valid) 789 return; 790 791 q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth); 792 if (q_depth > hal->stats.wstats.max_q_depth) 793 hal->stats.wstats.max_q_depth = q_depth; 794 795 if (hif_prevent_link_low_power_states(hal->hif_handle)) { 796 hal->stats.wstats.prevent_l1_fails++; 797 return; 798 } 799 800 while (true) { 801 qdf_rmb(); 802 if (!q_elem->valid) 803 break; 804 805 q_elem->dequeue_time = qdf_get_log_timestamp(); 806 ring_id = q_elem->srng->ring_id; 807 addr = q_elem->addr; 808 delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time - 809 q_elem->enqueue_time); 810 hal_reg_write_fill_sched_delay_hist(hal, delta_us); 811 812 hal->stats.wstats.dequeues++; 813 qdf_atomic_dec(&hal->stats.wstats.q_depth); 814 815 if (hal_reg_write_need_delay(q_elem)) 816 hal_verbose_debug("Delay reg writer for srng 0x%x, addr 0x%pK", 817 q_elem->srng->ring_id, q_elem->addr); 818 819 write_val = hal_process_reg_write_q_elem(hal, q_elem); 820 hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us", 821 hal->read_idx, ring_id, addr, write_val, delta_us); 822 823 qdf_trace_dp_del_reg_write(ring_id, q_elem->enqueue_val, 824 q_elem->dequeue_val, 825 q_elem->enqueue_time, 826 q_elem->dequeue_time); 827 828 num_processed++; 829 hal->read_idx = (hal->read_idx + 1) & 830 (HAL_REG_WRITE_QUEUE_LEN - 1); 831 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 832 } 833 834 hif_allow_link_low_power_states(hal->hif_handle); 835 /* 836 * Decrement active_work_cnt by the number of elements dequeued after 837 * hif_allow_link_low_power_states. 838 * This makes sure that hif_try_complete_tasks will wait till we make 839 * the bus access in hif_allow_link_low_power_states. This will avoid 840 * race condition between delayed register worker and bus suspend 841 * (system suspend or runtime suspend). 842 * 843 * The following decrement should be done at the end! 844 */ 845 qdf_atomic_sub(num_processed, &hal->active_work_cnt); 846 } 847 848 static void __hal_flush_reg_write_work(struct hal_soc *hal) 849 { 850 qdf_flush_work(&hal->reg_write_work); 851 qdf_disable_work(&hal->reg_write_work); 852 } 853 854 void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) 855 { __hal_flush_reg_write_work((struct hal_soc *)hal_handle); 856 } 857 858 /** 859 * hal_reg_write_enqueue() - enqueue register writes into kworker 860 * @hal_soc: hal_soc pointer 861 * @srng: srng pointer 862 * @addr: iomem address of register 863 * @value: value to be written to iomem address 864 * 865 * This function executes from within the SRNG LOCK 866 * 867 * Return: None 868 */ 869 static void hal_reg_write_enqueue(struct hal_soc *hal_soc, 870 struct hal_srng *srng, 871 void __iomem *addr, 872 uint32_t value) 873 { 874 struct hal_reg_write_q_elem *q_elem; 875 uint32_t write_idx; 876 877 if (srng->reg_write_in_progress) { 878 hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u", 879 srng->ring_id, addr, value); 880 qdf_atomic_inc(&hal_soc->stats.wstats.coalesces); 881 srng->wstats.coalesces++; 882 return; 883 } 884 885 write_idx = qdf_atomic_inc_return(&hal_soc->write_idx); 886 887 write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1); 888 889 q_elem = &hal_soc->reg_write_queue[write_idx]; 890 891 if (q_elem->valid) { 892 hal_err("queue full"); 893 QDF_BUG(0); 894 return; 895 } 896 897 qdf_atomic_inc(&hal_soc->stats.wstats.enqueues); 898 srng->wstats.enqueues++; 899 900 qdf_atomic_inc(&hal_soc->stats.wstats.q_depth); 901 902 q_elem->srng = srng; 903 q_elem->addr = addr; 904 q_elem->enqueue_val = value; 905 q_elem->enqueue_time = qdf_get_log_timestamp(); 906 907 /* 908 * Before the valid flag is set to true, all the other 909 * fields in the q_elem needs to be updated in memory. 910 * Else there is a chance that the dequeuing worker thread 911 * might read stale entries and process incorrect srng. 912 */ 913 qdf_wmb(); 914 q_elem->valid = true; 915 916 /* 917 * After all other fields in the q_elem has been updated 918 * in memory successfully, the valid flag needs to be updated 919 * in memory in time too. 920 * Else there is a chance that the dequeuing worker thread 921 * might read stale valid flag and the work will be bypassed 922 * for this round. And if there is no other work scheduled 923 * later, this hal register writing won't be updated any more. 924 */ 925 qdf_wmb(); 926 927 srng->reg_write_in_progress = true; 928 qdf_atomic_inc(&hal_soc->active_work_cnt); 929 930 hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u", 931 write_idx, srng->ring_id, addr, value); 932 933 qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq, 934 &hal_soc->reg_write_work); 935 } 936 937 /** 938 * hal_delayed_reg_write_init() - Initialization function for delayed reg writes 939 * @hal_soc: hal_soc pointer 940 * 941 * Initialize main data structures to process register writes in a delayed 942 * workqueue. 943 * 944 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 945 */ 946 static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 947 { 948 hal->reg_write_wq = 949 qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq"); 950 qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal); 951 hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN * 952 sizeof(*hal->reg_write_queue)); 953 if (!hal->reg_write_queue) { 954 hal_err("unable to allocate memory"); 955 QDF_BUG(0); 956 return QDF_STATUS_E_NOMEM; 957 } 958 959 /* Initial value of indices */ 960 hal->read_idx = 0; 961 qdf_atomic_set(&hal->write_idx, -1); 962 return QDF_STATUS_SUCCESS; 963 } 964 965 /** 966 * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing 967 * @hal_soc: hal_soc pointer 968 * 969 * De-initialize main data structures to process register writes in a delayed 970 * workqueue. 971 * 972 * Return: None 973 */ 974 static void hal_delayed_reg_write_deinit(struct hal_soc *hal) 975 { 976 __hal_flush_reg_write_work(hal); 977 978 qdf_flush_workqueue(0, hal->reg_write_wq); 979 qdf_destroy_workqueue(0, hal->reg_write_wq); 980 qdf_mem_free(hal->reg_write_queue); 981 } 982 983 #else 984 static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 985 { 986 return QDF_STATUS_SUCCESS; 987 } 988 989 static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal) 990 { 991 } 992 #endif 993 994 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 995 #ifdef HAL_RECORD_SUSPEND_WRITE 996 static struct hal_suspend_write_history 997 g_hal_suspend_write_history[HAL_SUSPEND_WRITE_HISTORY_MAX]; 998 999 static 1000 void hal_event_suspend_record(uint8_t ring_id, uint32_t value, uint32_t count) 1001 { 1002 uint32_t index = qdf_atomic_read(g_hal_suspend_write_history.index) & 1003 (HAL_SUSPEND_WRITE_HISTORY_MAX - 1); 1004 struct hal_suspend_write_record *cur_event = 1005 &hal_suspend_write_event.record[index]; 1006 1007 cur_event->ts = qdf_get_log_timestamp(); 1008 cur_event->ring_id = ring_id; 1009 cur_event->value = value; 1010 cur_event->direct_wcount = count; 1011 qdf_atomic_inc(g_hal_suspend_write_history.index); 1012 } 1013 1014 static inline 1015 void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count) 1016 { 1017 if (hif_rtpm_get_state() >= HIF_RTPM_STATE_SUSPENDING) 1018 hal_event_suspend_record(ring_id, value, count); 1019 } 1020 #else 1021 static inline 1022 void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count) 1023 { 1024 } 1025 #endif 1026 1027 #ifdef QCA_WIFI_QCA6750 1028 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1029 struct hal_srng *srng, 1030 void __iomem *addr, 1031 uint32_t value) 1032 { 1033 uint8_t vote_access; 1034 1035 switch (srng->ring_type) { 1036 case CE_SRC: 1037 case CE_DST: 1038 case CE_DST_STATUS: 1039 vote_access = hif_get_ep_vote_access(hal_soc->hif_handle, 1040 HIF_EP_VOTE_NONDP_ACCESS); 1041 if ((vote_access == HIF_EP_VOTE_ACCESS_DISABLE) || 1042 (vote_access == HIF_EP_VOTE_INTERMEDIATE_ACCESS && 1043 PLD_MHI_STATE_L0 == 1044 pld_get_mhi_state(hal_soc->qdf_dev->dev))) { 1045 hal_write_address_32_mb(hal_soc, addr, value, false); 1046 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1047 srng->wstats.direct++; 1048 } else { 1049 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1050 } 1051 break; 1052 default: 1053 if (hif_get_ep_vote_access(hal_soc->hif_handle, 1054 HIF_EP_VOTE_DP_ACCESS) == 1055 HIF_EP_VOTE_ACCESS_DISABLE || 1056 hal_is_reg_write_tput_level_high(hal_soc) || 1057 PLD_MHI_STATE_L0 == 1058 pld_get_mhi_state(hal_soc->qdf_dev->dev)) { 1059 hal_write_address_32_mb(hal_soc, addr, value, false); 1060 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1061 srng->wstats.direct++; 1062 } else { 1063 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1064 } 1065 1066 break; 1067 } 1068 } 1069 #else 1070 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1071 struct hal_srng *srng, 1072 void __iomem *addr, 1073 uint32_t value) 1074 { 1075 if (hal_is_reg_write_tput_level_high(hal_soc) || 1076 pld_is_device_awake(hal_soc->qdf_dev->dev)) { 1077 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1078 srng->wstats.direct++; 1079 hal_write_address_32_mb(hal_soc, addr, value, false); 1080 } else { 1081 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1082 } 1083 1084 hal_record_suspend_write(srng->ring_id, value, srng->wstats.direct); 1085 } 1086 #endif 1087 #endif 1088 1089 /** 1090 * hal_attach - Initialize HAL layer 1091 * @hif_handle: Opaque HIF handle 1092 * @qdf_dev: QDF device 1093 * 1094 * Return: Opaque HAL SOC handle 1095 * NULL on failure (if given ring is not available) 1096 * 1097 * This function should be called as part of HIF initialization (for accessing 1098 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 1099 * 1100 */ 1101 void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev) 1102 { 1103 struct hal_soc *hal; 1104 int i; 1105 1106 hal = qdf_mem_malloc(sizeof(*hal)); 1107 1108 if (!hal) { 1109 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1110 "%s: hal_soc allocation failed", __func__); 1111 goto fail0; 1112 } 1113 hal->hif_handle = hif_handle; 1114 hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */ 1115 hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */ 1116 hal->dev_base_addr_cmem = hif_get_dev_ba_cmem(hif_handle); /* CMEM */ 1117 hal->dev_base_addr_pmm = hif_get_dev_ba_pmm(hif_handle); /* PMM */ 1118 hal->qdf_dev = qdf_dev; 1119 hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent( 1120 qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) * 1121 HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr)); 1122 if (!hal->shadow_rdptr_mem_paddr) { 1123 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1124 "%s: hal->shadow_rdptr_mem_paddr allocation failed", 1125 __func__); 1126 goto fail1; 1127 } 1128 qdf_mem_zero(hal->shadow_rdptr_mem_vaddr, 1129 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX); 1130 1131 hal->shadow_wrptr_mem_vaddr = 1132 (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev, 1133 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 1134 &(hal->shadow_wrptr_mem_paddr)); 1135 if (!hal->shadow_wrptr_mem_vaddr) { 1136 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1137 "%s: hal->shadow_wrptr_mem_vaddr allocation failed", 1138 __func__); 1139 goto fail2; 1140 } 1141 qdf_mem_zero(hal->shadow_wrptr_mem_vaddr, 1142 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS); 1143 1144 for (i = 0; i < HAL_SRNG_ID_MAX; i++) { 1145 hal->srng_list[i].initialized = 0; 1146 hal->srng_list[i].ring_id = i; 1147 } 1148 1149 qdf_spinlock_create(&hal->register_access_lock); 1150 hal->register_window = 0; 1151 hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal)); 1152 hal->version = hif_get_soc_version(hif_handle); 1153 hal->ops = qdf_mem_malloc(sizeof(*hal->ops)); 1154 1155 if (!hal->ops) { 1156 hal_err("unable to allocable memory for HAL ops"); 1157 goto fail3; 1158 } 1159 1160 hal_target_based_configure(hal); 1161 1162 hal_reg_write_fail_history_init(hal); 1163 1164 qdf_minidump_log(hal, sizeof(*hal), "hal_soc"); 1165 1166 qdf_ssr_driver_dump_register_region("hal_soc", hal, sizeof(*hal)); 1167 1168 qdf_atomic_init(&hal->active_work_cnt); 1169 if (hal_delayed_reg_write_init(hal) != QDF_STATUS_SUCCESS) { 1170 hal_err("unable to initialize delayed reg write"); 1171 goto fail4; 1172 } 1173 1174 hif_rtpm_register(HIF_RTPM_ID_HAL_REO_CMD, NULL); 1175 1176 return (void *)hal; 1177 fail4: 1178 qdf_ssr_driver_dump_unregister_region("hal_soc"); 1179 qdf_minidump_remove(hal, sizeof(*hal), "hal_soc"); 1180 qdf_mem_free(hal->ops); 1181 fail3: 1182 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 1183 sizeof(*hal->shadow_wrptr_mem_vaddr) * 1184 HAL_MAX_LMAC_RINGS, 1185 hal->shadow_wrptr_mem_vaddr, 1186 hal->shadow_wrptr_mem_paddr, 0); 1187 fail2: 1188 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 1189 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 1190 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 1191 fail1: 1192 qdf_mem_free(hal); 1193 fail0: 1194 return NULL; 1195 } 1196 qdf_export_symbol(hal_attach); 1197 1198 /** 1199 * hal_mem_info - Retrieve hal memory base address 1200 * 1201 * @hal_soc: Opaque HAL SOC handle 1202 * @mem: pointer to structure to be updated with hal mem info 1203 */ 1204 void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem) 1205 { 1206 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1207 mem->dev_base_addr = (void *)hal->dev_base_addr; 1208 mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr; 1209 mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr; 1210 mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr; 1211 mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr; 1212 hif_read_phy_mem_base((void *)hal->hif_handle, 1213 (qdf_dma_addr_t *)&mem->dev_base_paddr); 1214 mem->lmac_srng_start_id = HAL_SRNG_LMAC1_ID_START; 1215 return; 1216 } 1217 qdf_export_symbol(hal_get_meminfo); 1218 1219 /** 1220 * hal_detach - Detach HAL layer 1221 * @hal_soc: HAL SOC handle 1222 * 1223 * Return: Opaque HAL SOC handle 1224 * NULL on failure (if given ring is not available) 1225 * 1226 * This function should be called as part of HIF initialization (for accessing 1227 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 1228 * 1229 */ 1230 extern void hal_detach(void *hal_soc) 1231 { 1232 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1233 1234 hif_rtpm_deregister(HIF_RTPM_ID_HAL_REO_CMD); 1235 hal_delayed_reg_write_deinit(hal); 1236 hal_reo_shared_qaddr_detach((hal_soc_handle_t)hal); 1237 qdf_ssr_driver_dump_unregister_region("hal_soc"); 1238 qdf_minidump_remove(hal, sizeof(*hal), "hal_soc"); 1239 qdf_mem_free(hal->ops); 1240 1241 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 1242 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 1243 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 1244 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 1245 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 1246 hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0); 1247 qdf_mem_free(hal); 1248 1249 return; 1250 } 1251 qdf_export_symbol(hal_detach); 1252 1253 #define HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(x) ((x) + 0x000000b0) 1254 #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff 1255 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040) 1256 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1257 /** 1258 * hal_ce_dst_setup - Initialize CE destination ring registers 1259 * @hal_soc: HAL SOC handle 1260 * @srng: SRNG ring pointer 1261 */ 1262 static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng, 1263 int ring_num) 1264 { 1265 uint32_t reg_val = 0; 1266 uint32_t reg_addr; 1267 struct hal_hw_srng_config *ring_config = 1268 HAL_SRNG_CONFIG(hal, CE_DST); 1269 1270 /* set DEST_MAX_LENGTH according to ce assignment */ 1271 reg_addr = HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR( 1272 ring_config->reg_start[R0_INDEX] + 1273 (ring_num * ring_config->reg_size[R0_INDEX])); 1274 1275 reg_val = HAL_REG_READ(hal, reg_addr); 1276 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 1277 reg_val |= srng->u.dst_ring.max_buffer_length & 1278 HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 1279 HAL_REG_WRITE(hal, reg_addr, reg_val); 1280 1281 if (srng->prefetch_timer) { 1282 reg_addr = HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR( 1283 ring_config->reg_start[R0_INDEX] + 1284 (ring_num * ring_config->reg_size[R0_INDEX])); 1285 1286 reg_val = HAL_REG_READ(hal, reg_addr); 1287 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK; 1288 reg_val |= srng->prefetch_timer; 1289 HAL_REG_WRITE(hal, reg_addr, reg_val); 1290 reg_val = HAL_REG_READ(hal, reg_addr); 1291 } 1292 1293 } 1294 1295 /** 1296 * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX 1297 * @hal: HAL SOC handle 1298 * @read: boolean value to indicate if read or write 1299 * @ix0: pointer to store IX0 reg value 1300 * @ix1: pointer to store IX1 reg value 1301 * @ix2: pointer to store IX2 reg value 1302 * @ix3: pointer to store IX3 reg value 1303 */ 1304 void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read, 1305 uint32_t *ix0, uint32_t *ix1, 1306 uint32_t *ix2, uint32_t *ix3) 1307 { 1308 uint32_t reg_offset; 1309 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1310 uint32_t reo_reg_base; 1311 1312 reo_reg_base = hal_get_reo_reg_base_offset(hal_soc_hdl); 1313 1314 if (read) { 1315 if (ix0) { 1316 reg_offset = 1317 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR( 1318 reo_reg_base); 1319 *ix0 = HAL_REG_READ(hal, reg_offset); 1320 } 1321 1322 if (ix1) { 1323 reg_offset = 1324 HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR( 1325 reo_reg_base); 1326 *ix1 = HAL_REG_READ(hal, reg_offset); 1327 } 1328 1329 if (ix2) { 1330 reg_offset = 1331 HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR( 1332 reo_reg_base); 1333 *ix2 = HAL_REG_READ(hal, reg_offset); 1334 } 1335 1336 if (ix3) { 1337 reg_offset = 1338 HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR( 1339 reo_reg_base); 1340 *ix3 = HAL_REG_READ(hal, reg_offset); 1341 } 1342 } else { 1343 if (ix0) { 1344 reg_offset = 1345 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR( 1346 reo_reg_base); 1347 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1348 *ix0, true); 1349 } 1350 1351 if (ix1) { 1352 reg_offset = 1353 HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR( 1354 reo_reg_base); 1355 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1356 *ix1, true); 1357 } 1358 1359 if (ix2) { 1360 reg_offset = 1361 HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR( 1362 reo_reg_base); 1363 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1364 *ix2, true); 1365 } 1366 1367 if (ix3) { 1368 reg_offset = 1369 HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR( 1370 reo_reg_base); 1371 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1372 *ix3, true); 1373 } 1374 } 1375 } 1376 1377 qdf_export_symbol(hal_reo_read_write_ctrl_ix); 1378 1379 /** 1380 * hal_srng_dst_set_hp_paddr_confirm() - Set physical address to dest ring head 1381 * pointer and confirm that write went through by reading back the value 1382 * @srng: sring pointer 1383 * @paddr: physical address 1384 * 1385 * Return: None 1386 */ 1387 void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr) 1388 { 1389 SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff); 1390 SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_MSB, paddr >> 32); 1391 } 1392 1393 qdf_export_symbol(hal_srng_dst_set_hp_paddr_confirm); 1394 1395 /** 1396 * hal_srng_dst_init_hp() - Initialize destination ring head 1397 * pointer 1398 * @hal_soc: hal_soc handle 1399 * @srng: sring pointer 1400 * @vaddr: virtual address 1401 */ 1402 void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc, 1403 struct hal_srng *srng, 1404 uint32_t *vaddr) 1405 { 1406 uint32_t reg_offset; 1407 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1408 1409 if (!srng) 1410 return; 1411 1412 srng->u.dst_ring.hp_addr = vaddr; 1413 reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr; 1414 HAL_REG_WRITE_CONFIRM_RETRY( 1415 hal, reg_offset, srng->u.dst_ring.cached_hp, true); 1416 1417 if (vaddr) { 1418 *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp; 1419 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1420 "hp_addr=%pK, cached_hp=%d", 1421 (void *)srng->u.dst_ring.hp_addr, 1422 srng->u.dst_ring.cached_hp); 1423 } 1424 } 1425 1426 qdf_export_symbol(hal_srng_dst_init_hp); 1427 1428 /** 1429 * hal_srng_hw_init - Private function to initialize SRNG HW 1430 * @hal_soc: HAL SOC handle 1431 * @srng: SRNG ring pointer 1432 * @idle_check: Check if ring is idle 1433 * @idx: ring index 1434 */ 1435 static inline void hal_srng_hw_init(struct hal_soc *hal, 1436 struct hal_srng *srng, bool idle_check, uint32_t idx) 1437 { 1438 if (srng->ring_dir == HAL_SRNG_SRC_RING) 1439 hal_srng_src_hw_init(hal, srng, idle_check, idx); 1440 else 1441 hal_srng_dst_hw_init(hal, srng, idle_check, idx); 1442 } 1443 1444 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 1445 /** 1446 * hal_srng_is_near_full_irq_supported() - Check if near full irq is 1447 * supported on this SRNG 1448 * @hal_soc: HAL SoC handle 1449 * @ring_type: SRNG type 1450 * @ring_num: ring number 1451 * 1452 * Return: true, if near full irq is supported for this SRNG 1453 * false, if near full irq is not supported for this SRNG 1454 */ 1455 bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc, 1456 int ring_type, int ring_num) 1457 { 1458 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1459 struct hal_hw_srng_config *ring_config = 1460 HAL_SRNG_CONFIG(hal, ring_type); 1461 1462 return ring_config->nf_irq_support; 1463 } 1464 1465 /** 1466 * hal_srng_set_msi2_params() - Set MSI2 params to SRNG data structure from 1467 * ring params 1468 * @srng: SRNG handle 1469 * @ring_params: ring params for this SRNG 1470 * 1471 * Return: None 1472 */ 1473 static inline void 1474 hal_srng_set_msi2_params(struct hal_srng *srng, 1475 struct hal_srng_params *ring_params) 1476 { 1477 srng->msi2_addr = ring_params->msi2_addr; 1478 srng->msi2_data = ring_params->msi2_data; 1479 } 1480 1481 /** 1482 * hal_srng_get_nf_params() - Get the near full MSI2 params from srng 1483 * @srng: SRNG handle 1484 * @ring_params: ring params for this SRNG 1485 * 1486 * Return: None 1487 */ 1488 static inline void 1489 hal_srng_get_nf_params(struct hal_srng *srng, 1490 struct hal_srng_params *ring_params) 1491 { 1492 ring_params->msi2_addr = srng->msi2_addr; 1493 ring_params->msi2_data = srng->msi2_data; 1494 } 1495 1496 /** 1497 * hal_srng_set_nf_thresholds() - Set the near full thresholds in SRNG 1498 * @srng: SRNG handle where the params are to be set 1499 * @ring_params: ring params, from where threshold is to be fetched 1500 * 1501 * Return: None 1502 */ 1503 static inline void 1504 hal_srng_set_nf_thresholds(struct hal_srng *srng, 1505 struct hal_srng_params *ring_params) 1506 { 1507 srng->u.dst_ring.nf_irq_support = ring_params->nf_irq_support; 1508 srng->u.dst_ring.high_thresh = ring_params->high_thresh; 1509 } 1510 #else 1511 static inline void 1512 hal_srng_set_msi2_params(struct hal_srng *srng, 1513 struct hal_srng_params *ring_params) 1514 { 1515 } 1516 1517 static inline void 1518 hal_srng_get_nf_params(struct hal_srng *srng, 1519 struct hal_srng_params *ring_params) 1520 { 1521 } 1522 1523 static inline void 1524 hal_srng_set_nf_thresholds(struct hal_srng *srng, 1525 struct hal_srng_params *ring_params) 1526 { 1527 } 1528 #endif 1529 1530 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 1531 /** 1532 * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr 1533 * 1534 * @srng: Source ring pointer 1535 * 1536 * Return: None 1537 */ 1538 static inline 1539 void hal_srng_last_desc_cleared_init(struct hal_srng *srng) 1540 { 1541 srng->last_desc_cleared = srng->ring_size - srng->entry_size; 1542 } 1543 1544 #else 1545 static inline 1546 void hal_srng_last_desc_cleared_init(struct hal_srng *srng) 1547 { 1548 } 1549 #endif /* CLEAR_SW2TCL_CONSUMED_DESC */ 1550 1551 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 1552 static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng) 1553 { 1554 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100] = 1555 ((srng->num_entries * 90) / 100); 1556 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90] = 1557 ((srng->num_entries * 80) / 100); 1558 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80] = 1559 ((srng->num_entries * 70) / 100); 1560 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70] = 1561 ((srng->num_entries * 60) / 100); 1562 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60] = 1563 ((srng->num_entries * 50) / 100); 1564 /* Below 50% threshold is not needed */ 1565 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT] = 0; 1566 1567 hal_info("ring_id: %u, wm_thresh- <50:%u, 50-60:%u, 60-70:%u, 70-80:%u, 80-90:%u, 90-100:%u", 1568 srng->ring_id, 1569 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT], 1570 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60], 1571 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70], 1572 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80], 1573 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90], 1574 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100]); 1575 } 1576 #else 1577 static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng) 1578 { 1579 } 1580 #endif 1581 1582 /** 1583 * hal_srng_setup_idx - Initialize HW SRNG ring. 1584 * @hal_soc: Opaque HAL SOC handle 1585 * @ring_type: one of the types from hal_ring_type 1586 * @ring_num: Ring number if there are multiple rings of same type (staring 1587 * from 0) 1588 * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings 1589 * @ring_params: SRNG ring params in hal_srng_params structure. 1590 * @idle_check: Check if ring is idle 1591 * @idx: Ring index to be programmed as init value in HP/TP based on srng type 1592 * 1593 * Callers are expected to allocate contiguous ring memory of size 1594 * 'num_entries * entry_size' bytes and pass the physical and virtual base 1595 * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in 1596 * hal_srng_params structure. Ring base address should be 8 byte aligned 1597 * and size of each ring entry should be queried using the API 1598 * hal_srng_get_entrysize 1599 * 1600 * Return: Opaque pointer to ring on success 1601 * NULL on failure (if given ring is not available) 1602 */ 1603 void *hal_srng_setup_idx(void *hal_soc, int ring_type, int ring_num, int mac_id, 1604 struct hal_srng_params *ring_params, bool idle_check, 1605 uint32_t idx) 1606 { 1607 int ring_id; 1608 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1609 hal_soc_handle_t hal_hdl = (hal_soc_handle_t)hal; 1610 struct hal_srng *srng; 1611 struct hal_hw_srng_config *ring_config = 1612 HAL_SRNG_CONFIG(hal, ring_type); 1613 void *dev_base_addr; 1614 int i; 1615 1616 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id); 1617 if (ring_id < 0) 1618 return NULL; 1619 1620 hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id); 1621 1622 srng = hal_get_srng(hal_soc, ring_id); 1623 1624 if (srng->initialized) { 1625 hal_verbose_debug("Ring (ring_type, ring_num) already initialized"); 1626 return NULL; 1627 } 1628 1629 dev_base_addr = hal->dev_base_addr; 1630 srng->ring_id = ring_id; 1631 srng->ring_type = ring_type; 1632 srng->ring_dir = ring_config->ring_dir; 1633 srng->ring_base_paddr = ring_params->ring_base_paddr; 1634 srng->ring_base_vaddr = ring_params->ring_base_vaddr; 1635 srng->entry_size = ring_config->entry_size; 1636 srng->num_entries = ring_params->num_entries; 1637 srng->ring_size = srng->num_entries * srng->entry_size; 1638 srng->ring_size_mask = srng->ring_size - 1; 1639 srng->ring_vaddr_end = srng->ring_base_vaddr + srng->ring_size; 1640 srng->msi_addr = ring_params->msi_addr; 1641 srng->msi_data = ring_params->msi_data; 1642 srng->intr_timer_thres_us = ring_params->intr_timer_thres_us; 1643 srng->intr_batch_cntr_thres_entries = 1644 ring_params->intr_batch_cntr_thres_entries; 1645 if (!idle_check) 1646 srng->prefetch_timer = ring_params->prefetch_timer; 1647 srng->hal_soc = hal_soc; 1648 hal_srng_set_msi2_params(srng, ring_params); 1649 hal_srng_update_high_wm_thresholds(srng); 1650 1651 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) { 1652 srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i] 1653 + (ring_num * ring_config->reg_size[i]); 1654 } 1655 1656 /* Zero out the entire ring memory */ 1657 qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size * 1658 srng->num_entries) << 2); 1659 1660 srng->flags = ring_params->flags; 1661 1662 /* For cached descriptors flush and invalidate the memory*/ 1663 if (srng->flags & HAL_SRNG_CACHED_DESC) { 1664 qdf_nbuf_dma_clean_range( 1665 srng->ring_base_vaddr, 1666 srng->ring_base_vaddr + 1667 ((srng->entry_size * srng->num_entries))); 1668 qdf_nbuf_dma_inv_range( 1669 srng->ring_base_vaddr, 1670 srng->ring_base_vaddr + 1671 ((srng->entry_size * srng->num_entries))); 1672 } 1673 #ifdef BIG_ENDIAN_HOST 1674 /* TODO: See if we should we get these flags from caller */ 1675 srng->flags |= HAL_SRNG_DATA_TLV_SWAP; 1676 srng->flags |= HAL_SRNG_MSI_SWAP; 1677 srng->flags |= HAL_SRNG_RING_PTR_SWAP; 1678 #endif 1679 1680 hal_srng_last_desc_cleared_init(srng); 1681 1682 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1683 srng->u.src_ring.hp = 0; 1684 srng->u.src_ring.reap_hp = srng->ring_size - 1685 srng->entry_size; 1686 srng->u.src_ring.tp_addr = 1687 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1688 srng->u.src_ring.low_threshold = 1689 ring_params->low_threshold * srng->entry_size; 1690 1691 if (srng->u.src_ring.tp_addr) 1692 qdf_mem_zero(srng->u.src_ring.tp_addr, 1693 sizeof(*hal->shadow_rdptr_mem_vaddr)); 1694 1695 if (ring_config->lmac_ring) { 1696 /* For LMAC rings, head pointer updates will be done 1697 * through FW by writing to a shared memory location 1698 */ 1699 srng->u.src_ring.hp_addr = 1700 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1701 HAL_SRNG_LMAC1_ID_START]); 1702 srng->flags |= HAL_SRNG_LMAC_RING; 1703 1704 if (srng->u.src_ring.hp_addr) 1705 qdf_mem_zero(srng->u.src_ring.hp_addr, 1706 sizeof(*hal->shadow_wrptr_mem_vaddr)); 1707 1708 } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) { 1709 srng->u.src_ring.hp_addr = 1710 hal_get_window_address(hal, 1711 SRNG_SRC_ADDR(srng, HP)); 1712 1713 if (CHECK_SHADOW_REGISTERS) { 1714 QDF_TRACE(QDF_MODULE_ID_TXRX, 1715 QDF_TRACE_LEVEL_ERROR, 1716 "%s: Ring (%d, %d) missing shadow config", 1717 __func__, ring_type, ring_num); 1718 } 1719 } else { 1720 hal_validate_shadow_register(hal, 1721 SRNG_SRC_ADDR(srng, HP), 1722 srng->u.src_ring.hp_addr); 1723 } 1724 } else { 1725 /* During initialization loop count in all the descriptors 1726 * will be set to zero, and HW will set it to 1 on completing 1727 * descriptor update in first loop, and increments it by 1 on 1728 * subsequent loops (loop count wraps around after reaching 1729 * 0xffff). The 'loop_cnt' in SW ring state is the expected 1730 * loop count in descriptors updated by HW (to be processed 1731 * by SW). 1732 */ 1733 hal_srng_set_nf_thresholds(srng, ring_params); 1734 srng->u.dst_ring.loop_cnt = 1; 1735 srng->u.dst_ring.tp = 0; 1736 srng->u.dst_ring.hp_addr = 1737 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1738 1739 if (srng->u.dst_ring.hp_addr) 1740 qdf_mem_zero(srng->u.dst_ring.hp_addr, 1741 sizeof(*hal->shadow_rdptr_mem_vaddr)); 1742 1743 if (ring_config->lmac_ring) { 1744 /* For LMAC rings, tail pointer updates will be done 1745 * through FW by writing to a shared memory location 1746 */ 1747 srng->u.dst_ring.tp_addr = 1748 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1749 HAL_SRNG_LMAC1_ID_START]); 1750 srng->flags |= HAL_SRNG_LMAC_RING; 1751 1752 if (srng->u.dst_ring.tp_addr) 1753 qdf_mem_zero(srng->u.dst_ring.tp_addr, 1754 sizeof(*hal->shadow_wrptr_mem_vaddr)); 1755 1756 } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) { 1757 srng->u.dst_ring.tp_addr = 1758 hal_get_window_address(hal, 1759 SRNG_DST_ADDR(srng, TP)); 1760 1761 if (CHECK_SHADOW_REGISTERS) { 1762 QDF_TRACE(QDF_MODULE_ID_TXRX, 1763 QDF_TRACE_LEVEL_ERROR, 1764 "%s: Ring (%d, %d) missing shadow config", 1765 __func__, ring_type, ring_num); 1766 } 1767 } else { 1768 hal_validate_shadow_register(hal, 1769 SRNG_DST_ADDR(srng, TP), 1770 srng->u.dst_ring.tp_addr); 1771 } 1772 } 1773 1774 if (!(ring_config->lmac_ring)) { 1775 if (idx) { 1776 hal->ops->hal_tx_ring_halt_set(hal_hdl); 1777 do { 1778 hal_info("Waiting for ring reset\n"); 1779 } while (!(hal->ops->hal_tx_ring_halt_poll(hal_hdl))); 1780 } 1781 hal_srng_hw_init(hal, srng, idle_check, idx); 1782 1783 if (idx) { 1784 hal->ops->hal_tx_ring_halt_reset(hal_hdl); 1785 } 1786 1787 1788 if (ring_type == CE_DST) { 1789 srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length; 1790 hal_ce_dst_setup(hal, srng, ring_num); 1791 } 1792 } 1793 1794 SRNG_LOCK_INIT(&srng->lock); 1795 1796 srng->srng_event = 0; 1797 1798 srng->initialized = true; 1799 1800 return (void *)srng; 1801 } 1802 qdf_export_symbol(hal_srng_setup_idx); 1803 1804 /** 1805 * hal_srng_setup - Initialize HW SRNG ring. 1806 * @hal_soc: Opaque HAL SOC handle 1807 * @ring_type: one of the types from hal_ring_type 1808 * @ring_num: Ring number if there are multiple rings of same type (staring 1809 * from 0) 1810 * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings 1811 * @ring_params: SRNG ring params in hal_srng_params structure. 1812 * @idle_check: Check if ring is idle 1813 * 1814 * Callers are expected to allocate contiguous ring memory of size 1815 * 'num_entries * entry_size' bytes and pass the physical and virtual base 1816 * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in 1817 * hal_srng_params structure. Ring base address should be 8 byte aligned 1818 * and size of each ring entry should be queried using the API 1819 * hal_srng_get_entrysize 1820 * 1821 * Return: Opaque pointer to ring on success 1822 * NULL on failure (if given ring is not available) 1823 */ 1824 void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num, 1825 int mac_id, struct hal_srng_params *ring_params, 1826 bool idle_check) 1827 { 1828 return hal_srng_setup_idx(hal_soc, ring_type, ring_num, mac_id, 1829 ring_params, idle_check, 0); 1830 } 1831 qdf_export_symbol(hal_srng_setup); 1832 1833 /** 1834 * hal_srng_cleanup - Deinitialize HW SRNG ring. 1835 * @hal_soc: Opaque HAL SOC handle 1836 * @hal_srng: Opaque HAL SRNG pointer 1837 */ 1838 void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl) 1839 { 1840 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1841 SRNG_LOCK_DESTROY(&srng->lock); 1842 srng->initialized = 0; 1843 hal_srng_hw_disable(hal_soc, srng); 1844 } 1845 qdf_export_symbol(hal_srng_cleanup); 1846 1847 /** 1848 * hal_srng_get_entrysize - Returns size of ring entry in bytes 1849 * @hal_soc: Opaque HAL SOC handle 1850 * @ring_type: one of the types from hal_ring_type 1851 * 1852 */ 1853 uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type) 1854 { 1855 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1856 struct hal_hw_srng_config *ring_config = 1857 HAL_SRNG_CONFIG(hal, ring_type); 1858 return ring_config->entry_size << 2; 1859 } 1860 qdf_export_symbol(hal_srng_get_entrysize); 1861 1862 /** 1863 * hal_srng_max_entries - Returns maximum possible number of ring entries 1864 * @hal_soc: Opaque HAL SOC handle 1865 * @ring_type: one of the types from hal_ring_type 1866 * 1867 * Return: Maximum number of entries for the given ring_type 1868 */ 1869 uint32_t hal_srng_max_entries(void *hal_soc, int ring_type) 1870 { 1871 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1872 struct hal_hw_srng_config *ring_config = 1873 HAL_SRNG_CONFIG(hal, ring_type); 1874 1875 return ring_config->max_size / ring_config->entry_size; 1876 } 1877 qdf_export_symbol(hal_srng_max_entries); 1878 1879 enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type) 1880 { 1881 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1882 struct hal_hw_srng_config *ring_config = 1883 HAL_SRNG_CONFIG(hal, ring_type); 1884 1885 return ring_config->ring_dir; 1886 } 1887 1888 /** 1889 * hal_srng_dump - Dump ring status 1890 * @srng: hal srng pointer 1891 */ 1892 void hal_srng_dump(struct hal_srng *srng) 1893 { 1894 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1895 hal_debug("=== SRC RING %d ===", srng->ring_id); 1896 hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u", 1897 srng->u.src_ring.hp, 1898 srng->u.src_ring.reap_hp, 1899 *srng->u.src_ring.tp_addr, 1900 srng->u.src_ring.cached_tp); 1901 } else { 1902 hal_debug("=== DST RING %d ===", srng->ring_id); 1903 hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u", 1904 srng->u.dst_ring.tp, 1905 *srng->u.dst_ring.hp_addr, 1906 srng->u.dst_ring.cached_hp, 1907 srng->u.dst_ring.loop_cnt); 1908 } 1909 } 1910 1911 /** 1912 * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL 1913 * 1914 * @hal_soc: Opaque HAL SOC handle 1915 * @hal_ring: Ring pointer (Source or Destination ring) 1916 * @ring_params: SRNG parameters will be returned through this structure 1917 */ 1918 extern void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl, 1919 hal_ring_handle_t hal_ring_hdl, 1920 struct hal_srng_params *ring_params) 1921 { 1922 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1923 int i =0; 1924 ring_params->ring_id = srng->ring_id; 1925 ring_params->ring_dir = srng->ring_dir; 1926 ring_params->entry_size = srng->entry_size; 1927 1928 ring_params->ring_base_paddr = srng->ring_base_paddr; 1929 ring_params->ring_base_vaddr = srng->ring_base_vaddr; 1930 ring_params->num_entries = srng->num_entries; 1931 ring_params->msi_addr = srng->msi_addr; 1932 ring_params->msi_data = srng->msi_data; 1933 ring_params->intr_timer_thres_us = srng->intr_timer_thres_us; 1934 ring_params->intr_batch_cntr_thres_entries = 1935 srng->intr_batch_cntr_thres_entries; 1936 ring_params->low_threshold = srng->u.src_ring.low_threshold; 1937 ring_params->flags = srng->flags; 1938 ring_params->ring_id = srng->ring_id; 1939 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) 1940 ring_params->hwreg_base[i] = srng->hwreg_base[i]; 1941 1942 hal_srng_get_nf_params(srng, ring_params); 1943 } 1944 qdf_export_symbol(hal_get_srng_params); 1945 1946 void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl, 1947 uint32_t low_threshold) 1948 { 1949 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1950 srng->u.src_ring.low_threshold = low_threshold * srng->entry_size; 1951 } 1952 qdf_export_symbol(hal_set_low_threshold); 1953 1954 #ifdef FEATURE_RUNTIME_PM 1955 void 1956 hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl, 1957 hal_ring_handle_t hal_ring_hdl, 1958 uint32_t rtpm_id) 1959 { 1960 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1961 1962 if (qdf_unlikely(!hal_ring_hdl)) { 1963 qdf_print("Error: Invalid hal_ring\n"); 1964 return; 1965 } 1966 1967 if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, rtpm_id) == 0) { 1968 if (hif_system_pm_state_check(hal_soc->hif_handle)) { 1969 hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl); 1970 hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT); 1971 hal_srng_inc_flush_cnt(hal_ring_hdl); 1972 } else { 1973 hal_srng_access_end(hal_soc_hdl, hal_ring_hdl); 1974 } 1975 1976 hif_rtpm_put(HIF_RTPM_PUT_ASYNC, rtpm_id); 1977 } else { 1978 hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl); 1979 hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT); 1980 hal_srng_inc_flush_cnt(hal_ring_hdl); 1981 } 1982 } 1983 1984 qdf_export_symbol(hal_srng_rtpm_access_end); 1985 #endif /* FEATURE_RUNTIME_PM */ 1986 1987 #ifdef FORCE_WAKE 1988 void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase) 1989 { 1990 struct hal_soc *hal_soc = (struct hal_soc *)soc; 1991 hal_soc->init_phase = init_phase; 1992 } 1993 #endif /* FORCE_WAKE */ 1994