1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_HW_DEFINES_H_ 20 #define _HAL_RX_HW_DEFINES_H_ 21 22 /* Unified desc fields */ 23 #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000 24 #define HAL_RX_USER_TLV32_TYPE_LSB 1 25 #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE 26 27 #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000 28 #define HAL_RX_USER_TLV32_LEN_LSB 10 29 #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00 30 31 #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000 32 #define HAL_RX_USER_TLV32_USERID_LSB 26 33 #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000 34 35 /* rx mpdu desc info */ 36 #define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x0 37 #define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 38 #define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff 39 40 /* reo entrance ring */ 41 #define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x1c 42 #define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 43 #define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 44 45 #define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x18 46 #define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 47 #define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 48 49 #define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x18 50 #define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 51 #define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c 52 53 #define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x8 54 #define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 55 #define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 56 57 #define HAL_SW2WBM_RELEASE_RING_BM_ACTION_OFFSET 0x8 58 #define HAL_SW2WBM_RELEASE_RING_BM_ACTION_LSB 3 59 #define HAL_SW2WBM_RELEASE_RING_BM_ACTION_MASK 0x00000038 60 61 #define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x8 62 #define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 63 #define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 64 65 /* REO CMD entry offsets */ 66 #define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0 67 #define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 68 #define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 69 70 #define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 71 #define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 72 #define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 73 74 #define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 75 #define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 76 #define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 77 78 #define HAL_WBM_INTERNAL_ERROR_OFFSET 0x8 79 #define HAL_WBM_INTERNAL_ERROR_LSB 31 80 #define HAL_WBM_INTERNAL_ERROR_MASK 0x80000000 81 82 #define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x8 83 #define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB 6 84 #define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 85 86 /* RX Flow search entry MACROS */ 87 #define HAL_RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 88 #define HAL_RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 89 #define HAL_RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 90 91 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 92 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 93 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff 94 95 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 96 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 97 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff 98 99 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 100 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 101 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff 102 103 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c 104 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 105 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff 106 107 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 108 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 109 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff 110 111 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 112 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 113 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff 114 115 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 116 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 117 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff 118 119 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c 120 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 121 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff 122 123 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 124 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 125 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 126 127 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 128 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 129 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff 130 131 #define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 132 #define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 133 #define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff 134 135 #endif /* _HAL_RX_HW_DEFINES_H_ */ 136