1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 24 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 25 #define HAL_RX_LSB(block, field) block##_##field##_LSB 26 #define HAL_RX_MASk(block, field) block##_##field##_MASK 27 28 #define HAL_RX_GET(_ptr, block, field) \ 29 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 30 HAL_RX_MASk(block, field)) >> \ 31 HAL_RX_LSB(block, field)) 32 33 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 34 #ifndef RX_DATA_BUFFER_SIZE 35 #define RX_DATA_BUFFER_SIZE 2048 36 #endif 37 38 #ifndef RX_MONITOR_BUFFER_SIZE 39 #define RX_MONITOR_BUFFER_SIZE 2048 40 #endif 41 42 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 43 #define HAL_RX_NON_QOS_TID 16 44 45 enum { 46 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 47 HAL_HW_RX_DECAP_FORMAT_NWIFI, 48 HAL_HW_RX_DECAP_FORMAT_ETH2, 49 HAL_HW_RX_DECAP_FORMAT_8023, 50 }; 51 52 /** 53 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 54 * 55 * @reo_psh_rsn: REO push reason 56 * @reo_err_code: REO Error code 57 * @rxdma_psh_rsn: RXDMA push reason 58 * @rxdma_err_code: RXDMA Error code 59 * @reserved_1: Reserved bits 60 * @wbm_err_src: WBM error source 61 * @pool_id: pool ID, indicates which rxdma pool 62 * @reserved_2: Reserved bits 63 */ 64 struct hal_wbm_err_desc_info { 65 uint16_t reo_psh_rsn:2, 66 reo_err_code:5, 67 rxdma_psh_rsn:2, 68 rxdma_err_code:5, 69 reserved_1:2; 70 uint8_t wbm_err_src:3, 71 pool_id:2, 72 reserved_2:3; 73 }; 74 75 /** 76 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 77 * 78 * @l3_hdr_pad: l3 header padding 79 * @reserved: Reserved bits 80 * @sa_sw_peer_id: sa sw peer id 81 * @sa_idx: sa index 82 * @da_idx: da index 83 */ 84 struct hal_rx_msdu_metadata { 85 uint32_t l3_hdr_pad:16, 86 sa_sw_peer_id:16; 87 uint32_t sa_idx:16, 88 da_idx:16; 89 }; 90 91 /** 92 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 93 * 94 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 95 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 96 */ 97 enum hal_reo_error_status { 98 HAL_REO_ERROR_DETECTED = 0, 99 HAL_REO_ROUTING_INSTRUCTION = 1, 100 }; 101 102 /** 103 * @msdu_flags: [0] first_msdu_in_mpdu 104 * [1] last_msdu_in_mpdu 105 * [2] msdu_continuation - MSDU spread across buffers 106 * [23] sa_is_valid - SA match in peer table 107 * [24] sa_idx_timeout - Timeout while searching for SA match 108 * [25] da_is_valid - Used to identtify intra-bss forwarding 109 * [26] da_is_MCBC 110 * [27] da_idx_timeout - Timeout while searching for DA match 111 * 112 */ 113 struct hal_rx_msdu_desc_info { 114 uint32_t msdu_flags; 115 uint16_t msdu_len; /* 14 bits for length */ 116 }; 117 118 /** 119 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 120 * 121 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 122 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 123 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 124 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 125 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 126 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 127 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 128 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 129 */ 130 enum hal_rx_msdu_desc_flags { 131 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 132 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 133 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 134 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 135 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 136 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 137 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 138 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 139 }; 140 141 /* 142 * @msdu_count: no. of msdus in the MPDU 143 * @mpdu_seq: MPDU sequence number 144 * @mpdu_flags [0] Fragment flag 145 * [1] MPDU_retry_bit 146 * [2] AMPDU flag 147 * [3] raw_ampdu 148 * @peer_meta_data: Upper bits containing peer id, vdev id 149 */ 150 struct hal_rx_mpdu_desc_info { 151 uint16_t msdu_count; 152 uint16_t mpdu_seq; /* 12 bits for length */ 153 uint32_t mpdu_flags; 154 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 155 }; 156 157 /** 158 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 159 * 160 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 161 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 162 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 163 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 164 */ 165 enum hal_rx_mpdu_desc_flags { 166 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 167 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 168 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 169 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 170 }; 171 172 /** 173 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 174 * BUFFER_ADDR_INFO structure 175 * 176 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 177 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 178 * descriptor list 179 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 180 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 181 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 182 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 183 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 184 */ 185 enum hal_rx_ret_buf_manager { 186 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 187 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 188 HAL_RX_BUF_RBM_FW_BM = 2, 189 HAL_RX_BUF_RBM_SW0_BM = 3, 190 HAL_RX_BUF_RBM_SW1_BM = 4, 191 HAL_RX_BUF_RBM_SW2_BM = 5, 192 HAL_RX_BUF_RBM_SW3_BM = 6, 193 }; 194 195 /* 196 * Given the offset of a field in bytes, returns uint8_t * 197 */ 198 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 199 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 200 201 /* 202 * Given the offset of a field in bytes, returns uint32_t * 203 */ 204 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 205 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 206 207 #define _HAL_MS(_word, _mask, _shift) \ 208 (((_word) & (_mask)) >> (_shift)) 209 210 /* 211 * macro to set the LSW of the nbuf data physical address 212 * to the rxdma ring entry 213 */ 214 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 215 ((*(((unsigned int *) buff_addr_info) + \ 216 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 217 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 218 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 219 220 /* 221 * macro to set the LSB of MSW of the nbuf data physical address 222 * to the rxdma ring entry 223 */ 224 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 225 ((*(((unsigned int *) buff_addr_info) + \ 226 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 227 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 228 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 229 230 /* 231 * macro to set the cookie into the rxdma ring entry 232 */ 233 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 234 ((*(((unsigned int *) buff_addr_info) + \ 235 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 236 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 237 ((*(((unsigned int *) buff_addr_info) + \ 238 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 239 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 240 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 241 242 /* 243 * macro to set the manager into the rxdma ring entry 244 */ 245 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 246 ((*(((unsigned int *) buff_addr_info) + \ 247 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 248 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 249 ((*(((unsigned int *) buff_addr_info) + \ 250 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 251 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 252 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 253 254 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 255 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 256 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 257 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 258 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 259 260 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 261 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 262 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 263 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 264 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 265 266 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 267 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 268 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 269 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 270 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 271 272 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 273 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 274 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 275 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 276 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 277 278 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 279 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 280 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 281 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 282 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 283 284 /* TODO: Convert the following structure fields accesseses to offsets */ 285 286 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 287 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 288 (((struct reo_destination_ring *) \ 289 reo_desc)->buf_or_link_desc_addr_info))) 290 291 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 292 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 293 (((struct reo_destination_ring *) \ 294 reo_desc)->buf_or_link_desc_addr_info))) 295 296 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 297 (HAL_RX_BUF_COOKIE_GET(& \ 298 (((struct reo_destination_ring *) \ 299 reo_desc)->buf_or_link_desc_addr_info))) 300 301 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 302 ((mpdu_info_ptr \ 303 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 304 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 305 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 306 307 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 308 ((mpdu_info_ptr \ 309 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 310 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 311 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 312 313 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 314 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 315 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 316 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 317 318 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 319 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 320 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 321 322 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 323 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 324 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 325 326 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 327 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 328 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 329 330 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 331 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 332 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 333 334 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 335 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 336 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 337 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 338 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 339 340 341 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 342 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 343 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 344 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 345 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 346 347 /* 348 * NOTE: None of the following _GET macros need a right 349 * shift by the corresponding _LSB. This is because, they are 350 * finally taken and "OR'ed" into a single word again. 351 */ 352 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 353 ((*(((uint32_t *)msdu_info_ptr) + \ 354 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 355 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 356 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 357 358 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 359 ((*(((uint32_t *)msdu_info_ptr) + \ 360 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 361 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 362 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 363 364 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 365 ((*(((uint32_t *)msdu_info_ptr) + \ 366 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 367 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 368 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 369 370 371 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 372 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 373 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 374 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 375 376 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 377 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 378 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 379 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 380 381 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 382 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 383 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 384 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 385 386 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 387 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 388 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 389 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 390 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 391 392 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 393 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 394 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 395 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 396 397 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 398 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 399 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 400 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 401 402 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 403 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 404 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 405 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 406 407 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 408 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 409 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 410 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 411 412 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 413 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 414 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 415 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 416 417 418 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 419 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 420 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 421 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 422 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 423 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 424 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 425 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 426 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 427 428 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 429 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 430 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 431 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 432 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 433 434 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 435 (*(uint32_t *)(((uint8_t *)_ptr) + \ 436 _wrd ## _ ## _field ## _OFFSET) |= \ 437 ((_val << _wrd ## _ ## _field ## _LSB) & \ 438 _wrd ## _ ## _field ## _MASK)) 439 440 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 441 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 442 _field, _val) 443 444 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 445 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 446 _field, _val) 447 448 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 449 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 450 _field, _val) 451 452 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 453 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 454 { 455 struct reo_destination_ring *reo_dst_ring; 456 uint32_t *mpdu_info; 457 458 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 459 460 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 461 462 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 463 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 464 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 465 mpdu_desc_info->peer_meta_data = 466 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 467 } 468 469 /* 470 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 471 * @ Specifically flags needed are: 472 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 473 * @ msdu_continuation, sa_is_valid, 474 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 475 * @ da_is_MCBC 476 * 477 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 478 * @ descriptor 479 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 480 * @ Return: void 481 */ 482 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 483 struct hal_rx_msdu_desc_info *msdu_desc_info) 484 { 485 struct reo_destination_ring *reo_dst_ring; 486 uint32_t *msdu_info; 487 488 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 489 490 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 491 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 492 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 493 } 494 495 /* 496 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 497 * rxdma ring entry. 498 * @rxdma_entry: descriptor entry 499 * @paddr: physical address of nbuf data pointer. 500 * @cookie: SW cookie used as a index to SW rx desc. 501 * @manager: who owns the nbuf (host, NSS, etc...). 502 * 503 */ 504 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 505 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 506 { 507 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 508 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 509 510 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 511 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 512 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 513 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 514 } 515 516 /* 517 * Structures & Macros to obtain fields from the TLV's in the Rx packet 518 * pre-header. 519 */ 520 521 /* 522 * Every Rx packet starts at an offset from the top of the buffer. 523 * If the host hasn't subscribed to any specific TLV, there is 524 * still space reserved for the following TLV's from the start of 525 * the buffer: 526 * -- RX ATTENTION 527 * -- RX MPDU START 528 * -- RX MSDU START 529 * -- RX MSDU END 530 * -- RX MPDU END 531 * -- RX PACKET HEADER (802.11) 532 * If the host subscribes to any of the TLV's above, that TLV 533 * if populated by the HW 534 */ 535 536 #define NUM_DWORDS_TAG 1 537 538 /* By default the packet header TLV is 128 bytes */ 539 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 540 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 541 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 542 543 #define RX_PKT_OFFSET_WORDS \ 544 ( \ 545 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 546 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 547 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 548 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 549 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 550 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 551 ) 552 553 #define RX_PKT_OFFSET_BYTES \ 554 (RX_PKT_OFFSET_WORDS << 2) 555 556 #define RX_PKT_HDR_TLV_LEN 120 557 558 /* 559 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 560 */ 561 struct rx_attention_tlv { 562 uint32_t tag; 563 struct rx_attention rx_attn; 564 }; 565 566 struct rx_mpdu_start_tlv { 567 uint32_t tag; 568 struct rx_mpdu_start rx_mpdu_start; 569 }; 570 571 struct rx_msdu_start_tlv { 572 uint32_t tag; 573 struct rx_msdu_start rx_msdu_start; 574 }; 575 576 struct rx_msdu_end_tlv { 577 uint32_t tag; 578 struct rx_msdu_end rx_msdu_end; 579 }; 580 581 struct rx_mpdu_end_tlv { 582 uint32_t tag; 583 struct rx_mpdu_end rx_mpdu_end; 584 }; 585 586 struct rx_pkt_hdr_tlv { 587 uint32_t tag; /* 4 B */ 588 uint32_t phy_ppdu_id; /* 4 B */ 589 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 590 }; 591 592 593 #define RXDMA_OPTIMIZATION 594 595 /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status 596 * buffers, monitor destination buffers and monitor descriptor buffers. 597 */ 598 #ifdef RXDMA_OPTIMIZATION 599 /* 600 * The RX_PADDING_BYTES is required so that the TLV's don't 601 * spread across the 128 byte boundary 602 * RXDMA optimization requires: 603 * 1) MSDU_END & ATTENTION TLV's follow in that order 604 * 2) TLV's don't span across 128 byte lines 605 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 606 */ 607 #define RX_PADDING0_BYTES 4 608 #define RX_PADDING1_BYTES 16 609 struct rx_pkt_tlvs { 610 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 611 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 612 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 613 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 614 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 615 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 616 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 617 #ifndef NO_RX_PKT_HDR_TLV 618 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 619 #endif 620 }; 621 #else /* RXDMA_OPTIMIZATION */ 622 struct rx_pkt_tlvs { 623 struct rx_attention_tlv attn_tlv; 624 struct rx_mpdu_start_tlv mpdu_start_tlv; 625 struct rx_msdu_start_tlv msdu_start_tlv; 626 struct rx_msdu_end_tlv msdu_end_tlv; 627 struct rx_mpdu_end_tlv mpdu_end_tlv; 628 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 629 }; 630 #endif /* RXDMA_OPTIMIZATION */ 631 632 /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */ 633 #ifdef RXDMA_OPTIMIZATION 634 struct rx_mon_pkt_tlvs { 635 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 636 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 637 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 638 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 639 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 640 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 641 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 642 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 643 }; 644 #else /* RXDMA_OPTIMIZATION */ 645 struct rx_mon_pkt_tlvs { 646 struct rx_attention_tlv attn_tlv; 647 struct rx_mpdu_start_tlv mpdu_start_tlv; 648 struct rx_msdu_start_tlv msdu_start_tlv; 649 struct rx_msdu_end_tlv msdu_end_tlv; 650 struct rx_mpdu_end_tlv mpdu_end_tlv; 651 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 652 }; 653 #endif 654 655 #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs) 656 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 657 658 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 659 660 #ifdef NO_RX_PKT_HDR_TLV 661 static inline uint8_t 662 *hal_rx_pkt_hdr_get(uint8_t *buf) 663 { 664 return buf + RX_PKT_TLVS_LEN; 665 } 666 #else 667 static inline uint8_t 668 *hal_rx_pkt_hdr_get(uint8_t *buf) 669 { 670 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 671 672 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 673 674 } 675 #endif 676 677 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 678 679 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 680 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 681 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 682 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 683 RX_PKT_TLV_OFFSET(msdu_start_tlv) 684 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 685 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 686 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 687 688 static inline uint8_t 689 *hal_rx_padding0_get(uint8_t *buf) 690 { 691 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 692 693 return pkt_tlvs->rx_padding0; 694 } 695 696 /* 697 * hal_rx_encryption_info_valid(): Returns encryption type. 698 * 699 * @hal_soc_hdl: hal soc handle 700 * @buf: rx_tlv_hdr of the received packet 701 * 702 * Return: encryption type 703 */ 704 static inline uint32_t 705 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 706 { 707 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 708 709 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 710 711 } 712 713 /* 714 * hal_rx_print_pn: Prints the PN of rx packet. 715 * @hal_soc_hdl: hal soc handle 716 * @buf: rx_tlv_hdr of the received packet 717 * 718 * Return: void 719 */ 720 static inline void 721 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 722 { 723 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 724 725 hal_soc->ops->hal_rx_print_pn(buf); 726 } 727 728 /* 729 * Get msdu_done bit from the RX_ATTENTION TLV 730 */ 731 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 732 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 733 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 734 RX_ATTENTION_2_MSDU_DONE_MASK, \ 735 RX_ATTENTION_2_MSDU_DONE_LSB)) 736 737 static inline uint32_t 738 hal_rx_attn_msdu_done_get(uint8_t *buf) 739 { 740 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 741 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 742 uint32_t msdu_done; 743 744 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 745 746 return msdu_done; 747 } 748 749 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 750 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 751 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 752 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 753 RX_ATTENTION_1_FIRST_MPDU_LSB)) 754 755 /* 756 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 757 * @buf: pointer to rx_pkt_tlvs 758 * 759 * reutm: uint32_t(first_msdu) 760 */ 761 static inline uint32_t 762 hal_rx_attn_first_mpdu_get(uint8_t *buf) 763 { 764 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 765 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 766 uint32_t first_mpdu; 767 768 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 769 770 return first_mpdu; 771 } 772 773 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 774 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 775 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 776 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 777 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 778 779 /* 780 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 781 * from rx attention 782 * @buf: pointer to rx_pkt_tlvs 783 * 784 * Return: tcp_udp_cksum_fail 785 */ 786 static inline bool 787 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 788 { 789 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 790 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 791 bool tcp_udp_cksum_fail; 792 793 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 794 795 return tcp_udp_cksum_fail; 796 } 797 798 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 799 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 800 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 801 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 802 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 803 804 /* 805 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 806 * from rx attention 807 * @buf: pointer to rx_pkt_tlvs 808 * 809 * Return: ip_cksum_fail 810 */ 811 static inline bool 812 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 813 { 814 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 815 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 816 bool ip_cksum_fail; 817 818 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 819 820 return ip_cksum_fail; 821 } 822 823 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 824 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 825 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 826 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 827 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 828 829 /* 830 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 831 * from rx attention 832 * @buf: pointer to rx_pkt_tlvs 833 * 834 * Return: phy_ppdu_id 835 */ 836 static inline uint16_t 837 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 838 { 839 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 840 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 841 uint16_t phy_ppdu_id; 842 843 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 844 845 return phy_ppdu_id; 846 } 847 848 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 849 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 850 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 851 RX_ATTENTION_1_CCE_MATCH_MASK, \ 852 RX_ATTENTION_1_CCE_MATCH_LSB)) 853 854 /* 855 * hal_rx_msdu_cce_match_get(): get CCE match bit 856 * from rx attention 857 * @buf: pointer to rx_pkt_tlvs 858 * Return: CCE match value 859 */ 860 static inline bool 861 hal_rx_msdu_cce_match_get(uint8_t *buf) 862 { 863 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 864 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 865 bool cce_match_val; 866 867 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 868 return cce_match_val; 869 } 870 871 /* 872 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 873 */ 874 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 875 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 876 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 877 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 878 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 879 880 static inline uint32_t 881 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 882 { 883 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 884 struct rx_mpdu_start *mpdu_start = 885 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 886 887 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 888 uint32_t peer_meta_data; 889 890 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 891 892 return peer_meta_data; 893 } 894 895 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 896 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 897 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 898 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 899 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 900 /** 901 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 902 * from rx mpdu info 903 * @buf: pointer to rx_pkt_tlvs 904 * 905 * Return: ampdu flag 906 */ 907 static inline bool 908 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 909 { 910 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 911 struct rx_mpdu_start *mpdu_start = 912 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 913 914 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 915 bool ampdu_flag; 916 917 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 918 919 return ampdu_flag; 920 } 921 922 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 923 ((*(((uint32_t *)_rx_mpdu_info) + \ 924 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 925 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 926 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 927 928 /* 929 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 930 * 931 * @ buf: rx_tlv_hdr of the received packet 932 * @ peer_mdata: peer meta data to be set. 933 * @ Return: void 934 */ 935 static inline void 936 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 937 { 938 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 939 struct rx_mpdu_start *mpdu_start = 940 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 941 942 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 943 944 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 945 } 946 947 /** 948 * LRO information needed from the TLVs 949 */ 950 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 951 (_HAL_MS( \ 952 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 953 msdu_end_tlv.rx_msdu_end), \ 954 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 955 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 956 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 957 958 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 959 (_HAL_MS( \ 960 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 961 msdu_end_tlv.rx_msdu_end), \ 962 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 963 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 964 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 965 966 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 967 (_HAL_MS( \ 968 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 969 msdu_end_tlv.rx_msdu_end), \ 970 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 971 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 972 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 973 974 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 975 (_HAL_MS( \ 976 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 977 msdu_end_tlv.rx_msdu_end), \ 978 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 979 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 980 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 981 982 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 983 (_HAL_MS( \ 984 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 985 msdu_start_tlv.rx_msdu_start), \ 986 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 987 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 988 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 989 990 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 991 (_HAL_MS( \ 992 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 993 msdu_start_tlv.rx_msdu_start), \ 994 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 995 RX_MSDU_START_2_TCP_PROTO_MASK, \ 996 RX_MSDU_START_2_TCP_PROTO_LSB)) 997 998 #define HAL_RX_TLV_GET_IPV6(buf) \ 999 (_HAL_MS( \ 1000 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1001 msdu_start_tlv.rx_msdu_start), \ 1002 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 1003 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 1004 RX_MSDU_START_2_IPV6_PROTO_LSB)) 1005 1006 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 1007 (_HAL_MS( \ 1008 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1009 msdu_start_tlv.rx_msdu_start), \ 1010 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 1011 RX_MSDU_START_1_L3_OFFSET_MASK, \ 1012 RX_MSDU_START_1_L3_OFFSET_LSB)) 1013 1014 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 1015 (_HAL_MS( \ 1016 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1017 msdu_start_tlv.rx_msdu_start), \ 1018 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 1019 RX_MSDU_START_1_L4_OFFSET_MASK, \ 1020 RX_MSDU_START_1_L4_OFFSET_LSB)) 1021 1022 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 1023 (_HAL_MS( \ 1024 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1025 msdu_start_tlv.rx_msdu_start), \ 1026 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1027 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1028 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1029 1030 /** 1031 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 1032 * l3_header padding from rx_msdu_end TLV 1033 * 1034 * @buf: pointer to the start of RX PKT TLV headers 1035 * Return: number of l3 header padding bytes 1036 */ 1037 static inline uint32_t 1038 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 1039 uint8_t *buf) 1040 { 1041 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1042 1043 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 1044 } 1045 1046 /** 1047 * hal_rx_msdu_end_sa_idx_get(): API to get the 1048 * sa_idx from rx_msdu_end TLV 1049 * 1050 * @ buf: pointer to the start of RX PKT TLV headers 1051 * Return: sa_idx (SA AST index) 1052 */ 1053 static inline uint16_t 1054 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 1055 uint8_t *buf) 1056 { 1057 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1058 1059 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 1060 } 1061 1062 /** 1063 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1064 * sa_is_valid bit from rx_msdu_end TLV 1065 * 1066 * @ buf: pointer to the start of RX PKT TLV headers 1067 * Return: sa_is_valid bit 1068 */ 1069 static inline uint8_t 1070 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1071 uint8_t *buf) 1072 { 1073 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1074 1075 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 1076 } 1077 1078 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1079 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1080 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1081 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1082 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1083 1084 /** 1085 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1086 * from rx_msdu_start TLV 1087 * 1088 * @ buf: pointer to the start of RX PKT TLV headers 1089 * Return: msdu length 1090 */ 1091 static inline uint32_t 1092 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1093 { 1094 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1095 struct rx_msdu_start *msdu_start = 1096 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1097 uint32_t msdu_len; 1098 1099 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1100 1101 return msdu_len; 1102 } 1103 1104 /** 1105 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1106 * from rx_msdu_start TLV 1107 * 1108 * @buf: pointer to the start of RX PKT TLV headers 1109 * @len: msdu length 1110 * 1111 * Return: none 1112 */ 1113 static inline void 1114 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1115 { 1116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1117 struct rx_msdu_start *msdu_start = 1118 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1119 void *wrd1; 1120 1121 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1122 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1123 *(uint32_t *)wrd1 |= len; 1124 } 1125 1126 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1127 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1128 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1129 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1130 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1131 1132 /* 1133 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1134 * Interval from rx_msdu_start 1135 * 1136 * @buf: pointer to the start of RX PKT TLV header 1137 * Return: uint32_t(bw) 1138 */ 1139 static inline uint32_t 1140 hal_rx_msdu_start_bw_get(uint8_t *buf) 1141 { 1142 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1143 struct rx_msdu_start *msdu_start = 1144 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1145 uint32_t bw; 1146 1147 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1148 1149 return bw; 1150 } 1151 1152 1153 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1155 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1156 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1157 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1158 1159 /** 1160 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1161 * from rx_msdu_start TLV 1162 * 1163 * @ buf: pointer to the start of RX PKT TLV headers 1164 * Return: toeplitz hash 1165 */ 1166 static inline uint32_t 1167 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1168 { 1169 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1170 struct rx_msdu_start *msdu_start = 1171 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1172 1173 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1174 } 1175 1176 /** 1177 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 1178 * 1179 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 1180 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 1181 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 1182 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 1183 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 1184 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 1185 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 1186 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 1187 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 1188 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 1189 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 1190 */ 1191 enum hal_rx_mpdu_info_sw_frame_group_id_type { 1192 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 1193 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 1194 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 1195 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 1196 HAL_MPDU_SW_FRAME_GROUP_MGMT, 1197 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 1198 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 1199 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 1200 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 1201 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 1202 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 1203 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 1204 }; 1205 1206 /** 1207 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 1208 * Retrieve qos control valid bit from the tlv. 1209 * @hal_soc_hdl: hal_soc handle 1210 * @buf: pointer to rx pkt TLV. 1211 * 1212 * Return: qos control value. 1213 */ 1214 static inline uint32_t 1215 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 1216 hal_soc_handle_t hal_soc_hdl, 1217 uint8_t *buf) 1218 { 1219 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1220 1221 if ((!hal_soc) || (!hal_soc->ops)) { 1222 hal_err("hal handle is NULL"); 1223 QDF_BUG(0); 1224 return QDF_STATUS_E_INVAL; 1225 } 1226 1227 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 1228 return hal_soc->ops-> 1229 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 1230 1231 return QDF_STATUS_E_INVAL; 1232 } 1233 1234 /** 1235 * hal_rx_is_unicast: check packet is unicast frame or not. 1236 * @hal_soc_hdl: hal_soc handle 1237 * @buf: pointer to rx pkt TLV. 1238 * 1239 * Return: true on unicast. 1240 */ 1241 static inline bool 1242 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1243 { 1244 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1245 1246 return hal_soc->ops->hal_rx_is_unicast(buf); 1247 } 1248 1249 /** 1250 * hal_rx_tid_get: get tid based on qos control valid. 1251 * @hal_soc_hdl: hal soc handle 1252 * @buf: pointer to rx pkt TLV. 1253 * 1254 * Return: tid 1255 */ 1256 static inline uint32_t 1257 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1258 { 1259 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1260 1261 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 1262 } 1263 1264 /** 1265 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 1266 * @hal_soc_hdl: hal soc handle 1267 * @buf: pointer to rx pkt TLV. 1268 * 1269 * Return: sw peer_id 1270 */ 1271 static inline uint32_t 1272 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1273 uint8_t *buf) 1274 { 1275 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1276 1277 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1278 } 1279 1280 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1281 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1282 RX_MSDU_START_5_SGI_OFFSET)), \ 1283 RX_MSDU_START_5_SGI_MASK, \ 1284 RX_MSDU_START_5_SGI_LSB)) 1285 /** 1286 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1287 * Interval from rx_msdu_start TLV 1288 * 1289 * @buf: pointer to the start of RX PKT TLV headers 1290 * Return: uint32_t(sgi) 1291 */ 1292 static inline uint32_t 1293 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1294 { 1295 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1296 struct rx_msdu_start *msdu_start = 1297 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1298 uint32_t sgi; 1299 1300 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1301 1302 return sgi; 1303 } 1304 1305 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1306 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1307 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1308 RX_MSDU_START_5_RATE_MCS_MASK, \ 1309 RX_MSDU_START_5_RATE_MCS_LSB)) 1310 /** 1311 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1312 * from rx_msdu_start TLV 1313 * 1314 * @buf: pointer to the start of RX PKT TLV headers 1315 * Return: uint32_t(rate_mcs) 1316 */ 1317 static inline uint32_t 1318 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1319 { 1320 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1321 struct rx_msdu_start *msdu_start = 1322 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1323 uint32_t rate_mcs; 1324 1325 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1326 1327 return rate_mcs; 1328 } 1329 1330 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1331 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1332 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1333 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1334 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1335 1336 /* 1337 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1338 * packet from rx_attention 1339 * 1340 * @buf: pointer to the start of RX PKT TLV header 1341 * Return: uint32_t(decryt status) 1342 */ 1343 1344 static inline uint32_t 1345 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1346 { 1347 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1348 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1349 uint32_t is_decrypt = 0; 1350 uint32_t decrypt_status; 1351 1352 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1353 1354 if (!decrypt_status) 1355 is_decrypt = 1; 1356 1357 return is_decrypt; 1358 } 1359 1360 /* 1361 * Get key index from RX_MSDU_END 1362 */ 1363 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1364 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1365 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1366 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1367 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1368 /* 1369 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1370 * from rx_msdu_end 1371 * 1372 * @buf: pointer to the start of RX PKT TLV header 1373 * Return: uint32_t(key id) 1374 */ 1375 1376 static inline uint32_t 1377 hal_rx_msdu_get_keyid(uint8_t *buf) 1378 { 1379 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1380 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1381 uint32_t keyid_octet; 1382 1383 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1384 1385 return keyid_octet & 0x3; 1386 } 1387 1388 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1389 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1390 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1391 RX_MSDU_START_5_USER_RSSI_MASK, \ 1392 RX_MSDU_START_5_USER_RSSI_LSB)) 1393 /* 1394 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1395 * from rx_msdu_start 1396 * 1397 * @buf: pointer to the start of RX PKT TLV header 1398 * Return: uint32_t(rssi) 1399 */ 1400 1401 static inline uint32_t 1402 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1403 { 1404 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1405 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1406 uint32_t rssi; 1407 1408 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1409 1410 return rssi; 1411 1412 } 1413 1414 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1415 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1416 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1417 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1418 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1419 1420 /* 1421 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1422 * from rx_msdu_start 1423 * 1424 * @buf: pointer to the start of RX PKT TLV header 1425 * Return: uint32_t(frequency) 1426 */ 1427 1428 static inline uint32_t 1429 hal_rx_msdu_start_get_freq(uint8_t *buf) 1430 { 1431 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1432 struct rx_msdu_start *msdu_start = 1433 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1434 uint32_t freq; 1435 1436 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1437 1438 return freq; 1439 } 1440 1441 1442 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1443 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1444 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1445 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1446 RX_MSDU_START_5_PKT_TYPE_LSB)) 1447 1448 /* 1449 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1450 * from rx_msdu_start 1451 * 1452 * @buf: pointer to the start of RX PKT TLV header 1453 * Return: uint32_t(pkt type) 1454 */ 1455 1456 static inline uint32_t 1457 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1458 { 1459 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1460 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1461 uint32_t pkt_type; 1462 1463 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1464 1465 return pkt_type; 1466 } 1467 1468 /* 1469 * hal_rx_mpdu_get_tods(): API to get the tods info 1470 * from rx_mpdu_start 1471 * 1472 * @buf: pointer to the start of RX PKT TLV header 1473 * Return: uint32_t(to_ds) 1474 */ 1475 1476 static inline uint32_t 1477 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1478 { 1479 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1480 1481 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1482 } 1483 1484 1485 /* 1486 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1487 * from rx_mpdu_start 1488 * @hal_soc_hdl: hal soc handle 1489 * @buf: pointer to the start of RX PKT TLV header 1490 * 1491 * Return: uint32_t(fr_ds) 1492 */ 1493 static inline uint32_t 1494 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1495 { 1496 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1497 1498 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1499 } 1500 1501 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1502 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1503 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1504 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1505 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1506 1507 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1508 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1509 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1510 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1511 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1512 1513 /* 1514 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1515 * @hal_soc_hdl: hal soc handle 1516 * @buf: pointer to the start of RX PKT TLV headera 1517 * @mac_addr: pointer to mac address 1518 * 1519 * Return: success/failure 1520 */ 1521 static inline 1522 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1523 uint8_t *buf, uint8_t *mac_addr) 1524 { 1525 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1526 1527 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1528 } 1529 1530 /* 1531 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1532 * in the packet 1533 * @hal_soc_hdl: hal soc handle 1534 * @buf: pointer to the start of RX PKT TLV header 1535 * @mac_addr: pointer to mac address 1536 * 1537 * Return: success/failure 1538 */ 1539 static inline 1540 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1541 uint8_t *buf, uint8_t *mac_addr) 1542 { 1543 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1544 1545 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1546 } 1547 1548 /* 1549 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1550 * in the packet 1551 * @hal_soc_hdl: hal soc handle 1552 * @buf: pointer to the start of RX PKT TLV header 1553 * @mac_addr: pointer to mac address 1554 * 1555 * Return: success/failure 1556 */ 1557 static inline 1558 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1559 uint8_t *buf, uint8_t *mac_addr) 1560 { 1561 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1562 1563 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1564 } 1565 1566 /* 1567 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1568 * in the packet 1569 * @hal_soc_hdl: hal_soc handle 1570 * @buf: pointer to the start of RX PKT TLV header 1571 * @mac_addr: pointer to mac address 1572 * Return: success/failure 1573 */ 1574 static inline 1575 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1576 uint8_t *buf, uint8_t *mac_addr) 1577 { 1578 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1579 1580 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1581 } 1582 1583 /** 1584 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1585 * from rx_msdu_end TLV 1586 * 1587 * @ buf: pointer to the start of RX PKT TLV headers 1588 * Return: da index 1589 */ 1590 static inline uint16_t 1591 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1592 { 1593 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1594 1595 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1596 } 1597 1598 /** 1599 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1600 * from rx_msdu_end TLV 1601 * @hal_soc_hdl: hal soc handle 1602 * @ buf: pointer to the start of RX PKT TLV headers 1603 * 1604 * Return: da_is_valid 1605 */ 1606 static inline uint8_t 1607 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1608 uint8_t *buf) 1609 { 1610 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1611 1612 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1613 } 1614 1615 /** 1616 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1617 * from rx_msdu_end TLV 1618 * 1619 * @buf: pointer to the start of RX PKT TLV headers 1620 * 1621 * Return: da_is_mcbc 1622 */ 1623 static inline uint8_t 1624 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1625 { 1626 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1627 1628 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1629 } 1630 1631 /** 1632 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1633 * from rx_msdu_end TLV 1634 * @hal_soc_hdl: hal soc handle 1635 * @buf: pointer to the start of RX PKT TLV headers 1636 * 1637 * Return: first_msdu 1638 */ 1639 static inline uint8_t 1640 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1641 uint8_t *buf) 1642 { 1643 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1644 1645 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1646 } 1647 1648 /** 1649 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1650 * from rx_msdu_end TLV 1651 * @hal_soc_hdl: hal soc handle 1652 * @buf: pointer to the start of RX PKT TLV headers 1653 * 1654 * Return: last_msdu 1655 */ 1656 static inline uint8_t 1657 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1658 uint8_t *buf) 1659 { 1660 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1661 1662 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1663 } 1664 1665 /** 1666 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1667 * from rx_msdu_end TLV 1668 * @buf: pointer to the start of RX PKT TLV headers 1669 * Return: cce_meta_data 1670 */ 1671 static inline uint16_t 1672 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1673 uint8_t *buf) 1674 { 1675 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1676 1677 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1678 } 1679 1680 /******************************************************************************* 1681 * RX ERROR APIS 1682 ******************************************************************************/ 1683 1684 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1685 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1686 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1687 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1688 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1689 1690 /** 1691 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1692 * from rx_mpdu_end TLV 1693 * 1694 * @buf: pointer to the start of RX PKT TLV headers 1695 * Return: uint32_t(decrypt_err) 1696 */ 1697 static inline uint32_t 1698 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1699 { 1700 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1701 struct rx_mpdu_end *mpdu_end = 1702 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1703 uint32_t decrypt_err; 1704 1705 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1706 1707 return decrypt_err; 1708 } 1709 1710 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1711 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1712 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1713 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1714 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1715 1716 /** 1717 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1718 * from rx_mpdu_end TLV 1719 * 1720 * @buf: pointer to the start of RX PKT TLV headers 1721 * Return: uint32_t(mic_err) 1722 */ 1723 static inline uint32_t 1724 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1725 { 1726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1727 struct rx_mpdu_end *mpdu_end = 1728 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1729 uint32_t mic_err; 1730 1731 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1732 1733 return mic_err; 1734 } 1735 1736 /******************************************************************************* 1737 * RX REO ERROR APIS 1738 ******************************************************************************/ 1739 1740 #define HAL_RX_NUM_MSDU_DESC 6 1741 #define HAL_RX_MAX_SAVED_RING_DESC 16 1742 1743 /* TODO: rework the structure */ 1744 struct hal_rx_msdu_list { 1745 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1746 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1747 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1748 /* physical address of the msdu */ 1749 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1750 }; 1751 1752 struct hal_buf_info { 1753 uint64_t paddr; 1754 uint32_t sw_cookie; 1755 uint8_t rbm; 1756 }; 1757 1758 /** 1759 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1760 * @msdu_link_ptr - msdu link ptr 1761 * @hal - pointer to hal_soc 1762 * Return - Pointer to rx_msdu_details structure 1763 * 1764 */ 1765 static inline 1766 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1767 struct hal_soc *hal_soc) 1768 { 1769 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1770 } 1771 1772 /** 1773 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1774 * @msdu_details_ptr - Pointer to msdu_details_ptr 1775 * @hal - pointer to hal_soc 1776 * Return - Pointer to rx_msdu_desc_info structure. 1777 * 1778 */ 1779 static inline 1780 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1781 struct hal_soc *hal_soc) 1782 { 1783 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1784 } 1785 1786 /* This special cookie value will be used to indicate FW allocated buffers 1787 * received through RXDMA2SW ring for RXDMA WARs 1788 */ 1789 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1790 1791 /** 1792 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1793 * from the MSDU link descriptor 1794 * 1795 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1796 * MSDU link descriptor (struct rx_msdu_link) 1797 * 1798 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1799 * 1800 * @num_msdus: Number of MSDUs in the MPDU 1801 * 1802 * Return: void 1803 */ 1804 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1805 void *msdu_link_desc, 1806 struct hal_rx_msdu_list *msdu_list, 1807 uint16_t *num_msdus) 1808 { 1809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1810 struct rx_msdu_details *msdu_details; 1811 struct rx_msdu_desc_info *msdu_desc_info; 1812 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1813 int i; 1814 1815 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1816 1817 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1818 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1819 __func__, __LINE__, msdu_link, msdu_details); 1820 1821 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1822 /* num_msdus received in mpdu descriptor may be incorrect 1823 * sometimes due to HW issue. Check msdu buffer address also 1824 */ 1825 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1826 &msdu_details[i].buffer_addr_info_details) == 0) { 1827 /* set the last msdu bit in the prev msdu_desc_info */ 1828 msdu_desc_info = 1829 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1830 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1831 break; 1832 } 1833 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1834 hal_soc); 1835 1836 /* set first MSDU bit or the last MSDU bit */ 1837 if (!i) 1838 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1839 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1840 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1841 1842 msdu_list->msdu_info[i].msdu_flags = 1843 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1844 msdu_list->msdu_info[i].msdu_len = 1845 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1846 msdu_list->sw_cookie[i] = 1847 HAL_RX_BUF_COOKIE_GET( 1848 &msdu_details[i].buffer_addr_info_details); 1849 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1850 &msdu_details[i].buffer_addr_info_details); 1851 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1852 &msdu_details[i].buffer_addr_info_details) | 1853 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1854 &msdu_details[i].buffer_addr_info_details) << 32; 1855 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1856 "[%s][%d] i=%d sw_cookie=%d", 1857 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1858 } 1859 *num_msdus = i; 1860 } 1861 1862 /** 1863 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1864 * destination ring ID from the msdu desc info 1865 * 1866 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1867 * the current descriptor 1868 * 1869 * Return: dst_ind (REO destination ring ID) 1870 */ 1871 static inline uint32_t 1872 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 1873 { 1874 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1875 struct rx_msdu_details *msdu_details; 1876 struct rx_msdu_desc_info *msdu_desc_info; 1877 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1878 uint32_t dst_ind; 1879 1880 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1881 1882 /* The first msdu in the link should exsist */ 1883 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1884 hal_soc); 1885 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1886 return dst_ind; 1887 } 1888 1889 /** 1890 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1891 * cookie from the REO destination ring element 1892 * 1893 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1894 * the current descriptor 1895 * @ buf_info: structure to return the buffer information 1896 * Return: void 1897 */ 1898 static inline 1899 void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc, 1900 struct hal_buf_info *buf_info) 1901 { 1902 struct reo_destination_ring *reo_ring = 1903 (struct reo_destination_ring *)rx_desc; 1904 1905 buf_info->paddr = 1906 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 1907 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 1908 1909 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 1910 } 1911 1912 /** 1913 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 1914 * 1915 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 1916 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 1917 * descriptor 1918 */ 1919 enum hal_rx_reo_buf_type { 1920 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 1921 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 1922 }; 1923 1924 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 1925 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 1926 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 1927 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 1928 1929 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 1930 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 1931 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 1932 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 1933 1934 /** 1935 * enum hal_reo_error_code: Error code describing the type of error detected 1936 * 1937 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 1938 * REO_ENTRANCE ring is set to 0 1939 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 1940 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 1941 * having been setup 1942 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 1943 * Retry bit set: duplicate frame 1944 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 1945 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 1946 * received with 2K jump in SN 1947 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 1948 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 1949 * with SN falling within the OOR window 1950 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 1951 * OOR window 1952 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 1953 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 1954 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 1955 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1956 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 1957 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1958 * of the pn_error_detected_flag been set in the REO Queue descriptor 1959 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 1960 * the queue descriptor(address) being blocked as SW/FW seems to be currently 1961 * in the process of making updates to this descriptor 1962 */ 1963 enum hal_reo_error_code { 1964 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 1965 HAL_REO_ERR_QUEUE_DESC_INVALID, 1966 HAL_REO_ERR_AMPDU_IN_NON_BA, 1967 HAL_REO_ERR_NON_BA_DUPLICATE, 1968 HAL_REO_ERR_BA_DUPLICATE, 1969 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 1970 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 1971 HAL_REO_ERR_REGULAR_FRAME_OOR, 1972 HAL_REO_ERR_BAR_FRAME_OOR, 1973 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 1974 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 1975 HAL_REO_ERR_PN_CHECK_FAILED, 1976 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 1977 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 1978 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 1979 HAL_REO_ERR_MAX 1980 }; 1981 1982 /** 1983 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 1984 * 1985 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 1986 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 1987 * overflow 1988 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 1989 * incomplete 1990 * MPDU from the PHY 1991 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 1992 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 1993 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 1994 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 1995 * encrypted but wasn’t 1996 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 1997 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 1998 * the max allowed 1999 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2000 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2001 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2002 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2003 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2004 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2005 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2006 */ 2007 enum hal_rxdma_error_code { 2008 HAL_RXDMA_ERR_OVERFLOW = 0, 2009 HAL_RXDMA_ERR_MPDU_LENGTH, 2010 HAL_RXDMA_ERR_FCS, 2011 HAL_RXDMA_ERR_DECRYPT, 2012 HAL_RXDMA_ERR_TKIP_MIC, 2013 HAL_RXDMA_ERR_UNENCRYPTED, 2014 HAL_RXDMA_ERR_MSDU_LEN, 2015 HAL_RXDMA_ERR_MSDU_LIMIT, 2016 HAL_RXDMA_ERR_WIFI_PARSE, 2017 HAL_RXDMA_ERR_AMSDU_PARSE, 2018 HAL_RXDMA_ERR_SA_TIMEOUT, 2019 HAL_RXDMA_ERR_DA_TIMEOUT, 2020 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2021 HAL_RXDMA_ERR_FLUSH_REQUEST, 2022 HAL_RXDMA_ERR_WAR = 31, 2023 HAL_RXDMA_ERR_MAX 2024 }; 2025 2026 /** 2027 * HW BM action settings in WBM release ring 2028 */ 2029 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2030 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2031 2032 /** 2033 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2034 * release of this buffer or descriptor 2035 * 2036 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2037 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2038 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2039 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2040 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2041 */ 2042 enum hal_rx_wbm_error_source { 2043 HAL_RX_WBM_ERR_SRC_TQM = 0, 2044 HAL_RX_WBM_ERR_SRC_RXDMA, 2045 HAL_RX_WBM_ERR_SRC_REO, 2046 HAL_RX_WBM_ERR_SRC_FW, 2047 HAL_RX_WBM_ERR_SRC_SW, 2048 }; 2049 2050 /** 2051 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2052 * released 2053 * 2054 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2055 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2056 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2057 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2058 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2059 */ 2060 enum hal_rx_wbm_buf_type { 2061 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2062 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2063 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2064 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2065 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2066 }; 2067 2068 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2069 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2070 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2071 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2072 2073 /** 2074 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2075 * PN check failure 2076 * 2077 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2078 * 2079 * Return: true: error caused by PN check, false: other error 2080 */ 2081 static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc) 2082 { 2083 struct reo_destination_ring *reo_desc = 2084 (struct reo_destination_ring *)rx_desc; 2085 2086 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2087 HAL_REO_ERR_PN_CHECK_FAILED) | 2088 (HAL_RX_REO_ERROR_GET(reo_desc) == 2089 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2090 true : false; 2091 } 2092 2093 /** 2094 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2095 * the sequence number 2096 * 2097 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2098 * 2099 * Return: true: error caused by 2K jump, false: other error 2100 */ 2101 static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc) 2102 { 2103 struct reo_destination_ring *reo_desc = 2104 (struct reo_destination_ring *)rx_desc; 2105 2106 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2107 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2108 (HAL_RX_REO_ERROR_GET(reo_desc) == 2109 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2110 true : false; 2111 } 2112 2113 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 2114 /** 2115 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 2116 * @hal_desc: hardware descriptor pointer 2117 * 2118 * This function will print wbm release descriptor 2119 * 2120 * Return: none 2121 */ 2122 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 2123 { 2124 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 2125 uint32_t i; 2126 2127 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2128 "Current Rx wbm release descriptor is"); 2129 2130 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 2131 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2132 "DWORD[i] = 0x%x", wbm_comp[i]); 2133 } 2134 } 2135 2136 /** 2137 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2138 * 2139 * @ hal_soc_hdl : HAL version of the SOC pointer 2140 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2141 * @ buf_addr_info : void pointer to the buffer_addr_info 2142 * @ bm_action : put in IDLE list or release to MSDU_LIST 2143 * 2144 * Return: void 2145 */ 2146 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2147 static inline 2148 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 2149 void *src_srng_desc, 2150 hal_buff_addrinfo_t buf_addr_info, 2151 uint8_t bm_action) 2152 { 2153 struct wbm_release_ring *wbm_rel_srng = 2154 (struct wbm_release_ring *)src_srng_desc; 2155 uint32_t addr_31_0; 2156 uint8_t addr_39_32; 2157 2158 /* Structure copy !!! */ 2159 wbm_rel_srng->released_buff_or_desc_addr_info = 2160 *((struct buffer_addr_info *)buf_addr_info); 2161 2162 addr_31_0 = 2163 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 2164 addr_39_32 = 2165 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 2166 2167 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2168 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2169 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2170 bm_action); 2171 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2172 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2173 2174 /* WBM error is indicated when any of the link descriptors given to 2175 * WBM has a NULL address, and one those paths is the link descriptors 2176 * released from host after processing RXDMA errors, 2177 * or from Rx defrag path, and we want to add an assert here to ensure 2178 * host is not releasing descriptors with NULL address. 2179 */ 2180 2181 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 2182 hal_dump_wbm_rel_desc(src_srng_desc); 2183 qdf_assert_always(0); 2184 } 2185 } 2186 2187 /* 2188 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2189 * REO entrance ring 2190 * 2191 * @ soc: HAL version of the SOC pointer 2192 * @ pa: Physical address of the MSDU Link Descriptor 2193 * @ cookie: SW cookie to get to the virtual address 2194 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2195 * to the error enabled REO queue 2196 * 2197 * Return: void 2198 */ 2199 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2200 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2201 { 2202 /* TODO */ 2203 } 2204 2205 /** 2206 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2207 * BUFFER_ADDR_INFO, give the RX descriptor 2208 * (Assumption -- BUFFER_ADDR_INFO is the 2209 * first field in the descriptor structure) 2210 */ 2211 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 2212 ((hal_link_desc_t)(ring_desc)) 2213 2214 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2215 2216 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2217 2218 /** 2219 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2220 * from the BUFFER_ADDR_INFO structure 2221 * given a REO destination ring descriptor. 2222 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2223 * 2224 * Return: uint8_t (value of the return_buffer_manager) 2225 */ 2226 static inline 2227 uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc) 2228 { 2229 /* 2230 * The following macro takes buf_addr_info as argument, 2231 * but since buf_addr_info is the first field in ring_desc 2232 * Hence the following call is OK 2233 */ 2234 return HAL_RX_BUF_RBM_GET(ring_desc); 2235 } 2236 2237 2238 /******************************************************************************* 2239 * RX WBM ERROR APIS 2240 ******************************************************************************/ 2241 2242 2243 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2244 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2245 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2246 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2247 2248 /** 2249 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2250 * the frame to this release ring 2251 * 2252 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2253 * frame to this queue 2254 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2255 * received routing instructions. No error within REO was detected 2256 */ 2257 enum hal_rx_wbm_reo_push_reason { 2258 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2259 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2260 }; 2261 2262 2263 /** 2264 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2265 * this release ring 2266 * 2267 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2268 * this frame to this queue 2269 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2270 * per received routing instructions. No error within RXDMA was detected 2271 */ 2272 enum hal_rx_wbm_rxdma_push_reason { 2273 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2274 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2275 }; 2276 2277 2278 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2279 (((*(((uint32_t *) wbm_desc) + \ 2280 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2281 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2282 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2283 2284 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2285 (((*(((uint32_t *) wbm_desc) + \ 2286 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2287 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2288 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2289 2290 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2291 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2292 wbm_desc)->released_buff_or_desc_addr_info) 2293 2294 /** 2295 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2296 * humman readable format. 2297 * @ rx_attn: pointer the rx_attention TLV in pkt. 2298 * @ dbg_level: log level. 2299 * 2300 * Return: void 2301 */ 2302 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2303 uint8_t dbg_level) 2304 { 2305 hal_verbose_debug( 2306 "rx_attention tlv (1/2) - " 2307 "rxpcu_mpdu_filter_in_category: %x " 2308 "sw_frame_group_id: %x " 2309 "reserved_0: %x " 2310 "phy_ppdu_id: %x " 2311 "first_mpdu : %x " 2312 "reserved_1a: %x " 2313 "mcast_bcast: %x " 2314 "ast_index_not_found: %x " 2315 "ast_index_timeout: %x " 2316 "power_mgmt: %x " 2317 "non_qos: %x " 2318 "null_data: %x " 2319 "mgmt_type: %x " 2320 "ctrl_type: %x " 2321 "more_data: %x " 2322 "eosp: %x " 2323 "a_msdu_error: %x " 2324 "fragment_flag: %x " 2325 "order: %x " 2326 "cce_match: %x " 2327 "overflow_err: %x " 2328 "msdu_length_err: %x " 2329 "tcp_udp_chksum_fail: %x " 2330 "ip_chksum_fail: %x " 2331 "sa_idx_invalid: %x " 2332 "da_idx_invalid: %x " 2333 "reserved_1b: %x " 2334 "rx_in_tx_decrypt_byp: %x ", 2335 rx_attn->rxpcu_mpdu_filter_in_category, 2336 rx_attn->sw_frame_group_id, 2337 rx_attn->reserved_0, 2338 rx_attn->phy_ppdu_id, 2339 rx_attn->first_mpdu, 2340 rx_attn->reserved_1a, 2341 rx_attn->mcast_bcast, 2342 rx_attn->ast_index_not_found, 2343 rx_attn->ast_index_timeout, 2344 rx_attn->power_mgmt, 2345 rx_attn->non_qos, 2346 rx_attn->null_data, 2347 rx_attn->mgmt_type, 2348 rx_attn->ctrl_type, 2349 rx_attn->more_data, 2350 rx_attn->eosp, 2351 rx_attn->a_msdu_error, 2352 rx_attn->fragment_flag, 2353 rx_attn->order, 2354 rx_attn->cce_match, 2355 rx_attn->overflow_err, 2356 rx_attn->msdu_length_err, 2357 rx_attn->tcp_udp_chksum_fail, 2358 rx_attn->ip_chksum_fail, 2359 rx_attn->sa_idx_invalid, 2360 rx_attn->da_idx_invalid, 2361 rx_attn->reserved_1b, 2362 rx_attn->rx_in_tx_decrypt_byp); 2363 2364 hal_verbose_debug( 2365 "rx_attention tlv (2/2) - " 2366 "encrypt_required: %x " 2367 "directed: %x " 2368 "buffer_fragment: %x " 2369 "mpdu_length_err: %x " 2370 "tkip_mic_err: %x " 2371 "decrypt_err: %x " 2372 "unencrypted_frame_err: %x " 2373 "fcs_err: %x " 2374 "flow_idx_timeout: %x " 2375 "flow_idx_invalid: %x " 2376 "wifi_parser_error: %x " 2377 "amsdu_parser_error: %x " 2378 "sa_idx_timeout: %x " 2379 "da_idx_timeout: %x " 2380 "msdu_limit_error: %x " 2381 "da_is_valid: %x " 2382 "da_is_mcbc: %x " 2383 "sa_is_valid: %x " 2384 "decrypt_status_code: %x " 2385 "rx_bitmap_not_updated: %x " 2386 "reserved_2: %x " 2387 "msdu_done: %x ", 2388 rx_attn->encrypt_required, 2389 rx_attn->directed, 2390 rx_attn->buffer_fragment, 2391 rx_attn->mpdu_length_err, 2392 rx_attn->tkip_mic_err, 2393 rx_attn->decrypt_err, 2394 rx_attn->unencrypted_frame_err, 2395 rx_attn->fcs_err, 2396 rx_attn->flow_idx_timeout, 2397 rx_attn->flow_idx_invalid, 2398 rx_attn->wifi_parser_error, 2399 rx_attn->amsdu_parser_error, 2400 rx_attn->sa_idx_timeout, 2401 rx_attn->da_idx_timeout, 2402 rx_attn->msdu_limit_error, 2403 rx_attn->da_is_valid, 2404 rx_attn->da_is_mcbc, 2405 rx_attn->sa_is_valid, 2406 rx_attn->decrypt_status_code, 2407 rx_attn->rx_bitmap_not_updated, 2408 rx_attn->reserved_2, 2409 rx_attn->msdu_done); 2410 } 2411 2412 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2413 uint8_t dbg_level, 2414 struct hal_soc *hal) 2415 { 2416 2417 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2418 } 2419 /** 2420 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2421 * human readable format. 2422 * @ msdu_end: pointer the msdu_end TLV in pkt. 2423 * @ dbg_level: log level. 2424 * 2425 * Return: void 2426 */ 2427 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2428 struct rx_msdu_end *msdu_end, 2429 uint8_t dbg_level) 2430 { 2431 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2432 } 2433 2434 /** 2435 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2436 * human readable format. 2437 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2438 * @ dbg_level: log level. 2439 * 2440 * Return: void 2441 */ 2442 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2443 uint8_t dbg_level) 2444 { 2445 hal_verbose_debug( 2446 "rx_mpdu_end tlv - " 2447 "rxpcu_mpdu_filter_in_category: %x " 2448 "sw_frame_group_id: %x " 2449 "phy_ppdu_id: %x " 2450 "unsup_ktype_short_frame: %x " 2451 "rx_in_tx_decrypt_byp: %x " 2452 "overflow_err: %x " 2453 "mpdu_length_err: %x " 2454 "tkip_mic_err: %x " 2455 "decrypt_err: %x " 2456 "unencrypted_frame_err: %x " 2457 "pn_fields_contain_valid_info: %x " 2458 "fcs_err: %x " 2459 "msdu_length_err: %x " 2460 "rxdma0_destination_ring: %x " 2461 "rxdma1_destination_ring: %x " 2462 "decrypt_status_code: %x " 2463 "rx_bitmap_not_updated: %x ", 2464 mpdu_end->rxpcu_mpdu_filter_in_category, 2465 mpdu_end->sw_frame_group_id, 2466 mpdu_end->phy_ppdu_id, 2467 mpdu_end->unsup_ktype_short_frame, 2468 mpdu_end->rx_in_tx_decrypt_byp, 2469 mpdu_end->overflow_err, 2470 mpdu_end->mpdu_length_err, 2471 mpdu_end->tkip_mic_err, 2472 mpdu_end->decrypt_err, 2473 mpdu_end->unencrypted_frame_err, 2474 mpdu_end->pn_fields_contain_valid_info, 2475 mpdu_end->fcs_err, 2476 mpdu_end->msdu_length_err, 2477 mpdu_end->rxdma0_destination_ring, 2478 mpdu_end->rxdma1_destination_ring, 2479 mpdu_end->decrypt_status_code, 2480 mpdu_end->rx_bitmap_not_updated); 2481 } 2482 2483 #ifdef NO_RX_PKT_HDR_TLV 2484 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2485 uint8_t dbg_level) 2486 { 2487 } 2488 #else 2489 /** 2490 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2491 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2492 * @ dbg_level: log level. 2493 * 2494 * Return: void 2495 */ 2496 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2497 uint8_t dbg_level) 2498 { 2499 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2500 2501 hal_verbose_debug( 2502 "\n---------------\n" 2503 "rx_pkt_hdr_tlv \n" 2504 "---------------\n" 2505 "phy_ppdu_id %d ", 2506 pkt_hdr_tlv->phy_ppdu_id); 2507 2508 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2509 } 2510 #endif 2511 2512 /** 2513 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2514 * structure 2515 * @hal_ring: pointer to hal_srng structure 2516 * 2517 * Return: ring_id 2518 */ 2519 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 2520 { 2521 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 2522 } 2523 2524 /* Rx MSDU link pointer info */ 2525 struct hal_rx_msdu_link_ptr_info { 2526 struct rx_msdu_link msdu_link; 2527 struct hal_buf_info msdu_link_buf_info; 2528 }; 2529 2530 /** 2531 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2532 * 2533 * @nbuf: Pointer to data buffer field 2534 * Returns: pointer to rx_pkt_tlvs 2535 */ 2536 static inline 2537 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2538 { 2539 return (struct rx_pkt_tlvs *)rx_buf_start; 2540 } 2541 2542 /** 2543 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2544 * 2545 * @pkt_tlvs: Pointer to pkt_tlvs 2546 * Returns: pointer to rx_mpdu_info structure 2547 */ 2548 static inline 2549 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2550 { 2551 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2552 } 2553 2554 #define DOT11_SEQ_FRAG_MASK 0x000f 2555 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2556 2557 /** 2558 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2559 * 2560 * @nbuf: Network buffer 2561 * Returns: rx fragment number 2562 */ 2563 static inline 2564 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 2565 uint8_t *buf) 2566 { 2567 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 2568 } 2569 2570 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2571 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2572 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2573 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2574 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2575 /** 2576 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2577 * 2578 * @nbuf: Network buffer 2579 * Returns: rx more fragment bit 2580 */ 2581 static inline 2582 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2583 { 2584 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2585 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2586 uint16_t frame_ctrl = 0; 2587 2588 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2589 DOT11_FC1_MORE_FRAG_OFFSET; 2590 2591 /* more fragment bit if at offset bit 4 */ 2592 return frame_ctrl; 2593 } 2594 2595 /** 2596 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2597 * 2598 * @nbuf: Network buffer 2599 * Returns: rx more fragment bit 2600 * 2601 */ 2602 static inline 2603 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2604 { 2605 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2606 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2607 uint16_t frame_ctrl = 0; 2608 2609 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2610 2611 return frame_ctrl; 2612 } 2613 2614 /* 2615 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2616 * 2617 * @nbuf: Network buffer 2618 * Returns: flag to indicate whether the nbuf has MC/BC address 2619 */ 2620 static inline 2621 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2622 { 2623 uint8 *buf = qdf_nbuf_data(nbuf); 2624 2625 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2626 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2627 2628 return rx_attn->mcast_bcast; 2629 } 2630 2631 /* 2632 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2633 * @hal_soc_hdl: hal soc handle 2634 * @nbuf: Network buffer 2635 * 2636 * Return: value of sequence control valid field 2637 */ 2638 static inline 2639 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 2640 uint8_t *buf) 2641 { 2642 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2643 2644 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 2645 } 2646 2647 /* 2648 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2649 * @hal_soc_hdl: hal soc handle 2650 * @nbuf: Network buffer 2651 * 2652 * Returns: value of frame control valid field 2653 */ 2654 static inline 2655 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 2656 uint8_t *buf) 2657 { 2658 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2659 2660 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 2661 } 2662 2663 /** 2664 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2665 * @hal_soc_hdl: hal soc handle 2666 * @nbuf: Network buffer 2667 * Returns: value of mpdu 4th address valid field 2668 */ 2669 static inline 2670 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 2671 uint8_t *buf) 2672 { 2673 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2674 2675 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 2676 } 2677 2678 /* 2679 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2680 * 2681 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2682 * Returns: None 2683 */ 2684 static inline 2685 void hal_rx_clear_mpdu_desc_info( 2686 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2687 { 2688 qdf_mem_zero(rx_mpdu_desc_info, 2689 sizeof(*rx_mpdu_desc_info)); 2690 } 2691 2692 /* 2693 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2694 * 2695 * @msdu_link_ptr: HAL view of msdu link ptr 2696 * @size: number of msdu link pointers 2697 * Returns: None 2698 */ 2699 static inline 2700 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2701 int size) 2702 { 2703 qdf_mem_zero(msdu_link_ptr, 2704 (sizeof(*msdu_link_ptr) * size)); 2705 } 2706 2707 /* 2708 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2709 * @msdu_link_ptr: msdu link pointer 2710 * @mpdu_desc_info: mpdu descriptor info 2711 * 2712 * Build a list of msdus using msdu link pointer. If the 2713 * number of msdus are more, chain them together 2714 * 2715 * Returns: Number of processed msdus 2716 */ 2717 static inline 2718 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2719 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2720 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2721 { 2722 int j; 2723 struct rx_msdu_link *msdu_link_ptr = 2724 &msdu_link_ptr_info->msdu_link; 2725 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2726 struct rx_msdu_details *msdu_details = 2727 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2728 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2729 struct rx_msdu_desc_info *msdu_desc_info; 2730 uint8_t fragno, more_frag; 2731 uint8_t *rx_desc_info; 2732 struct hal_rx_msdu_list msdu_list; 2733 2734 for (j = 0; j < num_msdus; j++) { 2735 msdu_desc_info = 2736 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2737 hal_soc); 2738 msdu_list.msdu_info[j].msdu_flags = 2739 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2740 msdu_list.msdu_info[j].msdu_len = 2741 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2742 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2743 &msdu_details[j].buffer_addr_info_details); 2744 } 2745 2746 /* Chain msdu links together */ 2747 if (prev_msdu_link_ptr) { 2748 /* 31-0 bits of the physical address */ 2749 prev_msdu_link_ptr-> 2750 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2751 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2752 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2753 /* 39-32 bits of the physical address */ 2754 prev_msdu_link_ptr-> 2755 next_msdu_link_desc_addr_info.buffer_addr_39_32 2756 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2757 >> 32) & 2758 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2759 prev_msdu_link_ptr-> 2760 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2761 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2762 } 2763 2764 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2765 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2766 /* mark first and last MSDUs */ 2767 rx_desc_info = qdf_nbuf_data(msdu); 2768 fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info); 2769 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2770 2771 /* TODO: create skb->fragslist[] */ 2772 2773 if (more_frag == 0) { 2774 msdu_list.msdu_info[num_msdus].msdu_flags |= 2775 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2776 } else if (fragno == 1) { 2777 msdu_list.msdu_info[num_msdus].msdu_flags |= 2778 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2779 2780 msdu_list.msdu_info[num_msdus].msdu_flags |= 2781 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2782 } 2783 2784 num_msdus++; 2785 2786 /* Number of MSDUs per mpdu descriptor is updated */ 2787 mpdu_desc_info->msdu_count += num_msdus; 2788 } else { 2789 num_msdus = 0; 2790 prev_msdu_link_ptr = msdu_link_ptr; 2791 } 2792 2793 return num_msdus; 2794 } 2795 2796 /* 2797 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2798 * 2799 * @ring_desc: HAL view of ring descriptor 2800 * @mpdu_des_info: saved mpdu desc info 2801 * @msdu_link_ptr: saved msdu link ptr 2802 * 2803 * API used explicitly for rx defrag to update ring desc with 2804 * mpdu desc info and msdu link ptr before reinjecting the 2805 * packet back to REO 2806 * 2807 * Returns: None 2808 */ 2809 static inline 2810 void hal_rx_defrag_update_src_ring_desc( 2811 hal_ring_desc_t ring_desc, 2812 void *saved_mpdu_desc_info, 2813 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 2814 { 2815 struct reo_entrance_ring *reo_ent_ring; 2816 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 2817 struct hal_buf_info buf_info; 2818 2819 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 2820 reo_ring_mpdu_desc_info = &reo_ent_ring-> 2821 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 2822 2823 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 2824 sizeof(*reo_ring_mpdu_desc_info)); 2825 2826 /* 2827 * TODO: Check for additional fields that need configuration in 2828 * reo_ring_mpdu_desc_info 2829 */ 2830 2831 /* Update msdu_link_ptr in the reo entrance ring */ 2832 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 2833 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 2834 buf_info.sw_cookie = 2835 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 2836 } 2837 2838 /* 2839 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 2840 * 2841 * @msdu_link_desc_va: msdu link descriptor handle 2842 * @msdu_link_ptr_info: HAL view of msdu link pointer info 2843 * 2844 * API used to save msdu link information along with physical 2845 * address. The API also copues the sw cookie. 2846 * 2847 * Returns: None 2848 */ 2849 static inline 2850 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 2851 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2852 struct hal_buf_info *hbi) 2853 { 2854 struct rx_msdu_link *msdu_link_ptr = 2855 (struct rx_msdu_link *)msdu_link_desc_va; 2856 2857 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 2858 sizeof(struct rx_msdu_link)); 2859 2860 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 2861 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 2862 } 2863 2864 /* 2865 * hal_rx_get_desc_len(): Returns rx descriptor length 2866 * 2867 * Returns the size of rx_pkt_tlvs which follows the 2868 * data in the nbuf 2869 * 2870 * Returns: Length of rx descriptor 2871 */ 2872 static inline 2873 uint16_t hal_rx_get_desc_len(void) 2874 { 2875 return SIZE_OF_DATA_RX_TLV; 2876 } 2877 2878 /* 2879 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 2880 * reo_entrance_ring descriptor 2881 * 2882 * @reo_ent_desc: reo_entrance_ring descriptor 2883 * Returns: value of rxdma_push_reason 2884 */ 2885 static inline 2886 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 2887 { 2888 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2889 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 2890 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 2891 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 2892 } 2893 2894 /** 2895 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 2896 * reo_entrance_ring descriptor 2897 * @reo_ent_desc: reo_entrance_ring descriptor 2898 * Return: value of rxdma_error_code 2899 */ 2900 static inline 2901 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 2902 { 2903 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2904 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 2905 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 2906 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 2907 } 2908 2909 /** 2910 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 2911 * save it to hal_wbm_err_desc_info structure passed by caller 2912 * @wbm_desc: wbm ring descriptor 2913 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2914 * Return: void 2915 */ 2916 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 2917 struct hal_wbm_err_desc_info *wbm_er_info, 2918 hal_soc_handle_t hal_soc_hdl) 2919 { 2920 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2921 2922 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 2923 } 2924 2925 /** 2926 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 2927 * the reserved bytes of rx_tlv_hdr 2928 * @buf: start of rx_tlv_hdr 2929 * @wbm_er_info: hal_wbm_err_desc_info structure 2930 * Return: void 2931 */ 2932 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 2933 struct hal_wbm_err_desc_info *wbm_er_info) 2934 { 2935 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2936 2937 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 2938 sizeof(struct hal_wbm_err_desc_info)); 2939 } 2940 2941 /** 2942 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 2943 * the reserved bytes of rx_tlv_hdr. 2944 * @buf: start of rx_tlv_hdr 2945 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2946 * Return: void 2947 */ 2948 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 2949 struct hal_wbm_err_desc_info *wbm_er_info) 2950 { 2951 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2952 2953 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 2954 sizeof(struct hal_wbm_err_desc_info)); 2955 } 2956 2957 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 2958 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 2959 RX_MSDU_START_5_NSS_OFFSET)), \ 2960 RX_MSDU_START_5_NSS_MASK, \ 2961 RX_MSDU_START_5_NSS_LSB)) 2962 2963 /** 2964 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 2965 * 2966 * @ hal_soc: HAL version of the SOC pointer 2967 * @ hw_desc_addr: Start address of Rx HW TLVs 2968 * @ rs: Status for monitor mode 2969 * 2970 * Return: void 2971 */ 2972 static inline 2973 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 2974 void *hw_desc_addr, 2975 struct mon_rx_status *rs) 2976 { 2977 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2978 2979 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 2980 } 2981 2982 /* 2983 * hal_rx_get_tlv(): API to get the tlv 2984 * 2985 * @hal_soc: HAL version of the SOC pointer 2986 * @rx_tlv: TLV data extracted from the rx packet 2987 * Return: uint8_t 2988 */ 2989 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 2990 { 2991 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 2992 } 2993 2994 /* 2995 * hal_rx_msdu_start_nss_get(): API to get the NSS 2996 * Interval from rx_msdu_start 2997 * 2998 * @hal_soc: HAL version of the SOC pointer 2999 * @buf: pointer to the start of RX PKT TLV header 3000 * Return: uint32_t(nss) 3001 */ 3002 static inline 3003 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3004 { 3005 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3006 3007 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3008 } 3009 3010 /** 3011 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3012 * human readable format. 3013 * @ msdu_start: pointer the msdu_start TLV in pkt. 3014 * @ dbg_level: log level. 3015 * 3016 * Return: void 3017 */ 3018 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3019 struct rx_msdu_start *msdu_start, 3020 uint8_t dbg_level) 3021 { 3022 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3023 } 3024 3025 /** 3026 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3027 * info details 3028 * 3029 * @ buf - Pointer to buffer containing rx pkt tlvs. 3030 * 3031 * 3032 */ 3033 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 3034 uint8_t *buf) 3035 { 3036 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3037 3038 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3039 } 3040 3041 /* 3042 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3043 * Interval from rx_msdu_start 3044 * 3045 * @buf: pointer to the start of RX PKT TLV header 3046 * Return: uint32_t(reception_type) 3047 */ 3048 static inline 3049 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 3050 uint8_t *buf) 3051 { 3052 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3053 3054 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3055 } 3056 3057 /** 3058 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3059 * RX TLVs 3060 * @ buf: pointer the pkt buffer. 3061 * @ dbg_level: log level. 3062 * 3063 * Return: void 3064 */ 3065 static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 3066 uint8_t *buf, uint8_t dbg_level) 3067 { 3068 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3069 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3070 struct rx_mpdu_start *mpdu_start = 3071 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3072 struct rx_msdu_start *msdu_start = 3073 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3074 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3075 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3076 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3077 3078 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3079 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3080 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3081 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3082 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3083 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3084 } 3085 3086 3087 /** 3088 * hal_reo_status_get_header_generic - Process reo desc info 3089 * @d - Pointer to reo descriptior 3090 * @b - tlv type info 3091 * @h - Pointer to hal_reo_status_header where info to be stored 3092 * @hal- pointer to hal_soc structure 3093 * Return - none. 3094 * 3095 */ 3096 static inline 3097 void hal_reo_status_get_header(uint32_t *d, int b, 3098 void *h, struct hal_soc *hal_soc) 3099 { 3100 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3101 } 3102 3103 /** 3104 * hal_rx_desc_is_first_msdu() - Check if first msdu 3105 * 3106 * @hal_soc_hdl: hal_soc handle 3107 * @hw_desc_addr: hardware descriptor address 3108 * 3109 * Return: 0 - success/ non-zero failure 3110 */ 3111 static inline 3112 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 3113 void *hw_desc_addr) 3114 { 3115 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3116 3117 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 3118 } 3119 3120 static inline 3121 uint32_t 3122 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3123 struct rx_msdu_start *rx_msdu_start; 3124 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3125 3126 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3127 3128 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3129 } 3130 3131 #ifdef NO_RX_PKT_HDR_TLV 3132 static inline 3133 uint8_t * 3134 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3135 uint8_t *rx_pkt_hdr; 3136 struct rx_mon_pkt_tlvs *rx_desc = 3137 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 3138 3139 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3140 3141 return rx_pkt_hdr; 3142 } 3143 #else 3144 static inline 3145 uint8_t * 3146 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3147 uint8_t *rx_pkt_hdr; 3148 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3149 3150 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3151 3152 return rx_pkt_hdr; 3153 } 3154 #endif 3155 3156 static inline 3157 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3158 uint8_t *rx_tlv_hdr) 3159 { 3160 uint8_t decap_format; 3161 3162 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 3163 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3164 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3165 return true; 3166 } 3167 3168 return false; 3169 } 3170 3171 /** 3172 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 3173 * from rx_msdu_end TLV 3174 * @buf: pointer to the start of RX PKT TLV headers 3175 * 3176 * Return: fse metadata value from MSDU END TLV 3177 */ 3178 static inline uint32_t 3179 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 3180 uint8_t *buf) 3181 { 3182 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3183 3184 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 3185 } 3186 3187 /** 3188 * hal_rx_msdu_flow_idx_get: API to get flow index 3189 * from rx_msdu_end TLV 3190 * @buf: pointer to the start of RX PKT TLV headers 3191 * 3192 * Return: flow index value from MSDU END TLV 3193 */ 3194 static inline uint32_t 3195 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 3196 uint8_t *buf) 3197 { 3198 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3199 3200 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 3201 } 3202 3203 /** 3204 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 3205 * from rx_msdu_end TLV 3206 * @buf: pointer to the start of RX PKT TLV headers 3207 * 3208 * Return: flow index timeout value from MSDU END TLV 3209 */ 3210 static inline bool 3211 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 3212 uint8_t *buf) 3213 { 3214 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3215 3216 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 3217 } 3218 3219 /** 3220 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 3221 * from rx_msdu_end TLV 3222 * @buf: pointer to the start of RX PKT TLV headers 3223 * 3224 * Return: flow index invalid value from MSDU END TLV 3225 */ 3226 static inline bool 3227 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 3228 uint8_t *buf) 3229 { 3230 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3231 3232 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 3233 } 3234 3235 /** 3236 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 3237 * @hal_soc_hdl: hal_soc handle 3238 * @hw_desc_addr: hardware descriptor address 3239 * 3240 * Return: 0 - success/ non-zero failure 3241 */ 3242 static inline 3243 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 3244 void *hw_desc_addr) 3245 { 3246 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3247 3248 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(hw_desc_addr); 3249 } 3250 3251 /** 3252 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 3253 * @hal_soc_hdl: hal_soc handle 3254 * @buf: rx tlv address 3255 * 3256 * Return: sw peer id 3257 */ 3258 static inline 3259 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 3260 uint8_t *buf) 3261 { 3262 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3263 3264 if ((!hal_soc) || (!hal_soc->ops)) { 3265 hal_err("hal handle is NULL"); 3266 QDF_BUG(0); 3267 return QDF_STATUS_E_INVAL; 3268 } 3269 3270 if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get) 3271 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 3272 3273 return QDF_STATUS_E_INVAL; 3274 } 3275 3276 static inline 3277 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 3278 void *link_desc_addr) 3279 { 3280 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3281 3282 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 3283 } 3284 3285 static inline 3286 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 3287 void *msdu_addr) 3288 { 3289 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3290 3291 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 3292 } 3293 3294 static inline 3295 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3296 void *hw_addr) 3297 { 3298 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3299 3300 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 3301 } 3302 3303 static inline 3304 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3305 void *hw_addr) 3306 { 3307 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3308 3309 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 3310 } 3311 3312 static inline 3313 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 3314 uint8_t *buf) 3315 { 3316 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3317 3318 return hal_soc->ops->hal_rx_get_fc_valid(buf); 3319 } 3320 3321 static inline 3322 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3323 { 3324 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3325 3326 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 3327 } 3328 3329 static inline 3330 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 3331 uint8_t *buf) 3332 { 3333 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3334 3335 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 3336 } 3337 3338 static inline 3339 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 3340 uint8_t *buf) 3341 { 3342 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3343 3344 return hal_soc->ops->hal_rx_get_filter_category(buf); 3345 } 3346 3347 static inline 3348 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 3349 uint8_t *buf) 3350 { 3351 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3352 3353 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 3354 } 3355 3356 /** 3357 * hal_reo_config(): Set reo config parameters 3358 * @soc: hal soc handle 3359 * @reg_val: value to be set 3360 * @reo_params: reo parameters 3361 * 3362 * Return: void 3363 */ 3364 static inline 3365 void hal_reo_config(struct hal_soc *hal_soc, 3366 uint32_t reg_val, 3367 struct hal_reo_params *reo_params) 3368 { 3369 hal_soc->ops->hal_reo_config(hal_soc, 3370 reg_val, 3371 reo_params); 3372 } 3373 3374 /** 3375 * hal_rx_msdu_get_flow_params: API to get flow index, 3376 * flow index invalid and flow index timeout from rx_msdu_end TLV 3377 * @buf: pointer to the start of RX PKT TLV headers 3378 * @flow_invalid: pointer to return value of flow_idx_valid 3379 * @flow_timeout: pointer to return value of flow_idx_timeout 3380 * @flow_index: pointer to return value of flow_idx 3381 * 3382 * Return: none 3383 */ 3384 static inline void 3385 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 3386 uint8_t *buf, 3387 bool *flow_invalid, 3388 bool *flow_timeout, 3389 uint32_t *flow_index) 3390 { 3391 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3392 3393 if ((!hal_soc) || (!hal_soc->ops)) { 3394 hal_err("hal handle is NULL"); 3395 QDF_BUG(0); 3396 return; 3397 } 3398 3399 if (hal_soc->ops->hal_rx_msdu_get_flow_params) 3400 hal_soc->ops-> 3401 hal_rx_msdu_get_flow_params(buf, 3402 flow_invalid, 3403 flow_timeout, 3404 flow_index); 3405 } 3406 3407 static inline 3408 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 3409 uint8_t *buf) 3410 { 3411 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3412 3413 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 3414 } 3415 3416 static inline 3417 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 3418 uint8_t *buf) 3419 { 3420 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3421 3422 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 3423 } 3424 3425 static inline void 3426 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 3427 void *rx_tlv, 3428 void *ppdu_info) 3429 { 3430 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3431 3432 if (hal_soc->ops->hal_rx_get_bb_info) 3433 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 3434 } 3435 3436 static inline void 3437 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 3438 void *rx_tlv, 3439 void *ppdu_info) 3440 { 3441 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3442 3443 if (hal_soc->ops->hal_rx_get_rtt_info) 3444 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 3445 } 3446 3447 /** 3448 * hal_rx_msdu_metadata_get(): API to get the 3449 * fast path information from rx_msdu_end TLV 3450 * 3451 * @ hal_soc_hdl: DP soc handle 3452 * @ buf: pointer to the start of RX PKT TLV headers 3453 * @ msdu_metadata: Structure to hold msdu end information 3454 * Return: none 3455 */ 3456 static inline void 3457 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 3458 struct hal_rx_msdu_metadata *msdu_md) 3459 { 3460 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3461 3462 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 3463 } 3464 #endif /* _HAL_RX_H */ 3465