1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 #include "hal_rx_hw_defines.h" 24 #include "hal_hw_headers.h" 25 26 /************************************* 27 * Ring desc offset/shift/masks 28 *************************************/ 29 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 30 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 31 #define HAL_RX_LSB(block, field) block##_##field##_LSB 32 #define HAL_RX_MASK(block, field) block##_##field##_MASK 33 34 #define HAL_RX_GET(_ptr, block, field) \ 35 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 36 HAL_RX_MASK(block, field)) >> \ 37 HAL_RX_LSB(block, field)) 38 39 #define HAL_RX_GET_64(_ptr, block, field) \ 40 (((*((volatile uint64_t *)(_ptr) + \ 41 (HAL_RX_OFFSET(block, field) >> 3))) & \ 42 HAL_RX_MASK(block, field)) >> \ 43 HAL_RX_LSB(block, field)) 44 45 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 46 (*(uint32_t *)(((uint8_t *)_ptr) + \ 47 _wrd ## _ ## _field ## _OFFSET) |= \ 48 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 49 _wrd ## _ ## _field ## _MASK)) 50 51 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 52 #ifndef RX_DATA_BUFFER_SIZE 53 #define RX_DATA_BUFFER_SIZE 2048 54 #endif 55 56 #ifndef RX_MONITOR_BUFFER_SIZE 57 #define RX_MONITOR_BUFFER_SIZE 2048 58 #endif 59 60 #define RXDMA_OPTIMIZATION 61 62 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 63 * including buffer reservation, buffer alignment and skb shared info size. 64 */ 65 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 66 #define RX_MON_STATUS_BUF_ALIGN 128 67 #define RX_MON_STATUS_BUF_RESERVATION 128 68 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 69 (RX_MON_STATUS_BUF_RESERVATION + \ 70 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 71 72 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 73 74 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 75 #define HAL_RX_NON_QOS_TID 16 76 77 enum { 78 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 79 HAL_HW_RX_DECAP_FORMAT_NWIFI, 80 HAL_HW_RX_DECAP_FORMAT_ETH2, 81 HAL_HW_RX_DECAP_FORMAT_8023, 82 }; 83 84 /** 85 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 86 * 87 * @reo_psh_rsn: REO push reason 88 * @reo_err_code: REO Error code 89 * @rxdma_psh_rsn: RXDMA push reason 90 * @rxdma_err_code: RXDMA Error code 91 * @reserved_1: Reserved bits 92 * @wbm_err_src: WBM error source 93 * @pool_id: pool ID, indicates which rxdma pool 94 * @reserved_2: Reserved bits 95 */ 96 struct hal_wbm_err_desc_info { 97 uint16_t reo_psh_rsn:2, 98 reo_err_code:5, 99 rxdma_psh_rsn:2, 100 rxdma_err_code:5, 101 reserved_1:2; 102 uint8_t wbm_err_src:3, 103 pool_id:2, 104 msdu_continued:1, 105 reserved_2:2; 106 }; 107 108 /** 109 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 110 * @first_buffer: First buffer of MSDU 111 * @last_buffer: Last buffer of MSDU 112 * @is_decap_raw: Is RAW Frame 113 * @reserved_1: Reserved 114 * 115 * MSDU with continuation: 116 * ----------------------------------------------------------- 117 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 118 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 119 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 120 * ----------------------------------------------------------- 121 * 122 * Single buffer MSDU: 123 * ------------------ 124 * | first_buffer:1 | 125 * | last_buffer :1 | 126 * | is_decap_raw:1/0 | 127 * ------------------ 128 */ 129 struct hal_rx_mon_dest_buf_info { 130 uint8_t first_buffer:1, 131 last_buffer:1, 132 is_decap_raw:1, 133 reserved_1:5; 134 }; 135 136 /** 137 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 138 * 139 * @l3_hdr_pad: l3 header padding 140 * @reserved: Reserved bits 141 * @sa_sw_peer_id: sa sw peer id 142 * @sa_idx: sa index 143 * @da_idx: da index 144 */ 145 struct hal_rx_msdu_metadata { 146 uint32_t l3_hdr_pad:16, 147 sa_sw_peer_id:16; 148 uint32_t sa_idx:16, 149 da_idx:16; 150 }; 151 152 struct hal_proto_params { 153 uint8_t tcp_proto; 154 uint8_t udp_proto; 155 uint8_t ipv6_proto; 156 }; 157 158 /** 159 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 160 * 161 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 162 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 163 */ 164 enum hal_reo_error_status { 165 HAL_REO_ERROR_DETECTED = 0, 166 HAL_REO_ROUTING_INSTRUCTION = 1, 167 }; 168 169 /** 170 * @msdu_flags: [0] first_msdu_in_mpdu 171 * [1] last_msdu_in_mpdu 172 * [2] msdu_continuation - MSDU spread across buffers 173 * [23] sa_is_valid - SA match in peer table 174 * [24] sa_idx_timeout - Timeout while searching for SA match 175 * [25] da_is_valid - Used to identtify intra-bss forwarding 176 * [26] da_is_MCBC 177 * [27] da_idx_timeout - Timeout while searching for DA match 178 * 179 */ 180 struct hal_rx_msdu_desc_info { 181 uint32_t msdu_flags; 182 uint16_t msdu_len; /* 14 bits for length */ 183 }; 184 185 /** 186 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 187 * 188 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 189 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 190 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 191 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 192 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 193 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 194 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 195 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 196 * @ HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 197 */ 198 enum hal_rx_msdu_desc_flags { 199 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 200 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 201 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 202 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 203 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 204 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 205 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 206 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 207 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 208 }; 209 210 /* 211 * @msdu_count: no. of msdus in the MPDU 212 * @mpdu_seq: MPDU sequence number 213 * @mpdu_flags [0] Fragment flag 214 * [1] MPDU_retry_bit 215 * [2] AMPDU flag 216 * [3] raw_ampdu 217 * @peer_meta_data: Upper bits containing peer id, vdev id 218 * @bar_frame: indicates if received frame is a bar frame 219 */ 220 struct hal_rx_mpdu_desc_info { 221 uint16_t msdu_count; 222 uint16_t mpdu_seq; /* 12 bits for length */ 223 uint32_t mpdu_flags; 224 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 225 uint16_t bar_frame; 226 }; 227 228 /** 229 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 230 * 231 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 232 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 233 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 234 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 235 */ 236 enum hal_rx_mpdu_desc_flags { 237 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 238 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 239 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 240 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 241 }; 242 243 /* Return Buffer manager ID */ 244 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 245 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 246 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 247 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 248 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 249 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 250 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 251 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 252 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 253 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 254 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 255 256 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 257 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 258 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 259 260 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 261 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 262 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 263 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 264 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 265 266 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 267 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 268 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 269 270 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 271 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 272 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 273 274 /* 275 * macro to set the LSW of the nbuf data physical address 276 * to the rxdma ring entry 277 */ 278 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 279 ((*(((unsigned int *) buff_addr_info) + \ 280 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 281 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 282 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 283 284 /* 285 * macro to set the LSB of MSW of the nbuf data physical address 286 * to the rxdma ring entry 287 */ 288 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 289 ((*(((unsigned int *) buff_addr_info) + \ 290 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 291 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 292 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 293 294 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 295 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 296 297 /* 298 * macro to get the invalid bit for sw cookie 299 */ 300 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 301 ((*(((unsigned int *)buff_addr_info) + \ 302 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 303 HAL_RX_COOKIE_INVALID_MASK) 304 305 /* 306 * macro to set the invalid bit for sw cookie 307 */ 308 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 309 ((*(((unsigned int *)buff_addr_info) + \ 310 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 311 HAL_RX_COOKIE_INVALID_MASK) 312 313 /* 314 * macro to reset the invalid bit for sw cookie 315 */ 316 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 317 ((*(((unsigned int *)buff_addr_info) + \ 318 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 319 ~HAL_RX_COOKIE_INVALID_MASK) 320 321 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 322 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 323 (((struct reo_destination_ring *) \ 324 reo_desc)->buf_or_link_desc_addr_info))) 325 326 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 327 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 328 (((struct reo_destination_ring *) \ 329 reo_desc)->buf_or_link_desc_addr_info))) 330 331 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 332 333 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 334 ((*(((unsigned int *)buff_addr_info) + \ 335 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 336 HAL_RX_LINK_COOKIE_INVALID_MASK) 337 338 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 339 ((*(((unsigned int *)buff_addr_info) + \ 340 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 341 HAL_RX_LINK_COOKIE_INVALID_MASK) 342 343 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 344 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 345 (((struct reo_destination_ring *) \ 346 reo_desc)->buf_or_link_desc_addr_info))) 347 348 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 349 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 350 (((struct reo_destination_ring *) \ 351 reo_desc)->buf_or_link_desc_addr_info))) 352 #endif 353 354 /* TODO: Convert the following structure fields accesseses to offsets */ 355 356 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 357 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 358 (((struct reo_destination_ring *) \ 359 reo_desc)->buf_or_link_desc_addr_info))) 360 361 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 362 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 363 (((struct reo_destination_ring *) \ 364 reo_desc)->buf_or_link_desc_addr_info))) 365 366 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 367 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 368 (((struct reo_destination_ring *) \ 369 reo_desc)->buf_or_link_desc_addr_info))) 370 371 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 372 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 373 _field, _val) 374 375 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 376 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 377 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 378 379 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 380 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 381 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 382 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 383 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 384 385 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 386 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 387 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 388 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 389 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 390 391 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 392 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 393 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 394 395 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 396 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 397 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 398 399 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 400 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 401 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 402 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 403 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 404 405 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 406 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 407 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 408 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 409 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 410 411 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 412 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 413 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 414 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 415 416 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 417 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 418 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 419 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 420 421 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 422 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 423 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 424 425 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 426 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 427 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 428 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 429 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 430 431 static inline uint32_t 432 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 433 rx_msdu_desc_info_t msdu_desc_info_hdl) 434 { 435 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 436 437 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 438 } 439 440 /* 441 * Structures & Macros to obtain fields from the TLV's in the Rx packet 442 * pre-header. 443 */ 444 445 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 446 void *hw_desc_addr) 447 { 448 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 449 450 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 451 } 452 453 /** 454 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 455 * @hal_soc_hdl: hal soc handle 456 * @desc_addr: ring descriptor 457 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 458 * 459 * Return: None 460 */ 461 static inline void 462 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 463 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 464 { 465 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 466 467 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 468 mpdu_desc_info); 469 } 470 471 #define HAL_RX_NUM_MSDU_DESC 6 472 #define HAL_RX_MAX_SAVED_RING_DESC 16 473 474 /* TODO: rework the structure */ 475 struct hal_rx_msdu_list { 476 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 477 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 478 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 479 /* physical address of the msdu */ 480 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 481 }; 482 483 struct hal_buf_info { 484 uint64_t paddr; 485 uint32_t sw_cookie; 486 uint8_t rbm; 487 }; 488 489 /* This special cookie value will be used to indicate FW allocated buffers 490 * received through RXDMA2SW ring for RXDMA WARs 491 */ 492 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 493 494 /** 495 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 496 * 497 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 498 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 499 * descriptor 500 */ 501 enum hal_rx_reo_buf_type { 502 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 503 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 504 }; 505 506 /** 507 * enum hal_reo_error_code: Error code describing the type of error detected 508 * 509 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 510 * REO_ENTRANCE ring is set to 0 511 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 512 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 513 * having been setup 514 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 515 * Retry bit set: duplicate frame 516 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 517 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 518 * received with 2K jump in SN 519 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 520 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 521 * with SN falling within the OOR window 522 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 523 * OOR window 524 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 525 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 526 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 527 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 528 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 529 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 530 * of the pn_error_detected_flag been set in the REO Queue descriptor 531 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 532 * the queue descriptor(address) being blocked as SW/FW seems to be currently 533 * in the process of making updates to this descriptor 534 */ 535 enum hal_reo_error_code { 536 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 537 HAL_REO_ERR_QUEUE_DESC_INVALID, 538 HAL_REO_ERR_AMPDU_IN_NON_BA, 539 HAL_REO_ERR_NON_BA_DUPLICATE, 540 HAL_REO_ERR_BA_DUPLICATE, 541 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 542 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 543 HAL_REO_ERR_REGULAR_FRAME_OOR, 544 HAL_REO_ERR_BAR_FRAME_OOR, 545 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 546 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 547 HAL_REO_ERR_PN_CHECK_FAILED, 548 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 549 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 550 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 551 HAL_REO_ERR_MAX 552 }; 553 554 /** 555 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 556 * 557 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 558 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 559 * overflow 560 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 561 * incomplete 562 * MPDU from the PHY 563 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 564 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 565 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 566 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 567 * encrypted but wasn’t 568 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 569 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 570 * the max allowed 571 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 572 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 573 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 574 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 575 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 576 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 577 * @ HAL_RXDMA_AMSDU_FRAGMENT : Rx PCU reported A-MSDU 578 * present as well as a fragmented MPDU 579 * @ HAL_RXDMA_MULTICAST_ECHO : RX OLE reported a multicast echo 580 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 581 */ 582 enum hal_rxdma_error_code { 583 HAL_RXDMA_ERR_OVERFLOW = 0, 584 HAL_RXDMA_ERR_MPDU_LENGTH, 585 HAL_RXDMA_ERR_FCS, 586 HAL_RXDMA_ERR_DECRYPT, 587 HAL_RXDMA_ERR_TKIP_MIC, 588 HAL_RXDMA_ERR_UNENCRYPTED, 589 HAL_RXDMA_ERR_MSDU_LEN, 590 HAL_RXDMA_ERR_MSDU_LIMIT, 591 HAL_RXDMA_ERR_WIFI_PARSE, 592 HAL_RXDMA_ERR_AMSDU_PARSE, 593 HAL_RXDMA_ERR_SA_TIMEOUT, 594 HAL_RXDMA_ERR_DA_TIMEOUT, 595 HAL_RXDMA_ERR_FLOW_TIMEOUT, 596 HAL_RXDMA_ERR_FLUSH_REQUEST, 597 HAL_RXDMA_AMSDU_FRAGMENT, 598 HAL_RXDMA_MULTICAST_ECHO, 599 HAL_RXDMA_ERR_WAR = 31, 600 HAL_RXDMA_ERR_MAX 601 }; 602 603 /** 604 * HW BM action settings in WBM release ring 605 */ 606 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 607 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 608 609 /** 610 * enum hal_rx_wbm_error_source: Indicates which module initiated the 611 * release of this buffer or descriptor 612 * 613 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 614 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 615 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 616 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 617 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 618 */ 619 enum hal_rx_wbm_error_source { 620 HAL_RX_WBM_ERR_SRC_TQM = 0, 621 HAL_RX_WBM_ERR_SRC_RXDMA, 622 HAL_RX_WBM_ERR_SRC_REO, 623 HAL_RX_WBM_ERR_SRC_FW, 624 HAL_RX_WBM_ERR_SRC_SW, 625 }; 626 627 /** 628 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 629 * released 630 * 631 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 632 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 633 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 634 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 635 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 636 */ 637 enum hal_rx_wbm_buf_type { 638 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 639 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 640 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 641 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 642 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 643 }; 644 645 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 646 647 //#include "hal_rx_be.h" 648 649 /* 650 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 651 * 652 * @nbuf: Network buffer 653 * Returns: flag to indicate whether the nbuf has MC/BC address 654 */ 655 static inline uint32_t 656 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 657 qdf_nbuf_t nbuf) 658 { 659 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 660 661 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 662 } 663 664 /** 665 * hal_rx_priv_info_set_in_tlv(): Save the private info to 666 * the reserved bytes of rx_tlv_hdr 667 * @buf: start of rx_tlv_hdr 668 * @wbm_er_info: hal_wbm_err_desc_info structure 669 * Return: void 670 */ 671 static inline void 672 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 673 uint8_t *buf, uint8_t *priv_data, 674 uint32_t len) 675 { 676 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 677 678 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 679 priv_data, 680 len); 681 } 682 683 /* 684 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 685 * reo_entrance_ring descriptor 686 * 687 * @reo_ent_desc: reo_entrance_ring descriptor 688 * Returns: value of rxdma_push_reason 689 */ 690 static inline 691 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 692 { 693 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 694 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 695 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 696 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 697 } 698 699 /** 700 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 701 * reo_entrance_ring descriptor 702 * @reo_ent_desc: reo_entrance_ring descriptor 703 * Return: value of rxdma_error_code 704 */ 705 static inline 706 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 707 { 708 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 709 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 710 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 711 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 712 } 713 714 /** 715 * hal_rx_priv_info_get_from_tlv(): retrieve the private data from 716 * the reserved bytes of rx_tlv_hdr. 717 * @buf: start of rx_tlv_hdr 718 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 719 * Return: void 720 */ 721 static inline void 722 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 723 uint8_t *buf, uint8_t *wbm_er_info, 724 uint32_t len) 725 { 726 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 727 728 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 729 wbm_er_info, 730 len); 731 } 732 733 static inline void 734 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 735 uint16_t *rx_mon_pkt_tlv_size) 736 { 737 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 738 739 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 740 rx_mon_pkt_tlv_size); 741 } 742 743 /* 744 * hal_rx_encryption_info_valid(): Returns encryption type. 745 * 746 * @hal_soc_hdl: hal soc handle 747 * @buf: rx_tlv_hdr of the received packet 748 * 749 * Return: encryption type 750 */ 751 static inline uint32_t 752 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 753 { 754 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 755 756 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 757 } 758 759 /* 760 * hal_rx_print_pn: Prints the PN of rx packet. 761 * @hal_soc_hdl: hal soc handle 762 * @buf: rx_tlv_hdr of the received packet 763 * 764 * Return: void 765 */ 766 static inline void 767 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 768 { 769 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 770 771 hal_soc->ops->hal_rx_print_pn(buf); 772 } 773 774 /** 775 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 776 * l3_header padding from rx_msdu_end TLV 777 * 778 * @buf: pointer to the start of RX PKT TLV headers 779 * Return: number of l3 header padding bytes 780 */ 781 static inline uint32_t 782 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 783 uint8_t *buf) 784 { 785 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 786 787 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 788 } 789 790 /** 791 * hal_rx_msdu_end_sa_idx_get(): API to get the 792 * sa_idx from rx_msdu_end TLV 793 * 794 * @ buf: pointer to the start of RX PKT TLV headers 795 * Return: sa_idx (SA AST index) 796 */ 797 static inline uint16_t 798 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 799 uint8_t *buf) 800 { 801 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 802 803 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 804 } 805 806 /** 807 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 808 * sa_is_valid bit from rx_msdu_end TLV 809 * 810 * @ buf: pointer to the start of RX PKT TLV headers 811 * Return: sa_is_valid bit 812 */ 813 static inline uint8_t 814 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 815 uint8_t *buf) 816 { 817 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 818 819 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 820 } 821 822 /** 823 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 824 * from rx_msdu_start TLV 825 * 826 * @buf: pointer to the start of RX PKT TLV headers 827 * @len: msdu length 828 * 829 * Return: none 830 */ 831 static inline void 832 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 833 uint32_t len) 834 { 835 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 836 837 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 838 } 839 840 /** 841 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 842 * 843 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 844 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 845 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 846 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 847 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 848 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 849 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 850 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 851 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 852 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 853 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 854 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 855 */ 856 enum hal_rx_mpdu_info_sw_frame_group_id_type { 857 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 858 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 859 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 860 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 861 HAL_MPDU_SW_FRAME_GROUP_MGMT, 862 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 863 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 864 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 865 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 866 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 867 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 868 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 869 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 870 }; 871 872 /** 873 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 874 * Retrieve qos control valid bit from the tlv. 875 * @hal_soc_hdl: hal_soc handle 876 * @buf: pointer to rx pkt TLV. 877 * 878 * Return: qos control value. 879 */ 880 static inline uint32_t 881 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 882 hal_soc_handle_t hal_soc_hdl, 883 uint8_t *buf) 884 { 885 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 886 887 if ((!hal_soc) || (!hal_soc->ops)) { 888 hal_err("hal handle is NULL"); 889 QDF_BUG(0); 890 return QDF_STATUS_E_INVAL; 891 } 892 893 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 894 return hal_soc->ops-> 895 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 896 897 return QDF_STATUS_E_INVAL; 898 } 899 900 /** 901 * hal_rx_is_unicast: check packet is unicast frame or not. 902 * @hal_soc_hdl: hal_soc handle 903 * @buf: pointer to rx pkt TLV. 904 * 905 * Return: true on unicast. 906 */ 907 static inline bool 908 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 909 { 910 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 911 912 return hal_soc->ops->hal_rx_is_unicast(buf); 913 } 914 915 /** 916 * hal_rx_tid_get: get tid based on qos control valid. 917 * @hal_soc_hdl: hal soc handle 918 * @buf: pointer to rx pkt TLV. 919 * 920 * Return: tid 921 */ 922 static inline uint32_t 923 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 924 { 925 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 926 927 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 928 } 929 930 /** 931 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 932 * @hal_soc_hdl: hal soc handle 933 * @buf: pointer to rx pkt TLV. 934 * 935 * Return: sw peer_id 936 */ 937 static inline uint32_t 938 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 939 uint8_t *buf) 940 { 941 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 942 943 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 944 } 945 946 /* 947 * hal_rx_mpdu_get_tods(): API to get the tods info 948 * from rx_mpdu_start 949 * 950 * @buf: pointer to the start of RX PKT TLV header 951 * Return: uint32_t(to_ds) 952 */ 953 954 static inline uint32_t 955 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 956 { 957 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 958 959 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 960 } 961 962 963 /* 964 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 965 * from rx_mpdu_start 966 * @hal_soc_hdl: hal soc handle 967 * @buf: pointer to the start of RX PKT TLV header 968 * 969 * Return: uint32_t(fr_ds) 970 */ 971 static inline uint32_t 972 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 973 { 974 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 975 976 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 977 } 978 979 /* 980 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 981 * @hal_soc_hdl: hal soc handle 982 * @buf: pointer to the start of RX PKT TLV headera 983 * @mac_addr: pointer to mac address 984 * 985 * Return: success/failure 986 */ 987 static inline 988 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 989 uint8_t *buf, uint8_t *mac_addr) 990 { 991 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 992 993 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 994 } 995 996 /* 997 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 998 * in the packet 999 * @hal_soc_hdl: hal soc handle 1000 * @buf: pointer to the start of RX PKT TLV header 1001 * @mac_addr: pointer to mac address 1002 * 1003 * Return: success/failure 1004 */ 1005 static inline 1006 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1007 uint8_t *buf, uint8_t *mac_addr) 1008 { 1009 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1010 1011 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1012 } 1013 1014 /* 1015 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1016 * in the packet 1017 * @hal_soc_hdl: hal soc handle 1018 * @buf: pointer to the start of RX PKT TLV header 1019 * @mac_addr: pointer to mac address 1020 * 1021 * Return: success/failure 1022 */ 1023 static inline 1024 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1025 uint8_t *buf, uint8_t *mac_addr) 1026 { 1027 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1028 1029 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1030 } 1031 1032 /* 1033 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1034 * in the packet 1035 * @hal_soc_hdl: hal_soc handle 1036 * @buf: pointer to the start of RX PKT TLV header 1037 * @mac_addr: pointer to mac address 1038 * Return: success/failure 1039 */ 1040 static inline 1041 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1042 uint8_t *buf, uint8_t *mac_addr) 1043 { 1044 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1045 1046 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1047 } 1048 1049 /** 1050 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1051 * from rx_msdu_end TLV 1052 * 1053 * @ buf: pointer to the start of RX PKT TLV headers 1054 * Return: da index 1055 */ 1056 static inline uint16_t 1057 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1058 { 1059 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1060 1061 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1062 } 1063 1064 /** 1065 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1066 * from rx_msdu_end TLV 1067 * @hal_soc_hdl: hal soc handle 1068 * @ buf: pointer to the start of RX PKT TLV headers 1069 * 1070 * Return: da_is_valid 1071 */ 1072 static inline uint8_t 1073 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1074 uint8_t *buf) 1075 { 1076 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1077 1078 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1079 } 1080 1081 /** 1082 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1083 * from rx_msdu_end TLV 1084 * 1085 * @buf: pointer to the start of RX PKT TLV headers 1086 * 1087 * Return: da_is_mcbc 1088 */ 1089 static inline uint8_t 1090 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1091 { 1092 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1093 1094 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1095 } 1096 1097 /** 1098 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1099 * from rx_msdu_end TLV 1100 * @hal_soc_hdl: hal soc handle 1101 * @buf: pointer to the start of RX PKT TLV headers 1102 * 1103 * Return: first_msdu 1104 */ 1105 static inline uint8_t 1106 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1107 uint8_t *buf) 1108 { 1109 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1110 1111 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1112 } 1113 1114 /** 1115 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1116 * from rx_msdu_end TLV 1117 * @hal_soc_hdl: hal soc handle 1118 * @buf: pointer to the start of RX PKT TLV headers 1119 * 1120 * Return: last_msdu 1121 */ 1122 static inline uint8_t 1123 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1124 uint8_t *buf) 1125 { 1126 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1127 1128 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1129 } 1130 1131 /** 1132 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1133 * from rx_msdu_end TLV 1134 * @buf: pointer to the start of RX PKT TLV headers 1135 * Return: cce_meta_data 1136 */ 1137 static inline uint16_t 1138 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1139 uint8_t *buf) 1140 { 1141 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1142 1143 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1144 } 1145 1146 /******************************************************************************* 1147 * RX REO ERROR APIS 1148 ******************************************************************************/ 1149 1150 /** 1151 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1152 * @msdu_link_ptr - msdu link ptr 1153 * @hal - pointer to hal_soc 1154 * Return - Pointer to rx_msdu_details structure 1155 * 1156 */ 1157 static inline 1158 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1159 struct hal_soc *hal_soc) 1160 { 1161 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1162 } 1163 1164 /** 1165 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1166 * @msdu_details_ptr - Pointer to msdu_details_ptr 1167 * @hal - pointer to hal_soc 1168 * Return - Pointer to rx_msdu_desc_info structure. 1169 * 1170 */ 1171 static inline 1172 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1173 struct hal_soc *hal_soc) 1174 { 1175 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1176 } 1177 1178 /** 1179 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1180 * cookie from the REO destination ring element 1181 * 1182 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1183 * the current descriptor 1184 * @ buf_info: structure to return the buffer information 1185 * Return: void 1186 */ 1187 static inline 1188 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1189 hal_ring_desc_t rx_desc, 1190 struct hal_buf_info *buf_info) 1191 { 1192 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1193 1194 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1195 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1196 rx_desc, 1197 buf_info); 1198 1199 } 1200 1201 /** 1202 * hal_rx_buf_cookie_rbm_get: Gets the physical address and 1203 * cookie from the REO entrance ring element 1204 * 1205 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1206 * the current descriptor 1207 * @ buf_info: structure to return the buffer information 1208 * @ msdu_cnt: pointer to msdu count in MPDU 1209 * Return: void 1210 */ 1211 static inline 1212 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1213 uint32_t *buf_addr_info, 1214 struct hal_buf_info *buf_info) 1215 { 1216 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1217 1218 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1219 buf_addr_info, 1220 buf_info); 1221 } 1222 1223 /** 1224 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1225 * from the MSDU link descriptor 1226 * 1227 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1228 * MSDU link descriptor (struct rx_msdu_link) 1229 * 1230 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1231 * 1232 * @num_msdus: Number of MSDUs in the MPDU 1233 * 1234 * Return: void 1235 */ 1236 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1237 void *msdu_link_desc, 1238 struct hal_rx_msdu_list *msdu_list, 1239 uint16_t *num_msdus) 1240 { 1241 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1242 struct rx_msdu_details *msdu_details; 1243 struct rx_msdu_desc_info *msdu_desc_info; 1244 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1245 int i; 1246 struct hal_buf_info buf_info; 1247 1248 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1249 1250 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1251 __func__, __LINE__, msdu_link, msdu_details); 1252 1253 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1254 /* num_msdus received in mpdu descriptor may be incorrect 1255 * sometimes due to HW issue. Check msdu buffer address also 1256 */ 1257 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1258 &msdu_details[i].buffer_addr_info_details) == 0)) 1259 break; 1260 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1261 &msdu_details[i].buffer_addr_info_details) == 0) { 1262 /* set the last msdu bit in the prev msdu_desc_info */ 1263 msdu_desc_info = 1264 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1265 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1266 break; 1267 } 1268 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1269 hal_soc); 1270 1271 /* set first MSDU bit or the last MSDU bit */ 1272 if (!i) 1273 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1274 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1275 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1276 1277 msdu_list->msdu_info[i].msdu_flags = 1278 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1279 msdu_list->msdu_info[i].msdu_len = 1280 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1281 1282 /* addr field in buf_info will not be valid */ 1283 hal_rx_buf_cookie_rbm_get( 1284 hal_soc_hdl, 1285 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1286 &buf_info); 1287 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1288 msdu_list->rbm[i] = buf_info.rbm; 1289 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1290 &msdu_details[i].buffer_addr_info_details) | 1291 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1292 &msdu_details[i].buffer_addr_info_details) << 32; 1293 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1294 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1295 } 1296 *num_msdus = i; 1297 } 1298 1299 /** 1300 * hal_rx_is_pn_error() - Indicate if this error was caused by a 1301 * PN check failure 1302 * 1303 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 1304 * 1305 * Return: true: error caused by PN check, false: other error 1306 */ 1307 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1308 { 1309 1310 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1311 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1312 true : false; 1313 } 1314 1315 /** 1316 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1317 * the sequence number 1318 * 1319 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1320 * 1321 * Return: true: error caused by 2K jump, false: other error 1322 */ 1323 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1324 { 1325 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1326 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1327 true : false; 1328 } 1329 1330 /** 1331 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1332 * 1333 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1334 * 1335 * Return: true: error caused by OOR, false: other error 1336 */ 1337 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1338 { 1339 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1340 true : false; 1341 } 1342 1343 /** 1344 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1345 * @error_code: error code obtained from ring descriptor. 1346 * 1347 * Return: true, if the error code is 2k-jump or OOR 1348 * false, for other error codes. 1349 */ 1350 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1351 { 1352 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1353 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1354 true : false; 1355 } 1356 1357 /** 1358 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1359 * @hal_desc: hardware descriptor pointer 1360 * 1361 * This function will print wbm release descriptor 1362 * 1363 * Return: none 1364 */ 1365 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1366 { 1367 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1368 uint32_t i; 1369 1370 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1371 "Current Rx wbm release descriptor is"); 1372 1373 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1374 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1375 "DWORD[i] = 0x%x", wbm_comp[i]); 1376 } 1377 } 1378 1379 /** 1380 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 1381 * 1382 * @ hal_soc_hdl : HAL version of the SOC pointer 1383 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 1384 * @ buf_addr_info : void pointer to the buffer_addr_info 1385 * @ bm_action : put in IDLE list or release to MSDU_LIST 1386 * 1387 * Return: void 1388 */ 1389 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1390 static inline 1391 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1392 void *src_srng_desc, 1393 hal_buff_addrinfo_t buf_addr_info, 1394 uint8_t bm_action) 1395 { 1396 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1397 1398 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1399 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1400 src_srng_desc, 1401 buf_addr_info, 1402 bm_action); 1403 } 1404 1405 /** 1406 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 1407 * BUFFER_ADDR_INFO, give the RX descriptor 1408 * (Assumption -- BUFFER_ADDR_INFO is the 1409 * first field in the descriptor structure) 1410 */ 1411 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1412 ((hal_link_desc_t)(ring_desc)) 1413 1414 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1415 1416 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1417 1418 /******************************************************************************* 1419 * RX WBM ERROR APIS 1420 ******************************************************************************/ 1421 1422 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1423 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1424 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1425 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1426 /** 1427 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 1428 * the frame to this release ring 1429 * 1430 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1431 * frame to this queue 1432 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1433 * received routing instructions. No error within REO was detected 1434 */ 1435 enum hal_rx_wbm_reo_push_reason { 1436 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1437 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1438 }; 1439 1440 1441 /** 1442 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 1443 * this release ring 1444 * 1445 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1446 * this frame to this queue 1447 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1448 * per received routing instructions. No error within RXDMA was detected 1449 */ 1450 enum hal_rx_wbm_rxdma_push_reason { 1451 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1452 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1453 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1454 }; 1455 1456 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 1457 uint8_t dbg_level, 1458 struct hal_soc *hal) 1459 { 1460 1461 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 1462 } 1463 1464 /** 1465 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 1466 * human readable format. 1467 * @ msdu_end: pointer the msdu_end TLV in pkt. 1468 * @ dbg_level: log level. 1469 * 1470 * Return: void 1471 */ 1472 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1473 struct rx_msdu_end *msdu_end, 1474 uint8_t dbg_level) 1475 { 1476 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 1477 } 1478 1479 /** 1480 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 1481 * structure 1482 * @hal_ring: pointer to hal_srng structure 1483 * 1484 * Return: ring_id 1485 */ 1486 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1487 { 1488 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1489 } 1490 1491 #define DOT11_SEQ_FRAG_MASK 0x000f 1492 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1493 1494 /** 1495 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 1496 * 1497 * @nbuf: Network buffer 1498 * Returns: rx fragment number 1499 */ 1500 static inline 1501 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1502 uint8_t *buf) 1503 { 1504 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1505 } 1506 1507 /* 1508 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 1509 * @hal_soc_hdl: hal soc handle 1510 * @nbuf: Network buffer 1511 * 1512 * Return: value of sequence control valid field 1513 */ 1514 static inline 1515 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1516 uint8_t *buf) 1517 { 1518 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1519 1520 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1521 } 1522 1523 /* 1524 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 1525 * @hal_soc_hdl: hal soc handle 1526 * @nbuf: Network buffer 1527 * 1528 * Returns: value of frame control valid field 1529 */ 1530 static inline 1531 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1532 uint8_t *buf) 1533 { 1534 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1535 1536 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1537 } 1538 1539 /** 1540 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 1541 * @hal_soc_hdl: hal soc handle 1542 * @nbuf: Network buffer 1543 * Returns: value of mpdu 4th address valid field 1544 */ 1545 static inline 1546 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1547 uint8_t *buf) 1548 { 1549 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1550 1551 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1552 } 1553 1554 /* 1555 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 1556 * 1557 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1558 * Returns: None 1559 */ 1560 static inline void 1561 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1562 { 1563 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1564 } 1565 1566 /** 1567 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 1568 * save it to hal_wbm_err_desc_info structure passed by caller 1569 * @wbm_desc: wbm ring descriptor 1570 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1571 * Return: void 1572 */ 1573 static inline 1574 void hal_rx_wbm_err_info_get(void *wbm_desc, 1575 struct hal_wbm_err_desc_info *wbm_er_info, 1576 hal_soc_handle_t hal_soc_hdl) 1577 { 1578 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1579 1580 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1581 } 1582 1583 /** 1584 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 1585 * bit from wbm release ring descriptor 1586 * @wbm_desc: wbm ring descriptor 1587 * Return: uint8_t 1588 */ 1589 static inline 1590 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1591 void *wbm_desc) 1592 { 1593 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1594 1595 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1596 } 1597 1598 /** 1599 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 1600 * 1601 * @ hal_soc: HAL version of the SOC pointer 1602 * @ hw_desc_addr: Start address of Rx HW TLVs 1603 * @ rs: Status for monitor mode 1604 * 1605 * Return: void 1606 */ 1607 static inline 1608 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1609 void *hw_desc_addr, 1610 struct mon_rx_status *rs) 1611 { 1612 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1613 1614 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1615 } 1616 1617 /* 1618 * hal_rx_get_tlv(): API to get the tlv 1619 * 1620 * @hal_soc: HAL version of the SOC pointer 1621 * @rx_tlv: TLV data extracted from the rx packet 1622 * Return: uint8_t 1623 */ 1624 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1625 { 1626 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1627 } 1628 1629 /* 1630 * hal_rx_msdu_start_nss_get(): API to get the NSS 1631 * Interval from rx_msdu_start 1632 * 1633 * @hal_soc: HAL version of the SOC pointer 1634 * @buf: pointer to the start of RX PKT TLV header 1635 * Return: uint32_t(nss) 1636 */ 1637 static inline 1638 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1639 { 1640 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1641 1642 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1643 } 1644 1645 /** 1646 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 1647 * human readable format. 1648 * @ msdu_start: pointer the msdu_start TLV in pkt. 1649 * @ dbg_level: log level. 1650 * 1651 * Return: void 1652 */ 1653 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1654 struct rx_msdu_start *msdu_start, 1655 uint8_t dbg_level) 1656 { 1657 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 1658 } 1659 1660 /** 1661 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 1662 * info details 1663 * 1664 * @ buf - Pointer to buffer containing rx pkt tlvs. 1665 * 1666 * 1667 */ 1668 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1669 uint8_t *buf) 1670 { 1671 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1672 1673 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1674 } 1675 1676 /* 1677 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 1678 * Interval from rx_msdu_start 1679 * 1680 * @buf: pointer to the start of RX PKT TLV header 1681 * Return: uint32_t(reception_type) 1682 */ 1683 static inline 1684 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1685 uint8_t *buf) 1686 { 1687 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1688 1689 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1690 } 1691 1692 /** 1693 * hal_reo_status_get_header_generic - Process reo desc info 1694 * @d - Pointer to reo descriptior 1695 * @b - tlv type info 1696 * @h - Pointer to hal_reo_status_header where info to be stored 1697 * @hal- pointer to hal_soc structure 1698 * Return - none. 1699 * 1700 */ 1701 static inline 1702 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1703 void *h, struct hal_soc *hal_soc) 1704 { 1705 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1706 } 1707 1708 /** 1709 * hal_rx_desc_is_first_msdu() - Check if first msdu 1710 * 1711 * @hal_soc_hdl: hal_soc handle 1712 * @hw_desc_addr: hardware descriptor address 1713 * 1714 * Return: 0 - success/ non-zero failure 1715 */ 1716 static inline 1717 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1718 void *hw_desc_addr) 1719 { 1720 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1721 1722 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1723 } 1724 1725 /** 1726 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1727 * the rx tlv fields. 1728 * @hal_soc_hdl: HAL SoC handle 1729 * @buf: rx tlv start address [To be validated by caller] 1730 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1731 * 1732 * Return: None 1733 */ 1734 static inline void 1735 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1736 uint8_t *buf, 1737 void *mpdu_desc_info_hdl) 1738 { 1739 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1740 1741 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1742 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1743 mpdu_desc_info_hdl); 1744 } 1745 1746 static inline uint32_t 1747 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1748 { 1749 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1750 1751 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1752 } 1753 1754 static inline 1755 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1756 uint8_t *rx_tlv_hdr) 1757 { 1758 uint8_t decap_format; 1759 1760 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1761 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1762 rx_tlv_hdr); 1763 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1764 return true; 1765 } 1766 1767 return false; 1768 } 1769 1770 /** 1771 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 1772 * from rx_msdu_end TLV 1773 * @buf: pointer to the start of RX PKT TLV headers 1774 * 1775 * Return: fse metadata value from MSDU END TLV 1776 */ 1777 static inline uint32_t 1778 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1779 uint8_t *buf) 1780 { 1781 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1782 1783 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1784 } 1785 1786 /** 1787 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 1788 * <struct buffer_addr_info> structure 1789 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1790 * @buf_info: structure to return the buffer information including 1791 * paddr/cookie 1792 * 1793 * return: None 1794 */ 1795 static inline 1796 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 1797 struct hal_buf_info *buf_info) 1798 { 1799 buf_info->paddr = 1800 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 1801 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 1802 } 1803 1804 /** 1805 * hal_rx_msdu_flow_idx_get: API to get flow index 1806 * from rx_msdu_end TLV 1807 * @buf: pointer to the start of RX PKT TLV headers 1808 * 1809 * Return: flow index value from MSDU END TLV 1810 */ 1811 static inline uint32_t 1812 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 1813 uint8_t *buf) 1814 { 1815 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1816 1817 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 1818 } 1819 1820 /** 1821 * hal_rx_msdu_get_reo_destination_indication: API to get reo 1822 * destination index from rx_msdu_end TLV 1823 * @buf: pointer to the start of RX PKT TLV headers 1824 * @reo_destination_indication: pointer to return value of 1825 * reo_destination_indication 1826 * 1827 * Return: reo_destination_indication value from MSDU END TLV 1828 */ 1829 static inline void 1830 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 1831 uint8_t *buf, 1832 uint32_t *reo_destination_indication) 1833 { 1834 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1835 1836 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 1837 reo_destination_indication); 1838 } 1839 1840 /** 1841 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 1842 * from rx_msdu_end TLV 1843 * @buf: pointer to the start of RX PKT TLV headers 1844 * 1845 * Return: flow index timeout value from MSDU END TLV 1846 */ 1847 static inline bool 1848 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 1849 uint8_t *buf) 1850 { 1851 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1852 1853 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 1854 } 1855 1856 /** 1857 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 1858 * from rx_msdu_end TLV 1859 * @buf: pointer to the start of RX PKT TLV headers 1860 * 1861 * Return: flow index invalid value from MSDU END TLV 1862 */ 1863 static inline bool 1864 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 1865 uint8_t *buf) 1866 { 1867 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1868 1869 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 1870 } 1871 1872 /** 1873 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 1874 * @hal_soc_hdl: hal_soc handle 1875 * @rx_tlv_hdr: Rx_tlv_hdr 1876 * @rxdma_dst_ring_desc: Rx HW descriptor 1877 * 1878 * Return: ppdu id 1879 */ 1880 static inline 1881 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 1882 void *rx_tlv_hdr, 1883 void *rxdma_dst_ring_desc) 1884 { 1885 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1886 1887 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 1888 rxdma_dst_ring_desc); 1889 } 1890 1891 /** 1892 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 1893 * @hal_soc_hdl: hal_soc handle 1894 * @buf: rx tlv address 1895 * 1896 * Return: sw peer id 1897 */ 1898 static inline 1899 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1900 uint8_t *buf) 1901 { 1902 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1903 1904 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 1905 } 1906 1907 static inline 1908 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 1909 void *link_desc_addr) 1910 { 1911 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1912 1913 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 1914 } 1915 1916 static inline 1917 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 1918 void *msdu_addr) 1919 { 1920 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1921 1922 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 1923 } 1924 1925 static inline 1926 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1927 void *hw_addr) 1928 { 1929 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1930 1931 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 1932 } 1933 1934 static inline 1935 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1936 void *hw_addr) 1937 { 1938 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1939 1940 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 1941 } 1942 1943 static inline 1944 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 1945 uint8_t *buf) 1946 { 1947 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1948 1949 return hal_soc->ops->hal_rx_get_fc_valid(buf); 1950 } 1951 1952 static inline 1953 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1954 { 1955 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1956 1957 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 1958 } 1959 1960 static inline 1961 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 1962 uint8_t *buf) 1963 { 1964 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1965 1966 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 1967 } 1968 1969 static inline 1970 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 1971 uint8_t *buf) 1972 { 1973 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1974 1975 return hal_soc->ops->hal_rx_get_filter_category(buf); 1976 } 1977 1978 static inline 1979 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 1980 uint8_t *buf) 1981 { 1982 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1983 1984 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 1985 } 1986 1987 /** 1988 * hal_reo_config(): Set reo config parameters 1989 * @soc: hal soc handle 1990 * @reg_val: value to be set 1991 * @reo_params: reo parameters 1992 * 1993 * Return: void 1994 */ 1995 static inline 1996 void hal_reo_config(struct hal_soc *hal_soc, 1997 uint32_t reg_val, 1998 struct hal_reo_params *reo_params) 1999 { 2000 hal_soc->ops->hal_reo_config(hal_soc, 2001 reg_val, 2002 reo_params); 2003 } 2004 2005 /** 2006 * hal_rx_msdu_get_flow_params: API to get flow index, 2007 * flow index invalid and flow index timeout from rx_msdu_end TLV 2008 * @buf: pointer to the start of RX PKT TLV headers 2009 * @flow_invalid: pointer to return value of flow_idx_valid 2010 * @flow_timeout: pointer to return value of flow_idx_timeout 2011 * @flow_index: pointer to return value of flow_idx 2012 * 2013 * Return: none 2014 */ 2015 static inline void 2016 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2017 uint8_t *buf, 2018 bool *flow_invalid, 2019 bool *flow_timeout, 2020 uint32_t *flow_index) 2021 { 2022 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2023 2024 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2025 flow_invalid, 2026 flow_timeout, 2027 flow_index); 2028 } 2029 2030 static inline 2031 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2032 uint8_t *buf) 2033 { 2034 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2035 2036 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2037 } 2038 2039 static inline 2040 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2041 uint8_t *buf) 2042 { 2043 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2044 2045 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2046 } 2047 2048 static inline void 2049 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2050 void *rx_tlv, 2051 void *ppdu_info) 2052 { 2053 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2054 2055 if (hal_soc->ops->hal_rx_get_bb_info) 2056 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2057 } 2058 2059 static inline void 2060 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2061 void *rx_tlv, 2062 void *ppdu_info) 2063 { 2064 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2065 2066 if (hal_soc->ops->hal_rx_get_rtt_info) 2067 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2068 } 2069 2070 /** 2071 * hal_rx_msdu_metadata_get(): API to get the 2072 * fast path information from rx_msdu_end TLV 2073 * 2074 * @ hal_soc_hdl: DP soc handle 2075 * @ buf: pointer to the start of RX PKT TLV headers 2076 * @ msdu_metadata: Structure to hold msdu end information 2077 * Return: none 2078 */ 2079 static inline void 2080 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2081 struct hal_rx_msdu_metadata *msdu_md) 2082 { 2083 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2084 2085 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2086 } 2087 2088 /** 2089 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 2090 * from rx_msdu_end TLV 2091 * @buf: pointer to the start of RX PKT TLV headers 2092 * 2093 * Return: cumulative_l4_checksum 2094 */ 2095 static inline uint16_t 2096 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2097 uint8_t *buf) 2098 { 2099 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2100 2101 if (!hal_soc || !hal_soc->ops) { 2102 hal_err("hal handle is NULL"); 2103 QDF_BUG(0); 2104 return 0; 2105 } 2106 2107 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2108 return 0; 2109 2110 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2111 } 2112 2113 /** 2114 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 2115 * from rx_msdu_end TLV 2116 * @buf: pointer to the start of RX PKT TLV headers 2117 * 2118 * Return: cumulative_ip_length 2119 */ 2120 static inline uint16_t 2121 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2122 uint8_t *buf) 2123 { 2124 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2125 2126 if (!hal_soc || !hal_soc->ops) { 2127 hal_err("hal handle is NULL"); 2128 QDF_BUG(0); 2129 return 0; 2130 } 2131 2132 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2133 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2134 2135 return 0; 2136 } 2137 2138 /** 2139 * hal_rx_get_udp_proto: API to get UDP proto field 2140 * from rx_msdu_start TLV 2141 * @buf: pointer to the start of RX PKT TLV headers 2142 * 2143 * Return: UDP proto field value 2144 */ 2145 static inline bool 2146 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2147 { 2148 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2149 2150 if (!hal_soc || !hal_soc->ops) { 2151 hal_err("hal handle is NULL"); 2152 QDF_BUG(0); 2153 return 0; 2154 } 2155 2156 if (hal_soc->ops->hal_rx_get_udp_proto) 2157 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2158 2159 return 0; 2160 } 2161 2162 /** 2163 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 2164 * from rx_msdu_end TLV 2165 * @buf: pointer to the start of RX PKT TLV headers 2166 * 2167 * Return: flow_agg_continuation bit field value 2168 */ 2169 static inline bool 2170 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2171 uint8_t *buf) 2172 { 2173 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2174 2175 if (!hal_soc || !hal_soc->ops) { 2176 hal_err("hal handle is NULL"); 2177 QDF_BUG(0); 2178 return 0; 2179 } 2180 2181 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2182 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2183 2184 return 0; 2185 } 2186 2187 /** 2188 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 2189 * rx_msdu_end TLV 2190 * @buf: pointer to the start of RX PKT TLV headers 2191 * 2192 * Return: flow_agg count value 2193 */ 2194 static inline uint8_t 2195 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2196 uint8_t *buf) 2197 { 2198 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2199 2200 if (!hal_soc || !hal_soc->ops) { 2201 hal_err("hal handle is NULL"); 2202 QDF_BUG(0); 2203 return 0; 2204 } 2205 2206 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2207 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2208 2209 return 0; 2210 } 2211 2212 /** 2213 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 2214 * @buf: pointer to the start of RX PKT TLV headers 2215 * 2216 * Return: fisa flow_agg timeout bit value 2217 */ 2218 static inline bool 2219 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2220 { 2221 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2222 2223 if (!hal_soc || !hal_soc->ops) { 2224 hal_err("hal handle is NULL"); 2225 QDF_BUG(0); 2226 return 0; 2227 } 2228 2229 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2230 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2231 2232 return 0; 2233 } 2234 2235 /** 2236 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 2237 * tag is valid 2238 * 2239 * @hal_soc_hdl: HAL SOC handle 2240 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2241 * 2242 * Return: true if RX_MPDU_START tlv tag is valid, else false 2243 */ 2244 2245 static inline uint8_t 2246 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2247 void *rx_tlv_hdr) 2248 { 2249 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2250 2251 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2252 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2253 2254 return 0; 2255 } 2256 2257 /** 2258 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 2259 * buffer addr info 2260 * @link_desc_va: pointer to current msdu link Desc 2261 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2262 * 2263 * return: None 2264 */ 2265 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2266 void *link_desc_va, 2267 struct buffer_addr_info *next_addr_info) 2268 { 2269 struct rx_msdu_link *msdu_link = link_desc_va; 2270 2271 if (!msdu_link) { 2272 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2273 return; 2274 } 2275 2276 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2277 } 2278 2279 /** 2280 * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc 2281 * buffer addr info 2282 * @link_desc_va: pointer to current msdu link Desc 2283 * 2284 * return: None 2285 */ 2286 static inline 2287 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2288 { 2289 struct rx_msdu_link *msdu_link = link_desc_va; 2290 2291 if (msdu_link) 2292 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2293 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2294 } 2295 2296 /** 2297 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 2298 * 2299 * @buf_addr_info: pointer to buf_addr_info structure 2300 * 2301 * return: true: has valid paddr, false: not. 2302 */ 2303 static inline 2304 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2305 { 2306 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2307 false : true; 2308 } 2309 2310 /** 2311 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 2312 * rx_pkt_tlvs structure 2313 * 2314 * @hal_soc_hdl: HAL SOC handle 2315 * return: msdu_end_tlv offset value 2316 */ 2317 static inline 2318 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2319 { 2320 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2321 2322 if (!hal_soc || !hal_soc->ops) { 2323 hal_err("hal handle is NULL"); 2324 QDF_BUG(0); 2325 return 0; 2326 } 2327 2328 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2329 } 2330 2331 /** 2332 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 2333 * rx_pkt_tlvs structure 2334 * 2335 * @hal_soc_hdl: HAL SOC handle 2336 * return: msdu_start_tlv offset value 2337 */ 2338 static inline 2339 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2340 { 2341 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2342 2343 if (!hal_soc || !hal_soc->ops) { 2344 hal_err("hal handle is NULL"); 2345 QDF_BUG(0); 2346 return 0; 2347 } 2348 2349 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2350 } 2351 2352 /** 2353 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 2354 * rx_pkt_tlvs structure 2355 * 2356 * @hal_soc_hdl: HAL SOC handle 2357 * return: mpdu_start_tlv offset value 2358 */ 2359 static inline 2360 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2361 { 2362 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2363 2364 if (!hal_soc || !hal_soc->ops) { 2365 hal_err("hal handle is NULL"); 2366 QDF_BUG(0); 2367 return 0; 2368 } 2369 2370 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2371 } 2372 2373 static inline 2374 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2375 { 2376 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2377 2378 if (!hal_soc || !hal_soc->ops) { 2379 hal_err("hal handle is NULL"); 2380 QDF_BUG(0); 2381 return 0; 2382 } 2383 2384 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2385 } 2386 2387 /** 2388 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 2389 * rx_pkt_tlvs structure 2390 * 2391 * @hal_soc_hdl: HAL SOC handle 2392 * return: mpdu_end_tlv offset value 2393 */ 2394 static inline 2395 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2396 { 2397 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2398 2399 if (!hal_soc || !hal_soc->ops) { 2400 hal_err("hal handle is NULL"); 2401 QDF_BUG(0); 2402 return 0; 2403 } 2404 2405 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2406 } 2407 2408 /** 2409 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 2410 * rx_pkt_tlvs structure 2411 * 2412 * @hal_soc_hdl: HAL SOC handle 2413 * return: attn_tlv offset value 2414 */ 2415 static inline 2416 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2417 { 2418 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2419 2420 if (!hal_soc || !hal_soc->ops) { 2421 hal_err("hal handle is NULL"); 2422 QDF_BUG(0); 2423 return 0; 2424 } 2425 2426 return hal_soc->ops->hal_rx_attn_offset_get(); 2427 } 2428 2429 /** 2430 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 2431 * @msdu_details_ptr - Pointer to msdu_details_ptr 2432 * @hal - pointer to hal_soc 2433 * Return - Pointer to rx_msdu_desc_info structure. 2434 * 2435 */ 2436 static inline 2437 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2438 struct hal_soc *hal_soc) 2439 { 2440 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2441 msdu_details_ptr); 2442 } 2443 2444 static inline void 2445 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2446 uint8_t *buf, uint8_t dbg_level) 2447 { 2448 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2449 2450 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2451 } 2452 2453 //TODO - Change the names to not include tlv names 2454 static inline uint16_t 2455 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2456 { 2457 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2458 2459 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2460 } 2461 2462 static inline uint32_t 2463 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2464 { 2465 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2466 2467 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2468 } 2469 2470 static inline uint32_t 2471 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2472 { 2473 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2474 2475 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2476 } 2477 2478 static inline uint16_t 2479 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2480 { 2481 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2482 2483 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2484 } 2485 2486 static inline int 2487 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2488 uint8_t *rx_pkt_tlv, 2489 struct hal_offload_info *offload_info) 2490 { 2491 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2492 2493 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2494 offload_info); 2495 2496 } 2497 2498 static inline int 2499 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2500 void *proto_params) 2501 { 2502 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2503 2504 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2505 } 2506 2507 static inline int 2508 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2509 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2510 { 2511 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2512 2513 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2514 l3_hdr_offset, 2515 l4_hdr_offset); 2516 } 2517 2518 static inline uint32_t 2519 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2520 { 2521 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2522 2523 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2524 } 2525 2526 /* 2527 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 2528 * from rx_msdu_start 2529 * 2530 * @buf: pointer to the start of RX PKT TLV header 2531 * Return: uint32_t(pkt type) 2532 */ 2533 2534 static inline uint32_t 2535 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2536 { 2537 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2538 2539 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2540 } 2541 2542 static inline void 2543 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2544 uint8_t *buf, uint64_t *pn_num) 2545 { 2546 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2547 2548 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2549 } 2550 2551 static inline uint32_t 2552 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2553 { 2554 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2555 2556 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2557 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2558 2559 return 0; 2560 } 2561 2562 static inline uint8_t * 2563 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2564 { 2565 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2566 2567 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2568 } 2569 2570 static inline uint8_t 2571 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2572 { 2573 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2574 2575 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2576 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2577 2578 return 0; 2579 } 2580 2581 static inline uint32_t 2582 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2583 { 2584 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2585 2586 if (hal_soc->ops->hal_rx_tlv_get_freq) 2587 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2588 2589 return 0; 2590 } 2591 2592 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2593 void *mpdu_desc_info, uint32_t val) 2594 { 2595 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2596 2597 if (hal_soc->ops->hal_mpdu_desc_info_set) 2598 return hal_soc->ops->hal_mpdu_desc_info_set( 2599 hal_soc_hdl, mpdu_desc_info, val); 2600 } 2601 2602 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2603 void *msdu_desc_info, 2604 uint32_t val, uint32_t nbuf_len) 2605 { 2606 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2607 2608 if (hal_soc->ops->hal_msdu_desc_info_set) 2609 return hal_soc->ops->hal_msdu_desc_info_set( 2610 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2611 } 2612 2613 static inline uint32_t 2614 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2615 { 2616 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2617 2618 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2619 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2620 hal_soc_hdl, msdu_link_desc); 2621 2622 return 0; 2623 } 2624 2625 static inline uint32_t 2626 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2627 { 2628 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2629 2630 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2631 } 2632 2633 static inline uint32_t 2634 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2635 { 2636 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2637 2638 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2639 } 2640 2641 static inline uint32_t 2642 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2643 { 2644 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2645 2646 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2647 } 2648 2649 static inline uint32_t 2650 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2651 { 2652 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2653 2654 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2655 } 2656 2657 static inline uint32_t 2658 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2659 { 2660 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2661 2662 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2663 } 2664 2665 static inline uint32_t 2666 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2667 hal_ring_desc_t ring_desc) 2668 { 2669 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2670 2671 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2672 } 2673 2674 /** 2675 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2676 * from the BUFFER_ADDR_INFO structure 2677 * given a REO destination ring descriptor. 2678 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2679 * 2680 * Return: uint8_t (value of the return_buffer_manager) 2681 */ 2682 static inline uint8_t 2683 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2684 hal_ring_desc_t ring_desc) 2685 { 2686 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2687 2688 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2689 } 2690 2691 /* 2692 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2693 * rxdma ring entry. 2694 * @rxdma_entry: descriptor entry 2695 * @paddr: physical address of nbuf data pointer. 2696 * @cookie: SW cookie used as a index to SW rx desc. 2697 * @manager: who owns the nbuf (host, NSS, etc...). 2698 * 2699 */ 2700 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 2701 void *rxdma_entry, 2702 qdf_dma_addr_t paddr, 2703 uint32_t cookie, 2704 uint8_t manager) 2705 { 2706 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2707 2708 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 2709 paddr, 2710 cookie, 2711 manager); 2712 } 2713 2714 static inline uint32_t 2715 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2716 { 2717 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2718 2719 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 2720 } 2721 2722 static inline void 2723 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 2724 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 2725 { 2726 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2727 2728 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 2729 ip_csum_err, 2730 tcp_udp_csum_err); 2731 } 2732 2733 static inline void 2734 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 2735 uint8_t *rx_tlv_hdr, 2736 struct hal_rx_pkt_capture_flags *flags) 2737 { 2738 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2739 2740 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 2741 flags); 2742 } 2743 2744 static inline uint8_t 2745 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2746 { 2747 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2748 2749 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 2750 } 2751 2752 static inline uint8_t 2753 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2754 { 2755 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2756 2757 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 2758 } 2759 2760 /** 2761 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 2762 * @hal_soc_hdl: HAL SoC handle 2763 * @ring_desc: REO ring descriptor 2764 * @prev_pn: Buffer to populate the previos PN 2765 * 2766 * Return: None 2767 */ 2768 static inline void 2769 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 2770 uint64_t *prev_pn) 2771 { 2772 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2773 2774 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 2775 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 2776 } 2777 2778 /** 2779 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 2780 * from rx mpdu info 2781 * @buf: pointer to rx_pkt_tlvs 2782 * 2783 * No input validdataion, since this function is supposed to be 2784 * called from fastpath. 2785 * 2786 * Return: ampdu flag 2787 */ 2788 static inline bool 2789 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2790 { 2791 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2792 2793 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 2794 } 2795 2796 #endif /* _HAL_RX_H */ 2797