1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_internal.h> 23 24 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 25 #define HAL_RX_LSB(block, field) block##_##field##_LSB 26 #define HAL_RX_MASk(block, field) block##_##field##_MASK 27 28 #define HAL_RX_GET(_ptr, block, field) \ 29 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 30 HAL_RX_MASk(block, field)) >> \ 31 HAL_RX_LSB(block, field)) 32 33 #ifdef NO_RX_PKT_HDR_TLV 34 /* RX_BUFFER_SIZE = 1536 data bytes + 256 RX TLV bytes. We are avoiding 35 * 128 bytes of RX_PKT_HEADER_TLV. 36 */ 37 #define RX_BUFFER_SIZE 1792 38 #else 39 /* RX_BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 40 #define RX_BUFFER_SIZE 2048 41 #endif 42 43 enum { 44 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 45 HAL_HW_RX_DECAP_FORMAT_NWIFI, 46 HAL_HW_RX_DECAP_FORMAT_ETH2, 47 HAL_HW_RX_DECAP_FORMAT_8023, 48 }; 49 50 /** 51 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 52 * 53 * @reo_psh_rsn: REO push reason 54 * @reo_err_code: REO Error code 55 * @rxdma_psh_rsn: RXDMA push reason 56 * @rxdma_err_code: RXDMA Error code 57 * @reserved_1: Reserved bits 58 * @wbm_err_src: WBM error source 59 * @pool_id: pool ID, indicates which rxdma pool 60 * @reserved_2: Reserved bits 61 */ 62 struct hal_wbm_err_desc_info { 63 uint16_t reo_psh_rsn:2, 64 reo_err_code:5, 65 rxdma_psh_rsn:2, 66 rxdma_err_code:5, 67 reserved_1:2; 68 uint8_t wbm_err_src:3, 69 pool_id:2, 70 reserved_2:3; 71 }; 72 73 /** 74 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 75 * 76 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 77 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 78 */ 79 enum hal_reo_error_status { 80 HAL_REO_ERROR_DETECTED = 0, 81 HAL_REO_ROUTING_INSTRUCTION = 1, 82 }; 83 84 /** 85 * @msdu_flags: [0] first_msdu_in_mpdu 86 * [1] last_msdu_in_mpdu 87 * [2] msdu_continuation - MSDU spread across buffers 88 * [23] sa_is_valid - SA match in peer table 89 * [24] sa_idx_timeout - Timeout while searching for SA match 90 * [25] da_is_valid - Used to identtify intra-bss forwarding 91 * [26] da_is_MCBC 92 * [27] da_idx_timeout - Timeout while searching for DA match 93 * 94 */ 95 struct hal_rx_msdu_desc_info { 96 uint32_t msdu_flags; 97 uint16_t msdu_len; /* 14 bits for length */ 98 }; 99 100 /** 101 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 102 * 103 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 104 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 105 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 106 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 107 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 108 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 109 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 110 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 111 */ 112 enum hal_rx_msdu_desc_flags { 113 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 114 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 115 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 116 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 117 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 118 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 119 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 120 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 121 }; 122 123 /* 124 * @msdu_count: no. of msdus in the MPDU 125 * @mpdu_seq: MPDU sequence number 126 * @mpdu_flags [0] Fragment flag 127 * [1] MPDU_retry_bit 128 * [2] AMPDU flag 129 * [3] raw_ampdu 130 * @peer_meta_data: Upper bits containing peer id, vdev id 131 */ 132 struct hal_rx_mpdu_desc_info { 133 uint16_t msdu_count; 134 uint16_t mpdu_seq; /* 12 bits for length */ 135 uint32_t mpdu_flags; 136 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 137 }; 138 139 /** 140 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 141 * 142 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 143 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 144 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 145 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 146 */ 147 enum hal_rx_mpdu_desc_flags { 148 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 149 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 150 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 151 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 152 }; 153 154 /** 155 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 156 * BUFFER_ADDR_INFO structure 157 * 158 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 159 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 160 * descriptor list 161 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 162 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 163 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 164 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 165 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 166 */ 167 enum hal_rx_ret_buf_manager { 168 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 169 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 170 HAL_RX_BUF_RBM_FW_BM = 2, 171 HAL_RX_BUF_RBM_SW0_BM = 3, 172 HAL_RX_BUF_RBM_SW1_BM = 4, 173 HAL_RX_BUF_RBM_SW2_BM = 5, 174 HAL_RX_BUF_RBM_SW3_BM = 6, 175 }; 176 177 /* 178 * Given the offset of a field in bytes, returns uint8_t * 179 */ 180 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 181 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 182 183 /* 184 * Given the offset of a field in bytes, returns uint32_t * 185 */ 186 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 187 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 188 189 #define _HAL_MS(_word, _mask, _shift) \ 190 (((_word) & (_mask)) >> (_shift)) 191 192 /* 193 * macro to set the LSW of the nbuf data physical address 194 * to the rxdma ring entry 195 */ 196 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 197 ((*(((unsigned int *) buff_addr_info) + \ 198 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 199 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 200 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 201 202 /* 203 * macro to set the LSB of MSW of the nbuf data physical address 204 * to the rxdma ring entry 205 */ 206 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 207 ((*(((unsigned int *) buff_addr_info) + \ 208 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 209 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 210 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 211 212 /* 213 * macro to set the cookie into the rxdma ring entry 214 */ 215 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 216 ((*(((unsigned int *) buff_addr_info) + \ 217 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 218 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 219 ((*(((unsigned int *) buff_addr_info) + \ 220 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 221 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 222 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 223 224 /* 225 * macro to set the manager into the rxdma ring entry 226 */ 227 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 228 ((*(((unsigned int *) buff_addr_info) + \ 229 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 230 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 231 ((*(((unsigned int *) buff_addr_info) + \ 232 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 233 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 234 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 235 236 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 237 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 238 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 239 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 240 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 241 242 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 243 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 244 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 245 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 246 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 247 248 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 249 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 250 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 251 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 252 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 253 254 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 255 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 256 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 257 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 258 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 259 260 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 261 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 262 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 263 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 264 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 265 266 /* TODO: Convert the following structure fields accesseses to offsets */ 267 268 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 269 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 270 (((struct reo_destination_ring *) \ 271 reo_desc)->buf_or_link_desc_addr_info))) 272 273 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 274 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 275 (((struct reo_destination_ring *) \ 276 reo_desc)->buf_or_link_desc_addr_info))) 277 278 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 279 (HAL_RX_BUF_COOKIE_GET(& \ 280 (((struct reo_destination_ring *) \ 281 reo_desc)->buf_or_link_desc_addr_info))) 282 283 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 284 ((mpdu_info_ptr \ 285 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 286 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 287 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 288 289 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 290 ((mpdu_info_ptr \ 291 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 292 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 293 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 294 295 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 296 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 297 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 298 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 299 300 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 301 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 302 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 303 304 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 305 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 306 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 307 308 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 309 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 310 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 311 312 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 313 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 314 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 315 316 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 317 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 318 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 319 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 320 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 321 322 323 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 324 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 325 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 326 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 327 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 328 329 /* 330 * NOTE: None of the following _GET macros need a right 331 * shift by the corresponding _LSB. This is because, they are 332 * finally taken and "OR'ed" into a single word again. 333 */ 334 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 335 ((*(((uint32_t *)msdu_info_ptr) + \ 336 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 337 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 338 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 339 340 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 341 ((*(((uint32_t *)msdu_info_ptr) + \ 342 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 343 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 344 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 345 346 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 347 ((*(((uint32_t *)msdu_info_ptr) + \ 348 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 349 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 350 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 351 352 353 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 354 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 355 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 356 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 357 358 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 359 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 360 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 361 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 362 363 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 364 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 365 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 366 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 367 368 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 369 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 370 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 371 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 372 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 373 374 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 375 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 376 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 377 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 378 379 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 380 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 381 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 382 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 383 384 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 385 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 386 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 387 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 388 389 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 390 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 391 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 392 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 393 394 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 395 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 396 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 397 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 398 399 400 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 401 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 402 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 403 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 404 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 405 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 406 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 407 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 408 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 409 410 411 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 412 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 413 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 414 RX_MPDU_INFO_4_PN_31_0_MASK, \ 415 RX_MPDU_INFO_4_PN_31_0_LSB)) 416 417 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 418 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 419 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 420 RX_MPDU_INFO_5_PN_63_32_MASK, \ 421 RX_MPDU_INFO_5_PN_63_32_LSB)) 422 423 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 424 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 425 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 426 RX_MPDU_INFO_6_PN_95_64_MASK, \ 427 RX_MPDU_INFO_6_PN_95_64_LSB)) 428 429 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 430 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 431 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 432 RX_MPDU_INFO_7_PN_127_96_MASK, \ 433 RX_MPDU_INFO_7_PN_127_96_LSB)) 434 435 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 436 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 437 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 438 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 439 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 440 441 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 442 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 443 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 444 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 445 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 446 447 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 448 (*(uint32_t *)(((uint8_t *)_ptr) + \ 449 _wrd ## _ ## _field ## _OFFSET) |= \ 450 ((_val << _wrd ## _ ## _field ## _LSB) & \ 451 _wrd ## _ ## _field ## _MASK)) 452 453 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 454 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 455 _field, _val) 456 457 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 458 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 459 _field, _val) 460 461 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 462 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 463 _field, _val) 464 465 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 466 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 467 { 468 struct reo_destination_ring *reo_dst_ring; 469 uint32_t mpdu_info[NUM_OF_DWORDS_RX_MPDU_DESC_INFO]; 470 471 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 472 473 qdf_mem_copy(&mpdu_info, 474 (const void *)&reo_dst_ring->rx_mpdu_desc_info_details, 475 sizeof(struct rx_mpdu_desc_info)); 476 477 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 478 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 479 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 480 mpdu_desc_info->peer_meta_data = 481 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 482 } 483 484 /* 485 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 486 * @ Specifically flags needed are: 487 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 488 * @ msdu_continuation, sa_is_valid, 489 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 490 * @ da_is_MCBC 491 * 492 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 493 * @ descriptor 494 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 495 * @ Return: void 496 */ 497 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 498 struct hal_rx_msdu_desc_info *msdu_desc_info) 499 { 500 struct reo_destination_ring *reo_dst_ring; 501 uint32_t msdu_info[NUM_OF_DWORDS_RX_MSDU_DESC_INFO]; 502 503 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 504 505 qdf_mem_copy(&msdu_info, 506 (const void *)&reo_dst_ring->rx_msdu_desc_info_details, 507 sizeof(struct rx_msdu_desc_info)); 508 509 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 510 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 511 } 512 513 /* 514 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 515 * rxdma ring entry. 516 * @rxdma_entry: descriptor entry 517 * @paddr: physical address of nbuf data pointer. 518 * @cookie: SW cookie used as a index to SW rx desc. 519 * @manager: who owns the nbuf (host, NSS, etc...). 520 * 521 */ 522 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 523 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 524 { 525 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 526 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 527 528 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 529 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 530 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 531 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 532 } 533 534 /* 535 * Structures & Macros to obtain fields from the TLV's in the Rx packet 536 * pre-header. 537 */ 538 539 /* 540 * Every Rx packet starts at an offset from the top of the buffer. 541 * If the host hasn't subscribed to any specific TLV, there is 542 * still space reserved for the following TLV's from the start of 543 * the buffer: 544 * -- RX ATTENTION 545 * -- RX MPDU START 546 * -- RX MSDU START 547 * -- RX MSDU END 548 * -- RX MPDU END 549 * -- RX PACKET HEADER (802.11) 550 * If the host subscribes to any of the TLV's above, that TLV 551 * if populated by the HW 552 */ 553 554 #define NUM_DWORDS_TAG 1 555 556 /* By default the packet header TLV is 128 bytes */ 557 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 558 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 559 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 560 561 #define RX_PKT_OFFSET_WORDS \ 562 ( \ 563 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 564 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 565 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 566 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 567 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 568 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 569 ) 570 571 #define RX_PKT_OFFSET_BYTES \ 572 (RX_PKT_OFFSET_WORDS << 2) 573 574 #define RX_PKT_HDR_TLV_LEN 120 575 576 /* 577 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 578 */ 579 struct rx_attention_tlv { 580 uint32_t tag; 581 struct rx_attention rx_attn; 582 }; 583 584 struct rx_mpdu_start_tlv { 585 uint32_t tag; 586 struct rx_mpdu_start rx_mpdu_start; 587 }; 588 589 struct rx_msdu_start_tlv { 590 uint32_t tag; 591 struct rx_msdu_start rx_msdu_start; 592 }; 593 594 struct rx_msdu_end_tlv { 595 uint32_t tag; 596 struct rx_msdu_end rx_msdu_end; 597 }; 598 599 struct rx_mpdu_end_tlv { 600 uint32_t tag; 601 struct rx_mpdu_end rx_mpdu_end; 602 }; 603 604 struct rx_pkt_hdr_tlv { 605 uint32_t tag; /* 4 B */ 606 uint32_t phy_ppdu_id; /* 4 B */ 607 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 608 }; 609 610 611 #define RXDMA_OPTIMIZATION 612 613 #ifdef RXDMA_OPTIMIZATION 614 /* 615 * The RX_PADDING_BYTES is required so that the TLV's don't 616 * spread across the 128 byte boundary 617 * RXDMA optimization requires: 618 * 1) MSDU_END & ATTENTION TLV's follow in that order 619 * 2) TLV's don't span across 128 byte lines 620 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 621 */ 622 #define RX_PADDING0_BYTES 4 623 #define RX_PADDING1_BYTES 16 624 struct rx_pkt_tlvs { 625 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 626 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 627 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 628 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 629 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 630 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 631 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 632 #ifndef NO_RX_PKT_HDR_TLV 633 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 634 #endif 635 }; 636 #else /* RXDMA_OPTIMIZATION */ 637 struct rx_pkt_tlvs { 638 struct rx_attention_tlv attn_tlv; 639 struct rx_mpdu_start_tlv mpdu_start_tlv; 640 struct rx_msdu_start_tlv msdu_start_tlv; 641 struct rx_msdu_end_tlv msdu_end_tlv; 642 struct rx_mpdu_end_tlv mpdu_end_tlv; 643 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 644 }; 645 #endif /* RXDMA_OPTIMIZATION */ 646 647 #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs)) 648 649 #ifdef NO_RX_PKT_HDR_TLV 650 static inline uint8_t 651 *hal_rx_pkt_hdr_get(uint8_t *buf) 652 { 653 return buf + RX_PKT_TLVS_LEN; 654 } 655 #else 656 static inline uint8_t 657 *hal_rx_pkt_hdr_get(uint8_t *buf) 658 { 659 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 660 661 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 662 663 } 664 #endif 665 666 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 667 668 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 669 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 670 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 671 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 672 RX_PKT_TLV_OFFSET(msdu_start_tlv) 673 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 674 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 675 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 676 677 static inline uint8_t 678 *hal_rx_padding0_get(uint8_t *buf) 679 { 680 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 681 682 return pkt_tlvs->rx_padding0; 683 } 684 685 /* 686 * @ hal_rx_encryption_info_valid: Returns encryption type. 687 * 688 * @ buf: rx_tlv_hdr of the received packet 689 * @ Return: encryption type 690 */ 691 static inline uint32_t 692 hal_rx_encryption_info_valid(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_mpdu_start *mpdu_start = 696 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 697 struct rx_mpdu_info *mpdu_info = &(mpdu_start->rx_mpdu_info_details); 698 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 699 700 return encryption_info; 701 } 702 703 /* 704 * @ hal_rx_print_pn: Prints the PN of rx packet. 705 * 706 * @ buf: rx_tlv_hdr of the received packet 707 * @ Return: void 708 */ 709 static inline void 710 hal_rx_print_pn(uint8_t *buf) 711 { 712 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 713 struct rx_mpdu_start *mpdu_start = 714 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 715 struct rx_mpdu_info *mpdu_info = &(mpdu_start->rx_mpdu_info_details); 716 717 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 718 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 719 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 720 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 721 722 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 723 "PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 724 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 725 } 726 727 /* 728 * Get msdu_done bit from the RX_ATTENTION TLV 729 */ 730 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 731 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 732 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 733 RX_ATTENTION_2_MSDU_DONE_MASK, \ 734 RX_ATTENTION_2_MSDU_DONE_LSB)) 735 736 static inline uint32_t 737 hal_rx_attn_msdu_done_get(uint8_t *buf) 738 { 739 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 740 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 741 uint32_t msdu_done; 742 743 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 744 745 return msdu_done; 746 } 747 748 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 749 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 750 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 751 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 752 RX_ATTENTION_1_FIRST_MPDU_LSB)) 753 754 /* 755 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 756 * @buf: pointer to rx_pkt_tlvs 757 * 758 * reutm: uint32_t(first_msdu) 759 */ 760 static inline uint32_t 761 hal_rx_attn_first_mpdu_get(uint8_t *buf) 762 { 763 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 764 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 765 uint32_t first_mpdu; 766 767 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 768 769 return first_mpdu; 770 } 771 772 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 773 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 774 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 775 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 776 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 777 778 /* 779 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 780 * from rx attention 781 * @buf: pointer to rx_pkt_tlvs 782 * 783 * Return: tcp_udp_cksum_fail 784 */ 785 static inline bool 786 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 787 { 788 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 789 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 790 bool tcp_udp_cksum_fail; 791 792 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 793 794 return tcp_udp_cksum_fail; 795 } 796 797 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 798 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 799 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 800 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 801 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 802 803 /* 804 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 805 * from rx attention 806 * @buf: pointer to rx_pkt_tlvs 807 * 808 * Return: ip_cksum_fail 809 */ 810 static inline bool 811 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 812 { 813 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 814 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 815 bool ip_cksum_fail; 816 817 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 818 819 return ip_cksum_fail; 820 } 821 822 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 823 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 824 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 825 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 826 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 827 828 /* 829 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 830 * from rx attention 831 * @buf: pointer to rx_pkt_tlvs 832 * 833 * Return: phy_ppdu_id 834 */ 835 static inline uint16_t 836 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 837 { 838 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 839 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 840 uint16_t phy_ppdu_id; 841 842 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 843 844 return phy_ppdu_id; 845 } 846 847 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 848 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 849 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 850 RX_ATTENTION_1_CCE_MATCH_MASK, \ 851 RX_ATTENTION_1_CCE_MATCH_LSB)) 852 853 /* 854 * hal_rx_msdu_cce_match_get(): get CCE match bit 855 * from rx attention 856 * @buf: pointer to rx_pkt_tlvs 857 * Return: CCE match value 858 */ 859 static inline bool 860 hal_rx_msdu_cce_match_get(uint8_t *buf) 861 { 862 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 863 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 864 bool cce_match_val; 865 866 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 867 return cce_match_val; 868 } 869 870 /* 871 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 872 */ 873 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 874 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 875 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 876 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 877 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 878 879 static inline uint32_t 880 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 881 { 882 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 883 struct rx_mpdu_start *mpdu_start = 884 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 885 886 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 887 uint32_t peer_meta_data; 888 889 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 890 891 return peer_meta_data; 892 } 893 894 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 895 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 896 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 897 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 898 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 899 /** 900 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 901 * from rx mpdu info 902 * @buf: pointer to rx_pkt_tlvs 903 * 904 * Return: ampdu flag 905 */ 906 static inline bool 907 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 908 { 909 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 910 struct rx_mpdu_start *mpdu_start = 911 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 912 913 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 914 bool ampdu_flag; 915 916 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 917 918 return ampdu_flag; 919 } 920 921 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 922 ((*(((uint32_t *)_rx_mpdu_info) + \ 923 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 924 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 925 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 926 927 /* 928 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 929 * 930 * @ buf: rx_tlv_hdr of the received packet 931 * @ peer_mdata: peer meta data to be set. 932 * @ Return: void 933 */ 934 static inline void 935 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 936 { 937 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 938 struct rx_mpdu_start *mpdu_start = 939 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 940 941 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 942 943 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 944 } 945 946 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 947 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 948 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 949 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 950 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 951 952 /** 953 * LRO information needed from the TLVs 954 */ 955 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 956 (_HAL_MS( \ 957 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 958 msdu_end_tlv.rx_msdu_end), \ 959 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 960 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 961 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 962 963 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 964 (_HAL_MS( \ 965 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 966 msdu_end_tlv.rx_msdu_end), \ 967 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 968 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 969 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 970 971 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 972 (_HAL_MS( \ 973 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 974 msdu_end_tlv.rx_msdu_end), \ 975 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 976 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 977 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 978 979 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 980 (_HAL_MS( \ 981 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 982 msdu_end_tlv.rx_msdu_end), \ 983 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 984 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 985 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 986 987 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 988 (_HAL_MS( \ 989 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 990 msdu_end_tlv.rx_msdu_end), \ 991 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 992 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 993 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 994 995 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 996 (_HAL_MS( \ 997 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 998 msdu_start_tlv.rx_msdu_start), \ 999 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 1000 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 1001 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 1002 1003 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 1004 (_HAL_MS( \ 1005 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1006 msdu_start_tlv.rx_msdu_start), \ 1007 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 1008 RX_MSDU_START_2_TCP_PROTO_MASK, \ 1009 RX_MSDU_START_2_TCP_PROTO_LSB)) 1010 1011 #define HAL_RX_TLV_GET_IPV6(buf) \ 1012 (_HAL_MS( \ 1013 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1014 msdu_start_tlv.rx_msdu_start), \ 1015 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 1016 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 1017 RX_MSDU_START_2_IPV6_PROTO_LSB)) 1018 1019 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 1020 (_HAL_MS( \ 1021 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1022 msdu_start_tlv.rx_msdu_start), \ 1023 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 1024 RX_MSDU_START_1_L3_OFFSET_MASK, \ 1025 RX_MSDU_START_1_L3_OFFSET_LSB)) 1026 1027 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 1028 (_HAL_MS( \ 1029 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1030 msdu_start_tlv.rx_msdu_start), \ 1031 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 1032 RX_MSDU_START_1_L4_OFFSET_MASK, \ 1033 RX_MSDU_START_1_L4_OFFSET_LSB)) 1034 1035 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 1036 (_HAL_MS( \ 1037 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1038 msdu_start_tlv.rx_msdu_start), \ 1039 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1040 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1041 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1042 1043 /** 1044 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 1045 * l3_header padding from rx_msdu_end TLV 1046 * 1047 * @ buf: pointer to the start of RX PKT TLV headers 1048 * Return: number of l3 header padding bytes 1049 */ 1050 static inline uint32_t 1051 hal_rx_msdu_end_l3_hdr_padding_get(uint8_t *buf) 1052 { 1053 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1054 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1055 uint32_t l3_header_padding; 1056 1057 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1058 1059 return l3_header_padding; 1060 } 1061 1062 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 1063 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1064 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 1065 RX_MSDU_END_13_SA_IDX_MASK, \ 1066 RX_MSDU_END_13_SA_IDX_LSB)) 1067 1068 /** 1069 * hal_rx_msdu_end_sa_idx_get(): API to get the 1070 * sa_idx from rx_msdu_end TLV 1071 * 1072 * @ buf: pointer to the start of RX PKT TLV headers 1073 * Return: sa_idx (SA AST index) 1074 */ 1075 static inline uint16_t 1076 hal_rx_msdu_end_sa_idx_get(uint8_t *buf) 1077 { 1078 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1079 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1080 uint16_t sa_idx; 1081 1082 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1083 1084 return sa_idx; 1085 } 1086 1087 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 1088 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1089 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 1090 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 1091 RX_MSDU_END_5_SA_IS_VALID_LSB)) 1092 1093 /** 1094 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1095 * sa_is_valid bit from rx_msdu_end TLV 1096 * 1097 * @ buf: pointer to the start of RX PKT TLV headers 1098 * Return: sa_is_valid bit 1099 */ 1100 static inline uint8_t 1101 hal_rx_msdu_end_sa_is_valid_get(uint8_t *buf) 1102 { 1103 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1104 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1105 uint8_t sa_is_valid; 1106 1107 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 1108 1109 return sa_is_valid; 1110 } 1111 1112 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 1113 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1114 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 1115 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 1116 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 1117 1118 /** 1119 * hal_rx_msdu_end_sa_sw_peer_id_get(): API to get the 1120 * sa_sw_peer_id from rx_msdu_end TLV 1121 * 1122 * @ buf: pointer to the start of RX PKT TLV headers 1123 * Return: sa_sw_peer_id index 1124 */ 1125 static inline uint32_t 1126 hal_rx_msdu_end_sa_sw_peer_id_get(uint8_t *buf) 1127 { 1128 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1129 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1130 uint32_t sa_sw_peer_id; 1131 1132 sa_sw_peer_id = HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1133 1134 return sa_sw_peer_id; 1135 } 1136 1137 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1138 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1139 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1140 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1141 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1142 1143 /** 1144 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1145 * from rx_msdu_start TLV 1146 * 1147 * @ buf: pointer to the start of RX PKT TLV headers 1148 * Return: msdu length 1149 */ 1150 static inline uint32_t 1151 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1152 { 1153 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1154 struct rx_msdu_start *msdu_start = 1155 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1156 uint32_t msdu_len; 1157 1158 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1159 1160 return msdu_len; 1161 } 1162 1163 /** 1164 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1165 * from rx_msdu_start TLV 1166 * 1167 * @buf: pointer to the start of RX PKT TLV headers 1168 * @len: msdu length 1169 * 1170 * Return: none 1171 */ 1172 static inline void 1173 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1174 { 1175 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1176 struct rx_msdu_start *msdu_start = 1177 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1178 void *wrd1; 1179 1180 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1181 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1182 *(uint32_t *)wrd1 |= len; 1183 } 1184 1185 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1186 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1187 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1188 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1189 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1190 1191 /* 1192 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1193 * Interval from rx_msdu_start 1194 * 1195 * @buf: pointer to the start of RX PKT TLV header 1196 * Return: uint32_t(bw) 1197 */ 1198 static inline uint32_t 1199 hal_rx_msdu_start_bw_get(uint8_t *buf) 1200 { 1201 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1202 struct rx_msdu_start *msdu_start = 1203 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1204 uint32_t bw; 1205 1206 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1207 1208 return bw; 1209 } 1210 1211 1212 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1214 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1215 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1216 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1217 1218 /** 1219 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1220 * from rx_msdu_start TLV 1221 * 1222 * @ buf: pointer to the start of RX PKT TLV headers 1223 * Return: toeplitz hash 1224 */ 1225 static inline uint32_t 1226 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1227 { 1228 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1229 struct rx_msdu_start *msdu_start = 1230 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1231 1232 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1233 } 1234 1235 /* 1236 * Get qos_control_valid from RX_MPDU_START 1237 */ 1238 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 1239 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 1240 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 1241 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 1242 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 1243 1244 static inline uint32_t 1245 hal_rx_mpdu_start_mpdu_qos_control_valid_get(uint8_t *buf) 1246 { 1247 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1248 struct rx_mpdu_start *mpdu_start = 1249 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1250 uint32_t qos_control_valid; 1251 1252 qos_control_valid = HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1253 &(mpdu_start->rx_mpdu_info_details)); 1254 1255 return qos_control_valid; 1256 } 1257 1258 1259 /* 1260 * Get SW peer id from RX_MPDU_START 1261 */ 1262 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 1263 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 1264 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 1265 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 1266 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 1267 1268 static inline uint32_t 1269 hal_rx_mpdu_start_sw_peer_id_get(uint8_t *buf) 1270 { 1271 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1272 struct rx_mpdu_start *mpdu_start = 1273 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1274 uint32_t sw_peer_id; 1275 1276 sw_peer_id = HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 1277 &(mpdu_start->rx_mpdu_info_details)); 1278 1279 return sw_peer_id; 1280 } 1281 1282 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1283 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1284 RX_MSDU_START_5_SGI_OFFSET)), \ 1285 RX_MSDU_START_5_SGI_MASK, \ 1286 RX_MSDU_START_5_SGI_LSB)) 1287 /** 1288 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1289 * Interval from rx_msdu_start TLV 1290 * 1291 * @buf: pointer to the start of RX PKT TLV headers 1292 * Return: uint32_t(sgi) 1293 */ 1294 static inline uint32_t 1295 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1296 { 1297 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1298 struct rx_msdu_start *msdu_start = 1299 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1300 uint32_t sgi; 1301 1302 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1303 1304 return sgi; 1305 } 1306 1307 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1308 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1309 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1310 RX_MSDU_START_5_RATE_MCS_MASK, \ 1311 RX_MSDU_START_5_RATE_MCS_LSB)) 1312 /** 1313 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1314 * from rx_msdu_start TLV 1315 * 1316 * @buf: pointer to the start of RX PKT TLV headers 1317 * Return: uint32_t(rate_mcs) 1318 */ 1319 static inline uint32_t 1320 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1321 { 1322 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1323 struct rx_msdu_start *msdu_start = 1324 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1325 uint32_t rate_mcs; 1326 1327 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1328 1329 return rate_mcs; 1330 } 1331 1332 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1333 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1334 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1335 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1336 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1337 1338 /* 1339 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1340 * packet from rx_attention 1341 * 1342 * @buf: pointer to the start of RX PKT TLV header 1343 * Return: uint32_t(decryt status) 1344 */ 1345 1346 static inline uint32_t 1347 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1348 { 1349 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1350 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1351 uint32_t is_decrypt = 0; 1352 uint32_t decrypt_status; 1353 1354 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1355 1356 if (!decrypt_status) 1357 is_decrypt = 1; 1358 1359 return is_decrypt; 1360 } 1361 1362 /* 1363 * Get key index from RX_MSDU_END 1364 */ 1365 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1366 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1367 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1368 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1369 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1370 /* 1371 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1372 * from rx_msdu_end 1373 * 1374 * @buf: pointer to the start of RX PKT TLV header 1375 * Return: uint32_t(key id) 1376 */ 1377 1378 static inline uint32_t 1379 hal_rx_msdu_get_keyid(uint8_t *buf) 1380 { 1381 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1382 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1383 uint32_t keyid_octet; 1384 1385 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1386 1387 return keyid_octet & 0x3; 1388 } 1389 1390 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1391 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1392 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1393 RX_MSDU_START_5_USER_RSSI_MASK, \ 1394 RX_MSDU_START_5_USER_RSSI_LSB)) 1395 /* 1396 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1397 * from rx_msdu_start 1398 * 1399 * @buf: pointer to the start of RX PKT TLV header 1400 * Return: uint32_t(rssi) 1401 */ 1402 1403 static inline uint32_t 1404 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1405 { 1406 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1407 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1408 uint32_t rssi; 1409 1410 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1411 1412 return rssi; 1413 1414 } 1415 1416 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1417 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1418 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1419 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1420 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1421 1422 /* 1423 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1424 * from rx_msdu_start 1425 * 1426 * @buf: pointer to the start of RX PKT TLV header 1427 * Return: uint32_t(frequency) 1428 */ 1429 1430 static inline uint32_t 1431 hal_rx_msdu_start_get_freq(uint8_t *buf) 1432 { 1433 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1434 struct rx_msdu_start *msdu_start = 1435 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1436 uint32_t freq; 1437 1438 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1439 1440 return freq; 1441 } 1442 1443 1444 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1445 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1446 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1447 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1448 RX_MSDU_START_5_PKT_TYPE_LSB)) 1449 1450 /* 1451 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1452 * from rx_msdu_start 1453 * 1454 * @buf: pointer to the start of RX PKT TLV header 1455 * Return: uint32_t(pkt type) 1456 */ 1457 1458 static inline uint32_t 1459 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1460 { 1461 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1462 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1463 uint32_t pkt_type; 1464 1465 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1466 1467 return pkt_type; 1468 } 1469 1470 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 1471 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1472 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 1473 RX_MPDU_INFO_2_TO_DS_MASK, \ 1474 RX_MPDU_INFO_2_TO_DS_LSB)) 1475 1476 /* 1477 * hal_rx_mpdu_get_tods(): API to get the tods info 1478 * from rx_mpdu_start 1479 * 1480 * @buf: pointer to the start of RX PKT TLV header 1481 * Return: uint32_t(to_ds) 1482 */ 1483 1484 static inline uint32_t 1485 hal_rx_mpdu_get_to_ds(uint8_t *buf) 1486 { 1487 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1488 struct rx_mpdu_start *mpdu_start = 1489 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1490 1491 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1492 uint32_t to_ds; 1493 1494 to_ds = HAL_RX_MPDU_GET_TODS(mpdu_info); 1495 1496 return to_ds; 1497 } 1498 1499 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 1500 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1501 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 1502 RX_MPDU_INFO_2_FR_DS_MASK, \ 1503 RX_MPDU_INFO_2_FR_DS_LSB)) 1504 1505 /* 1506 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1507 * from rx_mpdu_start 1508 * 1509 * @buf: pointer to the start of RX PKT TLV header 1510 * Return: uint32_t(fr_ds) 1511 */ 1512 1513 static inline uint32_t 1514 hal_rx_mpdu_get_fr_ds(uint8_t *buf) 1515 { 1516 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1517 struct rx_mpdu_start *mpdu_start = 1518 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1519 1520 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1521 uint32_t fr_ds; 1522 1523 fr_ds = HAL_RX_MPDU_GET_FROMDS(mpdu_info); 1524 1525 return fr_ds; 1526 } 1527 1528 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 1529 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1530 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 1531 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 1532 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 1533 1534 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 1535 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1536 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 1537 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 1538 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 1539 1540 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 1541 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1542 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 1543 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 1544 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 1545 1546 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 1547 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1548 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 1549 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 1550 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 1551 1552 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 1553 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1554 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 1555 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 1556 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 1557 1558 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 1559 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1560 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 1561 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 1562 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 1563 1564 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 1565 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1566 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 1567 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 1568 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 1569 1570 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 1571 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1572 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 1573 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 1574 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 1575 1576 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 1577 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1578 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 1579 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 1580 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 1581 1582 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 1583 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1584 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 1585 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 1586 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 1587 1588 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1589 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1590 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1591 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1592 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1593 1594 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1595 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1596 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1597 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1598 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1599 1600 /* 1601 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1602 * 1603 * @buf: pointer to the start of RX PKT TLV headera 1604 * @mac_addr: pointer to mac address 1605 * Return: success/failure 1606 */ 1607 static inline 1608 QDF_STATUS hal_rx_mpdu_get_addr1(uint8_t *buf, uint8_t *mac_addr) 1609 { 1610 struct __attribute__((__packed__)) hal_addr1 { 1611 uint32_t ad1_31_0; 1612 uint16_t ad1_47_32; 1613 }; 1614 1615 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1616 struct rx_mpdu_start *mpdu_start = 1617 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1618 1619 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1620 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 1621 uint32_t mac_addr_ad1_valid; 1622 1623 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 1624 1625 if (mac_addr_ad1_valid) { 1626 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 1627 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 1628 return QDF_STATUS_SUCCESS; 1629 } 1630 1631 return QDF_STATUS_E_FAILURE; 1632 } 1633 1634 /* 1635 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1636 * in the packet 1637 * 1638 * @buf: pointer to the start of RX PKT TLV header 1639 * @mac_addr: pointer to mac address 1640 * Return: success/failure 1641 */ 1642 static inline 1643 QDF_STATUS hal_rx_mpdu_get_addr2(uint8_t *buf, uint8_t *mac_addr) 1644 { 1645 struct __attribute__((__packed__)) hal_addr2 { 1646 uint16_t ad2_15_0; 1647 uint32_t ad2_47_16; 1648 }; 1649 1650 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1651 struct rx_mpdu_start *mpdu_start = 1652 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1653 1654 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1655 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 1656 uint32_t mac_addr_ad2_valid; 1657 1658 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 1659 1660 if (mac_addr_ad2_valid) { 1661 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 1662 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 1663 return QDF_STATUS_SUCCESS; 1664 } 1665 1666 return QDF_STATUS_E_FAILURE; 1667 } 1668 1669 /* 1670 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1671 * in the packet 1672 * 1673 * @buf: pointer to the start of RX PKT TLV header 1674 * @mac_addr: pointer to mac address 1675 * Return: success/failure 1676 */ 1677 static inline 1678 QDF_STATUS hal_rx_mpdu_get_addr3(uint8_t *buf, uint8_t *mac_addr) 1679 { 1680 struct __attribute__((__packed__)) hal_addr3 { 1681 uint32_t ad3_31_0; 1682 uint16_t ad3_47_32; 1683 }; 1684 1685 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1686 struct rx_mpdu_start *mpdu_start = 1687 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1688 1689 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1690 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1691 uint32_t mac_addr_ad3_valid; 1692 1693 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1694 1695 if (mac_addr_ad3_valid) { 1696 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1697 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1698 return QDF_STATUS_SUCCESS; 1699 } 1700 1701 return QDF_STATUS_E_FAILURE; 1702 } 1703 1704 /* 1705 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1706 * in the packet 1707 * 1708 * @buf: pointer to the start of RX PKT TLV header 1709 * @mac_addr: pointer to mac address 1710 * Return: success/failure 1711 */ 1712 static inline 1713 QDF_STATUS hal_rx_mpdu_get_addr4(uint8_t *buf, uint8_t *mac_addr) 1714 { 1715 struct __attribute__((__packed__)) hal_addr4 { 1716 uint32_t ad4_31_0; 1717 uint16_t ad4_47_32; 1718 }; 1719 1720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1721 struct rx_mpdu_start *mpdu_start = 1722 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1723 1724 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1725 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1726 uint32_t mac_addr_ad4_valid; 1727 1728 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1729 1730 if (mac_addr_ad4_valid) { 1731 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1732 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1733 return QDF_STATUS_SUCCESS; 1734 } 1735 1736 return QDF_STATUS_E_FAILURE; 1737 } 1738 1739 /** 1740 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1741 * from rx_msdu_end TLV 1742 * 1743 * @ buf: pointer to the start of RX PKT TLV headers 1744 * Return: da index 1745 */ 1746 static inline uint16_t 1747 hal_rx_msdu_end_da_idx_get(struct hal_soc *hal_soc, uint8_t *buf) 1748 { 1749 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1750 } 1751 1752 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 1753 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1754 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 1755 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 1756 RX_MSDU_END_5_DA_IS_VALID_LSB)) 1757 1758 /** 1759 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1760 * from rx_msdu_end TLV 1761 * 1762 * @ buf: pointer to the start of RX PKT TLV headers 1763 * Return: da_is_valid 1764 */ 1765 static inline uint8_t 1766 hal_rx_msdu_end_da_is_valid_get(uint8_t *buf) 1767 { 1768 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1769 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1770 uint8_t da_is_valid; 1771 1772 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 1773 1774 return da_is_valid; 1775 } 1776 1777 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 1778 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1779 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 1780 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 1781 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 1782 1783 /** 1784 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1785 * from rx_msdu_end TLV 1786 * 1787 * @ buf: pointer to the start of RX PKT TLV headers 1788 * Return: da_is_mcbc 1789 */ 1790 static inline uint8_t 1791 hal_rx_msdu_end_da_is_mcbc_get(uint8_t *buf) 1792 { 1793 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1794 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1795 uint8_t da_is_mcbc; 1796 1797 da_is_mcbc = HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 1798 1799 return da_is_mcbc; 1800 } 1801 1802 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 1803 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1804 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 1805 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 1806 RX_MSDU_END_5_FIRST_MSDU_LSB)) 1807 1808 /** 1809 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1810 * from rx_msdu_end TLV 1811 * 1812 * @ buf: pointer to the start of RX PKT TLV headers 1813 * Return: first_msdu 1814 */ 1815 static inline uint8_t 1816 hal_rx_msdu_end_first_msdu_get(uint8_t *buf) 1817 { 1818 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1819 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1820 uint8_t first_msdu; 1821 1822 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 1823 1824 return first_msdu; 1825 } 1826 1827 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 1828 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1829 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 1830 RX_MSDU_END_5_LAST_MSDU_MASK, \ 1831 RX_MSDU_END_5_LAST_MSDU_LSB)) 1832 1833 /** 1834 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1835 * from rx_msdu_end TLV 1836 * 1837 * @ buf: pointer to the start of RX PKT TLV headers 1838 * Return: last_msdu 1839 */ 1840 static inline uint8_t 1841 hal_rx_msdu_end_last_msdu_get(uint8_t *buf) 1842 { 1843 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1844 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1845 uint8_t last_msdu; 1846 1847 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 1848 1849 return last_msdu; 1850 } 1851 1852 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 1853 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1854 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 1855 RX_MSDU_END_16_CCE_METADATA_MASK, \ 1856 RX_MSDU_END_16_CCE_METADATA_LSB)) 1857 1858 /** 1859 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1860 * from rx_msdu_end TLV 1861 * @ buf: pointer to the start of RX PKT TLV headers 1862 * Return: last_msdu 1863 */ 1864 1865 static inline uint32_t 1866 hal_rx_msdu_cce_metadata_get(uint8_t *buf) 1867 { 1868 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1869 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1870 uint32_t cce_metadata; 1871 1872 cce_metadata = HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1873 return cce_metadata; 1874 } 1875 1876 /******************************************************************************* 1877 * RX ERROR APIS 1878 ******************************************************************************/ 1879 1880 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1881 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1882 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1883 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1884 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1885 1886 /** 1887 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1888 * from rx_mpdu_end TLV 1889 * 1890 * @buf: pointer to the start of RX PKT TLV headers 1891 * Return: uint32_t(decrypt_err) 1892 */ 1893 static inline uint32_t 1894 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1895 { 1896 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1897 struct rx_mpdu_end *mpdu_end = 1898 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1899 uint32_t decrypt_err; 1900 1901 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1902 1903 return decrypt_err; 1904 } 1905 1906 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1907 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1908 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1909 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1910 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1911 1912 /** 1913 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1914 * from rx_mpdu_end TLV 1915 * 1916 * @buf: pointer to the start of RX PKT TLV headers 1917 * Return: uint32_t(mic_err) 1918 */ 1919 static inline uint32_t 1920 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1921 { 1922 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1923 struct rx_mpdu_end *mpdu_end = 1924 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1925 uint32_t mic_err; 1926 1927 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1928 1929 return mic_err; 1930 } 1931 1932 /******************************************************************************* 1933 * RX REO ERROR APIS 1934 ******************************************************************************/ 1935 1936 #define HAL_RX_NUM_MSDU_DESC 6 1937 #define HAL_RX_MAX_SAVED_RING_DESC 16 1938 1939 /* TODO: rework the structure */ 1940 struct hal_rx_msdu_list { 1941 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1942 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1943 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1944 /* physical address of the msdu */ 1945 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1946 }; 1947 1948 struct hal_buf_info { 1949 uint64_t paddr; 1950 uint32_t sw_cookie; 1951 }; 1952 1953 /** 1954 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1955 * @msdu_link_ptr - msdu link ptr 1956 * @hal - pointer to hal_soc 1957 * Return - Pointer to rx_msdu_details structure 1958 * 1959 */ 1960 static inline void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, void *hal) 1961 { 1962 struct hal_soc *hal_soc = (struct hal_soc *)hal; 1963 1964 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1965 } 1966 1967 /** 1968 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1969 * @msdu_details_ptr - Pointer to msdu_details_ptr 1970 * @hal - pointer to hal_soc 1971 * Return - Pointer to rx_msdu_desc_info structure. 1972 * 1973 */ 1974 static inline void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, void *hal) 1975 { 1976 struct hal_soc *hal_soc = (struct hal_soc *)hal; 1977 1978 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1979 } 1980 1981 /* This special cookie value will be used to indicate FW allocated buffers 1982 * received through RXDMA2SW ring for RXDMA WARs 1983 */ 1984 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1985 1986 /** 1987 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1988 * from the MSDU link descriptor 1989 * 1990 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1991 * MSDU link descriptor (struct rx_msdu_link) 1992 * 1993 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1994 * 1995 * @num_msdus: Number of MSDUs in the MPDU 1996 * 1997 * Return: void 1998 */ 1999 static inline void hal_rx_msdu_list_get(struct hal_soc *hal_soc, 2000 void *msdu_link_desc, 2001 struct hal_rx_msdu_list *msdu_list, 2002 uint16_t *num_msdus) 2003 { 2004 struct rx_msdu_details *msdu_details; 2005 struct rx_msdu_desc_info *msdu_desc_info; 2006 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 2007 int i; 2008 2009 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 2010 2011 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2012 "[%s][%d] msdu_link=%pK msdu_details=%pK", 2013 __func__, __LINE__, msdu_link, msdu_details); 2014 2015 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 2016 /* num_msdus received in mpdu descriptor may be incorrect 2017 * sometimes due to HW issue. Check msdu buffer address also 2018 */ 2019 if (HAL_RX_BUFFER_ADDR_31_0_GET( 2020 &msdu_details[i].buffer_addr_info_details) == 0) { 2021 /* set the last msdu bit in the prev msdu_desc_info */ 2022 msdu_desc_info = 2023 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 2024 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 2025 break; 2026 } 2027 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 2028 hal_soc); 2029 2030 /* set first MSDU bit or the last MSDU bit */ 2031 if (!i) 2032 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 2033 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 2034 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 2035 2036 msdu_list->msdu_info[i].msdu_flags = 2037 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2038 msdu_list->msdu_info[i].msdu_len = 2039 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2040 msdu_list->sw_cookie[i] = 2041 HAL_RX_BUF_COOKIE_GET( 2042 &msdu_details[i].buffer_addr_info_details); 2043 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 2044 &msdu_details[i].buffer_addr_info_details); 2045 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 2046 &msdu_details[i].buffer_addr_info_details) | 2047 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 2048 &msdu_details[i].buffer_addr_info_details) << 32; 2049 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2050 "[%s][%d] i=%d sw_cookie=%d", 2051 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 2052 } 2053 *num_msdus = i; 2054 } 2055 2056 /** 2057 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 2058 * destination ring ID from the msdu desc info 2059 * 2060 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 2061 * the current descriptor 2062 * 2063 * Return: dst_ind (REO destination ring ID) 2064 */ 2065 static inline uint32_t 2066 hal_rx_msdu_reo_dst_ind_get(struct hal_soc *hal_soc, void *msdu_link_desc) 2067 { 2068 struct rx_msdu_details *msdu_details; 2069 struct rx_msdu_desc_info *msdu_desc_info; 2070 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 2071 uint32_t dst_ind; 2072 2073 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 2074 2075 /* The first msdu in the link should exsist */ 2076 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 2077 hal_soc); 2078 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 2079 return dst_ind; 2080 } 2081 2082 /** 2083 * hal_rx_reo_buf_paddr_get: Gets the physical address and 2084 * cookie from the REO destination ring element 2085 * 2086 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 2087 * the current descriptor 2088 * @ buf_info: structure to return the buffer information 2089 * Return: void 2090 */ 2091 static inline void hal_rx_reo_buf_paddr_get(void *rx_desc, 2092 struct hal_buf_info *buf_info) 2093 { 2094 struct reo_destination_ring *reo_ring = 2095 (struct reo_destination_ring *)rx_desc; 2096 2097 buf_info->paddr = 2098 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 2099 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 2100 2101 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 2102 } 2103 2104 /** 2105 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 2106 * 2107 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 2108 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 2109 * descriptor 2110 */ 2111 enum hal_rx_reo_buf_type { 2112 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 2113 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 2114 }; 2115 2116 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2117 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 2118 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 2119 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 2120 2121 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 2122 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 2123 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 2124 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 2125 2126 /** 2127 * enum hal_reo_error_code: Error code describing the type of error detected 2128 * 2129 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 2130 * REO_ENTRANCE ring is set to 0 2131 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 2132 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 2133 * having been setup 2134 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 2135 * Retry bit set: duplicate frame 2136 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 2137 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 2138 * received with 2K jump in SN 2139 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 2140 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 2141 * with SN falling within the OOR window 2142 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 2143 * OOR window 2144 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 2145 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 2146 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 2147 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2148 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 2149 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2150 * of the pn_error_detected_flag been set in the REO Queue descriptor 2151 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 2152 * the queue descriptor(address) being blocked as SW/FW seems to be currently 2153 * in the process of making updates to this descriptor 2154 */ 2155 enum hal_reo_error_code { 2156 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 2157 HAL_REO_ERR_QUEUE_DESC_INVALID, 2158 HAL_REO_ERR_AMPDU_IN_NON_BA, 2159 HAL_REO_ERR_NON_BA_DUPLICATE, 2160 HAL_REO_ERR_BA_DUPLICATE, 2161 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 2162 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 2163 HAL_REO_ERR_REGULAR_FRAME_OOR, 2164 HAL_REO_ERR_BAR_FRAME_OOR, 2165 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 2166 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 2167 HAL_REO_ERR_PN_CHECK_FAILED, 2168 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 2169 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 2170 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 2171 HAL_REO_ERR_MAX 2172 }; 2173 2174 /** 2175 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 2176 * 2177 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 2178 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 2179 * overflow 2180 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 2181 * incomplete 2182 * MPDU from the PHY 2183 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 2184 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 2185 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 2186 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 2187 * encrypted but wasn’t 2188 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 2189 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 2190 * the max allowed 2191 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2192 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2193 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2194 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2195 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2196 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2197 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2198 */ 2199 enum hal_rxdma_error_code { 2200 HAL_RXDMA_ERR_OVERFLOW = 0, 2201 HAL_RXDMA_ERR_MPDU_LENGTH, 2202 HAL_RXDMA_ERR_FCS, 2203 HAL_RXDMA_ERR_DECRYPT, 2204 HAL_RXDMA_ERR_TKIP_MIC, 2205 HAL_RXDMA_ERR_UNENCRYPTED, 2206 HAL_RXDMA_ERR_MSDU_LEN, 2207 HAL_RXDMA_ERR_MSDU_LIMIT, 2208 HAL_RXDMA_ERR_WIFI_PARSE, 2209 HAL_RXDMA_ERR_AMSDU_PARSE, 2210 HAL_RXDMA_ERR_SA_TIMEOUT, 2211 HAL_RXDMA_ERR_DA_TIMEOUT, 2212 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2213 HAL_RXDMA_ERR_FLUSH_REQUEST, 2214 HAL_RXDMA_ERR_WAR = 31, 2215 HAL_RXDMA_ERR_MAX 2216 }; 2217 2218 /** 2219 * HW BM action settings in WBM release ring 2220 */ 2221 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2222 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2223 2224 /** 2225 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2226 * release of this buffer or descriptor 2227 * 2228 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2229 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2230 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2231 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2232 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2233 */ 2234 enum hal_rx_wbm_error_source { 2235 HAL_RX_WBM_ERR_SRC_TQM = 0, 2236 HAL_RX_WBM_ERR_SRC_RXDMA, 2237 HAL_RX_WBM_ERR_SRC_REO, 2238 HAL_RX_WBM_ERR_SRC_FW, 2239 HAL_RX_WBM_ERR_SRC_SW, 2240 }; 2241 2242 /** 2243 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2244 * released 2245 * 2246 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2247 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2248 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2249 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2250 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2251 */ 2252 enum hal_rx_wbm_buf_type { 2253 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2254 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2255 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2256 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2257 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2258 }; 2259 2260 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2261 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2262 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2263 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2264 2265 /** 2266 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2267 * PN check failure 2268 * 2269 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2270 * 2271 * Return: true: error caused by PN check, false: other error 2272 */ 2273 static inline bool hal_rx_reo_is_pn_error(void *rx_desc) 2274 { 2275 struct reo_destination_ring *reo_desc = 2276 (struct reo_destination_ring *)rx_desc; 2277 2278 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2279 HAL_REO_ERR_PN_CHECK_FAILED) | 2280 (HAL_RX_REO_ERROR_GET(reo_desc) == 2281 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2282 true : false; 2283 } 2284 2285 /** 2286 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2287 * the sequence number 2288 * 2289 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2290 * 2291 * Return: true: error caused by 2K jump, false: other error 2292 */ 2293 static inline bool hal_rx_reo_is_2k_jump(void *rx_desc) 2294 { 2295 struct reo_destination_ring *reo_desc = 2296 (struct reo_destination_ring *)rx_desc; 2297 2298 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2299 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2300 (HAL_RX_REO_ERROR_GET(reo_desc) == 2301 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2302 true : false; 2303 } 2304 2305 /** 2306 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2307 * 2308 * @ soc : HAL version of the SOC pointer 2309 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2310 * @ buf_addr_info : void pointer to the buffer_addr_info 2311 * @ bm_action : put in IDLE list or release to MSDU_LIST 2312 * 2313 * Return: void 2314 */ 2315 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2316 static inline void hal_rx_msdu_link_desc_set(struct hal_soc *soc, 2317 void *src_srng_desc, void *buf_addr_info, 2318 uint8_t bm_action) 2319 { 2320 struct wbm_release_ring *wbm_rel_srng = 2321 (struct wbm_release_ring *)src_srng_desc; 2322 2323 /* Structure copy !!! */ 2324 wbm_rel_srng->released_buff_or_desc_addr_info = 2325 *((struct buffer_addr_info *)buf_addr_info); 2326 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2327 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2328 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2329 bm_action); 2330 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2331 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2332 } 2333 2334 /* 2335 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2336 * REO entrance ring 2337 * 2338 * @ soc: HAL version of the SOC pointer 2339 * @ pa: Physical address of the MSDU Link Descriptor 2340 * @ cookie: SW cookie to get to the virtual address 2341 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2342 * to the error enabled REO queue 2343 * 2344 * Return: void 2345 */ 2346 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2347 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2348 { 2349 /* TODO */ 2350 } 2351 2352 /** 2353 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2354 * BUFFER_ADDR_INFO, give the RX descriptor 2355 * (Assumption -- BUFFER_ADDR_INFO is the 2356 * first field in the descriptor structure) 2357 */ 2358 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) ((void *)(ring_desc)) 2359 2360 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2361 2362 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2363 2364 /** 2365 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2366 * from the BUFFER_ADDR_INFO structure 2367 * given a REO destination ring descriptor. 2368 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2369 * 2370 * Return: uint8_t (value of the return_buffer_manager) 2371 */ 2372 static inline 2373 uint8_t hal_rx_ret_buf_manager_get(void *ring_desc) 2374 { 2375 /* 2376 * The following macro takes buf_addr_info as argument, 2377 * but since buf_addr_info is the first field in ring_desc 2378 * Hence the following call is OK 2379 */ 2380 return HAL_RX_BUF_RBM_GET(ring_desc); 2381 } 2382 2383 2384 /******************************************************************************* 2385 * RX WBM ERROR APIS 2386 ******************************************************************************/ 2387 2388 2389 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2390 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2391 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2392 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2393 2394 /** 2395 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2396 * the frame to this release ring 2397 * 2398 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2399 * frame to this queue 2400 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2401 * received routing instructions. No error within REO was detected 2402 */ 2403 enum hal_rx_wbm_reo_push_reason { 2404 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2405 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2406 }; 2407 2408 2409 /** 2410 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2411 * this release ring 2412 * 2413 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2414 * this frame to this queue 2415 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2416 * per received routing instructions. No error within RXDMA was detected 2417 */ 2418 enum hal_rx_wbm_rxdma_push_reason { 2419 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2420 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2421 }; 2422 2423 2424 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2425 (((*(((uint32_t *) wbm_desc) + \ 2426 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2427 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2428 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2429 2430 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2431 (((*(((uint32_t *) wbm_desc) + \ 2432 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2433 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2434 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2435 2436 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2437 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2438 wbm_desc)->released_buff_or_desc_addr_info) 2439 2440 /** 2441 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2442 * humman readable format. 2443 * @ rx_attn: pointer the rx_attention TLV in pkt. 2444 * @ dbg_level: log level. 2445 * 2446 * Return: void 2447 */ 2448 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2449 uint8_t dbg_level) 2450 { 2451 hal_verbose_debug( 2452 "rx_attention tlv (1/2) - " 2453 "rxpcu_mpdu_filter_in_category: %x " 2454 "sw_frame_group_id: %x " 2455 "reserved_0: %x " 2456 "phy_ppdu_id: %x " 2457 "first_mpdu : %x " 2458 "reserved_1a: %x " 2459 "mcast_bcast: %x " 2460 "ast_index_not_found: %x " 2461 "ast_index_timeout: %x " 2462 "power_mgmt: %x " 2463 "non_qos: %x " 2464 "null_data: %x " 2465 "mgmt_type: %x " 2466 "ctrl_type: %x " 2467 "more_data: %x " 2468 "eosp: %x " 2469 "a_msdu_error: %x " 2470 "fragment_flag: %x " 2471 "order: %x " 2472 "cce_match: %x " 2473 "overflow_err: %x " 2474 "msdu_length_err: %x " 2475 "tcp_udp_chksum_fail: %x " 2476 "ip_chksum_fail: %x " 2477 "sa_idx_invalid: %x " 2478 "da_idx_invalid: %x " 2479 "reserved_1b: %x " 2480 "rx_in_tx_decrypt_byp: %x ", 2481 rx_attn->rxpcu_mpdu_filter_in_category, 2482 rx_attn->sw_frame_group_id, 2483 rx_attn->reserved_0, 2484 rx_attn->phy_ppdu_id, 2485 rx_attn->first_mpdu, 2486 rx_attn->reserved_1a, 2487 rx_attn->mcast_bcast, 2488 rx_attn->ast_index_not_found, 2489 rx_attn->ast_index_timeout, 2490 rx_attn->power_mgmt, 2491 rx_attn->non_qos, 2492 rx_attn->null_data, 2493 rx_attn->mgmt_type, 2494 rx_attn->ctrl_type, 2495 rx_attn->more_data, 2496 rx_attn->eosp, 2497 rx_attn->a_msdu_error, 2498 rx_attn->fragment_flag, 2499 rx_attn->order, 2500 rx_attn->cce_match, 2501 rx_attn->overflow_err, 2502 rx_attn->msdu_length_err, 2503 rx_attn->tcp_udp_chksum_fail, 2504 rx_attn->ip_chksum_fail, 2505 rx_attn->sa_idx_invalid, 2506 rx_attn->da_idx_invalid, 2507 rx_attn->reserved_1b, 2508 rx_attn->rx_in_tx_decrypt_byp); 2509 2510 hal_verbose_debug( 2511 "rx_attention tlv (2/2) - " 2512 "encrypt_required: %x " 2513 "directed: %x " 2514 "buffer_fragment: %x " 2515 "mpdu_length_err: %x " 2516 "tkip_mic_err: %x " 2517 "decrypt_err: %x " 2518 "unencrypted_frame_err: %x " 2519 "fcs_err: %x " 2520 "flow_idx_timeout: %x " 2521 "flow_idx_invalid: %x " 2522 "wifi_parser_error: %x " 2523 "amsdu_parser_error: %x " 2524 "sa_idx_timeout: %x " 2525 "da_idx_timeout: %x " 2526 "msdu_limit_error: %x " 2527 "da_is_valid: %x " 2528 "da_is_mcbc: %x " 2529 "sa_is_valid: %x " 2530 "decrypt_status_code: %x " 2531 "rx_bitmap_not_updated: %x " 2532 "reserved_2: %x " 2533 "msdu_done: %x ", 2534 rx_attn->encrypt_required, 2535 rx_attn->directed, 2536 rx_attn->buffer_fragment, 2537 rx_attn->mpdu_length_err, 2538 rx_attn->tkip_mic_err, 2539 rx_attn->decrypt_err, 2540 rx_attn->unencrypted_frame_err, 2541 rx_attn->fcs_err, 2542 rx_attn->flow_idx_timeout, 2543 rx_attn->flow_idx_invalid, 2544 rx_attn->wifi_parser_error, 2545 rx_attn->amsdu_parser_error, 2546 rx_attn->sa_idx_timeout, 2547 rx_attn->da_idx_timeout, 2548 rx_attn->msdu_limit_error, 2549 rx_attn->da_is_valid, 2550 rx_attn->da_is_mcbc, 2551 rx_attn->sa_is_valid, 2552 rx_attn->decrypt_status_code, 2553 rx_attn->rx_bitmap_not_updated, 2554 rx_attn->reserved_2, 2555 rx_attn->msdu_done); 2556 } 2557 2558 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2559 uint8_t dbg_level, 2560 struct hal_soc *hal) 2561 { 2562 2563 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2564 } 2565 /** 2566 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2567 * human readable format. 2568 * @ msdu_end: pointer the msdu_end TLV in pkt. 2569 * @ dbg_level: log level. 2570 * 2571 * Return: void 2572 */ 2573 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2574 struct rx_msdu_end *msdu_end, 2575 uint8_t dbg_level) 2576 { 2577 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2578 } 2579 2580 /** 2581 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2582 * human readable format. 2583 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2584 * @ dbg_level: log level. 2585 * 2586 * Return: void 2587 */ 2588 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2589 uint8_t dbg_level) 2590 { 2591 hal_verbose_debug( 2592 "rx_mpdu_end tlv - " 2593 "rxpcu_mpdu_filter_in_category: %x " 2594 "sw_frame_group_id: %x " 2595 "phy_ppdu_id: %x " 2596 "unsup_ktype_short_frame: %x " 2597 "rx_in_tx_decrypt_byp: %x " 2598 "overflow_err: %x " 2599 "mpdu_length_err: %x " 2600 "tkip_mic_err: %x " 2601 "decrypt_err: %x " 2602 "unencrypted_frame_err: %x " 2603 "pn_fields_contain_valid_info: %x " 2604 "fcs_err: %x " 2605 "msdu_length_err: %x " 2606 "rxdma0_destination_ring: %x " 2607 "rxdma1_destination_ring: %x " 2608 "decrypt_status_code: %x " 2609 "rx_bitmap_not_updated: %x ", 2610 mpdu_end->rxpcu_mpdu_filter_in_category, 2611 mpdu_end->sw_frame_group_id, 2612 mpdu_end->phy_ppdu_id, 2613 mpdu_end->unsup_ktype_short_frame, 2614 mpdu_end->rx_in_tx_decrypt_byp, 2615 mpdu_end->overflow_err, 2616 mpdu_end->mpdu_length_err, 2617 mpdu_end->tkip_mic_err, 2618 mpdu_end->decrypt_err, 2619 mpdu_end->unencrypted_frame_err, 2620 mpdu_end->pn_fields_contain_valid_info, 2621 mpdu_end->fcs_err, 2622 mpdu_end->msdu_length_err, 2623 mpdu_end->rxdma0_destination_ring, 2624 mpdu_end->rxdma1_destination_ring, 2625 mpdu_end->decrypt_status_code, 2626 mpdu_end->rx_bitmap_not_updated); 2627 } 2628 2629 #ifdef NO_RX_PKT_HDR_TLV 2630 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2631 uint8_t dbg_level) 2632 { 2633 } 2634 #else 2635 /** 2636 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2637 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2638 * @ dbg_level: log level. 2639 * 2640 * Return: void 2641 */ 2642 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2643 uint8_t dbg_level) 2644 { 2645 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2646 2647 hal_verbose_debug( 2648 "\n---------------\n" 2649 "rx_pkt_hdr_tlv \n" 2650 "---------------\n" 2651 "phy_ppdu_id %d ", 2652 pkt_hdr_tlv->phy_ppdu_id); 2653 2654 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2655 } 2656 #endif 2657 2658 /** 2659 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2660 * structure 2661 * @hal_ring: pointer to hal_srng structure 2662 * 2663 * Return: ring_id 2664 */ 2665 static inline uint8_t hal_srng_ring_id_get(void *hal_ring) 2666 { 2667 return ((struct hal_srng *)hal_ring)->ring_id; 2668 } 2669 2670 /* Rx MSDU link pointer info */ 2671 struct hal_rx_msdu_link_ptr_info { 2672 struct rx_msdu_link msdu_link; 2673 struct hal_buf_info msdu_link_buf_info; 2674 }; 2675 2676 /** 2677 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2678 * 2679 * @nbuf: Pointer to data buffer field 2680 * Returns: pointer to rx_pkt_tlvs 2681 */ 2682 static inline 2683 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2684 { 2685 return (struct rx_pkt_tlvs *)rx_buf_start; 2686 } 2687 2688 /** 2689 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2690 * 2691 * @pkt_tlvs: Pointer to pkt_tlvs 2692 * Returns: pointer to rx_mpdu_info structure 2693 */ 2694 static inline 2695 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2696 { 2697 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2698 } 2699 2700 /** 2701 * hal_rx_get_rx_sequence(): Function to retrieve rx sequence number 2702 * 2703 * @nbuf: Network buffer 2704 * Returns: rx sequence number 2705 */ 2706 #define DOT11_SEQ_FRAG_MASK 0x000f 2707 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2708 2709 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 2710 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2711 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 2712 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 2713 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 2714 static inline 2715 uint16_t hal_rx_get_rx_sequence(uint8_t *buf) 2716 { 2717 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2718 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2719 uint16_t seq_number = 0; 2720 2721 seq_number = HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 2722 2723 return seq_number; 2724 } 2725 2726 /** 2727 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2728 * 2729 * @nbuf: Network buffer 2730 * Returns: rx fragment number 2731 */ 2732 static inline 2733 uint8_t hal_rx_get_rx_fragment_number(uint8_t *buf) 2734 { 2735 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2736 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2737 uint8_t frag_number = 0; 2738 2739 frag_number = HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 2740 DOT11_SEQ_FRAG_MASK; 2741 2742 /* Return first 4 bits as fragment number */ 2743 return frag_number; 2744 } 2745 2746 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2747 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2748 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2749 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2750 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2751 /** 2752 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2753 * 2754 * @nbuf: Network buffer 2755 * Returns: rx more fragment bit 2756 */ 2757 static inline 2758 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2759 { 2760 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2761 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2762 uint16_t frame_ctrl = 0; 2763 2764 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2765 DOT11_FC1_MORE_FRAG_OFFSET; 2766 2767 /* more fragment bit if at offset bit 4 */ 2768 return frame_ctrl; 2769 } 2770 2771 /** 2772 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2773 * 2774 * @nbuf: Network buffer 2775 * Returns: rx more fragment bit 2776 * 2777 */ 2778 static inline 2779 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2780 { 2781 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2782 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2783 uint16_t frame_ctrl = 0; 2784 2785 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2786 2787 return frame_ctrl; 2788 } 2789 2790 /* 2791 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2792 * 2793 * @nbuf: Network buffer 2794 * Returns: flag to indicate whether the nbuf has MC/BC address 2795 */ 2796 static inline 2797 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2798 { 2799 uint8 *buf = qdf_nbuf_data(nbuf); 2800 2801 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2802 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2803 2804 return rx_attn->mcast_bcast; 2805 } 2806 2807 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 2808 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2809 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 2810 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 2811 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 2812 /* 2813 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2814 * 2815 * @nbuf: Network buffer 2816 * Returns: value of sequence control valid field 2817 */ 2818 static inline 2819 uint8_t hal_rx_get_mpdu_sequence_control_valid(uint8_t *buf) 2820 { 2821 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2822 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2823 uint8_t seq_ctrl_valid = 0; 2824 2825 seq_ctrl_valid = 2826 HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 2827 2828 return seq_ctrl_valid; 2829 } 2830 2831 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 2832 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2833 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 2834 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 2835 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 2836 /* 2837 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2838 * 2839 * @nbuf: Network buffer 2840 * Returns: value of frame control valid field 2841 */ 2842 static inline 2843 uint8_t hal_rx_get_mpdu_frame_control_valid(uint8_t *buf) 2844 { 2845 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2846 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2847 uint8_t frm_ctrl_valid = 0; 2848 2849 frm_ctrl_valid = 2850 HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 2851 2852 return frm_ctrl_valid; 2853 } 2854 2855 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 2856 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2857 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 2858 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 2859 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 2860 /* 2861 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2862 * 2863 * @nbuf: Network buffer 2864 * Returns: value of mpdu 4th address valid field 2865 */ 2866 static inline 2867 bool hal_rx_get_mpdu_mac_ad4_valid(uint8_t *buf) 2868 { 2869 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2870 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2871 bool ad4_valid = 0; 2872 2873 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 2874 2875 return ad4_valid; 2876 } 2877 2878 /* 2879 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2880 * 2881 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2882 * Returns: None 2883 */ 2884 static inline 2885 void hal_rx_clear_mpdu_desc_info( 2886 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2887 { 2888 qdf_mem_zero(rx_mpdu_desc_info, 2889 sizeof(*rx_mpdu_desc_info)); 2890 } 2891 2892 /* 2893 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2894 * 2895 * @msdu_link_ptr: HAL view of msdu link ptr 2896 * @size: number of msdu link pointers 2897 * Returns: None 2898 */ 2899 static inline 2900 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2901 int size) 2902 { 2903 qdf_mem_zero(msdu_link_ptr, 2904 (sizeof(*msdu_link_ptr) * size)); 2905 } 2906 2907 /* 2908 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2909 * @msdu_link_ptr: msdu link pointer 2910 * @mpdu_desc_info: mpdu descriptor info 2911 * 2912 * Build a list of msdus using msdu link pointer. If the 2913 * number of msdus are more, chain them together 2914 * 2915 * Returns: Number of processed msdus 2916 */ 2917 static inline 2918 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2919 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2920 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2921 { 2922 int j; 2923 struct rx_msdu_link *msdu_link_ptr = 2924 &msdu_link_ptr_info->msdu_link; 2925 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2926 struct rx_msdu_details *msdu_details = 2927 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2928 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2929 struct rx_msdu_desc_info *msdu_desc_info; 2930 uint8_t fragno, more_frag; 2931 uint8_t *rx_desc_info; 2932 struct hal_rx_msdu_list msdu_list; 2933 2934 for (j = 0; j < num_msdus; j++) { 2935 msdu_desc_info = 2936 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2937 hal_soc); 2938 msdu_list.msdu_info[j].msdu_flags = 2939 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2940 msdu_list.msdu_info[j].msdu_len = 2941 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2942 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2943 &msdu_details[j].buffer_addr_info_details); 2944 } 2945 2946 /* Chain msdu links together */ 2947 if (prev_msdu_link_ptr) { 2948 /* 31-0 bits of the physical address */ 2949 prev_msdu_link_ptr-> 2950 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2951 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2952 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2953 /* 39-32 bits of the physical address */ 2954 prev_msdu_link_ptr-> 2955 next_msdu_link_desc_addr_info.buffer_addr_39_32 2956 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2957 >> 32) & 2958 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2959 prev_msdu_link_ptr-> 2960 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2961 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2962 } 2963 2964 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2965 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2966 /* mark first and last MSDUs */ 2967 rx_desc_info = qdf_nbuf_data(msdu); 2968 fragno = hal_rx_get_rx_fragment_number(rx_desc_info); 2969 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2970 2971 /* TODO: create skb->fragslist[] */ 2972 2973 if (more_frag == 0) { 2974 msdu_list.msdu_info[num_msdus].msdu_flags |= 2975 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2976 } else if (fragno == 1) { 2977 msdu_list.msdu_info[num_msdus].msdu_flags |= 2978 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2979 2980 msdu_list.msdu_info[num_msdus].msdu_flags |= 2981 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2982 } 2983 2984 num_msdus++; 2985 2986 /* Number of MSDUs per mpdu descriptor is updated */ 2987 mpdu_desc_info->msdu_count += num_msdus; 2988 } else { 2989 num_msdus = 0; 2990 prev_msdu_link_ptr = msdu_link_ptr; 2991 } 2992 2993 return num_msdus; 2994 } 2995 2996 /* 2997 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2998 * 2999 * @ring_desc: HAL view of ring descriptor 3000 * @mpdu_des_info: saved mpdu desc info 3001 * @msdu_link_ptr: saved msdu link ptr 3002 * 3003 * API used explicitly for rx defrag to update ring desc with 3004 * mpdu desc info and msdu link ptr before reinjecting the 3005 * packet back to REO 3006 * 3007 * Returns: None 3008 */ 3009 static inline 3010 void hal_rx_defrag_update_src_ring_desc(void *ring_desc, 3011 void *saved_mpdu_desc_info, 3012 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 3013 { 3014 struct reo_entrance_ring *reo_ent_ring; 3015 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 3016 struct hal_buf_info buf_info; 3017 3018 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 3019 reo_ring_mpdu_desc_info = &reo_ent_ring-> 3020 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 3021 3022 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 3023 sizeof(*reo_ring_mpdu_desc_info)); 3024 3025 /* 3026 * TODO: Check for additional fields that need configuration in 3027 * reo_ring_mpdu_desc_info 3028 */ 3029 3030 /* Update msdu_link_ptr in the reo entrance ring */ 3031 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 3032 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 3033 buf_info.sw_cookie = 3034 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 3035 } 3036 3037 /* 3038 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 3039 * 3040 * @msdu_link_desc_va: msdu link descriptor handle 3041 * @msdu_link_ptr_info: HAL view of msdu link pointer info 3042 * 3043 * API used to save msdu link information along with physical 3044 * address. The API also copues the sw cookie. 3045 * 3046 * Returns: None 3047 */ 3048 static inline 3049 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 3050 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 3051 struct hal_buf_info *hbi) 3052 { 3053 struct rx_msdu_link *msdu_link_ptr = 3054 (struct rx_msdu_link *)msdu_link_desc_va; 3055 3056 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 3057 sizeof(struct rx_msdu_link)); 3058 3059 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 3060 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 3061 } 3062 3063 /* 3064 * hal_rx_get_desc_len(): Returns rx descriptor length 3065 * 3066 * Returns the size of rx_pkt_tlvs which follows the 3067 * data in the nbuf 3068 * 3069 * Returns: Length of rx descriptor 3070 */ 3071 static inline 3072 uint16_t hal_rx_get_desc_len(void) 3073 { 3074 return sizeof(struct rx_pkt_tlvs); 3075 } 3076 3077 /* 3078 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 3079 * reo_entrance_ring descriptor 3080 * 3081 * @reo_ent_desc: reo_entrance_ring descriptor 3082 * Returns: value of rxdma_push_reason 3083 */ 3084 static inline 3085 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(void *reo_ent_desc) 3086 { 3087 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3088 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 3089 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 3090 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 3091 } 3092 3093 /** 3094 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 3095 * reo_entrance_ring descriptor 3096 * @reo_ent_desc: reo_entrance_ring descriptor 3097 * Return: value of rxdma_error_code 3098 */ 3099 static inline 3100 uint8_t hal_rx_reo_ent_rxdma_error_code_get(void *reo_ent_desc) 3101 { 3102 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3103 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 3104 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 3105 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 3106 } 3107 3108 /** 3109 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 3110 * save it to hal_wbm_err_desc_info structure passed by caller 3111 * @wbm_desc: wbm ring descriptor 3112 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3113 * Return: void 3114 */ 3115 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 3116 struct hal_wbm_err_desc_info *wbm_er_info, 3117 struct hal_soc *hal_soc) 3118 { 3119 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 3120 } 3121 3122 /** 3123 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 3124 * the reserved bytes of rx_tlv_hdr 3125 * @buf: start of rx_tlv_hdr 3126 * @wbm_er_info: hal_wbm_err_desc_info structure 3127 * Return: void 3128 */ 3129 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 3130 struct hal_wbm_err_desc_info *wbm_er_info) 3131 { 3132 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3133 3134 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 3135 sizeof(struct hal_wbm_err_desc_info)); 3136 } 3137 3138 /** 3139 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 3140 * the reserved bytes of rx_tlv_hdr. 3141 * @buf: start of rx_tlv_hdr 3142 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3143 * Return: void 3144 */ 3145 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 3146 struct hal_wbm_err_desc_info *wbm_er_info) 3147 { 3148 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3149 3150 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 3151 sizeof(struct hal_wbm_err_desc_info)); 3152 } 3153 3154 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 3155 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 3156 RX_MSDU_START_5_NSS_OFFSET)), \ 3157 RX_MSDU_START_5_NSS_MASK, \ 3158 RX_MSDU_START_5_NSS_LSB)) 3159 3160 /** 3161 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 3162 * 3163 * @ hal_soc: HAL version of the SOC pointer 3164 * @ hw_desc_addr: Start address of Rx HW TLVs 3165 * @ rs: Status for monitor mode 3166 * 3167 * Return: void 3168 */ 3169 static inline void hal_rx_mon_hw_desc_get_mpdu_status(struct hal_soc *hal_soc, 3170 void *hw_desc_addr, 3171 struct mon_rx_status *rs) 3172 { 3173 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 3174 } 3175 3176 /* 3177 * hal_rx_get_tlv(): API to get the tlv 3178 * 3179 * @hal_soc: HAL version of the SOC pointer 3180 * @rx_tlv: TLV data extracted from the rx packet 3181 * Return: uint8_t 3182 */ 3183 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 3184 { 3185 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 3186 } 3187 3188 /* 3189 * hal_rx_msdu_start_nss_get(): API to get the NSS 3190 * Interval from rx_msdu_start 3191 * 3192 * @hal_soc: HAL version of the SOC pointer 3193 * @buf: pointer to the start of RX PKT TLV header 3194 * Return: uint32_t(nss) 3195 */ 3196 static inline uint32_t hal_rx_msdu_start_nss_get(struct hal_soc *hal_soc, 3197 uint8_t *buf) 3198 { 3199 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3200 } 3201 3202 /** 3203 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3204 * human readable format. 3205 * @ msdu_start: pointer the msdu_start TLV in pkt. 3206 * @ dbg_level: log level. 3207 * 3208 * Return: void 3209 */ 3210 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3211 struct rx_msdu_start *msdu_start, 3212 uint8_t dbg_level) 3213 { 3214 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3215 } 3216 3217 /** 3218 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3219 * info details 3220 * 3221 * @ buf - Pointer to buffer containing rx pkt tlvs. 3222 * 3223 * 3224 */ 3225 static inline uint32_t hal_rx_mpdu_start_tid_get(struct hal_soc *hal_soc, 3226 uint8_t *buf) 3227 { 3228 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3229 } 3230 3231 /* 3232 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3233 * Interval from rx_msdu_start 3234 * 3235 * @buf: pointer to the start of RX PKT TLV header 3236 * Return: uint32_t(reception_type) 3237 */ 3238 static inline 3239 uint32_t hal_rx_msdu_start_reception_type_get(struct hal_soc *hal_soc, 3240 uint8_t *buf) 3241 { 3242 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3243 } 3244 3245 /** 3246 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3247 * RX TLVs 3248 * @ buf: pointer the pkt buffer. 3249 * @ dbg_level: log level. 3250 * 3251 * Return: void 3252 */ 3253 static inline void hal_rx_dump_pkt_tlvs(struct hal_soc *hal_soc, 3254 uint8_t *buf, uint8_t dbg_level) 3255 { 3256 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3257 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3258 struct rx_mpdu_start *mpdu_start = 3259 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3260 struct rx_msdu_start *msdu_start = 3261 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3262 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3263 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3264 3265 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3266 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3267 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3268 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3269 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3270 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3271 } 3272 3273 3274 /** 3275 * hal_reo_status_get_header_generic - Process reo desc info 3276 * @d - Pointer to reo descriptior 3277 * @b - tlv type info 3278 * @h - Pointer to hal_reo_status_header where info to be stored 3279 * @hal- pointer to hal_soc structure 3280 * Return - none. 3281 * 3282 */ 3283 static inline void hal_reo_status_get_header(uint32_t *d, int b, 3284 void *h, void *hal) 3285 { 3286 struct hal_soc *hal_soc = (struct hal_soc *)hal; 3287 3288 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3289 } 3290 3291 static inline 3292 uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr) 3293 { 3294 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 3295 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 3296 3297 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 3298 } 3299 3300 static inline 3301 uint32_t 3302 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3303 struct rx_msdu_start *rx_msdu_start; 3304 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3305 3306 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3307 3308 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3309 } 3310 3311 #ifdef NO_RX_PKT_HDR_TLV 3312 static inline 3313 uint8_t * 3314 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3315 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3316 "[%s][%d] decap format not raw", __func__, __LINE__); 3317 QDF_ASSERT(0); 3318 return 0; 3319 } 3320 #else 3321 static inline 3322 uint8_t * 3323 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3324 uint8_t *rx_pkt_hdr; 3325 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3326 3327 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3328 3329 return rx_pkt_hdr; 3330 } 3331 #endif 3332 3333 #ifdef NO_RX_PKT_HDR_TLV 3334 static inline 3335 bool HAL_IS_DECAP_FORMAT_RAW(uint8_t *rx_tlv_hdr) 3336 { 3337 uint8_t decap_format; 3338 3339 if (hal_rx_desc_is_first_msdu(rx_tlv_hdr)) { 3340 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3341 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3342 return true; 3343 } 3344 3345 return false; 3346 } 3347 #else 3348 static inline 3349 bool HAL_IS_DECAP_FORMAT_RAW(uint8_t *rx_tlv_hdr) 3350 { 3351 return true; 3352 } 3353 #endif 3354 #endif /* _HAL_RX_H */ 3355