1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_RX_H_ 21 #define _HAL_RX_H_ 22 23 #include <hal_api.h> 24 #include "hal_rx_hw_defines.h" 25 #include "hal_hw_headers.h" 26 27 /************************************* 28 * Ring desc offset/shift/masks 29 *************************************/ 30 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 31 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 32 #define HAL_RX_LSB(block, field) block##_##field##_LSB 33 #define HAL_RX_MASK(block, field) block##_##field##_MASK 34 35 #define HAL_RX_GET(_ptr, block, field) \ 36 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 37 HAL_RX_MASK(block, field)) >> \ 38 HAL_RX_LSB(block, field)) 39 40 #define HAL_RX_GET_64(_ptr, block, field) \ 41 (((*((volatile uint64_t *)(_ptr) + \ 42 (HAL_RX_OFFSET(block, field) >> 3))) & \ 43 HAL_RX_MASK(block, field)) >> \ 44 HAL_RX_LSB(block, field)) 45 46 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 47 (*(uint32_t *)(((uint8_t *)_ptr) + \ 48 _wrd ## _ ## _field ## _OFFSET) |= \ 49 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 50 _wrd ## _ ## _field ## _MASK)) 51 52 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 53 #ifndef RX_DATA_BUFFER_SIZE 54 #define RX_DATA_BUFFER_SIZE 2048 55 #endif 56 57 #ifndef RX_MONITOR_BUFFER_SIZE 58 #define RX_MONITOR_BUFFER_SIZE 2048 59 #endif 60 61 #define RXDMA_OPTIMIZATION 62 63 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 64 * including buffer reservation, buffer alignment and skb shared info size. 65 */ 66 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 67 #define RX_MON_STATUS_BUF_ALIGN 128 68 #define RX_MON_STATUS_BUF_RESERVATION 128 69 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 70 (RX_MON_STATUS_BUF_RESERVATION + \ 71 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 72 73 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 74 75 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 76 #define HAL_RX_NON_QOS_TID 16 77 78 enum { 79 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 80 HAL_HW_RX_DECAP_FORMAT_NWIFI, 81 HAL_HW_RX_DECAP_FORMAT_ETH2, 82 HAL_HW_RX_DECAP_FORMAT_8023, 83 }; 84 85 /** 86 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 87 * 88 * @reo_psh_rsn: REO push reason 89 * @reo_err_code: REO Error code 90 * @rxdma_psh_rsn: RXDMA push reason 91 * @rxdma_err_code: RXDMA Error code 92 * @reserved_1: Reserved bits 93 * @wbm_err_src: WBM error source 94 * @pool_id: pool ID, indicates which rxdma pool 95 * @reserved_2: Reserved bits 96 */ 97 struct hal_wbm_err_desc_info { 98 uint16_t reo_psh_rsn:2, 99 reo_err_code:5, 100 rxdma_psh_rsn:2, 101 rxdma_err_code:5, 102 reserved_1:2; 103 uint8_t wbm_err_src:3, 104 pool_id:2, 105 msdu_continued:1, 106 reserved_2:2; 107 }; 108 109 /** 110 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 111 * @first_buffer: First buffer of MSDU 112 * @last_buffer: Last buffer of MSDU 113 * @is_decap_raw: Is RAW Frame 114 * @reserved_1: Reserved 115 * 116 * MSDU with continuation: 117 * ----------------------------------------------------------- 118 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 119 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 120 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 121 * ----------------------------------------------------------- 122 * 123 * Single buffer MSDU: 124 * ------------------ 125 * | first_buffer:1 | 126 * | last_buffer :1 | 127 * | is_decap_raw:1/0 | 128 * ------------------ 129 */ 130 struct hal_rx_mon_dest_buf_info { 131 uint8_t first_buffer:1, 132 last_buffer:1, 133 is_decap_raw:1, 134 reserved_1:5; 135 }; 136 137 /** 138 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 139 * 140 * @l3_hdr_pad: l3 header padding 141 * @reserved: Reserved bits 142 * @sa_sw_peer_id: sa sw peer id 143 * @sa_idx: sa index 144 * @da_idx: da index 145 */ 146 struct hal_rx_msdu_metadata { 147 uint32_t l3_hdr_pad:16, 148 sa_sw_peer_id:16; 149 uint32_t sa_idx:16, 150 da_idx:16; 151 }; 152 153 struct hal_proto_params { 154 uint8_t tcp_proto; 155 uint8_t udp_proto; 156 uint8_t ipv6_proto; 157 }; 158 159 /** 160 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 161 * 162 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 163 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 164 */ 165 enum hal_reo_error_status { 166 HAL_REO_ERROR_DETECTED = 0, 167 HAL_REO_ROUTING_INSTRUCTION = 1, 168 }; 169 170 /** 171 * @msdu_flags: [0] first_msdu_in_mpdu 172 * [1] last_msdu_in_mpdu 173 * [2] msdu_continuation - MSDU spread across buffers 174 * [23] sa_is_valid - SA match in peer table 175 * [24] sa_idx_timeout - Timeout while searching for SA match 176 * [25] da_is_valid - Used to identtify intra-bss forwarding 177 * [26] da_is_MCBC 178 * [27] da_idx_timeout - Timeout while searching for DA match 179 * 180 */ 181 struct hal_rx_msdu_desc_info { 182 uint32_t msdu_flags; 183 uint16_t msdu_len; /* 14 bits for length */ 184 }; 185 186 /** 187 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 188 * 189 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 190 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 191 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 192 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 193 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 194 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 195 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 196 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 197 * @ HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 198 */ 199 enum hal_rx_msdu_desc_flags { 200 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 201 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 202 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 203 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 204 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 205 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 206 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 207 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 208 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 209 }; 210 211 /* 212 * @msdu_count: no. of msdus in the MPDU 213 * @mpdu_seq: MPDU sequence number 214 * @mpdu_flags [0] Fragment flag 215 * [1] MPDU_retry_bit 216 * [2] AMPDU flag 217 * [3] raw_ampdu 218 * @peer_meta_data: Upper bits containing peer id, vdev id 219 * @bar_frame: indicates if received frame is a bar frame 220 * @tid: tid value of received MPDU 221 */ 222 struct hal_rx_mpdu_desc_info { 223 uint16_t msdu_count; 224 uint16_t mpdu_seq; /* 12 bits for length */ 225 uint32_t mpdu_flags; 226 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 227 uint16_t bar_frame; 228 uint8_t tid:4, 229 reserved:4; 230 }; 231 232 /** 233 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 234 * 235 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 236 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 237 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 238 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 239 * @ HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field 240 */ 241 enum hal_rx_mpdu_desc_flags { 242 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 243 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 244 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 245 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30), 246 HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31) 247 }; 248 249 /* Return Buffer manager ID */ 250 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 251 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 252 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 253 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 254 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 255 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 256 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 257 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 258 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 259 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 260 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 261 262 #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id) 263 264 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 265 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 266 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 267 268 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 269 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 270 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 271 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 272 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 273 274 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 275 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 276 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 277 278 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 279 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 280 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 281 282 /* 283 * macro to set the LSW of the nbuf data physical address 284 * to the rxdma ring entry 285 */ 286 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 287 ((*(((unsigned int *) buff_addr_info) + \ 288 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 289 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 290 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 291 292 /* 293 * macro to set the LSB of MSW of the nbuf data physical address 294 * to the rxdma ring entry 295 */ 296 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 297 ((*(((unsigned int *) buff_addr_info) + \ 298 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 299 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 300 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 301 302 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 303 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 304 305 /* 306 * macro to get the invalid bit for sw cookie 307 */ 308 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 309 ((*(((unsigned int *)buff_addr_info) + \ 310 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 311 HAL_RX_COOKIE_INVALID_MASK) 312 313 /* 314 * macro to set the invalid bit for sw cookie 315 */ 316 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 317 ((*(((unsigned int *)buff_addr_info) + \ 318 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 319 HAL_RX_COOKIE_INVALID_MASK) 320 321 /* 322 * macro to reset the invalid bit for sw cookie 323 */ 324 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 325 ((*(((unsigned int *)buff_addr_info) + \ 326 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 327 ~HAL_RX_COOKIE_INVALID_MASK) 328 329 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 330 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 331 (((struct reo_destination_ring *) \ 332 reo_desc)->buf_or_link_desc_addr_info))) 333 334 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 335 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 336 (((struct reo_destination_ring *) \ 337 reo_desc)->buf_or_link_desc_addr_info))) 338 339 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 340 341 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 342 ((*(((unsigned int *)buff_addr_info) + \ 343 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 344 HAL_RX_LINK_COOKIE_INVALID_MASK) 345 346 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 347 ((*(((unsigned int *)buff_addr_info) + \ 348 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 349 HAL_RX_LINK_COOKIE_INVALID_MASK) 350 351 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 352 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 353 (((struct reo_destination_ring *) \ 354 reo_desc)->buf_or_link_desc_addr_info))) 355 356 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 357 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 358 (((struct reo_destination_ring *) \ 359 reo_desc)->buf_or_link_desc_addr_info))) 360 #endif 361 362 /* TODO: Convert the following structure fields accesseses to offsets */ 363 364 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 365 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 366 (((struct reo_destination_ring *) \ 367 reo_desc)->buf_or_link_desc_addr_info))) 368 369 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 370 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 371 (((struct reo_destination_ring *) \ 372 reo_desc)->buf_or_link_desc_addr_info))) 373 374 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 375 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 376 (((struct reo_destination_ring *) \ 377 reo_desc)->buf_or_link_desc_addr_info))) 378 379 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 380 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 381 _field, _val) 382 383 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 384 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 385 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 386 387 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 388 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 389 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 390 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 391 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 392 393 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 394 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 395 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 396 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 397 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 398 399 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 400 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 401 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 402 403 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 404 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 405 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 406 407 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 408 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 409 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 410 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 411 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 412 413 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 414 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 415 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 416 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 417 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 418 419 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 420 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 421 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 422 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 423 424 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 425 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 426 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 427 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 428 429 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 430 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 431 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 432 433 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 434 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 435 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 436 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 437 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 438 439 static inline uint32_t 440 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 441 rx_msdu_desc_info_t msdu_desc_info_hdl) 442 { 443 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 444 445 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 446 } 447 448 /* 449 * Structures & Macros to obtain fields from the TLV's in the Rx packet 450 * pre-header. 451 */ 452 453 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 454 void *hw_desc_addr) 455 { 456 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 457 458 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 459 } 460 461 /** 462 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 463 * @hal_soc_hdl: hal soc handle 464 * @desc_addr: ring descriptor 465 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 466 * 467 * Return: None 468 */ 469 static inline void 470 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 471 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 472 { 473 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 474 475 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 476 mpdu_desc_info); 477 } 478 479 #define HAL_RX_NUM_MSDU_DESC 6 480 #define HAL_RX_MAX_SAVED_RING_DESC 16 481 482 /* TODO: rework the structure */ 483 struct hal_rx_msdu_list { 484 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 485 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 486 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 487 /* physical address of the msdu */ 488 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 489 }; 490 491 struct hal_buf_info { 492 uint64_t paddr; 493 uint32_t sw_cookie; 494 uint8_t rbm; 495 }; 496 497 /* This special cookie value will be used to indicate FW allocated buffers 498 * received through RXDMA2SW ring for RXDMA WARs 499 */ 500 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 501 502 /** 503 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 504 * 505 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 506 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 507 * descriptor 508 */ 509 enum hal_rx_reo_buf_type { 510 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 511 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 512 }; 513 514 /** 515 * enum hal_reo_error_code: Error code describing the type of error detected 516 * 517 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 518 * REO_ENTRANCE ring is set to 0 519 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 520 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 521 * having been setup 522 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 523 * Retry bit set: duplicate frame 524 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 525 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 526 * received with 2K jump in SN 527 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 528 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 529 * with SN falling within the OOR window 530 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 531 * OOR window 532 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 533 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 534 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 535 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 536 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 537 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 538 * of the pn_error_detected_flag been set in the REO Queue descriptor 539 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 540 * the queue descriptor(address) being blocked as SW/FW seems to be currently 541 * in the process of making updates to this descriptor 542 */ 543 enum hal_reo_error_code { 544 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 545 HAL_REO_ERR_QUEUE_DESC_INVALID, 546 HAL_REO_ERR_AMPDU_IN_NON_BA, 547 HAL_REO_ERR_NON_BA_DUPLICATE, 548 HAL_REO_ERR_BA_DUPLICATE, 549 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 550 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 551 HAL_REO_ERR_REGULAR_FRAME_OOR, 552 HAL_REO_ERR_BAR_FRAME_OOR, 553 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 554 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 555 HAL_REO_ERR_PN_CHECK_FAILED, 556 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 557 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 558 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 559 HAL_REO_ERR_MAX 560 }; 561 562 /** 563 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 564 * 565 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 566 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 567 * overflow 568 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 569 * incomplete 570 * MPDU from the PHY 571 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 572 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 573 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 574 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 575 * encrypted but wasn’t 576 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 577 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 578 * the max allowed 579 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 580 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 581 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 582 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 583 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 584 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 585 * @ HAL_RXDMA_AMSDU_FRAGMENT : Rx PCU reported A-MSDU 586 * present as well as a fragmented MPDU 587 * @ HAL_RXDMA_MULTICAST_ECHO : RX OLE reported a multicast echo 588 * @ HAL_RXDMA_AMSDU_ADDR_MISMATCH : RX OLE reported AMSDU address mismatch 589 * @ HAL_RXDMA_UNAUTHORIZED_WDS : RX PCU reported unauthorized wds 590 * @ HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS :RX PCU reported group cast AMSDU or WDS 591 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 592 */ 593 enum hal_rxdma_error_code { 594 HAL_RXDMA_ERR_OVERFLOW = 0, 595 HAL_RXDMA_ERR_MPDU_LENGTH, 596 HAL_RXDMA_ERR_FCS, 597 HAL_RXDMA_ERR_DECRYPT, 598 HAL_RXDMA_ERR_TKIP_MIC, 599 HAL_RXDMA_ERR_UNENCRYPTED, 600 HAL_RXDMA_ERR_MSDU_LEN, 601 HAL_RXDMA_ERR_MSDU_LIMIT, 602 HAL_RXDMA_ERR_WIFI_PARSE, 603 HAL_RXDMA_ERR_AMSDU_PARSE, 604 HAL_RXDMA_ERR_SA_TIMEOUT, 605 HAL_RXDMA_ERR_DA_TIMEOUT, 606 HAL_RXDMA_ERR_FLOW_TIMEOUT, 607 HAL_RXDMA_ERR_FLUSH_REQUEST, 608 HAL_RXDMA_AMSDU_FRAGMENT, 609 HAL_RXDMA_MULTICAST_ECHO, 610 HAL_RXDMA_AMSDU_ADDR_MISMATCH, 611 HAL_RXDMA_UNAUTHORIZED_WDS, 612 HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS, 613 HAL_RXDMA_ERR_WAR = 31, 614 HAL_RXDMA_ERR_MAX 615 }; 616 617 /** 618 * HW BM action settings in WBM release ring 619 */ 620 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 621 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 622 623 /** 624 * enum hal_rx_wbm_error_source: Indicates which module initiated the 625 * release of this buffer or descriptor 626 * 627 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 628 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 629 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 630 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 631 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 632 */ 633 enum hal_rx_wbm_error_source { 634 HAL_RX_WBM_ERR_SRC_TQM = 0, 635 HAL_RX_WBM_ERR_SRC_RXDMA, 636 HAL_RX_WBM_ERR_SRC_REO, 637 HAL_RX_WBM_ERR_SRC_FW, 638 HAL_RX_WBM_ERR_SRC_SW, 639 }; 640 641 /** 642 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 643 * released 644 * 645 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 646 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 647 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 648 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 649 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 650 */ 651 enum hal_rx_wbm_buf_type { 652 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 653 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 654 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 655 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 656 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 657 }; 658 659 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 660 661 //#include "hal_rx_be.h" 662 663 /* 664 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 665 * 666 * @nbuf: Network buffer 667 * Returns: flag to indicate whether the nbuf has MC/BC address 668 */ 669 static inline uint32_t 670 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 671 qdf_nbuf_t nbuf) 672 { 673 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 674 675 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 676 } 677 678 /** 679 * hal_rx_priv_info_set_in_tlv(): Save the private info to 680 * the reserved bytes of rx_tlv_hdr 681 * @buf: start of rx_tlv_hdr 682 * @wbm_er_info: hal_wbm_err_desc_info structure 683 * Return: void 684 */ 685 static inline void 686 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 687 uint8_t *buf, uint8_t *priv_data, 688 uint32_t len) 689 { 690 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 691 692 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 693 priv_data, 694 len); 695 } 696 697 /* 698 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 699 * reo_entrance_ring descriptor 700 * 701 * @reo_ent_desc: reo_entrance_ring descriptor 702 * Returns: value of rxdma_push_reason 703 */ 704 static inline 705 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 706 { 707 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 708 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 709 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 710 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 711 } 712 713 /** 714 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 715 * reo_entrance_ring descriptor 716 * @reo_ent_desc: reo_entrance_ring descriptor 717 * Return: value of rxdma_error_code 718 */ 719 static inline 720 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 721 { 722 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 723 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 724 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 725 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 726 } 727 728 /** 729 * hal_rx_priv_info_get_from_tlv(): retrieve the private data from 730 * the reserved bytes of rx_tlv_hdr. 731 * @buf: start of rx_tlv_hdr 732 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 733 * Return: void 734 */ 735 static inline void 736 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 737 uint8_t *buf, uint8_t *wbm_er_info, 738 uint32_t len) 739 { 740 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 741 742 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 743 wbm_er_info, 744 len); 745 } 746 747 static inline void 748 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 749 uint16_t *rx_mon_pkt_tlv_size) 750 { 751 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 752 753 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 754 rx_mon_pkt_tlv_size); 755 } 756 757 /* 758 * hal_rx_encryption_info_valid(): Returns encryption type. 759 * 760 * @hal_soc_hdl: hal soc handle 761 * @buf: rx_tlv_hdr of the received packet 762 * 763 * Return: encryption type 764 */ 765 static inline uint32_t 766 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 767 { 768 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 769 770 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 771 } 772 773 /* 774 * hal_rx_print_pn: Prints the PN of rx packet. 775 * @hal_soc_hdl: hal soc handle 776 * @buf: rx_tlv_hdr of the received packet 777 * 778 * Return: void 779 */ 780 static inline void 781 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 782 { 783 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 784 785 hal_soc->ops->hal_rx_print_pn(buf); 786 } 787 788 /** 789 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 790 * l3_header padding from rx_msdu_end TLV 791 * 792 * @buf: pointer to the start of RX PKT TLV headers 793 * Return: number of l3 header padding bytes 794 */ 795 static inline uint32_t 796 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 797 uint8_t *buf) 798 { 799 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 800 801 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 802 } 803 804 /** 805 * hal_rx_msdu_end_sa_idx_get(): API to get the 806 * sa_idx from rx_msdu_end TLV 807 * 808 * @ buf: pointer to the start of RX PKT TLV headers 809 * Return: sa_idx (SA AST index) 810 */ 811 static inline uint16_t 812 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 813 uint8_t *buf) 814 { 815 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 816 817 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 818 } 819 820 /** 821 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 822 * sa_is_valid bit from rx_msdu_end TLV 823 * 824 * @ buf: pointer to the start of RX PKT TLV headers 825 * Return: sa_is_valid bit 826 */ 827 static inline uint8_t 828 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 829 uint8_t *buf) 830 { 831 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 832 833 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 834 } 835 836 /** 837 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 838 * from rx_msdu_start TLV 839 * 840 * @buf: pointer to the start of RX PKT TLV headers 841 * @len: msdu length 842 * 843 * Return: none 844 */ 845 static inline void 846 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 847 uint32_t len) 848 { 849 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 850 851 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 852 } 853 854 /** 855 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 856 * 857 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 858 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 859 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 860 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 861 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 862 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 863 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 864 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 865 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 866 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 867 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 868 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 869 */ 870 enum hal_rx_mpdu_info_sw_frame_group_id_type { 871 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 872 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 873 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 874 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 875 HAL_MPDU_SW_FRAME_GROUP_MGMT, 876 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 877 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 878 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 879 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 880 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 881 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 882 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 883 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 884 }; 885 886 /** 887 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 888 * Retrieve qos control valid bit from the tlv. 889 * @hal_soc_hdl: hal_soc handle 890 * @buf: pointer to rx pkt TLV. 891 * 892 * Return: qos control value. 893 */ 894 static inline uint32_t 895 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 896 hal_soc_handle_t hal_soc_hdl, 897 uint8_t *buf) 898 { 899 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 900 901 if ((!hal_soc) || (!hal_soc->ops)) { 902 hal_err("hal handle is NULL"); 903 QDF_BUG(0); 904 return QDF_STATUS_E_INVAL; 905 } 906 907 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 908 return hal_soc->ops-> 909 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 910 911 return QDF_STATUS_E_INVAL; 912 } 913 914 /** 915 * hal_rx_is_unicast: check packet is unicast frame or not. 916 * @hal_soc_hdl: hal_soc handle 917 * @buf: pointer to rx pkt TLV. 918 * 919 * Return: true on unicast. 920 */ 921 static inline bool 922 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 923 { 924 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 925 926 return hal_soc->ops->hal_rx_is_unicast(buf); 927 } 928 929 /** 930 * hal_rx_tid_get: get tid based on qos control valid. 931 * @hal_soc_hdl: hal soc handle 932 * @buf: pointer to rx pkt TLV. 933 * 934 * Return: tid 935 */ 936 static inline uint32_t 937 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 938 { 939 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 940 941 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 942 } 943 944 /** 945 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 946 * @hal_soc_hdl: hal soc handle 947 * @buf: pointer to rx pkt TLV. 948 * 949 * Return: sw peer_id 950 */ 951 static inline uint32_t 952 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 953 uint8_t *buf) 954 { 955 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 956 957 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 958 } 959 960 /** 961 * hal_rx_mpdu_peer_meta_data_get() - Retrieve PEER_META_DATA 962 * @hal_soc_hdl: hal soc handle 963 * @buf: pointer to rx pkt TLV. 964 * 965 * Return: peer meta data 966 */ 967 static inline uint32_t 968 hal_rx_mpdu_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl, 969 uint8_t *buf) 970 { 971 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 972 973 return hal_soc->ops->hal_rx_mpdu_peer_meta_data_get(buf); 974 } 975 976 /* 977 * hal_rx_mpdu_get_tods(): API to get the tods info 978 * from rx_mpdu_start 979 * 980 * @buf: pointer to the start of RX PKT TLV header 981 * Return: uint32_t(to_ds) 982 */ 983 984 static inline uint32_t 985 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 986 { 987 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 988 989 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 990 } 991 992 993 /* 994 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 995 * from rx_mpdu_start 996 * @hal_soc_hdl: hal soc handle 997 * @buf: pointer to the start of RX PKT TLV header 998 * 999 * Return: uint32_t(fr_ds) 1000 */ 1001 static inline uint32_t 1002 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1003 { 1004 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1005 1006 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1007 } 1008 1009 /* 1010 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1011 * @hal_soc_hdl: hal soc handle 1012 * @buf: pointer to the start of RX PKT TLV headera 1013 * @mac_addr: pointer to mac address 1014 * 1015 * Return: success/failure 1016 */ 1017 static inline 1018 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1019 uint8_t *buf, uint8_t *mac_addr) 1020 { 1021 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1022 1023 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1024 } 1025 1026 /* 1027 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1028 * in the packet 1029 * @hal_soc_hdl: hal soc handle 1030 * @buf: pointer to the start of RX PKT TLV header 1031 * @mac_addr: pointer to mac address 1032 * 1033 * Return: success/failure 1034 */ 1035 static inline 1036 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1037 uint8_t *buf, uint8_t *mac_addr) 1038 { 1039 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1040 1041 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1042 } 1043 1044 /* 1045 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1046 * in the packet 1047 * @hal_soc_hdl: hal soc handle 1048 * @buf: pointer to the start of RX PKT TLV header 1049 * @mac_addr: pointer to mac address 1050 * 1051 * Return: success/failure 1052 */ 1053 static inline 1054 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1055 uint8_t *buf, uint8_t *mac_addr) 1056 { 1057 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1058 1059 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1060 } 1061 1062 /* 1063 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1064 * in the packet 1065 * @hal_soc_hdl: hal_soc handle 1066 * @buf: pointer to the start of RX PKT TLV header 1067 * @mac_addr: pointer to mac address 1068 * Return: success/failure 1069 */ 1070 static inline 1071 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1072 uint8_t *buf, uint8_t *mac_addr) 1073 { 1074 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1075 1076 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1077 } 1078 1079 /** 1080 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1081 * from rx_msdu_end TLV 1082 * 1083 * @ buf: pointer to the start of RX PKT TLV headers 1084 * Return: da index 1085 */ 1086 static inline uint16_t 1087 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1088 { 1089 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1090 1091 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1092 } 1093 1094 /** 1095 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1096 * from rx_msdu_end TLV 1097 * @hal_soc_hdl: hal soc handle 1098 * @ buf: pointer to the start of RX PKT TLV headers 1099 * 1100 * Return: da_is_valid 1101 */ 1102 static inline uint8_t 1103 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1104 uint8_t *buf) 1105 { 1106 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1107 1108 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1109 } 1110 1111 /** 1112 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1113 * from rx_msdu_end TLV 1114 * 1115 * @buf: pointer to the start of RX PKT TLV headers 1116 * 1117 * Return: da_is_mcbc 1118 */ 1119 static inline uint8_t 1120 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1121 { 1122 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1123 1124 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1125 } 1126 1127 /** 1128 * hal_rx_msdu_end_is_tkip_mic_err: API to check if pkt has mic error 1129 * from rx_msdu_end TLV 1130 * 1131 * @buf: pointer to the start of RX PKT TLV headers 1132 * 1133 * Return: tkip_mic_err 1134 */ 1135 static inline uint8_t 1136 hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl, 1137 uint8_t *buf) 1138 { 1139 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1140 1141 if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err) 1142 return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf); 1143 else 1144 return 0; 1145 } 1146 1147 /** 1148 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1149 * from rx_msdu_end TLV 1150 * @hal_soc_hdl: hal soc handle 1151 * @buf: pointer to the start of RX PKT TLV headers 1152 * 1153 * Return: first_msdu 1154 */ 1155 static inline uint8_t 1156 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1157 uint8_t *buf) 1158 { 1159 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1160 1161 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1162 } 1163 1164 /** 1165 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1166 * from rx_msdu_end TLV 1167 * @hal_soc_hdl: hal soc handle 1168 * @buf: pointer to the start of RX PKT TLV headers 1169 * 1170 * Return: last_msdu 1171 */ 1172 static inline uint8_t 1173 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1174 uint8_t *buf) 1175 { 1176 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1177 1178 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1179 } 1180 1181 /** 1182 * hal_rx_msdu_cce_match_get: API to get CCE match 1183 * from rx_msdu_end TLV 1184 * @buf: pointer to the start of RX PKT TLV headers 1185 * Return: cce_meta_data 1186 */ 1187 static inline bool 1188 hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl, 1189 uint8_t *buf) 1190 { 1191 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1192 1193 return hal_soc->ops->hal_rx_msdu_cce_match_get(buf); 1194 } 1195 1196 /** 1197 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1198 * from rx_msdu_end TLV 1199 * @buf: pointer to the start of RX PKT TLV headers 1200 * Return: cce_meta_data 1201 */ 1202 static inline uint16_t 1203 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1204 uint8_t *buf) 1205 { 1206 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1207 1208 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1209 } 1210 1211 /******************************************************************************* 1212 * RX REO ERROR APIS 1213 ******************************************************************************/ 1214 1215 /** 1216 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1217 * @msdu_link_ptr - msdu link ptr 1218 * @hal - pointer to hal_soc 1219 * Return - Pointer to rx_msdu_details structure 1220 * 1221 */ 1222 static inline 1223 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1224 struct hal_soc *hal_soc) 1225 { 1226 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1227 } 1228 1229 /** 1230 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1231 * @msdu_details_ptr - Pointer to msdu_details_ptr 1232 * @hal - pointer to hal_soc 1233 * Return - Pointer to rx_msdu_desc_info structure. 1234 * 1235 */ 1236 static inline 1237 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1238 struct hal_soc *hal_soc) 1239 { 1240 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1241 } 1242 1243 /** 1244 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1245 * cookie from the REO destination ring element 1246 * 1247 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1248 * the current descriptor 1249 * @ buf_info: structure to return the buffer information 1250 * Return: void 1251 */ 1252 static inline 1253 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1254 hal_ring_desc_t rx_desc, 1255 struct hal_buf_info *buf_info) 1256 { 1257 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1258 1259 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1260 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1261 rx_desc, 1262 buf_info); 1263 1264 } 1265 1266 /** 1267 * hal_rx_wbm_rel_buf_paddr_get: Gets the physical address and 1268 * cookie from the WBM release ring element 1269 * 1270 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1271 * the current descriptor 1272 * @ buf_info: structure to return the buffer information 1273 * Return: void 1274 */ 1275 static inline 1276 void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1277 hal_ring_desc_t rx_desc, 1278 struct hal_buf_info *buf_info) 1279 { 1280 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1281 1282 if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get) 1283 return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc, 1284 buf_info); 1285 } 1286 1287 /** 1288 * hal_rx_buf_cookie_rbm_get: Gets the physical address and 1289 * cookie from the REO entrance ring element 1290 * 1291 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1292 * the current descriptor 1293 * @ buf_info: structure to return the buffer information 1294 * @ msdu_cnt: pointer to msdu count in MPDU 1295 * Return: void 1296 */ 1297 static inline 1298 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1299 uint32_t *buf_addr_info, 1300 struct hal_buf_info *buf_info) 1301 { 1302 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1303 1304 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1305 buf_addr_info, 1306 buf_info); 1307 } 1308 1309 /** 1310 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1311 * from the MSDU link descriptor 1312 * 1313 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1314 * MSDU link descriptor (struct rx_msdu_link) 1315 * 1316 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1317 * 1318 * @num_msdus: Number of MSDUs in the MPDU 1319 * 1320 * Return: void 1321 */ 1322 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1323 void *msdu_link_desc, 1324 struct hal_rx_msdu_list *msdu_list, 1325 uint16_t *num_msdus) 1326 { 1327 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1328 struct rx_msdu_details *msdu_details; 1329 struct rx_msdu_desc_info *msdu_desc_info; 1330 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1331 int i; 1332 struct hal_buf_info buf_info; 1333 1334 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1335 1336 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1337 __func__, __LINE__, msdu_link, msdu_details); 1338 1339 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1340 /* num_msdus received in mpdu descriptor may be incorrect 1341 * sometimes due to HW issue. Check msdu buffer address also 1342 */ 1343 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1344 &msdu_details[i].buffer_addr_info_details) == 0)) 1345 break; 1346 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1347 &msdu_details[i].buffer_addr_info_details) == 0) { 1348 /* set the last msdu bit in the prev msdu_desc_info */ 1349 msdu_desc_info = 1350 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1351 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1352 break; 1353 } 1354 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1355 hal_soc); 1356 1357 /* set first MSDU bit or the last MSDU bit */ 1358 if (!i) 1359 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1360 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1361 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1362 1363 msdu_list->msdu_info[i].msdu_flags = 1364 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1365 msdu_list->msdu_info[i].msdu_len = 1366 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1367 1368 /* addr field in buf_info will not be valid */ 1369 hal_rx_buf_cookie_rbm_get( 1370 hal_soc_hdl, 1371 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1372 &buf_info); 1373 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1374 msdu_list->rbm[i] = buf_info.rbm; 1375 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1376 &msdu_details[i].buffer_addr_info_details) | 1377 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1378 &msdu_details[i].buffer_addr_info_details) << 32; 1379 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1380 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1381 } 1382 *num_msdus = i; 1383 } 1384 1385 /** 1386 * hal_rx_is_pn_error() - Indicate if this error was caused by a 1387 * PN check failure 1388 * 1389 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 1390 * 1391 * Return: true: error caused by PN check, false: other error 1392 */ 1393 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1394 { 1395 1396 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1397 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1398 true : false; 1399 } 1400 1401 /** 1402 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1403 * the sequence number 1404 * 1405 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1406 * 1407 * Return: true: error caused by 2K jump, false: other error 1408 */ 1409 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1410 { 1411 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1412 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1413 true : false; 1414 } 1415 1416 /** 1417 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1418 * 1419 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1420 * 1421 * Return: true: error caused by OOR, false: other error 1422 */ 1423 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1424 { 1425 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1426 true : false; 1427 } 1428 1429 /** 1430 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1431 * @error_code: error code obtained from ring descriptor. 1432 * 1433 * Return: true, if the error code is 2k-jump or OOR 1434 * false, for other error codes. 1435 */ 1436 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1437 { 1438 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1439 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1440 true : false; 1441 } 1442 1443 /** 1444 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1445 * @hal_desc: hardware descriptor pointer 1446 * 1447 * This function will print wbm release descriptor 1448 * 1449 * Return: none 1450 */ 1451 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1452 { 1453 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1454 uint32_t i; 1455 1456 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1457 "Current Rx wbm release descriptor is"); 1458 1459 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1460 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1461 "DWORD[i] = 0x%x", wbm_comp[i]); 1462 } 1463 } 1464 1465 /** 1466 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 1467 * 1468 * @ hal_soc_hdl : HAL version of the SOC pointer 1469 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 1470 * @ buf_addr_info : void pointer to the buffer_addr_info 1471 * @ bm_action : put in IDLE list or release to MSDU_LIST 1472 * 1473 * Return: void 1474 */ 1475 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1476 static inline 1477 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1478 void *src_srng_desc, 1479 hal_buff_addrinfo_t buf_addr_info, 1480 uint8_t bm_action) 1481 { 1482 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1483 1484 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1485 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1486 src_srng_desc, 1487 buf_addr_info, 1488 bm_action); 1489 } 1490 1491 /** 1492 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 1493 * BUFFER_ADDR_INFO, give the RX descriptor 1494 * (Assumption -- BUFFER_ADDR_INFO is the 1495 * first field in the descriptor structure) 1496 */ 1497 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1498 ((hal_link_desc_t)(ring_desc)) 1499 1500 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1501 1502 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1503 1504 /******************************************************************************* 1505 * RX WBM ERROR APIS 1506 ******************************************************************************/ 1507 1508 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1509 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1510 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1511 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1512 /** 1513 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 1514 * the frame to this release ring 1515 * 1516 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1517 * frame to this queue 1518 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1519 * received routing instructions. No error within REO was detected 1520 */ 1521 enum hal_rx_wbm_reo_push_reason { 1522 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1523 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1524 }; 1525 1526 1527 /** 1528 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 1529 * this release ring 1530 * 1531 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1532 * this frame to this queue 1533 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1534 * per received routing instructions. No error within RXDMA was detected 1535 */ 1536 enum hal_rx_wbm_rxdma_push_reason { 1537 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1538 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1539 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1540 }; 1541 1542 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 1543 uint8_t dbg_level, 1544 struct hal_soc *hal) 1545 { 1546 1547 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 1548 } 1549 1550 /** 1551 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 1552 * human readable format. 1553 * @ msdu_end: pointer the msdu_end TLV in pkt. 1554 * @ dbg_level: log level. 1555 * 1556 * Return: void 1557 */ 1558 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1559 struct rx_msdu_end *msdu_end, 1560 uint8_t dbg_level) 1561 { 1562 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 1563 } 1564 1565 /** 1566 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 1567 * structure 1568 * @hal_ring: pointer to hal_srng structure 1569 * 1570 * Return: ring_id 1571 */ 1572 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1573 { 1574 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1575 } 1576 1577 #define DOT11_SEQ_FRAG_MASK 0x000f 1578 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1579 1580 /** 1581 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 1582 * 1583 * @nbuf: Network buffer 1584 * Returns: rx fragment number 1585 */ 1586 static inline 1587 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1588 uint8_t *buf) 1589 { 1590 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1591 } 1592 1593 /* 1594 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 1595 * @hal_soc_hdl: hal soc handle 1596 * @nbuf: Network buffer 1597 * 1598 * Return: value of sequence control valid field 1599 */ 1600 static inline 1601 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1602 uint8_t *buf) 1603 { 1604 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1605 1606 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1607 } 1608 1609 /* 1610 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 1611 * @hal_soc_hdl: hal soc handle 1612 * @nbuf: Network buffer 1613 * 1614 * Returns: value of frame control valid field 1615 */ 1616 static inline 1617 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1618 uint8_t *buf) 1619 { 1620 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1621 1622 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1623 } 1624 1625 /** 1626 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 1627 * @hal_soc_hdl: hal soc handle 1628 * @nbuf: Network buffer 1629 * Returns: value of mpdu 4th address valid field 1630 */ 1631 static inline 1632 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1633 uint8_t *buf) 1634 { 1635 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1636 1637 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1638 } 1639 1640 /* 1641 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 1642 * 1643 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1644 * Returns: None 1645 */ 1646 static inline void 1647 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1648 { 1649 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1650 } 1651 1652 /** 1653 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 1654 * save it to hal_wbm_err_desc_info structure passed by caller 1655 * @wbm_desc: wbm ring descriptor 1656 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1657 * Return: void 1658 */ 1659 static inline 1660 void hal_rx_wbm_err_info_get(void *wbm_desc, 1661 struct hal_wbm_err_desc_info *wbm_er_info, 1662 hal_soc_handle_t hal_soc_hdl) 1663 { 1664 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1665 1666 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1667 } 1668 1669 /** 1670 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 1671 * bit from wbm release ring descriptor 1672 * @wbm_desc: wbm ring descriptor 1673 * Return: uint8_t 1674 */ 1675 static inline 1676 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1677 void *wbm_desc) 1678 { 1679 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1680 1681 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1682 } 1683 1684 /** 1685 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 1686 * 1687 * @ hal_soc: HAL version of the SOC pointer 1688 * @ hw_desc_addr: Start address of Rx HW TLVs 1689 * @ rs: Status for monitor mode 1690 * 1691 * Return: void 1692 */ 1693 static inline 1694 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1695 void *hw_desc_addr, 1696 struct mon_rx_status *rs) 1697 { 1698 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1699 1700 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1701 } 1702 1703 /* 1704 * hal_rx_get_tlv(): API to get the tlv 1705 * 1706 * @hal_soc: HAL version of the SOC pointer 1707 * @rx_tlv: TLV data extracted from the rx packet 1708 * Return: uint8_t 1709 */ 1710 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1711 { 1712 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1713 } 1714 1715 /* 1716 * hal_rx_msdu_start_nss_get(): API to get the NSS 1717 * Interval from rx_msdu_start 1718 * 1719 * @hal_soc: HAL version of the SOC pointer 1720 * @buf: pointer to the start of RX PKT TLV header 1721 * Return: uint32_t(nss) 1722 */ 1723 static inline 1724 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1725 { 1726 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1727 1728 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1729 } 1730 1731 /** 1732 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 1733 * human readable format. 1734 * @ msdu_start: pointer the msdu_start TLV in pkt. 1735 * @ dbg_level: log level. 1736 * 1737 * Return: void 1738 */ 1739 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1740 struct rx_msdu_start *msdu_start, 1741 uint8_t dbg_level) 1742 { 1743 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 1744 } 1745 1746 /** 1747 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 1748 * info details 1749 * 1750 * @ buf - Pointer to buffer containing rx pkt tlvs. 1751 * 1752 * 1753 */ 1754 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1755 uint8_t *buf) 1756 { 1757 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1758 1759 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1760 } 1761 1762 /* 1763 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 1764 * Interval from rx_msdu_start 1765 * 1766 * @buf: pointer to the start of RX PKT TLV header 1767 * Return: uint32_t(reception_type) 1768 */ 1769 static inline 1770 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1771 uint8_t *buf) 1772 { 1773 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1774 1775 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1776 } 1777 1778 /** 1779 * hal_reo_status_get_header_generic - Process reo desc info 1780 * @d - Pointer to reo descriptior 1781 * @b - tlv type info 1782 * @h - Pointer to hal_reo_status_header where info to be stored 1783 * @hal- pointer to hal_soc structure 1784 * Return - none. 1785 * 1786 */ 1787 static inline 1788 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1789 void *h, struct hal_soc *hal_soc) 1790 { 1791 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1792 } 1793 1794 /** 1795 * hal_rx_desc_is_first_msdu() - Check if first msdu 1796 * 1797 * @hal_soc_hdl: hal_soc handle 1798 * @hw_desc_addr: hardware descriptor address 1799 * 1800 * Return: 0 - success/ non-zero failure 1801 */ 1802 static inline 1803 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1804 void *hw_desc_addr) 1805 { 1806 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1807 1808 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1809 } 1810 1811 /** 1812 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1813 * the rx tlv fields. 1814 * @hal_soc_hdl: HAL SoC handle 1815 * @buf: rx tlv start address [To be validated by caller] 1816 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1817 * 1818 * Return: None 1819 */ 1820 static inline void 1821 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1822 uint8_t *buf, 1823 void *mpdu_desc_info_hdl) 1824 { 1825 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1826 1827 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1828 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1829 mpdu_desc_info_hdl); 1830 } 1831 1832 static inline uint32_t 1833 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1834 { 1835 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1836 1837 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1838 } 1839 1840 static inline 1841 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1842 uint8_t *rx_tlv_hdr) 1843 { 1844 uint8_t decap_format; 1845 1846 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1847 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1848 rx_tlv_hdr); 1849 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1850 return true; 1851 } 1852 1853 return false; 1854 } 1855 1856 /** 1857 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 1858 * from rx_msdu_end TLV 1859 * @buf: pointer to the start of RX PKT TLV headers 1860 * 1861 * Return: fse metadata value from MSDU END TLV 1862 */ 1863 static inline uint32_t 1864 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1865 uint8_t *buf) 1866 { 1867 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1868 1869 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1870 } 1871 1872 /** 1873 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 1874 * <struct buffer_addr_info> structure 1875 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1876 * @buf_info: structure to return the buffer information including 1877 * paddr/cookie 1878 * 1879 * return: None 1880 */ 1881 static inline 1882 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 1883 struct hal_buf_info *buf_info) 1884 { 1885 buf_info->paddr = 1886 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 1887 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 1888 } 1889 1890 /** 1891 * hal_rx_msdu_flow_idx_get: API to get flow index 1892 * from rx_msdu_end TLV 1893 * @buf: pointer to the start of RX PKT TLV headers 1894 * 1895 * Return: flow index value from MSDU END TLV 1896 */ 1897 static inline uint32_t 1898 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 1899 uint8_t *buf) 1900 { 1901 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1902 1903 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 1904 } 1905 1906 /** 1907 * hal_rx_msdu_get_reo_destination_indication: API to get reo 1908 * destination index from rx_msdu_end TLV 1909 * @buf: pointer to the start of RX PKT TLV headers 1910 * @reo_destination_indication: pointer to return value of 1911 * reo_destination_indication 1912 * 1913 * Return: reo_destination_indication value from MSDU END TLV 1914 */ 1915 static inline void 1916 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 1917 uint8_t *buf, 1918 uint32_t *reo_destination_indication) 1919 { 1920 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1921 1922 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 1923 reo_destination_indication); 1924 } 1925 1926 /** 1927 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 1928 * from rx_msdu_end TLV 1929 * @buf: pointer to the start of RX PKT TLV headers 1930 * 1931 * Return: flow index timeout value from MSDU END TLV 1932 */ 1933 static inline bool 1934 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 1935 uint8_t *buf) 1936 { 1937 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1938 1939 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 1940 } 1941 1942 /** 1943 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 1944 * from rx_msdu_end TLV 1945 * @buf: pointer to the start of RX PKT TLV headers 1946 * 1947 * Return: flow index invalid value from MSDU END TLV 1948 */ 1949 static inline bool 1950 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 1951 uint8_t *buf) 1952 { 1953 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1954 1955 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 1956 } 1957 1958 /** 1959 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 1960 * @hal_soc_hdl: hal_soc handle 1961 * @rx_tlv_hdr: Rx_tlv_hdr 1962 * @rxdma_dst_ring_desc: Rx HW descriptor 1963 * 1964 * Return: ppdu id 1965 */ 1966 static inline 1967 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 1968 void *rx_tlv_hdr, 1969 void *rxdma_dst_ring_desc) 1970 { 1971 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1972 1973 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 1974 rxdma_dst_ring_desc); 1975 } 1976 1977 /** 1978 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 1979 * @hal_soc_hdl: hal_soc handle 1980 * @buf: rx tlv address 1981 * 1982 * Return: sw peer id 1983 */ 1984 static inline 1985 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1986 uint8_t *buf) 1987 { 1988 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1989 1990 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 1991 } 1992 1993 static inline 1994 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 1995 void *link_desc_addr) 1996 { 1997 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1998 1999 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 2000 } 2001 2002 static inline 2003 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 2004 void *msdu_addr) 2005 { 2006 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2007 2008 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 2009 } 2010 2011 static inline 2012 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2013 void *hw_addr) 2014 { 2015 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2016 2017 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 2018 } 2019 2020 static inline 2021 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2022 void *hw_addr) 2023 { 2024 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2025 2026 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 2027 } 2028 2029 static inline 2030 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 2031 uint8_t *buf) 2032 { 2033 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2034 2035 return hal_soc->ops->hal_rx_get_fc_valid(buf); 2036 } 2037 2038 static inline 2039 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2040 { 2041 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2042 2043 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 2044 } 2045 2046 static inline 2047 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 2048 uint8_t *buf) 2049 { 2050 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2051 2052 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 2053 } 2054 2055 static inline 2056 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 2057 uint8_t *buf) 2058 { 2059 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2060 2061 return hal_soc->ops->hal_rx_get_filter_category(buf); 2062 } 2063 2064 static inline 2065 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 2066 uint8_t *buf) 2067 { 2068 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2069 2070 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 2071 } 2072 2073 /** 2074 * hal_reo_config(): Set reo config parameters 2075 * @soc: hal soc handle 2076 * @reg_val: value to be set 2077 * @reo_params: reo parameters 2078 * 2079 * Return: void 2080 */ 2081 static inline 2082 void hal_reo_config(struct hal_soc *hal_soc, 2083 uint32_t reg_val, 2084 struct hal_reo_params *reo_params) 2085 { 2086 hal_soc->ops->hal_reo_config(hal_soc, 2087 reg_val, 2088 reo_params); 2089 } 2090 2091 /** 2092 * hal_rx_msdu_get_flow_params: API to get flow index, 2093 * flow index invalid and flow index timeout from rx_msdu_end TLV 2094 * @buf: pointer to the start of RX PKT TLV headers 2095 * @flow_invalid: pointer to return value of flow_idx_valid 2096 * @flow_timeout: pointer to return value of flow_idx_timeout 2097 * @flow_index: pointer to return value of flow_idx 2098 * 2099 * Return: none 2100 */ 2101 static inline void 2102 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2103 uint8_t *buf, 2104 bool *flow_invalid, 2105 bool *flow_timeout, 2106 uint32_t *flow_index) 2107 { 2108 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2109 2110 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2111 flow_invalid, 2112 flow_timeout, 2113 flow_index); 2114 } 2115 2116 static inline 2117 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2118 uint8_t *buf) 2119 { 2120 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2121 2122 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2123 } 2124 2125 static inline 2126 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2127 uint8_t *buf) 2128 { 2129 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2130 2131 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2132 } 2133 2134 static inline void 2135 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2136 void *rx_tlv, 2137 void *ppdu_info) 2138 { 2139 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2140 2141 if (hal_soc->ops->hal_rx_get_bb_info) 2142 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2143 } 2144 2145 static inline void 2146 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2147 void *rx_tlv, 2148 void *ppdu_info) 2149 { 2150 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2151 2152 if (hal_soc->ops->hal_rx_get_rtt_info) 2153 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2154 } 2155 2156 /** 2157 * hal_rx_msdu_metadata_get(): API to get the 2158 * fast path information from rx_msdu_end TLV 2159 * 2160 * @ hal_soc_hdl: DP soc handle 2161 * @ buf: pointer to the start of RX PKT TLV headers 2162 * @ msdu_metadata: Structure to hold msdu end information 2163 * Return: none 2164 */ 2165 static inline void 2166 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2167 struct hal_rx_msdu_metadata *msdu_md) 2168 { 2169 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2170 2171 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2172 } 2173 2174 /** 2175 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 2176 * from rx_msdu_end TLV 2177 * @buf: pointer to the start of RX PKT TLV headers 2178 * 2179 * Return: cumulative_l4_checksum 2180 */ 2181 static inline uint16_t 2182 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2183 uint8_t *buf) 2184 { 2185 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2186 2187 if (!hal_soc || !hal_soc->ops) { 2188 hal_err("hal handle is NULL"); 2189 QDF_BUG(0); 2190 return 0; 2191 } 2192 2193 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2194 return 0; 2195 2196 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2197 } 2198 2199 /** 2200 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 2201 * from rx_msdu_end TLV 2202 * @buf: pointer to the start of RX PKT TLV headers 2203 * 2204 * Return: cumulative_ip_length 2205 */ 2206 static inline uint16_t 2207 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2208 uint8_t *buf) 2209 { 2210 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2211 2212 if (!hal_soc || !hal_soc->ops) { 2213 hal_err("hal handle is NULL"); 2214 QDF_BUG(0); 2215 return 0; 2216 } 2217 2218 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2219 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2220 2221 return 0; 2222 } 2223 2224 /** 2225 * hal_rx_get_udp_proto: API to get UDP proto field 2226 * from rx_msdu_start TLV 2227 * @buf: pointer to the start of RX PKT TLV headers 2228 * 2229 * Return: UDP proto field value 2230 */ 2231 static inline bool 2232 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2233 { 2234 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2235 2236 if (!hal_soc || !hal_soc->ops) { 2237 hal_err("hal handle is NULL"); 2238 QDF_BUG(0); 2239 return 0; 2240 } 2241 2242 if (hal_soc->ops->hal_rx_get_udp_proto) 2243 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2244 2245 return 0; 2246 } 2247 2248 /** 2249 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 2250 * from rx_msdu_end TLV 2251 * @buf: pointer to the start of RX PKT TLV headers 2252 * 2253 * Return: flow_agg_continuation bit field value 2254 */ 2255 static inline bool 2256 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2257 uint8_t *buf) 2258 { 2259 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2260 2261 if (!hal_soc || !hal_soc->ops) { 2262 hal_err("hal handle is NULL"); 2263 QDF_BUG(0); 2264 return 0; 2265 } 2266 2267 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2268 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2269 2270 return 0; 2271 } 2272 2273 /** 2274 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 2275 * rx_msdu_end TLV 2276 * @buf: pointer to the start of RX PKT TLV headers 2277 * 2278 * Return: flow_agg count value 2279 */ 2280 static inline uint8_t 2281 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2282 uint8_t *buf) 2283 { 2284 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2285 2286 if (!hal_soc || !hal_soc->ops) { 2287 hal_err("hal handle is NULL"); 2288 QDF_BUG(0); 2289 return 0; 2290 } 2291 2292 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2293 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2294 2295 return 0; 2296 } 2297 2298 /** 2299 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 2300 * @buf: pointer to the start of RX PKT TLV headers 2301 * 2302 * Return: fisa flow_agg timeout bit value 2303 */ 2304 static inline bool 2305 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2306 { 2307 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2308 2309 if (!hal_soc || !hal_soc->ops) { 2310 hal_err("hal handle is NULL"); 2311 QDF_BUG(0); 2312 return 0; 2313 } 2314 2315 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2316 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2317 2318 return 0; 2319 } 2320 2321 /** 2322 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 2323 * tag is valid 2324 * 2325 * @hal_soc_hdl: HAL SOC handle 2326 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2327 * 2328 * Return: true if RX_MPDU_START tlv tag is valid, else false 2329 */ 2330 2331 static inline uint8_t 2332 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2333 void *rx_tlv_hdr) 2334 { 2335 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2336 2337 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2338 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2339 2340 return 0; 2341 } 2342 2343 /** 2344 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 2345 * buffer addr info 2346 * @link_desc_va: pointer to current msdu link Desc 2347 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2348 * 2349 * return: None 2350 */ 2351 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2352 void *link_desc_va, 2353 struct buffer_addr_info *next_addr_info) 2354 { 2355 struct rx_msdu_link *msdu_link = link_desc_va; 2356 2357 if (!msdu_link) { 2358 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2359 return; 2360 } 2361 2362 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2363 } 2364 2365 /** 2366 * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc 2367 * buffer addr info 2368 * @link_desc_va: pointer to current msdu link Desc 2369 * 2370 * return: None 2371 */ 2372 static inline 2373 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2374 { 2375 struct rx_msdu_link *msdu_link = link_desc_va; 2376 2377 if (msdu_link) 2378 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2379 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2380 } 2381 2382 /** 2383 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 2384 * 2385 * @buf_addr_info: pointer to buf_addr_info structure 2386 * 2387 * return: true: has valid paddr, false: not. 2388 */ 2389 static inline 2390 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2391 { 2392 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2393 false : true; 2394 } 2395 2396 /** 2397 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 2398 * rx_pkt_tlvs structure 2399 * 2400 * @hal_soc_hdl: HAL SOC handle 2401 * return: msdu_end_tlv offset value 2402 */ 2403 static inline 2404 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2405 { 2406 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2407 2408 if (!hal_soc || !hal_soc->ops) { 2409 hal_err("hal handle is NULL"); 2410 QDF_BUG(0); 2411 return 0; 2412 } 2413 2414 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2415 } 2416 2417 /** 2418 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 2419 * rx_pkt_tlvs structure 2420 * 2421 * @hal_soc_hdl: HAL SOC handle 2422 * return: msdu_start_tlv offset value 2423 */ 2424 static inline 2425 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2426 { 2427 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2428 2429 if (!hal_soc || !hal_soc->ops) { 2430 hal_err("hal handle is NULL"); 2431 QDF_BUG(0); 2432 return 0; 2433 } 2434 2435 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2436 } 2437 2438 /** 2439 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 2440 * rx_pkt_tlvs structure 2441 * 2442 * @hal_soc_hdl: HAL SOC handle 2443 * return: mpdu_start_tlv offset value 2444 */ 2445 static inline 2446 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2447 { 2448 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2449 2450 if (!hal_soc || !hal_soc->ops) { 2451 hal_err("hal handle is NULL"); 2452 QDF_BUG(0); 2453 return 0; 2454 } 2455 2456 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2457 } 2458 2459 static inline 2460 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2461 { 2462 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2463 2464 if (!hal_soc || !hal_soc->ops) { 2465 hal_err("hal handle is NULL"); 2466 QDF_BUG(0); 2467 return 0; 2468 } 2469 2470 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2471 } 2472 2473 /** 2474 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 2475 * rx_pkt_tlvs structure 2476 * 2477 * @hal_soc_hdl: HAL SOC handle 2478 * return: mpdu_end_tlv offset value 2479 */ 2480 static inline 2481 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2482 { 2483 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2484 2485 if (!hal_soc || !hal_soc->ops) { 2486 hal_err("hal handle is NULL"); 2487 QDF_BUG(0); 2488 return 0; 2489 } 2490 2491 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2492 } 2493 2494 /** 2495 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 2496 * rx_pkt_tlvs structure 2497 * 2498 * @hal_soc_hdl: HAL SOC handle 2499 * return: attn_tlv offset value 2500 */ 2501 static inline 2502 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2503 { 2504 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2505 2506 if (!hal_soc || !hal_soc->ops) { 2507 hal_err("hal handle is NULL"); 2508 QDF_BUG(0); 2509 return 0; 2510 } 2511 2512 return hal_soc->ops->hal_rx_attn_offset_get(); 2513 } 2514 2515 /** 2516 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 2517 * @msdu_details_ptr - Pointer to msdu_details_ptr 2518 * @hal - pointer to hal_soc 2519 * Return - Pointer to rx_msdu_desc_info structure. 2520 * 2521 */ 2522 static inline 2523 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2524 struct hal_soc *hal_soc) 2525 { 2526 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2527 msdu_details_ptr); 2528 } 2529 2530 static inline void 2531 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2532 uint8_t *buf, uint8_t dbg_level) 2533 { 2534 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2535 2536 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2537 } 2538 2539 //TODO - Change the names to not include tlv names 2540 static inline uint16_t 2541 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2542 { 2543 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2544 2545 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2546 } 2547 2548 static inline uint32_t 2549 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2550 { 2551 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2552 2553 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2554 } 2555 2556 static inline uint32_t 2557 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2558 { 2559 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2560 2561 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2562 } 2563 2564 static inline uint16_t 2565 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2566 { 2567 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2568 2569 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2570 } 2571 2572 static inline int 2573 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2574 uint8_t *rx_pkt_tlv, 2575 struct hal_offload_info *offload_info) 2576 { 2577 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2578 2579 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2580 offload_info); 2581 2582 } 2583 2584 static inline int 2585 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2586 void *proto_params) 2587 { 2588 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2589 2590 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2591 } 2592 2593 static inline int 2594 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2595 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2596 { 2597 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2598 2599 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2600 l3_hdr_offset, 2601 l4_hdr_offset); 2602 } 2603 2604 static inline uint32_t 2605 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2606 { 2607 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2608 2609 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2610 } 2611 2612 /* 2613 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 2614 * from rx_msdu_start 2615 * 2616 * @buf: pointer to the start of RX PKT TLV header 2617 * Return: uint32_t(pkt type) 2618 */ 2619 2620 static inline uint32_t 2621 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2622 { 2623 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2624 2625 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2626 } 2627 2628 static inline void 2629 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2630 uint8_t *buf, uint64_t *pn_num) 2631 { 2632 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2633 2634 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2635 } 2636 2637 static inline uint8_t * 2638 hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc) 2639 { 2640 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2641 2642 if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr) 2643 return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc); 2644 2645 return NULL; 2646 } 2647 2648 static inline uint64_t 2649 hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc, 2650 uint8_t *buf) 2651 { 2652 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2653 2654 if (hal_soc->ops->hal_rx_get_qdesc_addr) 2655 return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf); 2656 2657 return 0; 2658 } 2659 2660 static inline void 2661 hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl, 2662 uint8_t *desc, uint32_t dst_ind) 2663 { 2664 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2665 2666 if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind) 2667 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind); 2668 } 2669 2670 static inline uint32_t 2671 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2672 { 2673 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2674 2675 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2676 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2677 2678 return 0; 2679 } 2680 2681 static inline uint8_t * 2682 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2683 { 2684 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2685 2686 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2687 } 2688 2689 static inline uint8_t 2690 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2691 { 2692 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2693 2694 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2695 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2696 2697 return 0; 2698 } 2699 2700 static inline uint32_t 2701 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2702 { 2703 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2704 2705 if (hal_soc->ops->hal_rx_tlv_get_freq) 2706 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2707 2708 return 0; 2709 } 2710 2711 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2712 void *mpdu_desc_info, uint32_t val) 2713 { 2714 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2715 2716 if (hal_soc->ops->hal_mpdu_desc_info_set) 2717 return hal_soc->ops->hal_mpdu_desc_info_set( 2718 hal_soc_hdl, mpdu_desc_info, val); 2719 } 2720 2721 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2722 void *msdu_desc_info, 2723 uint32_t val, uint32_t nbuf_len) 2724 { 2725 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2726 2727 if (hal_soc->ops->hal_msdu_desc_info_set) 2728 return hal_soc->ops->hal_msdu_desc_info_set( 2729 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2730 } 2731 2732 static inline uint32_t 2733 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2734 { 2735 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2736 2737 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2738 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2739 hal_soc_hdl, msdu_link_desc); 2740 2741 return 0; 2742 } 2743 2744 static inline uint32_t 2745 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2746 { 2747 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2748 2749 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2750 } 2751 2752 static inline uint32_t 2753 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2754 { 2755 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2756 2757 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2758 } 2759 2760 static inline uint32_t 2761 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2762 { 2763 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2764 2765 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2766 } 2767 2768 static inline uint32_t 2769 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2770 { 2771 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2772 2773 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2774 } 2775 2776 static inline uint32_t 2777 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2778 { 2779 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2780 2781 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2782 } 2783 2784 static inline uint32_t 2785 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2786 hal_ring_desc_t ring_desc) 2787 { 2788 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2789 2790 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2791 } 2792 2793 /** 2794 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2795 * from the BUFFER_ADDR_INFO structure 2796 * given a REO destination ring descriptor. 2797 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2798 * 2799 * Return: uint8_t (value of the return_buffer_manager) 2800 */ 2801 static inline uint8_t 2802 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2803 hal_ring_desc_t ring_desc) 2804 { 2805 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2806 2807 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2808 } 2809 2810 /* 2811 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2812 * rxdma ring entry. 2813 * @rxdma_entry: descriptor entry 2814 * @paddr: physical address of nbuf data pointer. 2815 * @cookie: SW cookie used as a index to SW rx desc. 2816 * @manager: who owns the nbuf (host, NSS, etc...). 2817 * 2818 */ 2819 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 2820 void *rxdma_entry, 2821 qdf_dma_addr_t paddr, 2822 uint32_t cookie, 2823 uint8_t manager) 2824 { 2825 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2826 2827 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 2828 paddr, 2829 cookie, 2830 manager); 2831 } 2832 2833 static inline uint32_t 2834 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2835 { 2836 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2837 2838 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 2839 } 2840 2841 static inline void 2842 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 2843 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 2844 { 2845 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2846 2847 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 2848 ip_csum_err, 2849 tcp_udp_csum_err); 2850 } 2851 2852 static inline void 2853 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 2854 uint8_t *rx_tlv_hdr, 2855 struct hal_rx_pkt_capture_flags *flags) 2856 { 2857 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2858 2859 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 2860 flags); 2861 } 2862 2863 static inline uint8_t 2864 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2865 { 2866 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2867 2868 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 2869 } 2870 2871 static inline uint8_t 2872 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2873 { 2874 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2875 2876 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 2877 } 2878 2879 /** 2880 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 2881 * @hal_soc_hdl: HAL SoC handle 2882 * @ring_desc: REO ring descriptor 2883 * @prev_pn: Buffer to populate the previos PN 2884 * 2885 * Return: None 2886 */ 2887 static inline void 2888 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 2889 uint64_t *prev_pn) 2890 { 2891 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2892 2893 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 2894 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 2895 } 2896 2897 /** 2898 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 2899 * from rx mpdu info 2900 * @buf: pointer to rx_pkt_tlvs 2901 * 2902 * No input validdataion, since this function is supposed to be 2903 * called from fastpath. 2904 * 2905 * Return: ampdu flag 2906 */ 2907 static inline bool 2908 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2909 { 2910 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2911 2912 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 2913 } 2914 2915 #ifdef REO_SHARED_QREF_TABLE_EN 2916 /** 2917 * hal_reo_shared_qaddr_write(): Write REo tid queue addr 2918 * LUT shared by SW and HW at the index given by peer id 2919 * and tid. 2920 * 2921 * @hal_soc: hal soc pointer 2922 * @reo_qref_addr: pointer to index pointed to be peer_id 2923 * and tid 2924 * @tid: tid queue number 2925 * @hw_qdesc_paddr: reo queue addr 2926 */ 2927 static inline void 2928 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 2929 uint16_t peer_id, 2930 int tid, 2931 qdf_dma_addr_t hw_qdesc_paddr) 2932 { 2933 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2934 2935 if (hal_soc->ops->hal_reo_shared_qaddr_write) 2936 return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl, 2937 peer_id, tid, hw_qdesc_paddr); 2938 } 2939 2940 /** 2941 * hal_reo_shared_qaddr_init(): Initialize reo qref LUT 2942 * @hal_soc: Hal soc pointer 2943 * 2944 * Write MLO and Non MLO table start addr to HW reg 2945 * 2946 * Return: void 2947 */ 2948 static inline void 2949 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl) 2950 { 2951 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2952 2953 if (hal_soc->ops->hal_reo_shared_qaddr_init) 2954 return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl); 2955 } 2956 2957 /** 2958 * hal_reo_shared_qaddr_cache_clear(): Set and unset 'clear_qdesc_array' 2959 * bit in reo reg for shared qref feature. This is done for every MLO 2960 * connection to clear HW reo internal storage for clearing stale entry 2961 * of prev peer having same peer id 2962 * 2963 * @hal_soc: Hal soc pointer 2964 * 2965 * Write MLO and Non MLO table start addr to HW reg 2966 * 2967 * Return: void 2968 */ 2969 static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) 2970 { 2971 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2972 2973 if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear) 2974 return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl); 2975 } 2976 2977 #else 2978 static inline void 2979 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 2980 uint16_t peer_id, 2981 int tid, 2982 qdf_dma_addr_t hw_qdesc_paddr) {} 2983 static inline void 2984 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl) {} 2985 2986 static inline void 2987 hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {} 2988 2989 #endif /* REO_SHARED_QREF_TABLE_EN */ 2990 2991 static inline uint8_t 2992 hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl) 2993 { 2994 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2995 2996 return hal->reo_qref.reo_qref_table_en; 2997 } 2998 2999 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3000 static inline uint8_t 3001 hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3002 { 3003 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3004 3005 return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf); 3006 } 3007 #endif 3008 3009 static inline uint32_t 3010 hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3011 { 3012 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3013 3014 return hal_soc->ops->hal_rx_tlv_l3_type_get(buf); 3015 } 3016 #endif /* _HAL_RX_H */ 3017