1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 24 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 25 #define HAL_RX_LSB(block, field) block##_##field##_LSB 26 #define HAL_RX_MASk(block, field) block##_##field##_MASK 27 28 #define HAL_RX_GET(_ptr, block, field) \ 29 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 30 HAL_RX_MASk(block, field)) >> \ 31 HAL_RX_LSB(block, field)) 32 33 #ifdef NO_RX_PKT_HDR_TLV 34 /* RX_BUFFER_SIZE = 1536 data bytes + 256 RX TLV bytes. We are avoiding 35 * 128 bytes of RX_PKT_HEADER_TLV. 36 */ 37 #define RX_BUFFER_SIZE 1792 38 #else 39 /* RX_BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 40 #define RX_BUFFER_SIZE 2048 41 #endif 42 43 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 44 #define HAL_RX_NON_QOS_TID 16 45 46 enum { 47 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 48 HAL_HW_RX_DECAP_FORMAT_NWIFI, 49 HAL_HW_RX_DECAP_FORMAT_ETH2, 50 HAL_HW_RX_DECAP_FORMAT_8023, 51 }; 52 53 /** 54 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 55 * 56 * @reo_psh_rsn: REO push reason 57 * @reo_err_code: REO Error code 58 * @rxdma_psh_rsn: RXDMA push reason 59 * @rxdma_err_code: RXDMA Error code 60 * @reserved_1: Reserved bits 61 * @wbm_err_src: WBM error source 62 * @pool_id: pool ID, indicates which rxdma pool 63 * @reserved_2: Reserved bits 64 */ 65 struct hal_wbm_err_desc_info { 66 uint16_t reo_psh_rsn:2, 67 reo_err_code:5, 68 rxdma_psh_rsn:2, 69 rxdma_err_code:5, 70 reserved_1:2; 71 uint8_t wbm_err_src:3, 72 pool_id:2, 73 reserved_2:3; 74 }; 75 76 /** 77 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 78 * 79 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 80 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 81 */ 82 enum hal_reo_error_status { 83 HAL_REO_ERROR_DETECTED = 0, 84 HAL_REO_ROUTING_INSTRUCTION = 1, 85 }; 86 87 /** 88 * @msdu_flags: [0] first_msdu_in_mpdu 89 * [1] last_msdu_in_mpdu 90 * [2] msdu_continuation - MSDU spread across buffers 91 * [23] sa_is_valid - SA match in peer table 92 * [24] sa_idx_timeout - Timeout while searching for SA match 93 * [25] da_is_valid - Used to identtify intra-bss forwarding 94 * [26] da_is_MCBC 95 * [27] da_idx_timeout - Timeout while searching for DA match 96 * 97 */ 98 struct hal_rx_msdu_desc_info { 99 uint32_t msdu_flags; 100 uint16_t msdu_len; /* 14 bits for length */ 101 }; 102 103 /** 104 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 105 * 106 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 107 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 108 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 109 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 110 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 111 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 112 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 113 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 114 */ 115 enum hal_rx_msdu_desc_flags { 116 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 117 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 118 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 119 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 120 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 121 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 122 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 123 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 124 }; 125 126 /* 127 * @msdu_count: no. of msdus in the MPDU 128 * @mpdu_seq: MPDU sequence number 129 * @mpdu_flags [0] Fragment flag 130 * [1] MPDU_retry_bit 131 * [2] AMPDU flag 132 * [3] raw_ampdu 133 * @peer_meta_data: Upper bits containing peer id, vdev id 134 */ 135 struct hal_rx_mpdu_desc_info { 136 uint16_t msdu_count; 137 uint16_t mpdu_seq; /* 12 bits for length */ 138 uint32_t mpdu_flags; 139 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 140 }; 141 142 /** 143 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 144 * 145 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 146 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 147 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 148 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 149 */ 150 enum hal_rx_mpdu_desc_flags { 151 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 152 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 153 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 154 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 155 }; 156 157 /** 158 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 159 * BUFFER_ADDR_INFO structure 160 * 161 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 162 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 163 * descriptor list 164 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 165 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 166 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 167 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 168 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 169 */ 170 enum hal_rx_ret_buf_manager { 171 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 172 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 173 HAL_RX_BUF_RBM_FW_BM = 2, 174 HAL_RX_BUF_RBM_SW0_BM = 3, 175 HAL_RX_BUF_RBM_SW1_BM = 4, 176 HAL_RX_BUF_RBM_SW2_BM = 5, 177 HAL_RX_BUF_RBM_SW3_BM = 6, 178 }; 179 180 /* 181 * Given the offset of a field in bytes, returns uint8_t * 182 */ 183 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 184 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 185 186 /* 187 * Given the offset of a field in bytes, returns uint32_t * 188 */ 189 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 190 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 191 192 #define _HAL_MS(_word, _mask, _shift) \ 193 (((_word) & (_mask)) >> (_shift)) 194 195 /* 196 * macro to set the LSW of the nbuf data physical address 197 * to the rxdma ring entry 198 */ 199 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 200 ((*(((unsigned int *) buff_addr_info) + \ 201 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 202 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 203 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 204 205 /* 206 * macro to set the LSB of MSW of the nbuf data physical address 207 * to the rxdma ring entry 208 */ 209 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 210 ((*(((unsigned int *) buff_addr_info) + \ 211 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 212 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 213 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 214 215 /* 216 * macro to set the cookie into the rxdma ring entry 217 */ 218 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 219 ((*(((unsigned int *) buff_addr_info) + \ 220 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 221 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 222 ((*(((unsigned int *) buff_addr_info) + \ 223 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 224 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 225 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 226 227 /* 228 * macro to set the manager into the rxdma ring entry 229 */ 230 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 231 ((*(((unsigned int *) buff_addr_info) + \ 232 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 233 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 234 ((*(((unsigned int *) buff_addr_info) + \ 235 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 236 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 237 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 238 239 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 240 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 241 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 242 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 243 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 244 245 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 246 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 247 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 248 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 249 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 250 251 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 252 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 253 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 254 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 255 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 256 257 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 258 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 259 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 260 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 261 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 262 263 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 264 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 265 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 266 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 267 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 268 269 /* TODO: Convert the following structure fields accesseses to offsets */ 270 271 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 272 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 273 (((struct reo_destination_ring *) \ 274 reo_desc)->buf_or_link_desc_addr_info))) 275 276 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 277 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 278 (((struct reo_destination_ring *) \ 279 reo_desc)->buf_or_link_desc_addr_info))) 280 281 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 282 (HAL_RX_BUF_COOKIE_GET(& \ 283 (((struct reo_destination_ring *) \ 284 reo_desc)->buf_or_link_desc_addr_info))) 285 286 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 287 ((mpdu_info_ptr \ 288 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 289 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 290 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 291 292 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 293 ((mpdu_info_ptr \ 294 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 295 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 296 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 297 298 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 299 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 300 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 301 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 302 303 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 304 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 305 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 306 307 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 308 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 309 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 310 311 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 312 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 313 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 314 315 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 316 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 317 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 318 319 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 320 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 321 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 322 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 323 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 324 325 326 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 327 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 328 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 329 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 330 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 331 332 /* 333 * NOTE: None of the following _GET macros need a right 334 * shift by the corresponding _LSB. This is because, they are 335 * finally taken and "OR'ed" into a single word again. 336 */ 337 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 338 ((*(((uint32_t *)msdu_info_ptr) + \ 339 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 340 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 341 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 342 343 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 344 ((*(((uint32_t *)msdu_info_ptr) + \ 345 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 346 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 347 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 348 349 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 350 ((*(((uint32_t *)msdu_info_ptr) + \ 351 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 352 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 353 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 354 355 356 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 357 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 358 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 359 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 360 361 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 362 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 363 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 364 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 365 366 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 367 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 368 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 369 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 370 371 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 372 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 373 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 374 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 375 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 376 377 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 378 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 379 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 380 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 381 382 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 383 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 384 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 385 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 386 387 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 388 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 389 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 390 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 391 392 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 393 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 394 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 395 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 396 397 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 398 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 399 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 400 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 401 402 403 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 404 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 405 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 406 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 407 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 408 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 409 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 410 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 411 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 412 413 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 414 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 415 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 416 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 417 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 418 419 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 420 (*(uint32_t *)(((uint8_t *)_ptr) + \ 421 _wrd ## _ ## _field ## _OFFSET) |= \ 422 ((_val << _wrd ## _ ## _field ## _LSB) & \ 423 _wrd ## _ ## _field ## _MASK)) 424 425 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 426 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 427 _field, _val) 428 429 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 430 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 431 _field, _val) 432 433 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 434 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 435 _field, _val) 436 437 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 438 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 439 { 440 struct reo_destination_ring *reo_dst_ring; 441 uint32_t *mpdu_info; 442 443 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 444 445 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 446 447 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 448 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 449 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 450 mpdu_desc_info->peer_meta_data = 451 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 452 } 453 454 /* 455 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 456 * @ Specifically flags needed are: 457 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 458 * @ msdu_continuation, sa_is_valid, 459 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 460 * @ da_is_MCBC 461 * 462 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 463 * @ descriptor 464 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 465 * @ Return: void 466 */ 467 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 468 struct hal_rx_msdu_desc_info *msdu_desc_info) 469 { 470 struct reo_destination_ring *reo_dst_ring; 471 uint32_t *msdu_info; 472 473 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 474 475 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 476 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 477 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 478 } 479 480 /* 481 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 482 * rxdma ring entry. 483 * @rxdma_entry: descriptor entry 484 * @paddr: physical address of nbuf data pointer. 485 * @cookie: SW cookie used as a index to SW rx desc. 486 * @manager: who owns the nbuf (host, NSS, etc...). 487 * 488 */ 489 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 490 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 491 { 492 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 493 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 494 495 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 496 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 497 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 498 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 499 } 500 501 /* 502 * Structures & Macros to obtain fields from the TLV's in the Rx packet 503 * pre-header. 504 */ 505 506 /* 507 * Every Rx packet starts at an offset from the top of the buffer. 508 * If the host hasn't subscribed to any specific TLV, there is 509 * still space reserved for the following TLV's from the start of 510 * the buffer: 511 * -- RX ATTENTION 512 * -- RX MPDU START 513 * -- RX MSDU START 514 * -- RX MSDU END 515 * -- RX MPDU END 516 * -- RX PACKET HEADER (802.11) 517 * If the host subscribes to any of the TLV's above, that TLV 518 * if populated by the HW 519 */ 520 521 #define NUM_DWORDS_TAG 1 522 523 /* By default the packet header TLV is 128 bytes */ 524 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 525 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 526 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 527 528 #define RX_PKT_OFFSET_WORDS \ 529 ( \ 530 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 531 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 532 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 533 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 534 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 535 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 536 ) 537 538 #define RX_PKT_OFFSET_BYTES \ 539 (RX_PKT_OFFSET_WORDS << 2) 540 541 #define RX_PKT_HDR_TLV_LEN 120 542 543 /* 544 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 545 */ 546 struct rx_attention_tlv { 547 uint32_t tag; 548 struct rx_attention rx_attn; 549 }; 550 551 struct rx_mpdu_start_tlv { 552 uint32_t tag; 553 struct rx_mpdu_start rx_mpdu_start; 554 }; 555 556 struct rx_msdu_start_tlv { 557 uint32_t tag; 558 struct rx_msdu_start rx_msdu_start; 559 }; 560 561 struct rx_msdu_end_tlv { 562 uint32_t tag; 563 struct rx_msdu_end rx_msdu_end; 564 }; 565 566 struct rx_mpdu_end_tlv { 567 uint32_t tag; 568 struct rx_mpdu_end rx_mpdu_end; 569 }; 570 571 struct rx_pkt_hdr_tlv { 572 uint32_t tag; /* 4 B */ 573 uint32_t phy_ppdu_id; /* 4 B */ 574 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 575 }; 576 577 578 #define RXDMA_OPTIMIZATION 579 580 #ifdef RXDMA_OPTIMIZATION 581 /* 582 * The RX_PADDING_BYTES is required so that the TLV's don't 583 * spread across the 128 byte boundary 584 * RXDMA optimization requires: 585 * 1) MSDU_END & ATTENTION TLV's follow in that order 586 * 2) TLV's don't span across 128 byte lines 587 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 588 */ 589 #define RX_PADDING0_BYTES 4 590 #define RX_PADDING1_BYTES 16 591 struct rx_pkt_tlvs { 592 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 593 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 594 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 595 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 596 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 597 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 598 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 599 #ifndef NO_RX_PKT_HDR_TLV 600 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 601 #endif 602 }; 603 #else /* RXDMA_OPTIMIZATION */ 604 struct rx_pkt_tlvs { 605 struct rx_attention_tlv attn_tlv; 606 struct rx_mpdu_start_tlv mpdu_start_tlv; 607 struct rx_msdu_start_tlv msdu_start_tlv; 608 struct rx_msdu_end_tlv msdu_end_tlv; 609 struct rx_mpdu_end_tlv mpdu_end_tlv; 610 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 611 }; 612 #endif /* RXDMA_OPTIMIZATION */ 613 614 #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs)) 615 616 #ifdef NO_RX_PKT_HDR_TLV 617 static inline uint8_t 618 *hal_rx_pkt_hdr_get(uint8_t *buf) 619 { 620 return buf + RX_PKT_TLVS_LEN; 621 } 622 #else 623 static inline uint8_t 624 *hal_rx_pkt_hdr_get(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 628 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 629 630 } 631 #endif 632 633 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 634 635 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 636 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 637 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 638 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 639 RX_PKT_TLV_OFFSET(msdu_start_tlv) 640 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 641 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 642 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 643 644 static inline uint8_t 645 *hal_rx_padding0_get(uint8_t *buf) 646 { 647 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 648 649 return pkt_tlvs->rx_padding0; 650 } 651 652 /* 653 * hal_rx_encryption_info_valid(): Returns encryption type. 654 * 655 * @hal_soc_hdl: hal soc handle 656 * @buf: rx_tlv_hdr of the received packet 657 * 658 * Return: encryption type 659 */ 660 static inline uint32_t 661 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 662 { 663 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 664 665 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 666 667 } 668 669 /* 670 * hal_rx_print_pn: Prints the PN of rx packet. 671 * @hal_soc_hdl: hal soc handle 672 * @buf: rx_tlv_hdr of the received packet 673 * 674 * Return: void 675 */ 676 static inline void 677 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 678 { 679 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 680 681 hal_soc->ops->hal_rx_print_pn(buf); 682 } 683 684 /* 685 * Get msdu_done bit from the RX_ATTENTION TLV 686 */ 687 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 688 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 689 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 690 RX_ATTENTION_2_MSDU_DONE_MASK, \ 691 RX_ATTENTION_2_MSDU_DONE_LSB)) 692 693 static inline uint32_t 694 hal_rx_attn_msdu_done_get(uint8_t *buf) 695 { 696 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 697 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 698 uint32_t msdu_done; 699 700 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 701 702 return msdu_done; 703 } 704 705 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 706 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 707 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 708 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 709 RX_ATTENTION_1_FIRST_MPDU_LSB)) 710 711 /* 712 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 713 * @buf: pointer to rx_pkt_tlvs 714 * 715 * reutm: uint32_t(first_msdu) 716 */ 717 static inline uint32_t 718 hal_rx_attn_first_mpdu_get(uint8_t *buf) 719 { 720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 721 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 722 uint32_t first_mpdu; 723 724 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 725 726 return first_mpdu; 727 } 728 729 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 730 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 731 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 732 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 733 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 734 735 /* 736 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 737 * from rx attention 738 * @buf: pointer to rx_pkt_tlvs 739 * 740 * Return: tcp_udp_cksum_fail 741 */ 742 static inline bool 743 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 744 { 745 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 746 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 747 bool tcp_udp_cksum_fail; 748 749 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 750 751 return tcp_udp_cksum_fail; 752 } 753 754 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 755 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 756 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 757 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 758 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 759 760 /* 761 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 762 * from rx attention 763 * @buf: pointer to rx_pkt_tlvs 764 * 765 * Return: ip_cksum_fail 766 */ 767 static inline bool 768 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 769 { 770 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 771 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 772 bool ip_cksum_fail; 773 774 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 775 776 return ip_cksum_fail; 777 } 778 779 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 780 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 781 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 782 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 783 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 784 785 /* 786 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 787 * from rx attention 788 * @buf: pointer to rx_pkt_tlvs 789 * 790 * Return: phy_ppdu_id 791 */ 792 static inline uint16_t 793 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 794 { 795 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 796 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 797 uint16_t phy_ppdu_id; 798 799 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 800 801 return phy_ppdu_id; 802 } 803 804 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 805 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 806 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 807 RX_ATTENTION_1_CCE_MATCH_MASK, \ 808 RX_ATTENTION_1_CCE_MATCH_LSB)) 809 810 /* 811 * hal_rx_msdu_cce_match_get(): get CCE match bit 812 * from rx attention 813 * @buf: pointer to rx_pkt_tlvs 814 * Return: CCE match value 815 */ 816 static inline bool 817 hal_rx_msdu_cce_match_get(uint8_t *buf) 818 { 819 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 820 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 821 bool cce_match_val; 822 823 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 824 return cce_match_val; 825 } 826 827 /* 828 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 829 */ 830 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 831 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 832 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 833 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 834 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 835 836 static inline uint32_t 837 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 838 { 839 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 840 struct rx_mpdu_start *mpdu_start = 841 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 842 843 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 844 uint32_t peer_meta_data; 845 846 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 847 848 return peer_meta_data; 849 } 850 851 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 852 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 853 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 854 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 855 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 856 /** 857 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 858 * from rx mpdu info 859 * @buf: pointer to rx_pkt_tlvs 860 * 861 * Return: ampdu flag 862 */ 863 static inline bool 864 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_mpdu_start *mpdu_start = 868 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 869 870 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 871 bool ampdu_flag; 872 873 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 874 875 return ampdu_flag; 876 } 877 878 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 879 ((*(((uint32_t *)_rx_mpdu_info) + \ 880 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 881 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 882 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 883 884 /* 885 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 886 * 887 * @ buf: rx_tlv_hdr of the received packet 888 * @ peer_mdata: peer meta data to be set. 889 * @ Return: void 890 */ 891 static inline void 892 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 893 { 894 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 895 struct rx_mpdu_start *mpdu_start = 896 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 897 898 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 899 900 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 901 } 902 903 /** 904 * LRO information needed from the TLVs 905 */ 906 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 907 (_HAL_MS( \ 908 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 909 msdu_end_tlv.rx_msdu_end), \ 910 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 911 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 912 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 913 914 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 915 (_HAL_MS( \ 916 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 917 msdu_end_tlv.rx_msdu_end), \ 918 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 919 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 920 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 921 922 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 923 (_HAL_MS( \ 924 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 925 msdu_end_tlv.rx_msdu_end), \ 926 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 927 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 928 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 929 930 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 931 (_HAL_MS( \ 932 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 933 msdu_end_tlv.rx_msdu_end), \ 934 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 935 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 936 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 937 938 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 939 (_HAL_MS( \ 940 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 941 msdu_start_tlv.rx_msdu_start), \ 942 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 943 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 944 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 945 946 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 947 (_HAL_MS( \ 948 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 949 msdu_start_tlv.rx_msdu_start), \ 950 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 951 RX_MSDU_START_2_TCP_PROTO_MASK, \ 952 RX_MSDU_START_2_TCP_PROTO_LSB)) 953 954 #define HAL_RX_TLV_GET_IPV6(buf) \ 955 (_HAL_MS( \ 956 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 957 msdu_start_tlv.rx_msdu_start), \ 958 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 959 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 960 RX_MSDU_START_2_IPV6_PROTO_LSB)) 961 962 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 963 (_HAL_MS( \ 964 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 965 msdu_start_tlv.rx_msdu_start), \ 966 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 967 RX_MSDU_START_1_L3_OFFSET_MASK, \ 968 RX_MSDU_START_1_L3_OFFSET_LSB)) 969 970 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 971 (_HAL_MS( \ 972 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 973 msdu_start_tlv.rx_msdu_start), \ 974 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 975 RX_MSDU_START_1_L4_OFFSET_MASK, \ 976 RX_MSDU_START_1_L4_OFFSET_LSB)) 977 978 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 979 (_HAL_MS( \ 980 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 981 msdu_start_tlv.rx_msdu_start), \ 982 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 983 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 984 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 985 986 /** 987 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 988 * l3_header padding from rx_msdu_end TLV 989 * 990 * @buf: pointer to the start of RX PKT TLV headers 991 * Return: number of l3 header padding bytes 992 */ 993 static inline uint32_t 994 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 995 uint8_t *buf) 996 { 997 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 998 999 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 1000 } 1001 1002 /** 1003 * hal_rx_msdu_end_sa_idx_get(): API to get the 1004 * sa_idx from rx_msdu_end TLV 1005 * 1006 * @ buf: pointer to the start of RX PKT TLV headers 1007 * Return: sa_idx (SA AST index) 1008 */ 1009 static inline uint16_t 1010 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 1011 uint8_t *buf) 1012 { 1013 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1014 1015 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 1016 } 1017 1018 /** 1019 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1020 * sa_is_valid bit from rx_msdu_end TLV 1021 * 1022 * @ buf: pointer to the start of RX PKT TLV headers 1023 * Return: sa_is_valid bit 1024 */ 1025 static inline uint8_t 1026 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1027 uint8_t *buf) 1028 { 1029 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1030 1031 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 1032 } 1033 1034 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1035 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1036 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1037 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1038 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1039 1040 /** 1041 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1042 * from rx_msdu_start TLV 1043 * 1044 * @ buf: pointer to the start of RX PKT TLV headers 1045 * Return: msdu length 1046 */ 1047 static inline uint32_t 1048 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1049 { 1050 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1051 struct rx_msdu_start *msdu_start = 1052 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1053 uint32_t msdu_len; 1054 1055 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1056 1057 return msdu_len; 1058 } 1059 1060 /** 1061 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1062 * from rx_msdu_start TLV 1063 * 1064 * @buf: pointer to the start of RX PKT TLV headers 1065 * @len: msdu length 1066 * 1067 * Return: none 1068 */ 1069 static inline void 1070 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1071 { 1072 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1073 struct rx_msdu_start *msdu_start = 1074 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1075 void *wrd1; 1076 1077 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1078 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1079 *(uint32_t *)wrd1 |= len; 1080 } 1081 1082 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1083 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1084 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1085 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1086 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1087 1088 /* 1089 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1090 * Interval from rx_msdu_start 1091 * 1092 * @buf: pointer to the start of RX PKT TLV header 1093 * Return: uint32_t(bw) 1094 */ 1095 static inline uint32_t 1096 hal_rx_msdu_start_bw_get(uint8_t *buf) 1097 { 1098 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1099 struct rx_msdu_start *msdu_start = 1100 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1101 uint32_t bw; 1102 1103 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1104 1105 return bw; 1106 } 1107 1108 1109 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1110 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1111 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1112 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1113 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1114 1115 /** 1116 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1117 * from rx_msdu_start TLV 1118 * 1119 * @ buf: pointer to the start of RX PKT TLV headers 1120 * Return: toeplitz hash 1121 */ 1122 static inline uint32_t 1123 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1124 { 1125 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1126 struct rx_msdu_start *msdu_start = 1127 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1128 1129 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1130 } 1131 1132 /** 1133 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 1134 * 1135 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 1136 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 1137 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 1138 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 1139 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 1140 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 1141 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 1142 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 1143 */ 1144 enum hal_rx_mpdu_info_sw_frame_group_id_type { 1145 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 1146 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 1147 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 1148 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 1149 HAL_MPDU_SW_FRAME_GROUP_MGMT, 1150 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 1151 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 1152 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 1153 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 1154 }; 1155 1156 /** 1157 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 1158 * Retrieve qos control valid bit from the tlv. 1159 * @hal_soc_hdl: hal_soc handle 1160 * @buf: pointer to rx pkt TLV. 1161 * 1162 * Return: qos control value. 1163 */ 1164 static inline uint32_t 1165 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 1166 hal_soc_handle_t hal_soc_hdl, 1167 uint8_t *buf) 1168 { 1169 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1170 1171 if ((!hal_soc) || (!hal_soc->ops)) { 1172 hal_err("hal handle is NULL"); 1173 QDF_BUG(0); 1174 return QDF_STATUS_E_INVAL; 1175 } 1176 1177 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 1178 return hal_soc->ops-> 1179 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 1180 1181 return QDF_STATUS_E_INVAL; 1182 } 1183 1184 /** 1185 * hal_rx_is_unicast: check packet is unicast frame or not. 1186 * @hal_soc_hdl: hal_soc handle 1187 * @buf: pointer to rx pkt TLV. 1188 * 1189 * Return: true on unicast. 1190 */ 1191 static inline bool 1192 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1193 { 1194 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1195 1196 return hal_soc->ops->hal_rx_is_unicast(buf); 1197 } 1198 1199 /** 1200 * hal_rx_tid_get: get tid based on qos control valid. 1201 * @hal_soc_hdl: hal soc handle 1202 * @buf: pointer to rx pkt TLV. 1203 * 1204 * Return: tid 1205 */ 1206 static inline uint32_t 1207 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1208 { 1209 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1210 1211 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 1212 } 1213 1214 /** 1215 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 1216 * @hal_soc_hdl: hal soc handle 1217 * @buf: pointer to rx pkt TLV. 1218 * 1219 * Return: sw peer_id 1220 */ 1221 static inline uint32_t 1222 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1223 uint8_t *buf) 1224 { 1225 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1226 1227 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1228 } 1229 1230 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1231 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1232 RX_MSDU_START_5_SGI_OFFSET)), \ 1233 RX_MSDU_START_5_SGI_MASK, \ 1234 RX_MSDU_START_5_SGI_LSB)) 1235 /** 1236 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1237 * Interval from rx_msdu_start TLV 1238 * 1239 * @buf: pointer to the start of RX PKT TLV headers 1240 * Return: uint32_t(sgi) 1241 */ 1242 static inline uint32_t 1243 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1244 { 1245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1246 struct rx_msdu_start *msdu_start = 1247 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1248 uint32_t sgi; 1249 1250 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1251 1252 return sgi; 1253 } 1254 1255 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1256 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1257 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1258 RX_MSDU_START_5_RATE_MCS_MASK, \ 1259 RX_MSDU_START_5_RATE_MCS_LSB)) 1260 /** 1261 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1262 * from rx_msdu_start TLV 1263 * 1264 * @buf: pointer to the start of RX PKT TLV headers 1265 * Return: uint32_t(rate_mcs) 1266 */ 1267 static inline uint32_t 1268 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1269 { 1270 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1271 struct rx_msdu_start *msdu_start = 1272 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1273 uint32_t rate_mcs; 1274 1275 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1276 1277 return rate_mcs; 1278 } 1279 1280 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1281 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1282 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1283 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1284 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1285 1286 /* 1287 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1288 * packet from rx_attention 1289 * 1290 * @buf: pointer to the start of RX PKT TLV header 1291 * Return: uint32_t(decryt status) 1292 */ 1293 1294 static inline uint32_t 1295 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1296 { 1297 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1298 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1299 uint32_t is_decrypt = 0; 1300 uint32_t decrypt_status; 1301 1302 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1303 1304 if (!decrypt_status) 1305 is_decrypt = 1; 1306 1307 return is_decrypt; 1308 } 1309 1310 /* 1311 * Get key index from RX_MSDU_END 1312 */ 1313 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1314 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1315 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1316 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1317 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1318 /* 1319 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1320 * from rx_msdu_end 1321 * 1322 * @buf: pointer to the start of RX PKT TLV header 1323 * Return: uint32_t(key id) 1324 */ 1325 1326 static inline uint32_t 1327 hal_rx_msdu_get_keyid(uint8_t *buf) 1328 { 1329 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1330 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1331 uint32_t keyid_octet; 1332 1333 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1334 1335 return keyid_octet & 0x3; 1336 } 1337 1338 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1339 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1340 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1341 RX_MSDU_START_5_USER_RSSI_MASK, \ 1342 RX_MSDU_START_5_USER_RSSI_LSB)) 1343 /* 1344 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1345 * from rx_msdu_start 1346 * 1347 * @buf: pointer to the start of RX PKT TLV header 1348 * Return: uint32_t(rssi) 1349 */ 1350 1351 static inline uint32_t 1352 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1353 { 1354 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1355 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1356 uint32_t rssi; 1357 1358 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1359 1360 return rssi; 1361 1362 } 1363 1364 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1365 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1366 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1367 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1368 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1369 1370 /* 1371 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1372 * from rx_msdu_start 1373 * 1374 * @buf: pointer to the start of RX PKT TLV header 1375 * Return: uint32_t(frequency) 1376 */ 1377 1378 static inline uint32_t 1379 hal_rx_msdu_start_get_freq(uint8_t *buf) 1380 { 1381 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1382 struct rx_msdu_start *msdu_start = 1383 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1384 uint32_t freq; 1385 1386 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1387 1388 return freq; 1389 } 1390 1391 1392 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1393 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1394 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1395 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1396 RX_MSDU_START_5_PKT_TYPE_LSB)) 1397 1398 /* 1399 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1400 * from rx_msdu_start 1401 * 1402 * @buf: pointer to the start of RX PKT TLV header 1403 * Return: uint32_t(pkt type) 1404 */ 1405 1406 static inline uint32_t 1407 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1408 { 1409 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1410 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1411 uint32_t pkt_type; 1412 1413 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1414 1415 return pkt_type; 1416 } 1417 1418 /* 1419 * hal_rx_mpdu_get_tods(): API to get the tods info 1420 * from rx_mpdu_start 1421 * 1422 * @buf: pointer to the start of RX PKT TLV header 1423 * Return: uint32_t(to_ds) 1424 */ 1425 1426 static inline uint32_t 1427 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1428 { 1429 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1430 1431 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1432 } 1433 1434 1435 /* 1436 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1437 * from rx_mpdu_start 1438 * @hal_soc_hdl: hal soc handle 1439 * @buf: pointer to the start of RX PKT TLV header 1440 * 1441 * Return: uint32_t(fr_ds) 1442 */ 1443 static inline uint32_t 1444 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1445 { 1446 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1447 1448 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1449 } 1450 1451 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1452 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1453 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1454 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1455 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1456 1457 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1458 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1459 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1460 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1461 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1462 1463 /* 1464 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1465 * @hal_soc_hdl: hal soc handle 1466 * @buf: pointer to the start of RX PKT TLV headera 1467 * @mac_addr: pointer to mac address 1468 * 1469 * Return: success/failure 1470 */ 1471 static inline 1472 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1473 uint8_t *buf, uint8_t *mac_addr) 1474 { 1475 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1476 1477 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1478 } 1479 1480 /* 1481 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1482 * in the packet 1483 * @hal_soc_hdl: hal soc handle 1484 * @buf: pointer to the start of RX PKT TLV header 1485 * @mac_addr: pointer to mac address 1486 * 1487 * Return: success/failure 1488 */ 1489 static inline 1490 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1491 uint8_t *buf, uint8_t *mac_addr) 1492 { 1493 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1494 1495 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1496 } 1497 1498 /* 1499 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1500 * in the packet 1501 * @hal_soc_hdl: hal soc handle 1502 * @buf: pointer to the start of RX PKT TLV header 1503 * @mac_addr: pointer to mac address 1504 * 1505 * Return: success/failure 1506 */ 1507 static inline 1508 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1509 uint8_t *buf, uint8_t *mac_addr) 1510 { 1511 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1512 1513 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1514 } 1515 1516 /* 1517 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1518 * in the packet 1519 * @hal_soc_hdl: hal_soc handle 1520 * @buf: pointer to the start of RX PKT TLV header 1521 * @mac_addr: pointer to mac address 1522 * Return: success/failure 1523 */ 1524 static inline 1525 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1526 uint8_t *buf, uint8_t *mac_addr) 1527 { 1528 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1529 1530 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1531 } 1532 1533 /** 1534 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1535 * from rx_msdu_end TLV 1536 * 1537 * @ buf: pointer to the start of RX PKT TLV headers 1538 * Return: da index 1539 */ 1540 static inline uint16_t 1541 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1542 { 1543 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1544 1545 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1546 } 1547 1548 /** 1549 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1550 * from rx_msdu_end TLV 1551 * @hal_soc_hdl: hal soc handle 1552 * @ buf: pointer to the start of RX PKT TLV headers 1553 * 1554 * Return: da_is_valid 1555 */ 1556 static inline uint8_t 1557 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1558 uint8_t *buf) 1559 { 1560 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1561 1562 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1563 } 1564 1565 /** 1566 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1567 * from rx_msdu_end TLV 1568 * 1569 * @buf: pointer to the start of RX PKT TLV headers 1570 * 1571 * Return: da_is_mcbc 1572 */ 1573 static inline uint8_t 1574 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1575 { 1576 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1577 1578 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1579 } 1580 1581 /** 1582 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1583 * from rx_msdu_end TLV 1584 * @hal_soc_hdl: hal soc handle 1585 * @buf: pointer to the start of RX PKT TLV headers 1586 * 1587 * Return: first_msdu 1588 */ 1589 static inline uint8_t 1590 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1591 uint8_t *buf) 1592 { 1593 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1594 1595 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1596 } 1597 1598 /** 1599 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1600 * from rx_msdu_end TLV 1601 * @hal_soc_hdl: hal soc handle 1602 * @buf: pointer to the start of RX PKT TLV headers 1603 * 1604 * Return: last_msdu 1605 */ 1606 static inline uint8_t 1607 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1608 uint8_t *buf) 1609 { 1610 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1611 1612 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1613 } 1614 1615 /** 1616 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1617 * from rx_msdu_end TLV 1618 * @buf: pointer to the start of RX PKT TLV headers 1619 * Return: cce_meta_data 1620 */ 1621 static inline uint16_t 1622 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1623 uint8_t *buf) 1624 { 1625 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1626 1627 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1628 } 1629 1630 /******************************************************************************* 1631 * RX ERROR APIS 1632 ******************************************************************************/ 1633 1634 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1635 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1636 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1637 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1638 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1639 1640 /** 1641 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1642 * from rx_mpdu_end TLV 1643 * 1644 * @buf: pointer to the start of RX PKT TLV headers 1645 * Return: uint32_t(decrypt_err) 1646 */ 1647 static inline uint32_t 1648 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1649 { 1650 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1651 struct rx_mpdu_end *mpdu_end = 1652 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1653 uint32_t decrypt_err; 1654 1655 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1656 1657 return decrypt_err; 1658 } 1659 1660 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1661 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1662 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1663 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1664 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1665 1666 /** 1667 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1668 * from rx_mpdu_end TLV 1669 * 1670 * @buf: pointer to the start of RX PKT TLV headers 1671 * Return: uint32_t(mic_err) 1672 */ 1673 static inline uint32_t 1674 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1675 { 1676 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1677 struct rx_mpdu_end *mpdu_end = 1678 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1679 uint32_t mic_err; 1680 1681 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1682 1683 return mic_err; 1684 } 1685 1686 /******************************************************************************* 1687 * RX REO ERROR APIS 1688 ******************************************************************************/ 1689 1690 #define HAL_RX_NUM_MSDU_DESC 6 1691 #define HAL_RX_MAX_SAVED_RING_DESC 16 1692 1693 /* TODO: rework the structure */ 1694 struct hal_rx_msdu_list { 1695 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1696 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1697 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1698 /* physical address of the msdu */ 1699 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1700 }; 1701 1702 struct hal_buf_info { 1703 uint64_t paddr; 1704 uint32_t sw_cookie; 1705 uint8_t rbm; 1706 }; 1707 1708 /** 1709 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1710 * @msdu_link_ptr - msdu link ptr 1711 * @hal - pointer to hal_soc 1712 * Return - Pointer to rx_msdu_details structure 1713 * 1714 */ 1715 static inline 1716 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1717 struct hal_soc *hal_soc) 1718 { 1719 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1720 } 1721 1722 /** 1723 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1724 * @msdu_details_ptr - Pointer to msdu_details_ptr 1725 * @hal - pointer to hal_soc 1726 * Return - Pointer to rx_msdu_desc_info structure. 1727 * 1728 */ 1729 static inline 1730 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1731 struct hal_soc *hal_soc) 1732 { 1733 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1734 } 1735 1736 /* This special cookie value will be used to indicate FW allocated buffers 1737 * received through RXDMA2SW ring for RXDMA WARs 1738 */ 1739 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1740 1741 /** 1742 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1743 * from the MSDU link descriptor 1744 * 1745 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1746 * MSDU link descriptor (struct rx_msdu_link) 1747 * 1748 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1749 * 1750 * @num_msdus: Number of MSDUs in the MPDU 1751 * 1752 * Return: void 1753 */ 1754 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1755 void *msdu_link_desc, 1756 struct hal_rx_msdu_list *msdu_list, 1757 uint16_t *num_msdus) 1758 { 1759 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1760 struct rx_msdu_details *msdu_details; 1761 struct rx_msdu_desc_info *msdu_desc_info; 1762 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1763 int i; 1764 1765 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1766 1767 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1768 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1769 __func__, __LINE__, msdu_link, msdu_details); 1770 1771 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1772 /* num_msdus received in mpdu descriptor may be incorrect 1773 * sometimes due to HW issue. Check msdu buffer address also 1774 */ 1775 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1776 &msdu_details[i].buffer_addr_info_details) == 0) { 1777 /* set the last msdu bit in the prev msdu_desc_info */ 1778 msdu_desc_info = 1779 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1780 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1781 break; 1782 } 1783 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1784 hal_soc); 1785 1786 /* set first MSDU bit or the last MSDU bit */ 1787 if (!i) 1788 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1789 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1790 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1791 1792 msdu_list->msdu_info[i].msdu_flags = 1793 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1794 msdu_list->msdu_info[i].msdu_len = 1795 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1796 msdu_list->sw_cookie[i] = 1797 HAL_RX_BUF_COOKIE_GET( 1798 &msdu_details[i].buffer_addr_info_details); 1799 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1800 &msdu_details[i].buffer_addr_info_details); 1801 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1802 &msdu_details[i].buffer_addr_info_details) | 1803 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1804 &msdu_details[i].buffer_addr_info_details) << 32; 1805 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1806 "[%s][%d] i=%d sw_cookie=%d", 1807 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1808 } 1809 *num_msdus = i; 1810 } 1811 1812 /** 1813 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1814 * destination ring ID from the msdu desc info 1815 * 1816 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1817 * the current descriptor 1818 * 1819 * Return: dst_ind (REO destination ring ID) 1820 */ 1821 static inline uint32_t 1822 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 1823 { 1824 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1825 struct rx_msdu_details *msdu_details; 1826 struct rx_msdu_desc_info *msdu_desc_info; 1827 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1828 uint32_t dst_ind; 1829 1830 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1831 1832 /* The first msdu in the link should exsist */ 1833 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1834 hal_soc); 1835 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1836 return dst_ind; 1837 } 1838 1839 /** 1840 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1841 * cookie from the REO destination ring element 1842 * 1843 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1844 * the current descriptor 1845 * @ buf_info: structure to return the buffer information 1846 * Return: void 1847 */ 1848 static inline 1849 void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc, 1850 struct hal_buf_info *buf_info) 1851 { 1852 struct reo_destination_ring *reo_ring = 1853 (struct reo_destination_ring *)rx_desc; 1854 1855 buf_info->paddr = 1856 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 1857 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 1858 1859 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 1860 } 1861 1862 /** 1863 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 1864 * 1865 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 1866 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 1867 * descriptor 1868 */ 1869 enum hal_rx_reo_buf_type { 1870 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 1871 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 1872 }; 1873 1874 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 1875 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 1876 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 1877 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 1878 1879 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 1880 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 1881 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 1882 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 1883 1884 /** 1885 * enum hal_reo_error_code: Error code describing the type of error detected 1886 * 1887 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 1888 * REO_ENTRANCE ring is set to 0 1889 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 1890 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 1891 * having been setup 1892 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 1893 * Retry bit set: duplicate frame 1894 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 1895 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 1896 * received with 2K jump in SN 1897 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 1898 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 1899 * with SN falling within the OOR window 1900 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 1901 * OOR window 1902 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 1903 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 1904 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 1905 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1906 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 1907 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1908 * of the pn_error_detected_flag been set in the REO Queue descriptor 1909 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 1910 * the queue descriptor(address) being blocked as SW/FW seems to be currently 1911 * in the process of making updates to this descriptor 1912 */ 1913 enum hal_reo_error_code { 1914 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 1915 HAL_REO_ERR_QUEUE_DESC_INVALID, 1916 HAL_REO_ERR_AMPDU_IN_NON_BA, 1917 HAL_REO_ERR_NON_BA_DUPLICATE, 1918 HAL_REO_ERR_BA_DUPLICATE, 1919 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 1920 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 1921 HAL_REO_ERR_REGULAR_FRAME_OOR, 1922 HAL_REO_ERR_BAR_FRAME_OOR, 1923 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 1924 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 1925 HAL_REO_ERR_PN_CHECK_FAILED, 1926 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 1927 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 1928 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 1929 HAL_REO_ERR_MAX 1930 }; 1931 1932 /** 1933 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 1934 * 1935 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 1936 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 1937 * overflow 1938 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 1939 * incomplete 1940 * MPDU from the PHY 1941 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 1942 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 1943 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 1944 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 1945 * encrypted but wasn’t 1946 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 1947 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 1948 * the max allowed 1949 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 1950 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 1951 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 1952 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 1953 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 1954 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 1955 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 1956 */ 1957 enum hal_rxdma_error_code { 1958 HAL_RXDMA_ERR_OVERFLOW = 0, 1959 HAL_RXDMA_ERR_MPDU_LENGTH, 1960 HAL_RXDMA_ERR_FCS, 1961 HAL_RXDMA_ERR_DECRYPT, 1962 HAL_RXDMA_ERR_TKIP_MIC, 1963 HAL_RXDMA_ERR_UNENCRYPTED, 1964 HAL_RXDMA_ERR_MSDU_LEN, 1965 HAL_RXDMA_ERR_MSDU_LIMIT, 1966 HAL_RXDMA_ERR_WIFI_PARSE, 1967 HAL_RXDMA_ERR_AMSDU_PARSE, 1968 HAL_RXDMA_ERR_SA_TIMEOUT, 1969 HAL_RXDMA_ERR_DA_TIMEOUT, 1970 HAL_RXDMA_ERR_FLOW_TIMEOUT, 1971 HAL_RXDMA_ERR_FLUSH_REQUEST, 1972 HAL_RXDMA_ERR_WAR = 31, 1973 HAL_RXDMA_ERR_MAX 1974 }; 1975 1976 /** 1977 * HW BM action settings in WBM release ring 1978 */ 1979 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 1980 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 1981 1982 /** 1983 * enum hal_rx_wbm_error_source: Indicates which module initiated the 1984 * release of this buffer or descriptor 1985 * 1986 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 1987 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 1988 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 1989 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 1990 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 1991 */ 1992 enum hal_rx_wbm_error_source { 1993 HAL_RX_WBM_ERR_SRC_TQM = 0, 1994 HAL_RX_WBM_ERR_SRC_RXDMA, 1995 HAL_RX_WBM_ERR_SRC_REO, 1996 HAL_RX_WBM_ERR_SRC_FW, 1997 HAL_RX_WBM_ERR_SRC_SW, 1998 }; 1999 2000 /** 2001 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2002 * released 2003 * 2004 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2005 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2006 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2007 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2008 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2009 */ 2010 enum hal_rx_wbm_buf_type { 2011 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2012 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2013 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2014 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2015 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2016 }; 2017 2018 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2019 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2020 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2021 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2022 2023 /** 2024 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2025 * PN check failure 2026 * 2027 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2028 * 2029 * Return: true: error caused by PN check, false: other error 2030 */ 2031 static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc) 2032 { 2033 struct reo_destination_ring *reo_desc = 2034 (struct reo_destination_ring *)rx_desc; 2035 2036 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2037 HAL_REO_ERR_PN_CHECK_FAILED) | 2038 (HAL_RX_REO_ERROR_GET(reo_desc) == 2039 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2040 true : false; 2041 } 2042 2043 /** 2044 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2045 * the sequence number 2046 * 2047 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2048 * 2049 * Return: true: error caused by 2K jump, false: other error 2050 */ 2051 static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc) 2052 { 2053 struct reo_destination_ring *reo_desc = 2054 (struct reo_destination_ring *)rx_desc; 2055 2056 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2057 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2058 (HAL_RX_REO_ERROR_GET(reo_desc) == 2059 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2060 true : false; 2061 } 2062 2063 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 2064 /** 2065 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 2066 * @hal_desc: hardware descriptor pointer 2067 * 2068 * This function will print wbm release descriptor 2069 * 2070 * Return: none 2071 */ 2072 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 2073 { 2074 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 2075 uint32_t i; 2076 2077 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2078 "Current Rx wbm release descriptor is"); 2079 2080 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 2081 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2082 "DWORD[i] = 0x%x", wbm_comp[i]); 2083 } 2084 } 2085 2086 /** 2087 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2088 * 2089 * @ hal_soc_hdl : HAL version of the SOC pointer 2090 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2091 * @ buf_addr_info : void pointer to the buffer_addr_info 2092 * @ bm_action : put in IDLE list or release to MSDU_LIST 2093 * 2094 * Return: void 2095 */ 2096 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2097 static inline 2098 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 2099 void *src_srng_desc, 2100 hal_buff_addrinfo_t buf_addr_info, 2101 uint8_t bm_action) 2102 { 2103 struct wbm_release_ring *wbm_rel_srng = 2104 (struct wbm_release_ring *)src_srng_desc; 2105 uint32_t addr_31_0; 2106 uint8_t addr_39_32; 2107 2108 /* Structure copy !!! */ 2109 wbm_rel_srng->released_buff_or_desc_addr_info = 2110 *((struct buffer_addr_info *)buf_addr_info); 2111 2112 addr_31_0 = 2113 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 2114 addr_39_32 = 2115 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 2116 2117 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2118 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2119 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2120 bm_action); 2121 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2122 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2123 2124 /* WBM error is indicated when any of the link descriptors given to 2125 * WBM has a NULL address, and one those paths is the link descriptors 2126 * released from host after processing RXDMA errors, 2127 * or from Rx defrag path, and we want to add an assert here to ensure 2128 * host is not releasing descriptors with NULL address. 2129 */ 2130 2131 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 2132 hal_dump_wbm_rel_desc(src_srng_desc); 2133 qdf_assert_always(0); 2134 } 2135 } 2136 2137 /* 2138 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2139 * REO entrance ring 2140 * 2141 * @ soc: HAL version of the SOC pointer 2142 * @ pa: Physical address of the MSDU Link Descriptor 2143 * @ cookie: SW cookie to get to the virtual address 2144 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2145 * to the error enabled REO queue 2146 * 2147 * Return: void 2148 */ 2149 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2150 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2151 { 2152 /* TODO */ 2153 } 2154 2155 /** 2156 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2157 * BUFFER_ADDR_INFO, give the RX descriptor 2158 * (Assumption -- BUFFER_ADDR_INFO is the 2159 * first field in the descriptor structure) 2160 */ 2161 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 2162 ((hal_link_desc_t)(ring_desc)) 2163 2164 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2165 2166 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2167 2168 /** 2169 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2170 * from the BUFFER_ADDR_INFO structure 2171 * given a REO destination ring descriptor. 2172 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2173 * 2174 * Return: uint8_t (value of the return_buffer_manager) 2175 */ 2176 static inline 2177 uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc) 2178 { 2179 /* 2180 * The following macro takes buf_addr_info as argument, 2181 * but since buf_addr_info is the first field in ring_desc 2182 * Hence the following call is OK 2183 */ 2184 return HAL_RX_BUF_RBM_GET(ring_desc); 2185 } 2186 2187 2188 /******************************************************************************* 2189 * RX WBM ERROR APIS 2190 ******************************************************************************/ 2191 2192 2193 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2194 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2195 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2196 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2197 2198 /** 2199 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2200 * the frame to this release ring 2201 * 2202 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2203 * frame to this queue 2204 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2205 * received routing instructions. No error within REO was detected 2206 */ 2207 enum hal_rx_wbm_reo_push_reason { 2208 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2209 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2210 }; 2211 2212 2213 /** 2214 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2215 * this release ring 2216 * 2217 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2218 * this frame to this queue 2219 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2220 * per received routing instructions. No error within RXDMA was detected 2221 */ 2222 enum hal_rx_wbm_rxdma_push_reason { 2223 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2224 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2225 }; 2226 2227 2228 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2229 (((*(((uint32_t *) wbm_desc) + \ 2230 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2231 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2232 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2233 2234 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2235 (((*(((uint32_t *) wbm_desc) + \ 2236 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2237 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2238 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2239 2240 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2241 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2242 wbm_desc)->released_buff_or_desc_addr_info) 2243 2244 /** 2245 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2246 * humman readable format. 2247 * @ rx_attn: pointer the rx_attention TLV in pkt. 2248 * @ dbg_level: log level. 2249 * 2250 * Return: void 2251 */ 2252 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2253 uint8_t dbg_level) 2254 { 2255 hal_verbose_debug( 2256 "rx_attention tlv (1/2) - " 2257 "rxpcu_mpdu_filter_in_category: %x " 2258 "sw_frame_group_id: %x " 2259 "reserved_0: %x " 2260 "phy_ppdu_id: %x " 2261 "first_mpdu : %x " 2262 "reserved_1a: %x " 2263 "mcast_bcast: %x " 2264 "ast_index_not_found: %x " 2265 "ast_index_timeout: %x " 2266 "power_mgmt: %x " 2267 "non_qos: %x " 2268 "null_data: %x " 2269 "mgmt_type: %x " 2270 "ctrl_type: %x " 2271 "more_data: %x " 2272 "eosp: %x " 2273 "a_msdu_error: %x " 2274 "fragment_flag: %x " 2275 "order: %x " 2276 "cce_match: %x " 2277 "overflow_err: %x " 2278 "msdu_length_err: %x " 2279 "tcp_udp_chksum_fail: %x " 2280 "ip_chksum_fail: %x " 2281 "sa_idx_invalid: %x " 2282 "da_idx_invalid: %x " 2283 "reserved_1b: %x " 2284 "rx_in_tx_decrypt_byp: %x ", 2285 rx_attn->rxpcu_mpdu_filter_in_category, 2286 rx_attn->sw_frame_group_id, 2287 rx_attn->reserved_0, 2288 rx_attn->phy_ppdu_id, 2289 rx_attn->first_mpdu, 2290 rx_attn->reserved_1a, 2291 rx_attn->mcast_bcast, 2292 rx_attn->ast_index_not_found, 2293 rx_attn->ast_index_timeout, 2294 rx_attn->power_mgmt, 2295 rx_attn->non_qos, 2296 rx_attn->null_data, 2297 rx_attn->mgmt_type, 2298 rx_attn->ctrl_type, 2299 rx_attn->more_data, 2300 rx_attn->eosp, 2301 rx_attn->a_msdu_error, 2302 rx_attn->fragment_flag, 2303 rx_attn->order, 2304 rx_attn->cce_match, 2305 rx_attn->overflow_err, 2306 rx_attn->msdu_length_err, 2307 rx_attn->tcp_udp_chksum_fail, 2308 rx_attn->ip_chksum_fail, 2309 rx_attn->sa_idx_invalid, 2310 rx_attn->da_idx_invalid, 2311 rx_attn->reserved_1b, 2312 rx_attn->rx_in_tx_decrypt_byp); 2313 2314 hal_verbose_debug( 2315 "rx_attention tlv (2/2) - " 2316 "encrypt_required: %x " 2317 "directed: %x " 2318 "buffer_fragment: %x " 2319 "mpdu_length_err: %x " 2320 "tkip_mic_err: %x " 2321 "decrypt_err: %x " 2322 "unencrypted_frame_err: %x " 2323 "fcs_err: %x " 2324 "flow_idx_timeout: %x " 2325 "flow_idx_invalid: %x " 2326 "wifi_parser_error: %x " 2327 "amsdu_parser_error: %x " 2328 "sa_idx_timeout: %x " 2329 "da_idx_timeout: %x " 2330 "msdu_limit_error: %x " 2331 "da_is_valid: %x " 2332 "da_is_mcbc: %x " 2333 "sa_is_valid: %x " 2334 "decrypt_status_code: %x " 2335 "rx_bitmap_not_updated: %x " 2336 "reserved_2: %x " 2337 "msdu_done: %x ", 2338 rx_attn->encrypt_required, 2339 rx_attn->directed, 2340 rx_attn->buffer_fragment, 2341 rx_attn->mpdu_length_err, 2342 rx_attn->tkip_mic_err, 2343 rx_attn->decrypt_err, 2344 rx_attn->unencrypted_frame_err, 2345 rx_attn->fcs_err, 2346 rx_attn->flow_idx_timeout, 2347 rx_attn->flow_idx_invalid, 2348 rx_attn->wifi_parser_error, 2349 rx_attn->amsdu_parser_error, 2350 rx_attn->sa_idx_timeout, 2351 rx_attn->da_idx_timeout, 2352 rx_attn->msdu_limit_error, 2353 rx_attn->da_is_valid, 2354 rx_attn->da_is_mcbc, 2355 rx_attn->sa_is_valid, 2356 rx_attn->decrypt_status_code, 2357 rx_attn->rx_bitmap_not_updated, 2358 rx_attn->reserved_2, 2359 rx_attn->msdu_done); 2360 } 2361 2362 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2363 uint8_t dbg_level, 2364 struct hal_soc *hal) 2365 { 2366 2367 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2368 } 2369 /** 2370 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2371 * human readable format. 2372 * @ msdu_end: pointer the msdu_end TLV in pkt. 2373 * @ dbg_level: log level. 2374 * 2375 * Return: void 2376 */ 2377 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2378 struct rx_msdu_end *msdu_end, 2379 uint8_t dbg_level) 2380 { 2381 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2382 } 2383 2384 /** 2385 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2386 * human readable format. 2387 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2388 * @ dbg_level: log level. 2389 * 2390 * Return: void 2391 */ 2392 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2393 uint8_t dbg_level) 2394 { 2395 hal_verbose_debug( 2396 "rx_mpdu_end tlv - " 2397 "rxpcu_mpdu_filter_in_category: %x " 2398 "sw_frame_group_id: %x " 2399 "phy_ppdu_id: %x " 2400 "unsup_ktype_short_frame: %x " 2401 "rx_in_tx_decrypt_byp: %x " 2402 "overflow_err: %x " 2403 "mpdu_length_err: %x " 2404 "tkip_mic_err: %x " 2405 "decrypt_err: %x " 2406 "unencrypted_frame_err: %x " 2407 "pn_fields_contain_valid_info: %x " 2408 "fcs_err: %x " 2409 "msdu_length_err: %x " 2410 "rxdma0_destination_ring: %x " 2411 "rxdma1_destination_ring: %x " 2412 "decrypt_status_code: %x " 2413 "rx_bitmap_not_updated: %x ", 2414 mpdu_end->rxpcu_mpdu_filter_in_category, 2415 mpdu_end->sw_frame_group_id, 2416 mpdu_end->phy_ppdu_id, 2417 mpdu_end->unsup_ktype_short_frame, 2418 mpdu_end->rx_in_tx_decrypt_byp, 2419 mpdu_end->overflow_err, 2420 mpdu_end->mpdu_length_err, 2421 mpdu_end->tkip_mic_err, 2422 mpdu_end->decrypt_err, 2423 mpdu_end->unencrypted_frame_err, 2424 mpdu_end->pn_fields_contain_valid_info, 2425 mpdu_end->fcs_err, 2426 mpdu_end->msdu_length_err, 2427 mpdu_end->rxdma0_destination_ring, 2428 mpdu_end->rxdma1_destination_ring, 2429 mpdu_end->decrypt_status_code, 2430 mpdu_end->rx_bitmap_not_updated); 2431 } 2432 2433 #ifdef NO_RX_PKT_HDR_TLV 2434 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2435 uint8_t dbg_level) 2436 { 2437 } 2438 #else 2439 /** 2440 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2441 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2442 * @ dbg_level: log level. 2443 * 2444 * Return: void 2445 */ 2446 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2447 uint8_t dbg_level) 2448 { 2449 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2450 2451 hal_verbose_debug( 2452 "\n---------------\n" 2453 "rx_pkt_hdr_tlv \n" 2454 "---------------\n" 2455 "phy_ppdu_id %d ", 2456 pkt_hdr_tlv->phy_ppdu_id); 2457 2458 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2459 } 2460 #endif 2461 2462 /** 2463 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2464 * structure 2465 * @hal_ring: pointer to hal_srng structure 2466 * 2467 * Return: ring_id 2468 */ 2469 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 2470 { 2471 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 2472 } 2473 2474 /* Rx MSDU link pointer info */ 2475 struct hal_rx_msdu_link_ptr_info { 2476 struct rx_msdu_link msdu_link; 2477 struct hal_buf_info msdu_link_buf_info; 2478 }; 2479 2480 /** 2481 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2482 * 2483 * @nbuf: Pointer to data buffer field 2484 * Returns: pointer to rx_pkt_tlvs 2485 */ 2486 static inline 2487 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2488 { 2489 return (struct rx_pkt_tlvs *)rx_buf_start; 2490 } 2491 2492 /** 2493 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2494 * 2495 * @pkt_tlvs: Pointer to pkt_tlvs 2496 * Returns: pointer to rx_mpdu_info structure 2497 */ 2498 static inline 2499 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2500 { 2501 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2502 } 2503 2504 #define DOT11_SEQ_FRAG_MASK 0x000f 2505 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2506 2507 /** 2508 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2509 * 2510 * @nbuf: Network buffer 2511 * Returns: rx fragment number 2512 */ 2513 static inline 2514 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 2515 uint8_t *buf) 2516 { 2517 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 2518 } 2519 2520 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2521 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2522 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2523 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2524 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2525 /** 2526 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2527 * 2528 * @nbuf: Network buffer 2529 * Returns: rx more fragment bit 2530 */ 2531 static inline 2532 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2533 { 2534 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2535 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2536 uint16_t frame_ctrl = 0; 2537 2538 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2539 DOT11_FC1_MORE_FRAG_OFFSET; 2540 2541 /* more fragment bit if at offset bit 4 */ 2542 return frame_ctrl; 2543 } 2544 2545 /** 2546 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2547 * 2548 * @nbuf: Network buffer 2549 * Returns: rx more fragment bit 2550 * 2551 */ 2552 static inline 2553 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2554 { 2555 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2556 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2557 uint16_t frame_ctrl = 0; 2558 2559 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2560 2561 return frame_ctrl; 2562 } 2563 2564 /* 2565 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2566 * 2567 * @nbuf: Network buffer 2568 * Returns: flag to indicate whether the nbuf has MC/BC address 2569 */ 2570 static inline 2571 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2572 { 2573 uint8 *buf = qdf_nbuf_data(nbuf); 2574 2575 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2576 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2577 2578 return rx_attn->mcast_bcast; 2579 } 2580 2581 /* 2582 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2583 * @hal_soc_hdl: hal soc handle 2584 * @nbuf: Network buffer 2585 * 2586 * Return: value of sequence control valid field 2587 */ 2588 static inline 2589 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 2590 uint8_t *buf) 2591 { 2592 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2593 2594 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 2595 } 2596 2597 /* 2598 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2599 * @hal_soc_hdl: hal soc handle 2600 * @nbuf: Network buffer 2601 * 2602 * Returns: value of frame control valid field 2603 */ 2604 static inline 2605 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 2606 uint8_t *buf) 2607 { 2608 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2609 2610 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 2611 } 2612 2613 /** 2614 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2615 * @hal_soc_hdl: hal soc handle 2616 * @nbuf: Network buffer 2617 * Returns: value of mpdu 4th address valid field 2618 */ 2619 static inline 2620 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 2621 uint8_t *buf) 2622 { 2623 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2624 2625 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 2626 } 2627 2628 /* 2629 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2630 * 2631 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2632 * Returns: None 2633 */ 2634 static inline 2635 void hal_rx_clear_mpdu_desc_info( 2636 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2637 { 2638 qdf_mem_zero(rx_mpdu_desc_info, 2639 sizeof(*rx_mpdu_desc_info)); 2640 } 2641 2642 /* 2643 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2644 * 2645 * @msdu_link_ptr: HAL view of msdu link ptr 2646 * @size: number of msdu link pointers 2647 * Returns: None 2648 */ 2649 static inline 2650 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2651 int size) 2652 { 2653 qdf_mem_zero(msdu_link_ptr, 2654 (sizeof(*msdu_link_ptr) * size)); 2655 } 2656 2657 /* 2658 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2659 * @msdu_link_ptr: msdu link pointer 2660 * @mpdu_desc_info: mpdu descriptor info 2661 * 2662 * Build a list of msdus using msdu link pointer. If the 2663 * number of msdus are more, chain them together 2664 * 2665 * Returns: Number of processed msdus 2666 */ 2667 static inline 2668 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2669 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2670 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2671 { 2672 int j; 2673 struct rx_msdu_link *msdu_link_ptr = 2674 &msdu_link_ptr_info->msdu_link; 2675 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2676 struct rx_msdu_details *msdu_details = 2677 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2678 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2679 struct rx_msdu_desc_info *msdu_desc_info; 2680 uint8_t fragno, more_frag; 2681 uint8_t *rx_desc_info; 2682 struct hal_rx_msdu_list msdu_list; 2683 2684 for (j = 0; j < num_msdus; j++) { 2685 msdu_desc_info = 2686 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2687 hal_soc); 2688 msdu_list.msdu_info[j].msdu_flags = 2689 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2690 msdu_list.msdu_info[j].msdu_len = 2691 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2692 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2693 &msdu_details[j].buffer_addr_info_details); 2694 } 2695 2696 /* Chain msdu links together */ 2697 if (prev_msdu_link_ptr) { 2698 /* 31-0 bits of the physical address */ 2699 prev_msdu_link_ptr-> 2700 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2701 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2702 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2703 /* 39-32 bits of the physical address */ 2704 prev_msdu_link_ptr-> 2705 next_msdu_link_desc_addr_info.buffer_addr_39_32 2706 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2707 >> 32) & 2708 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2709 prev_msdu_link_ptr-> 2710 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2711 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2712 } 2713 2714 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2715 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2716 /* mark first and last MSDUs */ 2717 rx_desc_info = qdf_nbuf_data(msdu); 2718 fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info); 2719 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2720 2721 /* TODO: create skb->fragslist[] */ 2722 2723 if (more_frag == 0) { 2724 msdu_list.msdu_info[num_msdus].msdu_flags |= 2725 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2726 } else if (fragno == 1) { 2727 msdu_list.msdu_info[num_msdus].msdu_flags |= 2728 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2729 2730 msdu_list.msdu_info[num_msdus].msdu_flags |= 2731 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2732 } 2733 2734 num_msdus++; 2735 2736 /* Number of MSDUs per mpdu descriptor is updated */ 2737 mpdu_desc_info->msdu_count += num_msdus; 2738 } else { 2739 num_msdus = 0; 2740 prev_msdu_link_ptr = msdu_link_ptr; 2741 } 2742 2743 return num_msdus; 2744 } 2745 2746 /* 2747 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2748 * 2749 * @ring_desc: HAL view of ring descriptor 2750 * @mpdu_des_info: saved mpdu desc info 2751 * @msdu_link_ptr: saved msdu link ptr 2752 * 2753 * API used explicitly for rx defrag to update ring desc with 2754 * mpdu desc info and msdu link ptr before reinjecting the 2755 * packet back to REO 2756 * 2757 * Returns: None 2758 */ 2759 static inline 2760 void hal_rx_defrag_update_src_ring_desc( 2761 hal_ring_desc_t ring_desc, 2762 void *saved_mpdu_desc_info, 2763 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 2764 { 2765 struct reo_entrance_ring *reo_ent_ring; 2766 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 2767 struct hal_buf_info buf_info; 2768 2769 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 2770 reo_ring_mpdu_desc_info = &reo_ent_ring-> 2771 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 2772 2773 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 2774 sizeof(*reo_ring_mpdu_desc_info)); 2775 2776 /* 2777 * TODO: Check for additional fields that need configuration in 2778 * reo_ring_mpdu_desc_info 2779 */ 2780 2781 /* Update msdu_link_ptr in the reo entrance ring */ 2782 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 2783 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 2784 buf_info.sw_cookie = 2785 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 2786 } 2787 2788 /* 2789 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 2790 * 2791 * @msdu_link_desc_va: msdu link descriptor handle 2792 * @msdu_link_ptr_info: HAL view of msdu link pointer info 2793 * 2794 * API used to save msdu link information along with physical 2795 * address. The API also copues the sw cookie. 2796 * 2797 * Returns: None 2798 */ 2799 static inline 2800 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 2801 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2802 struct hal_buf_info *hbi) 2803 { 2804 struct rx_msdu_link *msdu_link_ptr = 2805 (struct rx_msdu_link *)msdu_link_desc_va; 2806 2807 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 2808 sizeof(struct rx_msdu_link)); 2809 2810 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 2811 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 2812 } 2813 2814 /* 2815 * hal_rx_get_desc_len(): Returns rx descriptor length 2816 * 2817 * Returns the size of rx_pkt_tlvs which follows the 2818 * data in the nbuf 2819 * 2820 * Returns: Length of rx descriptor 2821 */ 2822 static inline 2823 uint16_t hal_rx_get_desc_len(void) 2824 { 2825 return sizeof(struct rx_pkt_tlvs); 2826 } 2827 2828 /* 2829 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 2830 * reo_entrance_ring descriptor 2831 * 2832 * @reo_ent_desc: reo_entrance_ring descriptor 2833 * Returns: value of rxdma_push_reason 2834 */ 2835 static inline 2836 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 2837 { 2838 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2839 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 2840 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 2841 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 2842 } 2843 2844 /** 2845 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 2846 * reo_entrance_ring descriptor 2847 * @reo_ent_desc: reo_entrance_ring descriptor 2848 * Return: value of rxdma_error_code 2849 */ 2850 static inline 2851 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 2852 { 2853 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2854 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 2855 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 2856 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 2857 } 2858 2859 /** 2860 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 2861 * save it to hal_wbm_err_desc_info structure passed by caller 2862 * @wbm_desc: wbm ring descriptor 2863 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2864 * Return: void 2865 */ 2866 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 2867 struct hal_wbm_err_desc_info *wbm_er_info, 2868 hal_soc_handle_t hal_soc_hdl) 2869 { 2870 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2871 2872 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 2873 } 2874 2875 /** 2876 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 2877 * the reserved bytes of rx_tlv_hdr 2878 * @buf: start of rx_tlv_hdr 2879 * @wbm_er_info: hal_wbm_err_desc_info structure 2880 * Return: void 2881 */ 2882 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 2883 struct hal_wbm_err_desc_info *wbm_er_info) 2884 { 2885 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2886 2887 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 2888 sizeof(struct hal_wbm_err_desc_info)); 2889 } 2890 2891 /** 2892 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 2893 * the reserved bytes of rx_tlv_hdr. 2894 * @buf: start of rx_tlv_hdr 2895 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2896 * Return: void 2897 */ 2898 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 2899 struct hal_wbm_err_desc_info *wbm_er_info) 2900 { 2901 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2902 2903 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 2904 sizeof(struct hal_wbm_err_desc_info)); 2905 } 2906 2907 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 2908 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 2909 RX_MSDU_START_5_NSS_OFFSET)), \ 2910 RX_MSDU_START_5_NSS_MASK, \ 2911 RX_MSDU_START_5_NSS_LSB)) 2912 2913 /** 2914 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 2915 * 2916 * @ hal_soc: HAL version of the SOC pointer 2917 * @ hw_desc_addr: Start address of Rx HW TLVs 2918 * @ rs: Status for monitor mode 2919 * 2920 * Return: void 2921 */ 2922 static inline 2923 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 2924 void *hw_desc_addr, 2925 struct mon_rx_status *rs) 2926 { 2927 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2928 2929 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 2930 } 2931 2932 /* 2933 * hal_rx_get_tlv(): API to get the tlv 2934 * 2935 * @hal_soc: HAL version of the SOC pointer 2936 * @rx_tlv: TLV data extracted from the rx packet 2937 * Return: uint8_t 2938 */ 2939 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 2940 { 2941 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 2942 } 2943 2944 /* 2945 * hal_rx_msdu_start_nss_get(): API to get the NSS 2946 * Interval from rx_msdu_start 2947 * 2948 * @hal_soc: HAL version of the SOC pointer 2949 * @buf: pointer to the start of RX PKT TLV header 2950 * Return: uint32_t(nss) 2951 */ 2952 static inline 2953 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2954 { 2955 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2956 2957 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 2958 } 2959 2960 /** 2961 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 2962 * human readable format. 2963 * @ msdu_start: pointer the msdu_start TLV in pkt. 2964 * @ dbg_level: log level. 2965 * 2966 * Return: void 2967 */ 2968 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 2969 struct rx_msdu_start *msdu_start, 2970 uint8_t dbg_level) 2971 { 2972 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 2973 } 2974 2975 /** 2976 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 2977 * info details 2978 * 2979 * @ buf - Pointer to buffer containing rx pkt tlvs. 2980 * 2981 * 2982 */ 2983 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 2984 uint8_t *buf) 2985 { 2986 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2987 2988 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 2989 } 2990 2991 /* 2992 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 2993 * Interval from rx_msdu_start 2994 * 2995 * @buf: pointer to the start of RX PKT TLV header 2996 * Return: uint32_t(reception_type) 2997 */ 2998 static inline 2999 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 3000 uint8_t *buf) 3001 { 3002 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3003 3004 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3005 } 3006 3007 /** 3008 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3009 * RX TLVs 3010 * @ buf: pointer the pkt buffer. 3011 * @ dbg_level: log level. 3012 * 3013 * Return: void 3014 */ 3015 static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 3016 uint8_t *buf, uint8_t dbg_level) 3017 { 3018 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3019 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3020 struct rx_mpdu_start *mpdu_start = 3021 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3022 struct rx_msdu_start *msdu_start = 3023 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3024 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3025 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3026 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3027 3028 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3029 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3030 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3031 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3032 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3033 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3034 } 3035 3036 3037 /** 3038 * hal_reo_status_get_header_generic - Process reo desc info 3039 * @d - Pointer to reo descriptior 3040 * @b - tlv type info 3041 * @h - Pointer to hal_reo_status_header where info to be stored 3042 * @hal- pointer to hal_soc structure 3043 * Return - none. 3044 * 3045 */ 3046 static inline 3047 void hal_reo_status_get_header(uint32_t *d, int b, 3048 void *h, struct hal_soc *hal_soc) 3049 { 3050 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3051 } 3052 3053 /** 3054 * hal_rx_desc_is_first_msdu() - Check if first msdu 3055 * 3056 * @hal_soc_hdl: hal_soc handle 3057 * @hw_desc_addr: hardware descriptor address 3058 * 3059 * Return: 0 - success/ non-zero failure 3060 */ 3061 static inline 3062 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 3063 void *hw_desc_addr) 3064 { 3065 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3066 3067 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 3068 } 3069 3070 static inline 3071 uint32_t 3072 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3073 struct rx_msdu_start *rx_msdu_start; 3074 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3075 3076 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3077 3078 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3079 } 3080 3081 #ifdef NO_RX_PKT_HDR_TLV 3082 static inline 3083 uint8_t * 3084 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3085 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3086 "[%s][%d] decap format not raw", __func__, __LINE__); 3087 QDF_ASSERT(0); 3088 return 0; 3089 } 3090 #else 3091 static inline 3092 uint8_t * 3093 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3094 uint8_t *rx_pkt_hdr; 3095 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3096 3097 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3098 3099 return rx_pkt_hdr; 3100 } 3101 #endif 3102 3103 static inline 3104 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3105 uint8_t *rx_tlv_hdr) 3106 { 3107 uint8_t decap_format; 3108 3109 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 3110 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3111 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3112 return true; 3113 } 3114 3115 return false; 3116 } 3117 3118 /** 3119 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 3120 * from rx_msdu_end TLV 3121 * @buf: pointer to the start of RX PKT TLV headers 3122 * 3123 * Return: fse metadata value from MSDU END TLV 3124 */ 3125 static inline uint32_t 3126 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 3127 uint8_t *buf) 3128 { 3129 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3130 3131 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 3132 } 3133 3134 /** 3135 * hal_rx_msdu_flow_idx_get: API to get flow index 3136 * from rx_msdu_end TLV 3137 * @buf: pointer to the start of RX PKT TLV headers 3138 * 3139 * Return: flow index value from MSDU END TLV 3140 */ 3141 static inline uint32_t 3142 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 3143 uint8_t *buf) 3144 { 3145 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3146 3147 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 3148 } 3149 3150 /** 3151 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 3152 * from rx_msdu_end TLV 3153 * @buf: pointer to the start of RX PKT TLV headers 3154 * 3155 * Return: flow index timeout value from MSDU END TLV 3156 */ 3157 static inline bool 3158 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 3159 uint8_t *buf) 3160 { 3161 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3162 3163 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 3164 } 3165 3166 /** 3167 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 3168 * from rx_msdu_end TLV 3169 * @buf: pointer to the start of RX PKT TLV headers 3170 * 3171 * Return: flow index invalid value from MSDU END TLV 3172 */ 3173 static inline bool 3174 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 3175 uint8_t *buf) 3176 { 3177 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3178 3179 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 3180 } 3181 3182 /** 3183 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 3184 * @hal_soc_hdl: hal_soc handle 3185 * @hw_desc_addr: hardware descriptor address 3186 * 3187 * Return: 0 - success/ non-zero failure 3188 */ 3189 static inline 3190 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 3191 void *hw_desc_addr) 3192 { 3193 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3194 3195 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(hw_desc_addr); 3196 } 3197 3198 /** 3199 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 3200 * @hal_soc_hdl: hal_soc handle 3201 * @buf: rx tlv address 3202 * 3203 * Return: sw peer id 3204 */ 3205 static inline 3206 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 3207 uint8_t *buf) 3208 { 3209 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3210 3211 if ((!hal_soc) || (!hal_soc->ops)) { 3212 hal_err("hal handle is NULL"); 3213 QDF_BUG(0); 3214 return QDF_STATUS_E_INVAL; 3215 } 3216 3217 if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get) 3218 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 3219 3220 return QDF_STATUS_E_INVAL; 3221 } 3222 3223 static inline 3224 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 3225 void *link_desc_addr) 3226 { 3227 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3228 3229 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 3230 } 3231 3232 static inline 3233 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 3234 void *msdu_addr) 3235 { 3236 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3237 3238 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 3239 } 3240 3241 static inline 3242 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3243 void *hw_addr) 3244 { 3245 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3246 3247 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 3248 } 3249 3250 static inline 3251 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3252 void *hw_addr) 3253 { 3254 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3255 3256 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 3257 } 3258 3259 static inline 3260 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 3261 uint8_t *buf) 3262 { 3263 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3264 3265 return hal_soc->ops->hal_rx_get_fc_valid(buf); 3266 } 3267 3268 static inline 3269 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3270 { 3271 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3272 3273 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 3274 } 3275 3276 static inline 3277 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 3278 uint8_t *buf) 3279 { 3280 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3281 3282 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 3283 } 3284 3285 static inline 3286 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 3287 uint8_t *buf) 3288 { 3289 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3290 3291 return hal_soc->ops->hal_rx_get_filter_category(buf); 3292 } 3293 3294 static inline 3295 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 3296 uint8_t *buf) 3297 { 3298 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3299 3300 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 3301 } 3302 3303 /** 3304 * hal_reo_config(): Set reo config parameters 3305 * @soc: hal soc handle 3306 * @reg_val: value to be set 3307 * @reo_params: reo parameters 3308 * 3309 * Return: void 3310 */ 3311 static inline 3312 void hal_reo_config(struct hal_soc *hal_soc, 3313 uint32_t reg_val, 3314 struct hal_reo_params *reo_params) 3315 { 3316 hal_soc->ops->hal_reo_config(hal_soc, 3317 reg_val, 3318 reo_params); 3319 } 3320 3321 /** 3322 * hal_rx_msdu_get_flow_params: API to get flow index, 3323 * flow index invalid and flow index timeout from rx_msdu_end TLV 3324 * @buf: pointer to the start of RX PKT TLV headers 3325 * @flow_invalid: pointer to return value of flow_idx_valid 3326 * @flow_timeout: pointer to return value of flow_idx_timeout 3327 * @flow_index: pointer to return value of flow_idx 3328 * 3329 * Return: none 3330 */ 3331 static inline void 3332 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 3333 uint8_t *buf, 3334 bool *flow_invalid, 3335 bool *flow_timeout, 3336 uint32_t *flow_index) 3337 { 3338 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3339 3340 if ((!hal_soc) || (!hal_soc->ops)) { 3341 hal_err("hal handle is NULL"); 3342 QDF_BUG(0); 3343 return; 3344 } 3345 3346 if (hal_soc->ops->hal_rx_msdu_get_flow_params) 3347 hal_soc->ops-> 3348 hal_rx_msdu_get_flow_params(buf, 3349 flow_invalid, 3350 flow_timeout, 3351 flow_index); 3352 } 3353 3354 static inline 3355 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 3356 uint8_t *buf) 3357 { 3358 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3359 3360 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 3361 } 3362 3363 static inline 3364 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 3365 uint8_t *buf) 3366 { 3367 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3368 3369 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 3370 } 3371 3372 static inline void 3373 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 3374 void *rx_tlv, 3375 void *ppdu_info) 3376 { 3377 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3378 3379 if (hal_soc->ops->hal_rx_get_bb_info) 3380 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 3381 } 3382 3383 static inline void 3384 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 3385 void *rx_tlv, 3386 void *ppdu_info) 3387 { 3388 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3389 3390 if (hal_soc->ops->hal_rx_get_rtt_info) 3391 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 3392 } 3393 #endif /* _HAL_RX_H */ 3394