1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 24 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 25 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 26 #define HAL_RX_LSB(block, field) block##_##field##_LSB 27 #define HAL_RX_MASk(block, field) block##_##field##_MASK 28 29 #define HAL_RX_GET(_ptr, block, field) \ 30 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 31 HAL_RX_MASk(block, field)) >> \ 32 HAL_RX_LSB(block, field)) 33 34 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 35 #ifndef RX_DATA_BUFFER_SIZE 36 #define RX_DATA_BUFFER_SIZE 2048 37 #endif 38 39 #ifndef RX_MONITOR_BUFFER_SIZE 40 #define RX_MONITOR_BUFFER_SIZE 2048 41 #endif 42 43 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 44 * including buffer reservation, buffer alignment and skb shared info size. 45 */ 46 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 47 #define RX_MON_STATUS_BUF_ALIGN 128 48 #define RX_MON_STATUS_BUF_RESERVATION 128 49 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 50 (RX_MON_STATUS_BUF_RESERVATION + \ 51 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 52 53 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 54 #define HAL_RX_NON_QOS_TID 16 55 56 enum { 57 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 58 HAL_HW_RX_DECAP_FORMAT_NWIFI, 59 HAL_HW_RX_DECAP_FORMAT_ETH2, 60 HAL_HW_RX_DECAP_FORMAT_8023, 61 }; 62 63 /** 64 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 65 * 66 * @reo_psh_rsn: REO push reason 67 * @reo_err_code: REO Error code 68 * @rxdma_psh_rsn: RXDMA push reason 69 * @rxdma_err_code: RXDMA Error code 70 * @reserved_1: Reserved bits 71 * @wbm_err_src: WBM error source 72 * @pool_id: pool ID, indicates which rxdma pool 73 * @reserved_2: Reserved bits 74 */ 75 struct hal_wbm_err_desc_info { 76 uint16_t reo_psh_rsn:2, 77 reo_err_code:5, 78 rxdma_psh_rsn:2, 79 rxdma_err_code:5, 80 reserved_1:2; 81 uint8_t wbm_err_src:3, 82 pool_id:2, 83 msdu_continued:1, 84 reserved_2:2; 85 }; 86 87 /** 88 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 89 * @first_buffer: First buffer of MSDU 90 * @last_buffer: Last buffer of MSDU 91 * @is_decap_raw: Is RAW Frame 92 * @reserved_1: Reserved 93 * 94 * MSDU with continuation: 95 * ----------------------------------------------------------- 96 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 97 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 98 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 99 * ----------------------------------------------------------- 100 * 101 * Single buffer MSDU: 102 * ------------------ 103 * | first_buffer:1 | 104 * | last_buffer :1 | 105 * | is_decap_raw:1/0 | 106 * ------------------ 107 */ 108 struct hal_rx_mon_dest_buf_info { 109 uint8_t first_buffer:1, 110 last_buffer:1, 111 is_decap_raw:1, 112 reserved_1:5; 113 }; 114 115 /** 116 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 117 * 118 * @l3_hdr_pad: l3 header padding 119 * @reserved: Reserved bits 120 * @sa_sw_peer_id: sa sw peer id 121 * @sa_idx: sa index 122 * @da_idx: da index 123 */ 124 struct hal_rx_msdu_metadata { 125 uint32_t l3_hdr_pad:16, 126 sa_sw_peer_id:16; 127 uint32_t sa_idx:16, 128 da_idx:16; 129 }; 130 131 /** 132 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 133 * 134 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 135 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 136 */ 137 enum hal_reo_error_status { 138 HAL_REO_ERROR_DETECTED = 0, 139 HAL_REO_ROUTING_INSTRUCTION = 1, 140 }; 141 142 /** 143 * @msdu_flags: [0] first_msdu_in_mpdu 144 * [1] last_msdu_in_mpdu 145 * [2] msdu_continuation - MSDU spread across buffers 146 * [23] sa_is_valid - SA match in peer table 147 * [24] sa_idx_timeout - Timeout while searching for SA match 148 * [25] da_is_valid - Used to identtify intra-bss forwarding 149 * [26] da_is_MCBC 150 * [27] da_idx_timeout - Timeout while searching for DA match 151 * 152 */ 153 struct hal_rx_msdu_desc_info { 154 uint32_t msdu_flags; 155 uint16_t msdu_len; /* 14 bits for length */ 156 }; 157 158 /** 159 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 160 * 161 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 162 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 163 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 164 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 165 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 166 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 167 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 168 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 169 */ 170 enum hal_rx_msdu_desc_flags { 171 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 172 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 173 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 174 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 175 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 176 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 177 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 178 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 179 }; 180 181 /* 182 * @msdu_count: no. of msdus in the MPDU 183 * @mpdu_seq: MPDU sequence number 184 * @mpdu_flags [0] Fragment flag 185 * [1] MPDU_retry_bit 186 * [2] AMPDU flag 187 * [3] raw_ampdu 188 * @peer_meta_data: Upper bits containing peer id, vdev id 189 * @bar_frame: indicates if received frame is a bar frame 190 */ 191 struct hal_rx_mpdu_desc_info { 192 uint16_t msdu_count; 193 uint16_t mpdu_seq; /* 12 bits for length */ 194 uint32_t mpdu_flags; 195 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 196 uint16_t bar_frame; 197 }; 198 199 /** 200 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 201 * 202 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 203 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 204 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 205 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 206 */ 207 enum hal_rx_mpdu_desc_flags { 208 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 209 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 210 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 211 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 212 }; 213 214 /** 215 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 216 * BUFFER_ADDR_INFO structure 217 * 218 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 219 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 220 * descriptor list 221 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 222 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 223 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 224 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 225 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 226 */ 227 enum hal_rx_ret_buf_manager { 228 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 229 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 230 HAL_RX_BUF_RBM_FW_BM = 2, 231 HAL_RX_BUF_RBM_SW0_BM = 3, 232 HAL_RX_BUF_RBM_SW1_BM = 4, 233 HAL_RX_BUF_RBM_SW2_BM = 5, 234 HAL_RX_BUF_RBM_SW3_BM = 6, 235 }; 236 237 /* 238 * Given the offset of a field in bytes, returns uint8_t * 239 */ 240 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 241 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 242 243 /* 244 * Given the offset of a field in bytes, returns uint32_t * 245 */ 246 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 247 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 248 249 #define _HAL_MS(_word, _mask, _shift) \ 250 (((_word) & (_mask)) >> (_shift)) 251 252 /* 253 * macro to set the LSW of the nbuf data physical address 254 * to the rxdma ring entry 255 */ 256 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 257 ((*(((unsigned int *) buff_addr_info) + \ 258 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 259 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 260 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 261 262 /* 263 * macro to set the LSB of MSW of the nbuf data physical address 264 * to the rxdma ring entry 265 */ 266 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 267 ((*(((unsigned int *) buff_addr_info) + \ 268 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 269 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 270 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 271 272 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 273 274 /* 275 * macro to get the invalid bit for sw cookie 276 */ 277 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 278 ((*(((unsigned int *)buff_addr_info) + \ 279 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 280 HAL_RX_COOKIE_INVALID_MASK) 281 282 /* 283 * macro to set the invalid bit for sw cookie 284 */ 285 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 286 ((*(((unsigned int *)buff_addr_info) + \ 287 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 288 HAL_RX_COOKIE_INVALID_MASK) 289 290 /* 291 * macro to set the cookie into the rxdma ring entry 292 */ 293 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 294 ((*(((unsigned int *) buff_addr_info) + \ 295 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 296 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 297 ((*(((unsigned int *) buff_addr_info) + \ 298 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 299 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 300 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 301 302 /* 303 * macro to set the manager into the rxdma ring entry 304 */ 305 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 306 ((*(((unsigned int *) buff_addr_info) + \ 307 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 308 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 309 ((*(((unsigned int *) buff_addr_info) + \ 310 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 311 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 312 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 313 314 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 315 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 316 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 317 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 318 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 319 320 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 321 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 322 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 323 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 324 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 325 326 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 327 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 328 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 329 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 330 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 331 332 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 333 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 334 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 335 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 336 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 337 338 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 339 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 340 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 341 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 342 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 343 344 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 345 346 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 347 ((*(((unsigned int *)buff_addr_info) + \ 348 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 349 HAL_RX_LINK_COOKIE_INVALID_MASK) 350 351 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 352 ((*(((unsigned int *)buff_addr_info) + \ 353 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 354 HAL_RX_LINK_COOKIE_INVALID_MASK) 355 356 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 357 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 358 (((struct reo_destination_ring *) \ 359 reo_desc)->buf_or_link_desc_addr_info))) 360 361 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 362 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 363 (((struct reo_destination_ring *) \ 364 reo_desc)->buf_or_link_desc_addr_info))) 365 366 /* TODO: Convert the following structure fields accesseses to offsets */ 367 368 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 369 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 370 (((struct reo_destination_ring *) \ 371 reo_desc)->buf_or_link_desc_addr_info))) 372 373 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 374 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 375 (((struct reo_destination_ring *) \ 376 reo_desc)->buf_or_link_desc_addr_info))) 377 378 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 379 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 380 (((struct reo_destination_ring *) \ 381 reo_desc)->buf_or_link_desc_addr_info))) 382 383 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 384 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 385 (((struct reo_destination_ring *) \ 386 reo_desc)->buf_or_link_desc_addr_info))) 387 388 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 389 (HAL_RX_BUF_COOKIE_GET(& \ 390 (((struct reo_destination_ring *) \ 391 reo_desc)->buf_or_link_desc_addr_info))) 392 393 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 394 ((mpdu_info_ptr \ 395 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 396 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 397 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 398 399 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 400 ((mpdu_info_ptr \ 401 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 402 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 403 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 404 405 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 406 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 407 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 408 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 409 410 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 411 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 412 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 413 414 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 415 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 416 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 417 418 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 419 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 420 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 421 422 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 423 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 424 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 425 426 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 427 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 428 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 429 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 430 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 431 432 #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \ 433 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET >> 2] & \ 434 RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK) >> \ 435 RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB) 436 437 438 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 439 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 440 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 441 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 442 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 443 444 /* 445 * NOTE: None of the following _GET macros need a right 446 * shift by the corresponding _LSB. This is because, they are 447 * finally taken and "OR'ed" into a single word again. 448 */ 449 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 450 ((*(((uint32_t *)msdu_info_ptr) + \ 451 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 452 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 453 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 454 455 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 456 ((*(((uint32_t *)msdu_info_ptr) + \ 457 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 458 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 459 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 460 461 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 462 ((*(((uint32_t *)msdu_info_ptr) + \ 463 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 464 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 465 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 466 467 468 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 469 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 470 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 471 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 472 473 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 474 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 475 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 476 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 477 478 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 479 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 480 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 481 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 482 483 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 484 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 485 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 486 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 487 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 488 489 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 490 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 491 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 492 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 493 494 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 495 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 496 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 497 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 498 499 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 500 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 501 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 502 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 503 504 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 505 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 506 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 507 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 508 509 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 510 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 511 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 512 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 513 514 #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc) \ 515 (HAL_RX_MSDU_REO_DST_IND_GET(& \ 516 (((struct reo_destination_ring *) \ 517 reo_desc)->rx_msdu_desc_info_details))) 518 519 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 520 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 521 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 522 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 523 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 524 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 525 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 526 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 527 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 528 529 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 530 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 531 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 532 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 533 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 534 535 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 536 (*(uint32_t *)(((uint8_t *)_ptr) + \ 537 _wrd ## _ ## _field ## _OFFSET) |= \ 538 ((_val << _wrd ## _ ## _field ## _LSB) & \ 539 _wrd ## _ ## _field ## _MASK)) 540 541 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 542 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 543 _field, _val) 544 545 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 546 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 547 _field, _val) 548 549 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 550 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 551 _field, _val) 552 553 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 554 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 555 { 556 struct reo_destination_ring *reo_dst_ring; 557 uint32_t *mpdu_info; 558 559 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 560 561 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 562 563 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 564 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 565 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 566 mpdu_desc_info->peer_meta_data = 567 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 568 mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info); 569 } 570 571 /* 572 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 573 * @ Specifically flags needed are: 574 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 575 * @ msdu_continuation, sa_is_valid, 576 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 577 * @ da_is_MCBC 578 * 579 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 580 * @ descriptor 581 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 582 * @ Return: void 583 */ 584 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 585 struct hal_rx_msdu_desc_info *msdu_desc_info) 586 { 587 struct reo_destination_ring *reo_dst_ring; 588 uint32_t *msdu_info; 589 590 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 591 592 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 593 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 594 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 595 } 596 597 /* 598 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 599 * rxdma ring entry. 600 * @rxdma_entry: descriptor entry 601 * @paddr: physical address of nbuf data pointer. 602 * @cookie: SW cookie used as a index to SW rx desc. 603 * @manager: who owns the nbuf (host, NSS, etc...). 604 * 605 */ 606 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 607 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 608 { 609 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 610 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 611 612 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 613 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 614 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 615 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 616 } 617 618 /* 619 * Structures & Macros to obtain fields from the TLV's in the Rx packet 620 * pre-header. 621 */ 622 623 /* 624 * Every Rx packet starts at an offset from the top of the buffer. 625 * If the host hasn't subscribed to any specific TLV, there is 626 * still space reserved for the following TLV's from the start of 627 * the buffer: 628 * -- RX ATTENTION 629 * -- RX MPDU START 630 * -- RX MSDU START 631 * -- RX MSDU END 632 * -- RX MPDU END 633 * -- RX PACKET HEADER (802.11) 634 * If the host subscribes to any of the TLV's above, that TLV 635 * if populated by the HW 636 */ 637 638 #define NUM_DWORDS_TAG 1 639 640 /* By default the packet header TLV is 128 bytes */ 641 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 642 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 643 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 644 645 #define RX_PKT_OFFSET_WORDS \ 646 ( \ 647 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 648 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 649 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 650 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 651 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 652 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 653 ) 654 655 #define RX_PKT_OFFSET_BYTES \ 656 (RX_PKT_OFFSET_WORDS << 2) 657 658 #define RX_PKT_HDR_TLV_LEN 120 659 660 /* 661 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 662 */ 663 struct rx_attention_tlv { 664 uint32_t tag; 665 struct rx_attention rx_attn; 666 }; 667 668 struct rx_mpdu_start_tlv { 669 uint32_t tag; 670 struct rx_mpdu_start rx_mpdu_start; 671 }; 672 673 struct rx_msdu_start_tlv { 674 uint32_t tag; 675 struct rx_msdu_start rx_msdu_start; 676 }; 677 678 struct rx_msdu_end_tlv { 679 uint32_t tag; 680 struct rx_msdu_end rx_msdu_end; 681 }; 682 683 struct rx_mpdu_end_tlv { 684 uint32_t tag; 685 struct rx_mpdu_end rx_mpdu_end; 686 }; 687 688 struct rx_pkt_hdr_tlv { 689 uint32_t tag; /* 4 B */ 690 uint32_t phy_ppdu_id; /* 4 B */ 691 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 692 }; 693 694 695 #define RXDMA_OPTIMIZATION 696 697 /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status 698 * buffers, monitor destination buffers and monitor descriptor buffers. 699 */ 700 #ifdef RXDMA_OPTIMIZATION 701 /* 702 * The RX_PADDING_BYTES is required so that the TLV's don't 703 * spread across the 128 byte boundary 704 * RXDMA optimization requires: 705 * 1) MSDU_END & ATTENTION TLV's follow in that order 706 * 2) TLV's don't span across 128 byte lines 707 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 708 */ 709 #define RX_PADDING0_BYTES 4 710 #define RX_PADDING1_BYTES 16 711 struct rx_pkt_tlvs { 712 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 713 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 714 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 715 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 716 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 717 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 718 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 719 #ifndef NO_RX_PKT_HDR_TLV 720 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 721 #endif 722 }; 723 #else /* RXDMA_OPTIMIZATION */ 724 struct rx_pkt_tlvs { 725 struct rx_attention_tlv attn_tlv; 726 struct rx_mpdu_start_tlv mpdu_start_tlv; 727 struct rx_msdu_start_tlv msdu_start_tlv; 728 struct rx_msdu_end_tlv msdu_end_tlv; 729 struct rx_mpdu_end_tlv mpdu_end_tlv; 730 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 731 }; 732 #endif /* RXDMA_OPTIMIZATION */ 733 734 /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */ 735 #ifdef RXDMA_OPTIMIZATION 736 struct rx_mon_pkt_tlvs { 737 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 738 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 739 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 740 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 741 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 742 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 743 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 744 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 745 }; 746 #else /* RXDMA_OPTIMIZATION */ 747 struct rx_mon_pkt_tlvs { 748 struct rx_attention_tlv attn_tlv; 749 struct rx_mpdu_start_tlv mpdu_start_tlv; 750 struct rx_msdu_start_tlv msdu_start_tlv; 751 struct rx_msdu_end_tlv msdu_end_tlv; 752 struct rx_mpdu_end_tlv mpdu_end_tlv; 753 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 754 }; 755 #endif 756 757 #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs) 758 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 759 760 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 761 762 #ifdef NO_RX_PKT_HDR_TLV 763 static inline uint8_t 764 *hal_rx_pkt_hdr_get(uint8_t *buf) 765 { 766 return buf + RX_PKT_TLVS_LEN; 767 } 768 #else 769 static inline uint8_t 770 *hal_rx_pkt_hdr_get(uint8_t *buf) 771 { 772 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 773 774 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 775 776 } 777 #endif 778 779 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 780 781 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 782 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 783 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 784 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 785 RX_PKT_TLV_OFFSET(msdu_start_tlv) 786 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 787 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 788 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 789 790 static inline uint8_t 791 *hal_rx_padding0_get(uint8_t *buf) 792 { 793 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 794 795 return pkt_tlvs->rx_padding0; 796 } 797 798 /* 799 * hal_rx_encryption_info_valid(): Returns encryption type. 800 * 801 * @hal_soc_hdl: hal soc handle 802 * @buf: rx_tlv_hdr of the received packet 803 * 804 * Return: encryption type 805 */ 806 static inline uint32_t 807 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 808 { 809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 810 811 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 812 813 } 814 815 /* 816 * hal_rx_print_pn: Prints the PN of rx packet. 817 * @hal_soc_hdl: hal soc handle 818 * @buf: rx_tlv_hdr of the received packet 819 * 820 * Return: void 821 */ 822 static inline void 823 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 824 { 825 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 826 827 hal_soc->ops->hal_rx_print_pn(buf); 828 } 829 830 /* 831 * Get msdu_done bit from the RX_ATTENTION TLV 832 */ 833 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 834 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 835 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 836 RX_ATTENTION_2_MSDU_DONE_MASK, \ 837 RX_ATTENTION_2_MSDU_DONE_LSB)) 838 839 static inline uint32_t 840 hal_rx_attn_msdu_done_get(uint8_t *buf) 841 { 842 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 843 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 844 uint32_t msdu_done; 845 846 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 847 848 return msdu_done; 849 } 850 851 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 852 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 853 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 854 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 855 RX_ATTENTION_1_FIRST_MPDU_LSB)) 856 857 /* 858 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 859 * @buf: pointer to rx_pkt_tlvs 860 * 861 * reutm: uint32_t(first_msdu) 862 */ 863 static inline uint32_t 864 hal_rx_attn_first_mpdu_get(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 868 uint32_t first_mpdu; 869 870 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 871 872 return first_mpdu; 873 } 874 875 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 876 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 877 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 878 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 879 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 880 881 /* 882 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 883 * from rx attention 884 * @buf: pointer to rx_pkt_tlvs 885 * 886 * Return: tcp_udp_cksum_fail 887 */ 888 static inline bool 889 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 890 { 891 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 892 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 893 bool tcp_udp_cksum_fail; 894 895 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 896 897 return tcp_udp_cksum_fail; 898 } 899 900 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 901 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 902 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 903 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 904 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 905 906 /* 907 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 908 * from rx attention 909 * @buf: pointer to rx_pkt_tlvs 910 * 911 * Return: ip_cksum_fail 912 */ 913 static inline bool 914 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 915 { 916 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 917 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 918 bool ip_cksum_fail; 919 920 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 921 922 return ip_cksum_fail; 923 } 924 925 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 926 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 927 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 928 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 929 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 930 931 /* 932 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 933 * from rx attention 934 * @buf: pointer to rx_pkt_tlvs 935 * 936 * Return: phy_ppdu_id 937 */ 938 static inline uint16_t 939 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 940 { 941 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 942 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 943 uint16_t phy_ppdu_id; 944 945 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 946 947 return phy_ppdu_id; 948 } 949 950 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 951 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 952 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 953 RX_ATTENTION_1_CCE_MATCH_MASK, \ 954 RX_ATTENTION_1_CCE_MATCH_LSB)) 955 956 /* 957 * hal_rx_msdu_cce_match_get(): get CCE match bit 958 * from rx attention 959 * @buf: pointer to rx_pkt_tlvs 960 * Return: CCE match value 961 */ 962 static inline bool 963 hal_rx_msdu_cce_match_get(uint8_t *buf) 964 { 965 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 966 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 967 bool cce_match_val; 968 969 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 970 return cce_match_val; 971 } 972 973 /* 974 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 975 */ 976 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 977 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 978 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 979 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 980 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 981 982 static inline uint32_t 983 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 984 { 985 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 986 struct rx_mpdu_start *mpdu_start = 987 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 988 989 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 990 uint32_t peer_meta_data; 991 992 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 993 994 return peer_meta_data; 995 } 996 997 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 998 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 999 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 1000 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 1001 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 1002 /** 1003 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 1004 * from rx mpdu info 1005 * @buf: pointer to rx_pkt_tlvs 1006 * 1007 * Return: ampdu flag 1008 */ 1009 static inline bool 1010 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 1011 { 1012 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1013 struct rx_mpdu_start *mpdu_start = 1014 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1015 1016 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1017 bool ampdu_flag; 1018 1019 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 1020 1021 return ampdu_flag; 1022 } 1023 1024 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 1025 ((*(((uint32_t *)_rx_mpdu_info) + \ 1026 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 1027 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 1028 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 1029 1030 /* 1031 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 1032 * 1033 * @ buf: rx_tlv_hdr of the received packet 1034 * @ peer_mdata: peer meta data to be set. 1035 * @ Return: void 1036 */ 1037 static inline void 1038 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 1039 { 1040 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1041 struct rx_mpdu_start *mpdu_start = 1042 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1043 1044 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1045 1046 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 1047 } 1048 1049 /** 1050 * LRO information needed from the TLVs 1051 */ 1052 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 1053 (_HAL_MS( \ 1054 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1055 msdu_end_tlv.rx_msdu_end), \ 1056 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 1057 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 1058 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 1059 1060 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 1061 (_HAL_MS( \ 1062 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1063 msdu_end_tlv.rx_msdu_end), \ 1064 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 1065 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 1066 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 1067 1068 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 1069 (_HAL_MS( \ 1070 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1071 msdu_end_tlv.rx_msdu_end), \ 1072 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 1073 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 1074 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 1075 1076 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 1077 (_HAL_MS( \ 1078 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1079 msdu_end_tlv.rx_msdu_end), \ 1080 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 1081 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 1082 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 1083 1084 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 1085 (_HAL_MS( \ 1086 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1087 msdu_start_tlv.rx_msdu_start), \ 1088 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 1089 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 1090 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 1091 1092 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 1093 (_HAL_MS( \ 1094 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1095 msdu_start_tlv.rx_msdu_start), \ 1096 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 1097 RX_MSDU_START_2_TCP_PROTO_MASK, \ 1098 RX_MSDU_START_2_TCP_PROTO_LSB)) 1099 1100 #define HAL_RX_TLV_GET_UDP_PROTO(buf) \ 1101 (_HAL_MS( \ 1102 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1103 msdu_start_tlv.rx_msdu_start), \ 1104 RX_MSDU_START_2_UDP_PROTO_OFFSET)), \ 1105 RX_MSDU_START_2_UDP_PROTO_MASK, \ 1106 RX_MSDU_START_2_UDP_PROTO_LSB)) 1107 1108 #define HAL_RX_TLV_GET_IPV6(buf) \ 1109 (_HAL_MS( \ 1110 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1111 msdu_start_tlv.rx_msdu_start), \ 1112 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 1113 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 1114 RX_MSDU_START_2_IPV6_PROTO_LSB)) 1115 1116 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 1117 (_HAL_MS( \ 1118 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1119 msdu_start_tlv.rx_msdu_start), \ 1120 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 1121 RX_MSDU_START_1_L3_OFFSET_MASK, \ 1122 RX_MSDU_START_1_L3_OFFSET_LSB)) 1123 1124 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 1125 (_HAL_MS( \ 1126 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1127 msdu_start_tlv.rx_msdu_start), \ 1128 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 1129 RX_MSDU_START_1_L4_OFFSET_MASK, \ 1130 RX_MSDU_START_1_L4_OFFSET_LSB)) 1131 1132 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 1133 (_HAL_MS( \ 1134 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1135 msdu_start_tlv.rx_msdu_start), \ 1136 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1137 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1138 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1139 1140 /** 1141 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 1142 * l3_header padding from rx_msdu_end TLV 1143 * 1144 * @buf: pointer to the start of RX PKT TLV headers 1145 * Return: number of l3 header padding bytes 1146 */ 1147 static inline uint32_t 1148 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 1149 uint8_t *buf) 1150 { 1151 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1152 1153 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 1154 } 1155 1156 /** 1157 * hal_rx_msdu_end_sa_idx_get(): API to get the 1158 * sa_idx from rx_msdu_end TLV 1159 * 1160 * @ buf: pointer to the start of RX PKT TLV headers 1161 * Return: sa_idx (SA AST index) 1162 */ 1163 static inline uint16_t 1164 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 1165 uint8_t *buf) 1166 { 1167 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1168 1169 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 1170 } 1171 1172 /** 1173 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1174 * sa_is_valid bit from rx_msdu_end TLV 1175 * 1176 * @ buf: pointer to the start of RX PKT TLV headers 1177 * Return: sa_is_valid bit 1178 */ 1179 static inline uint8_t 1180 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1181 uint8_t *buf) 1182 { 1183 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1184 1185 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 1186 } 1187 1188 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1190 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1191 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1192 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1193 1194 /** 1195 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1196 * from rx_msdu_start TLV 1197 * 1198 * @ buf: pointer to the start of RX PKT TLV headers 1199 * Return: msdu length 1200 */ 1201 static inline uint32_t 1202 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1203 { 1204 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1205 struct rx_msdu_start *msdu_start = 1206 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1207 uint32_t msdu_len; 1208 1209 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1210 1211 return msdu_len; 1212 } 1213 1214 /** 1215 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1216 * from rx_msdu_start TLV 1217 * 1218 * @buf: pointer to the start of RX PKT TLV headers 1219 * @len: msdu length 1220 * 1221 * Return: none 1222 */ 1223 static inline void 1224 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1225 { 1226 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1227 struct rx_msdu_start *msdu_start = 1228 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1229 void *wrd1; 1230 1231 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1232 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1233 *(uint32_t *)wrd1 |= len; 1234 } 1235 1236 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1237 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1238 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1239 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1240 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1241 1242 /* 1243 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1244 * Interval from rx_msdu_start 1245 * 1246 * @buf: pointer to the start of RX PKT TLV header 1247 * Return: uint32_t(bw) 1248 */ 1249 static inline uint32_t 1250 hal_rx_msdu_start_bw_get(uint8_t *buf) 1251 { 1252 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1253 struct rx_msdu_start *msdu_start = 1254 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1255 uint32_t bw; 1256 1257 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1258 1259 return bw; 1260 } 1261 1262 1263 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1264 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1265 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1266 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1267 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1268 1269 /** 1270 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1271 * from rx_msdu_start TLV 1272 * 1273 * @ buf: pointer to the start of RX PKT TLV headers 1274 * Return: toeplitz hash 1275 */ 1276 static inline uint32_t 1277 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1278 { 1279 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1280 struct rx_msdu_start *msdu_start = 1281 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1282 1283 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1284 } 1285 1286 /** 1287 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 1288 * 1289 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 1290 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 1291 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 1292 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 1293 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 1294 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 1295 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 1296 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 1297 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 1298 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 1299 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 1300 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 1301 */ 1302 enum hal_rx_mpdu_info_sw_frame_group_id_type { 1303 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 1304 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 1305 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 1306 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 1307 HAL_MPDU_SW_FRAME_GROUP_MGMT, 1308 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 1309 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 1310 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 1311 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 1312 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 1313 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 1314 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 1315 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 1316 }; 1317 1318 /** 1319 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 1320 * Retrieve qos control valid bit from the tlv. 1321 * @hal_soc_hdl: hal_soc handle 1322 * @buf: pointer to rx pkt TLV. 1323 * 1324 * Return: qos control value. 1325 */ 1326 static inline uint32_t 1327 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 1328 hal_soc_handle_t hal_soc_hdl, 1329 uint8_t *buf) 1330 { 1331 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1332 1333 if ((!hal_soc) || (!hal_soc->ops)) { 1334 hal_err("hal handle is NULL"); 1335 QDF_BUG(0); 1336 return QDF_STATUS_E_INVAL; 1337 } 1338 1339 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 1340 return hal_soc->ops-> 1341 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 1342 1343 return QDF_STATUS_E_INVAL; 1344 } 1345 1346 /** 1347 * hal_rx_is_unicast: check packet is unicast frame or not. 1348 * @hal_soc_hdl: hal_soc handle 1349 * @buf: pointer to rx pkt TLV. 1350 * 1351 * Return: true on unicast. 1352 */ 1353 static inline bool 1354 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1355 { 1356 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1357 1358 return hal_soc->ops->hal_rx_is_unicast(buf); 1359 } 1360 1361 /** 1362 * hal_rx_tid_get: get tid based on qos control valid. 1363 * @hal_soc_hdl: hal soc handle 1364 * @buf: pointer to rx pkt TLV. 1365 * 1366 * Return: tid 1367 */ 1368 static inline uint32_t 1369 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1370 { 1371 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1372 1373 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 1374 } 1375 1376 /** 1377 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 1378 * @hal_soc_hdl: hal soc handle 1379 * @buf: pointer to rx pkt TLV. 1380 * 1381 * Return: sw peer_id 1382 */ 1383 static inline uint32_t 1384 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1385 uint8_t *buf) 1386 { 1387 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1388 1389 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1390 } 1391 1392 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1393 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1394 RX_MSDU_START_5_SGI_OFFSET)), \ 1395 RX_MSDU_START_5_SGI_MASK, \ 1396 RX_MSDU_START_5_SGI_LSB)) 1397 /** 1398 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1399 * Interval from rx_msdu_start TLV 1400 * 1401 * @buf: pointer to the start of RX PKT TLV headers 1402 * Return: uint32_t(sgi) 1403 */ 1404 static inline uint32_t 1405 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1406 { 1407 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1408 struct rx_msdu_start *msdu_start = 1409 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1410 uint32_t sgi; 1411 1412 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1413 1414 return sgi; 1415 } 1416 1417 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1418 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1419 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1420 RX_MSDU_START_5_RATE_MCS_MASK, \ 1421 RX_MSDU_START_5_RATE_MCS_LSB)) 1422 /** 1423 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1424 * from rx_msdu_start TLV 1425 * 1426 * @buf: pointer to the start of RX PKT TLV headers 1427 * Return: uint32_t(rate_mcs) 1428 */ 1429 static inline uint32_t 1430 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1431 { 1432 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1433 struct rx_msdu_start *msdu_start = 1434 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1435 uint32_t rate_mcs; 1436 1437 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1438 1439 return rate_mcs; 1440 } 1441 1442 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1443 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1444 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1445 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1446 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1447 1448 /* 1449 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1450 * packet from rx_attention 1451 * 1452 * @buf: pointer to the start of RX PKT TLV header 1453 * Return: uint32_t(decryt status) 1454 */ 1455 1456 static inline uint32_t 1457 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1458 { 1459 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1460 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1461 uint32_t is_decrypt = 0; 1462 uint32_t decrypt_status; 1463 1464 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1465 1466 if (!decrypt_status) 1467 is_decrypt = 1; 1468 1469 return is_decrypt; 1470 } 1471 1472 /* 1473 * Get key index from RX_MSDU_END 1474 */ 1475 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1476 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1477 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1478 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1479 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1480 /* 1481 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1482 * from rx_msdu_end 1483 * 1484 * @buf: pointer to the start of RX PKT TLV header 1485 * Return: uint32_t(key id) 1486 */ 1487 1488 static inline uint32_t 1489 hal_rx_msdu_get_keyid(uint8_t *buf) 1490 { 1491 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1492 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1493 uint32_t keyid_octet; 1494 1495 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1496 1497 return keyid_octet & 0x3; 1498 } 1499 1500 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1501 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1502 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1503 RX_MSDU_START_5_USER_RSSI_MASK, \ 1504 RX_MSDU_START_5_USER_RSSI_LSB)) 1505 /* 1506 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1507 * from rx_msdu_start 1508 * 1509 * @buf: pointer to the start of RX PKT TLV header 1510 * Return: uint32_t(rssi) 1511 */ 1512 1513 static inline uint32_t 1514 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1515 { 1516 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1517 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1518 uint32_t rssi; 1519 1520 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1521 1522 return rssi; 1523 1524 } 1525 1526 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1527 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1528 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1529 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1530 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1531 1532 /* 1533 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1534 * from rx_msdu_start 1535 * 1536 * @buf: pointer to the start of RX PKT TLV header 1537 * Return: uint32_t(frequency) 1538 */ 1539 1540 static inline uint32_t 1541 hal_rx_msdu_start_get_freq(uint8_t *buf) 1542 { 1543 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1544 struct rx_msdu_start *msdu_start = 1545 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1546 uint32_t freq; 1547 1548 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1549 1550 return freq; 1551 } 1552 1553 1554 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1555 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1556 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1557 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1558 RX_MSDU_START_5_PKT_TYPE_LSB)) 1559 1560 /* 1561 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1562 * from rx_msdu_start 1563 * 1564 * @buf: pointer to the start of RX PKT TLV header 1565 * Return: uint32_t(pkt type) 1566 */ 1567 1568 static inline uint32_t 1569 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1570 { 1571 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1572 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1573 uint32_t pkt_type; 1574 1575 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1576 1577 return pkt_type; 1578 } 1579 1580 /* 1581 * hal_rx_mpdu_get_tods(): API to get the tods info 1582 * from rx_mpdu_start 1583 * 1584 * @buf: pointer to the start of RX PKT TLV header 1585 * Return: uint32_t(to_ds) 1586 */ 1587 1588 static inline uint32_t 1589 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1590 { 1591 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1592 1593 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1594 } 1595 1596 1597 /* 1598 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1599 * from rx_mpdu_start 1600 * @hal_soc_hdl: hal soc handle 1601 * @buf: pointer to the start of RX PKT TLV header 1602 * 1603 * Return: uint32_t(fr_ds) 1604 */ 1605 static inline uint32_t 1606 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1607 { 1608 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1609 1610 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1611 } 1612 1613 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1614 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1615 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1616 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1617 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1618 1619 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1620 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1621 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1622 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1623 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1624 1625 /* 1626 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1627 * @hal_soc_hdl: hal soc handle 1628 * @buf: pointer to the start of RX PKT TLV headera 1629 * @mac_addr: pointer to mac address 1630 * 1631 * Return: success/failure 1632 */ 1633 static inline 1634 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1635 uint8_t *buf, uint8_t *mac_addr) 1636 { 1637 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1638 1639 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1640 } 1641 1642 /* 1643 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1644 * in the packet 1645 * @hal_soc_hdl: hal soc handle 1646 * @buf: pointer to the start of RX PKT TLV header 1647 * @mac_addr: pointer to mac address 1648 * 1649 * Return: success/failure 1650 */ 1651 static inline 1652 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1653 uint8_t *buf, uint8_t *mac_addr) 1654 { 1655 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1656 1657 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1658 } 1659 1660 /* 1661 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1662 * in the packet 1663 * @hal_soc_hdl: hal soc handle 1664 * @buf: pointer to the start of RX PKT TLV header 1665 * @mac_addr: pointer to mac address 1666 * 1667 * Return: success/failure 1668 */ 1669 static inline 1670 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1671 uint8_t *buf, uint8_t *mac_addr) 1672 { 1673 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1674 1675 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1676 } 1677 1678 /* 1679 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1680 * in the packet 1681 * @hal_soc_hdl: hal_soc handle 1682 * @buf: pointer to the start of RX PKT TLV header 1683 * @mac_addr: pointer to mac address 1684 * Return: success/failure 1685 */ 1686 static inline 1687 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1688 uint8_t *buf, uint8_t *mac_addr) 1689 { 1690 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1691 1692 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1693 } 1694 1695 /** 1696 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1697 * from rx_msdu_end TLV 1698 * 1699 * @ buf: pointer to the start of RX PKT TLV headers 1700 * Return: da index 1701 */ 1702 static inline uint16_t 1703 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1704 { 1705 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1706 1707 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1708 } 1709 1710 /** 1711 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1712 * from rx_msdu_end TLV 1713 * @hal_soc_hdl: hal soc handle 1714 * @ buf: pointer to the start of RX PKT TLV headers 1715 * 1716 * Return: da_is_valid 1717 */ 1718 static inline uint8_t 1719 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1720 uint8_t *buf) 1721 { 1722 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1723 1724 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1725 } 1726 1727 /** 1728 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1729 * from rx_msdu_end TLV 1730 * 1731 * @buf: pointer to the start of RX PKT TLV headers 1732 * 1733 * Return: da_is_mcbc 1734 */ 1735 static inline uint8_t 1736 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1737 { 1738 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1739 1740 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1741 } 1742 1743 /** 1744 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1745 * from rx_msdu_end TLV 1746 * @hal_soc_hdl: hal soc handle 1747 * @buf: pointer to the start of RX PKT TLV headers 1748 * 1749 * Return: first_msdu 1750 */ 1751 static inline uint8_t 1752 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1753 uint8_t *buf) 1754 { 1755 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1756 1757 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1758 } 1759 1760 /** 1761 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1762 * from rx_msdu_end TLV 1763 * @hal_soc_hdl: hal soc handle 1764 * @buf: pointer to the start of RX PKT TLV headers 1765 * 1766 * Return: last_msdu 1767 */ 1768 static inline uint8_t 1769 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1770 uint8_t *buf) 1771 { 1772 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1773 1774 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1775 } 1776 1777 /** 1778 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1779 * from rx_msdu_end TLV 1780 * @buf: pointer to the start of RX PKT TLV headers 1781 * Return: cce_meta_data 1782 */ 1783 static inline uint16_t 1784 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1785 uint8_t *buf) 1786 { 1787 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1788 1789 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1790 } 1791 1792 /******************************************************************************* 1793 * RX ERROR APIS 1794 ******************************************************************************/ 1795 1796 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1797 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1798 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1799 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1800 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1801 1802 /** 1803 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1804 * from rx_mpdu_end TLV 1805 * 1806 * @buf: pointer to the start of RX PKT TLV headers 1807 * Return: uint32_t(decrypt_err) 1808 */ 1809 static inline uint32_t 1810 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1811 { 1812 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1813 struct rx_mpdu_end *mpdu_end = 1814 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1815 uint32_t decrypt_err; 1816 1817 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1818 1819 return decrypt_err; 1820 } 1821 1822 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1823 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1824 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1825 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1826 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1827 1828 /** 1829 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1830 * from rx_mpdu_end TLV 1831 * 1832 * @buf: pointer to the start of RX PKT TLV headers 1833 * Return: uint32_t(mic_err) 1834 */ 1835 static inline uint32_t 1836 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1837 { 1838 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1839 struct rx_mpdu_end *mpdu_end = 1840 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1841 uint32_t mic_err; 1842 1843 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1844 1845 return mic_err; 1846 } 1847 1848 /******************************************************************************* 1849 * RX REO ERROR APIS 1850 ******************************************************************************/ 1851 1852 #define HAL_RX_NUM_MSDU_DESC 6 1853 #define HAL_RX_MAX_SAVED_RING_DESC 16 1854 1855 /* TODO: rework the structure */ 1856 struct hal_rx_msdu_list { 1857 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1858 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1859 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1860 /* physical address of the msdu */ 1861 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1862 }; 1863 1864 struct hal_buf_info { 1865 uint64_t paddr; 1866 uint32_t sw_cookie; 1867 uint8_t rbm; 1868 }; 1869 1870 /** 1871 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1872 * @msdu_link_ptr - msdu link ptr 1873 * @hal - pointer to hal_soc 1874 * Return - Pointer to rx_msdu_details structure 1875 * 1876 */ 1877 static inline 1878 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1879 struct hal_soc *hal_soc) 1880 { 1881 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1882 } 1883 1884 /** 1885 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1886 * @msdu_details_ptr - Pointer to msdu_details_ptr 1887 * @hal - pointer to hal_soc 1888 * Return - Pointer to rx_msdu_desc_info structure. 1889 * 1890 */ 1891 static inline 1892 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1893 struct hal_soc *hal_soc) 1894 { 1895 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1896 } 1897 1898 /* This special cookie value will be used to indicate FW allocated buffers 1899 * received through RXDMA2SW ring for RXDMA WARs 1900 */ 1901 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1902 1903 /** 1904 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1905 * from the MSDU link descriptor 1906 * 1907 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1908 * MSDU link descriptor (struct rx_msdu_link) 1909 * 1910 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1911 * 1912 * @num_msdus: Number of MSDUs in the MPDU 1913 * 1914 * Return: void 1915 */ 1916 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1917 void *msdu_link_desc, 1918 struct hal_rx_msdu_list *msdu_list, 1919 uint16_t *num_msdus) 1920 { 1921 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1922 struct rx_msdu_details *msdu_details; 1923 struct rx_msdu_desc_info *msdu_desc_info; 1924 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1925 int i; 1926 1927 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1928 1929 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1930 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1931 __func__, __LINE__, msdu_link, msdu_details); 1932 1933 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1934 /* num_msdus received in mpdu descriptor may be incorrect 1935 * sometimes due to HW issue. Check msdu buffer address also 1936 */ 1937 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1938 &msdu_details[i].buffer_addr_info_details) == 0)) 1939 break; 1940 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1941 &msdu_details[i].buffer_addr_info_details) == 0) { 1942 /* set the last msdu bit in the prev msdu_desc_info */ 1943 msdu_desc_info = 1944 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1945 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1946 break; 1947 } 1948 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1949 hal_soc); 1950 1951 /* set first MSDU bit or the last MSDU bit */ 1952 if (!i) 1953 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1954 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1955 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1956 1957 msdu_list->msdu_info[i].msdu_flags = 1958 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1959 msdu_list->msdu_info[i].msdu_len = 1960 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1961 msdu_list->sw_cookie[i] = 1962 HAL_RX_BUF_COOKIE_GET( 1963 &msdu_details[i].buffer_addr_info_details); 1964 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1965 &msdu_details[i].buffer_addr_info_details); 1966 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1967 &msdu_details[i].buffer_addr_info_details) | 1968 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1969 &msdu_details[i].buffer_addr_info_details) << 32; 1970 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1971 "[%s][%d] i=%d sw_cookie=%d", 1972 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1973 } 1974 *num_msdus = i; 1975 } 1976 1977 /** 1978 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1979 * destination ring ID from the msdu desc info 1980 * 1981 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1982 * the current descriptor 1983 * 1984 * Return: dst_ind (REO destination ring ID) 1985 */ 1986 static inline uint32_t 1987 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 1988 { 1989 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1990 struct rx_msdu_details *msdu_details; 1991 struct rx_msdu_desc_info *msdu_desc_info; 1992 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1993 uint32_t dst_ind; 1994 1995 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1996 1997 /* The first msdu in the link should exsist */ 1998 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1999 hal_soc); 2000 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 2001 return dst_ind; 2002 } 2003 2004 /** 2005 * hal_rx_reo_buf_paddr_get: Gets the physical address and 2006 * cookie from the REO destination ring element 2007 * 2008 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 2009 * the current descriptor 2010 * @ buf_info: structure to return the buffer information 2011 * Return: void 2012 */ 2013 static inline 2014 void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc, 2015 struct hal_buf_info *buf_info) 2016 { 2017 struct reo_destination_ring *reo_ring = 2018 (struct reo_destination_ring *)rx_desc; 2019 2020 buf_info->paddr = 2021 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 2022 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 2023 2024 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 2025 } 2026 2027 /** 2028 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 2029 * 2030 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 2031 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 2032 * descriptor 2033 */ 2034 enum hal_rx_reo_buf_type { 2035 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 2036 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 2037 }; 2038 2039 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2040 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 2041 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 2042 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 2043 2044 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 2045 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 2046 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 2047 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 2048 2049 /** 2050 * enum hal_reo_error_code: Error code describing the type of error detected 2051 * 2052 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 2053 * REO_ENTRANCE ring is set to 0 2054 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 2055 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 2056 * having been setup 2057 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 2058 * Retry bit set: duplicate frame 2059 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 2060 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 2061 * received with 2K jump in SN 2062 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 2063 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 2064 * with SN falling within the OOR window 2065 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 2066 * OOR window 2067 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 2068 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 2069 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 2070 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2071 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 2072 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2073 * of the pn_error_detected_flag been set in the REO Queue descriptor 2074 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 2075 * the queue descriptor(address) being blocked as SW/FW seems to be currently 2076 * in the process of making updates to this descriptor 2077 */ 2078 enum hal_reo_error_code { 2079 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 2080 HAL_REO_ERR_QUEUE_DESC_INVALID, 2081 HAL_REO_ERR_AMPDU_IN_NON_BA, 2082 HAL_REO_ERR_NON_BA_DUPLICATE, 2083 HAL_REO_ERR_BA_DUPLICATE, 2084 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 2085 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 2086 HAL_REO_ERR_REGULAR_FRAME_OOR, 2087 HAL_REO_ERR_BAR_FRAME_OOR, 2088 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 2089 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 2090 HAL_REO_ERR_PN_CHECK_FAILED, 2091 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 2092 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 2093 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 2094 HAL_REO_ERR_MAX 2095 }; 2096 2097 /** 2098 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 2099 * 2100 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 2101 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 2102 * overflow 2103 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 2104 * incomplete 2105 * MPDU from the PHY 2106 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 2107 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 2108 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 2109 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 2110 * encrypted but wasn’t 2111 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 2112 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 2113 * the max allowed 2114 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2115 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2116 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2117 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2118 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2119 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2120 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2121 */ 2122 enum hal_rxdma_error_code { 2123 HAL_RXDMA_ERR_OVERFLOW = 0, 2124 HAL_RXDMA_ERR_MPDU_LENGTH, 2125 HAL_RXDMA_ERR_FCS, 2126 HAL_RXDMA_ERR_DECRYPT, 2127 HAL_RXDMA_ERR_TKIP_MIC, 2128 HAL_RXDMA_ERR_UNENCRYPTED, 2129 HAL_RXDMA_ERR_MSDU_LEN, 2130 HAL_RXDMA_ERR_MSDU_LIMIT, 2131 HAL_RXDMA_ERR_WIFI_PARSE, 2132 HAL_RXDMA_ERR_AMSDU_PARSE, 2133 HAL_RXDMA_ERR_SA_TIMEOUT, 2134 HAL_RXDMA_ERR_DA_TIMEOUT, 2135 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2136 HAL_RXDMA_ERR_FLUSH_REQUEST, 2137 HAL_RXDMA_ERR_WAR = 31, 2138 HAL_RXDMA_ERR_MAX 2139 }; 2140 2141 /** 2142 * HW BM action settings in WBM release ring 2143 */ 2144 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2145 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2146 2147 /** 2148 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2149 * release of this buffer or descriptor 2150 * 2151 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2152 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2153 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2154 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2155 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2156 */ 2157 enum hal_rx_wbm_error_source { 2158 HAL_RX_WBM_ERR_SRC_TQM = 0, 2159 HAL_RX_WBM_ERR_SRC_RXDMA, 2160 HAL_RX_WBM_ERR_SRC_REO, 2161 HAL_RX_WBM_ERR_SRC_FW, 2162 HAL_RX_WBM_ERR_SRC_SW, 2163 }; 2164 2165 /** 2166 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2167 * released 2168 * 2169 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2170 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2171 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2172 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2173 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2174 */ 2175 enum hal_rx_wbm_buf_type { 2176 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2177 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2178 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2179 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2180 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2181 }; 2182 2183 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2184 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2185 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2186 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2187 2188 /** 2189 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2190 * PN check failure 2191 * 2192 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2193 * 2194 * Return: true: error caused by PN check, false: other error 2195 */ 2196 static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc) 2197 { 2198 struct reo_destination_ring *reo_desc = 2199 (struct reo_destination_ring *)rx_desc; 2200 2201 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2202 HAL_REO_ERR_PN_CHECK_FAILED) | 2203 (HAL_RX_REO_ERROR_GET(reo_desc) == 2204 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2205 true : false; 2206 } 2207 2208 /** 2209 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2210 * the sequence number 2211 * 2212 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2213 * 2214 * Return: true: error caused by 2K jump, false: other error 2215 */ 2216 static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc) 2217 { 2218 struct reo_destination_ring *reo_desc = 2219 (struct reo_destination_ring *)rx_desc; 2220 2221 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2222 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2223 (HAL_RX_REO_ERROR_GET(reo_desc) == 2224 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2225 true : false; 2226 } 2227 2228 /** 2229 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 2230 * 2231 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2232 * 2233 * Return: true: error caused by OOR, false: other error 2234 */ 2235 static inline bool hal_rx_reo_is_oor_error(void *rx_desc) 2236 { 2237 struct reo_destination_ring *reo_desc = 2238 (struct reo_destination_ring *)rx_desc; 2239 2240 return (HAL_RX_REO_ERROR_GET(reo_desc) == 2241 HAL_REO_ERR_REGULAR_FRAME_OOR) ? true : false; 2242 } 2243 2244 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 2245 /** 2246 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 2247 * @hal_desc: hardware descriptor pointer 2248 * 2249 * This function will print wbm release descriptor 2250 * 2251 * Return: none 2252 */ 2253 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 2254 { 2255 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 2256 uint32_t i; 2257 2258 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2259 "Current Rx wbm release descriptor is"); 2260 2261 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 2262 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2263 "DWORD[i] = 0x%x", wbm_comp[i]); 2264 } 2265 } 2266 2267 /** 2268 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2269 * 2270 * @ hal_soc_hdl : HAL version of the SOC pointer 2271 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2272 * @ buf_addr_info : void pointer to the buffer_addr_info 2273 * @ bm_action : put in IDLE list or release to MSDU_LIST 2274 * 2275 * Return: void 2276 */ 2277 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2278 static inline 2279 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 2280 void *src_srng_desc, 2281 hal_buff_addrinfo_t buf_addr_info, 2282 uint8_t bm_action) 2283 { 2284 struct wbm_release_ring *wbm_rel_srng = 2285 (struct wbm_release_ring *)src_srng_desc; 2286 uint32_t addr_31_0; 2287 uint8_t addr_39_32; 2288 2289 /* Structure copy !!! */ 2290 wbm_rel_srng->released_buff_or_desc_addr_info = 2291 *((struct buffer_addr_info *)buf_addr_info); 2292 2293 addr_31_0 = 2294 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 2295 addr_39_32 = 2296 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 2297 2298 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2299 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2300 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2301 bm_action); 2302 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2303 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2304 2305 /* WBM error is indicated when any of the link descriptors given to 2306 * WBM has a NULL address, and one those paths is the link descriptors 2307 * released from host after processing RXDMA errors, 2308 * or from Rx defrag path, and we want to add an assert here to ensure 2309 * host is not releasing descriptors with NULL address. 2310 */ 2311 2312 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 2313 hal_dump_wbm_rel_desc(src_srng_desc); 2314 qdf_assert_always(0); 2315 } 2316 } 2317 2318 /* 2319 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2320 * REO entrance ring 2321 * 2322 * @ soc: HAL version of the SOC pointer 2323 * @ pa: Physical address of the MSDU Link Descriptor 2324 * @ cookie: SW cookie to get to the virtual address 2325 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2326 * to the error enabled REO queue 2327 * 2328 * Return: void 2329 */ 2330 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2331 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2332 { 2333 /* TODO */ 2334 } 2335 2336 /** 2337 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2338 * BUFFER_ADDR_INFO, give the RX descriptor 2339 * (Assumption -- BUFFER_ADDR_INFO is the 2340 * first field in the descriptor structure) 2341 */ 2342 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 2343 ((hal_link_desc_t)(ring_desc)) 2344 2345 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2346 2347 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2348 2349 /** 2350 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2351 * from the BUFFER_ADDR_INFO structure 2352 * given a REO destination ring descriptor. 2353 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2354 * 2355 * Return: uint8_t (value of the return_buffer_manager) 2356 */ 2357 static inline 2358 uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc) 2359 { 2360 /* 2361 * The following macro takes buf_addr_info as argument, 2362 * but since buf_addr_info is the first field in ring_desc 2363 * Hence the following call is OK 2364 */ 2365 return HAL_RX_BUF_RBM_GET(ring_desc); 2366 } 2367 2368 2369 /******************************************************************************* 2370 * RX WBM ERROR APIS 2371 ******************************************************************************/ 2372 2373 2374 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2375 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2376 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2377 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2378 2379 /** 2380 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2381 * the frame to this release ring 2382 * 2383 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2384 * frame to this queue 2385 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2386 * received routing instructions. No error within REO was detected 2387 */ 2388 enum hal_rx_wbm_reo_push_reason { 2389 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2390 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2391 }; 2392 2393 2394 /** 2395 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2396 * this release ring 2397 * 2398 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2399 * this frame to this queue 2400 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2401 * per received routing instructions. No error within RXDMA was detected 2402 */ 2403 enum hal_rx_wbm_rxdma_push_reason { 2404 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2405 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2406 }; 2407 2408 2409 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2410 (((*(((uint32_t *) wbm_desc) + \ 2411 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2412 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2413 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2414 2415 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2416 (((*(((uint32_t *) wbm_desc) + \ 2417 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2418 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2419 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2420 2421 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2422 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2423 wbm_desc)->released_buff_or_desc_addr_info) 2424 2425 /** 2426 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2427 * humman readable format. 2428 * @ rx_attn: pointer the rx_attention TLV in pkt. 2429 * @ dbg_level: log level. 2430 * 2431 * Return: void 2432 */ 2433 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2434 uint8_t dbg_level) 2435 { 2436 hal_verbose_debug( 2437 "rx_attention tlv (1/2) - " 2438 "rxpcu_mpdu_filter_in_category: %x " 2439 "sw_frame_group_id: %x " 2440 "reserved_0: %x " 2441 "phy_ppdu_id: %x " 2442 "first_mpdu : %x " 2443 "reserved_1a: %x " 2444 "mcast_bcast: %x " 2445 "ast_index_not_found: %x " 2446 "ast_index_timeout: %x " 2447 "power_mgmt: %x " 2448 "non_qos: %x " 2449 "null_data: %x " 2450 "mgmt_type: %x " 2451 "ctrl_type: %x " 2452 "more_data: %x " 2453 "eosp: %x " 2454 "a_msdu_error: %x " 2455 "fragment_flag: %x " 2456 "order: %x " 2457 "cce_match: %x " 2458 "overflow_err: %x " 2459 "msdu_length_err: %x " 2460 "tcp_udp_chksum_fail: %x " 2461 "ip_chksum_fail: %x " 2462 "sa_idx_invalid: %x " 2463 "da_idx_invalid: %x " 2464 "reserved_1b: %x " 2465 "rx_in_tx_decrypt_byp: %x ", 2466 rx_attn->rxpcu_mpdu_filter_in_category, 2467 rx_attn->sw_frame_group_id, 2468 rx_attn->reserved_0, 2469 rx_attn->phy_ppdu_id, 2470 rx_attn->first_mpdu, 2471 rx_attn->reserved_1a, 2472 rx_attn->mcast_bcast, 2473 rx_attn->ast_index_not_found, 2474 rx_attn->ast_index_timeout, 2475 rx_attn->power_mgmt, 2476 rx_attn->non_qos, 2477 rx_attn->null_data, 2478 rx_attn->mgmt_type, 2479 rx_attn->ctrl_type, 2480 rx_attn->more_data, 2481 rx_attn->eosp, 2482 rx_attn->a_msdu_error, 2483 rx_attn->fragment_flag, 2484 rx_attn->order, 2485 rx_attn->cce_match, 2486 rx_attn->overflow_err, 2487 rx_attn->msdu_length_err, 2488 rx_attn->tcp_udp_chksum_fail, 2489 rx_attn->ip_chksum_fail, 2490 rx_attn->sa_idx_invalid, 2491 rx_attn->da_idx_invalid, 2492 rx_attn->reserved_1b, 2493 rx_attn->rx_in_tx_decrypt_byp); 2494 2495 hal_verbose_debug( 2496 "rx_attention tlv (2/2) - " 2497 "encrypt_required: %x " 2498 "directed: %x " 2499 "buffer_fragment: %x " 2500 "mpdu_length_err: %x " 2501 "tkip_mic_err: %x " 2502 "decrypt_err: %x " 2503 "unencrypted_frame_err: %x " 2504 "fcs_err: %x " 2505 "flow_idx_timeout: %x " 2506 "flow_idx_invalid: %x " 2507 "wifi_parser_error: %x " 2508 "amsdu_parser_error: %x " 2509 "sa_idx_timeout: %x " 2510 "da_idx_timeout: %x " 2511 "msdu_limit_error: %x " 2512 "da_is_valid: %x " 2513 "da_is_mcbc: %x " 2514 "sa_is_valid: %x " 2515 "decrypt_status_code: %x " 2516 "rx_bitmap_not_updated: %x " 2517 "reserved_2: %x " 2518 "msdu_done: %x ", 2519 rx_attn->encrypt_required, 2520 rx_attn->directed, 2521 rx_attn->buffer_fragment, 2522 rx_attn->mpdu_length_err, 2523 rx_attn->tkip_mic_err, 2524 rx_attn->decrypt_err, 2525 rx_attn->unencrypted_frame_err, 2526 rx_attn->fcs_err, 2527 rx_attn->flow_idx_timeout, 2528 rx_attn->flow_idx_invalid, 2529 rx_attn->wifi_parser_error, 2530 rx_attn->amsdu_parser_error, 2531 rx_attn->sa_idx_timeout, 2532 rx_attn->da_idx_timeout, 2533 rx_attn->msdu_limit_error, 2534 rx_attn->da_is_valid, 2535 rx_attn->da_is_mcbc, 2536 rx_attn->sa_is_valid, 2537 rx_attn->decrypt_status_code, 2538 rx_attn->rx_bitmap_not_updated, 2539 rx_attn->reserved_2, 2540 rx_attn->msdu_done); 2541 } 2542 2543 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2544 uint8_t dbg_level, 2545 struct hal_soc *hal) 2546 { 2547 2548 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2549 } 2550 /** 2551 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2552 * human readable format. 2553 * @ msdu_end: pointer the msdu_end TLV in pkt. 2554 * @ dbg_level: log level. 2555 * 2556 * Return: void 2557 */ 2558 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2559 struct rx_msdu_end *msdu_end, 2560 uint8_t dbg_level) 2561 { 2562 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2563 } 2564 2565 /** 2566 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2567 * human readable format. 2568 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2569 * @ dbg_level: log level. 2570 * 2571 * Return: void 2572 */ 2573 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2574 uint8_t dbg_level) 2575 { 2576 hal_verbose_debug( 2577 "rx_mpdu_end tlv - " 2578 "rxpcu_mpdu_filter_in_category: %x " 2579 "sw_frame_group_id: %x " 2580 "phy_ppdu_id: %x " 2581 "unsup_ktype_short_frame: %x " 2582 "rx_in_tx_decrypt_byp: %x " 2583 "overflow_err: %x " 2584 "mpdu_length_err: %x " 2585 "tkip_mic_err: %x " 2586 "decrypt_err: %x " 2587 "unencrypted_frame_err: %x " 2588 "pn_fields_contain_valid_info: %x " 2589 "fcs_err: %x " 2590 "msdu_length_err: %x " 2591 "rxdma0_destination_ring: %x " 2592 "rxdma1_destination_ring: %x " 2593 "decrypt_status_code: %x " 2594 "rx_bitmap_not_updated: %x ", 2595 mpdu_end->rxpcu_mpdu_filter_in_category, 2596 mpdu_end->sw_frame_group_id, 2597 mpdu_end->phy_ppdu_id, 2598 mpdu_end->unsup_ktype_short_frame, 2599 mpdu_end->rx_in_tx_decrypt_byp, 2600 mpdu_end->overflow_err, 2601 mpdu_end->mpdu_length_err, 2602 mpdu_end->tkip_mic_err, 2603 mpdu_end->decrypt_err, 2604 mpdu_end->unencrypted_frame_err, 2605 mpdu_end->pn_fields_contain_valid_info, 2606 mpdu_end->fcs_err, 2607 mpdu_end->msdu_length_err, 2608 mpdu_end->rxdma0_destination_ring, 2609 mpdu_end->rxdma1_destination_ring, 2610 mpdu_end->decrypt_status_code, 2611 mpdu_end->rx_bitmap_not_updated); 2612 } 2613 2614 #ifdef NO_RX_PKT_HDR_TLV 2615 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2616 uint8_t dbg_level) 2617 { 2618 } 2619 #else 2620 /** 2621 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2622 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2623 * @ dbg_level: log level. 2624 * 2625 * Return: void 2626 */ 2627 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2628 uint8_t dbg_level) 2629 { 2630 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2631 2632 hal_verbose_debug( 2633 "\n---------------\n" 2634 "rx_pkt_hdr_tlv \n" 2635 "---------------\n" 2636 "phy_ppdu_id %d ", 2637 pkt_hdr_tlv->phy_ppdu_id); 2638 2639 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2640 } 2641 #endif 2642 2643 /** 2644 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2645 * structure 2646 * @hal_ring: pointer to hal_srng structure 2647 * 2648 * Return: ring_id 2649 */ 2650 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 2651 { 2652 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 2653 } 2654 2655 /* Rx MSDU link pointer info */ 2656 struct hal_rx_msdu_link_ptr_info { 2657 struct rx_msdu_link msdu_link; 2658 struct hal_buf_info msdu_link_buf_info; 2659 }; 2660 2661 /** 2662 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2663 * 2664 * @nbuf: Pointer to data buffer field 2665 * Returns: pointer to rx_pkt_tlvs 2666 */ 2667 static inline 2668 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2669 { 2670 return (struct rx_pkt_tlvs *)rx_buf_start; 2671 } 2672 2673 /** 2674 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2675 * 2676 * @pkt_tlvs: Pointer to pkt_tlvs 2677 * Returns: pointer to rx_mpdu_info structure 2678 */ 2679 static inline 2680 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2681 { 2682 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2683 } 2684 2685 #define DOT11_SEQ_FRAG_MASK 0x000f 2686 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2687 2688 /** 2689 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2690 * 2691 * @nbuf: Network buffer 2692 * Returns: rx fragment number 2693 */ 2694 static inline 2695 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 2696 uint8_t *buf) 2697 { 2698 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 2699 } 2700 2701 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2702 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2703 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2704 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2705 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2706 /** 2707 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2708 * 2709 * @nbuf: Network buffer 2710 * Returns: rx more fragment bit 2711 */ 2712 static inline 2713 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2714 { 2715 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2716 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2717 uint16_t frame_ctrl = 0; 2718 2719 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2720 DOT11_FC1_MORE_FRAG_OFFSET; 2721 2722 /* more fragment bit if at offset bit 4 */ 2723 return frame_ctrl; 2724 } 2725 2726 /** 2727 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2728 * 2729 * @nbuf: Network buffer 2730 * Returns: rx more fragment bit 2731 * 2732 */ 2733 static inline 2734 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2735 { 2736 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2737 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2738 uint16_t frame_ctrl = 0; 2739 2740 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2741 2742 return frame_ctrl; 2743 } 2744 2745 /* 2746 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2747 * 2748 * @nbuf: Network buffer 2749 * Returns: flag to indicate whether the nbuf has MC/BC address 2750 */ 2751 static inline 2752 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2753 { 2754 uint8 *buf = qdf_nbuf_data(nbuf); 2755 2756 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2757 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2758 2759 return rx_attn->mcast_bcast; 2760 } 2761 2762 /* 2763 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2764 * @hal_soc_hdl: hal soc handle 2765 * @nbuf: Network buffer 2766 * 2767 * Return: value of sequence control valid field 2768 */ 2769 static inline 2770 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 2771 uint8_t *buf) 2772 { 2773 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2774 2775 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 2776 } 2777 2778 /* 2779 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2780 * @hal_soc_hdl: hal soc handle 2781 * @nbuf: Network buffer 2782 * 2783 * Returns: value of frame control valid field 2784 */ 2785 static inline 2786 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 2787 uint8_t *buf) 2788 { 2789 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2790 2791 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 2792 } 2793 2794 /** 2795 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2796 * @hal_soc_hdl: hal soc handle 2797 * @nbuf: Network buffer 2798 * Returns: value of mpdu 4th address valid field 2799 */ 2800 static inline 2801 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 2802 uint8_t *buf) 2803 { 2804 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2805 2806 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 2807 } 2808 2809 /* 2810 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2811 * 2812 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2813 * Returns: None 2814 */ 2815 static inline 2816 void hal_rx_clear_mpdu_desc_info( 2817 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2818 { 2819 qdf_mem_zero(rx_mpdu_desc_info, 2820 sizeof(*rx_mpdu_desc_info)); 2821 } 2822 2823 /* 2824 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2825 * 2826 * @msdu_link_ptr: HAL view of msdu link ptr 2827 * @size: number of msdu link pointers 2828 * Returns: None 2829 */ 2830 static inline 2831 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2832 int size) 2833 { 2834 qdf_mem_zero(msdu_link_ptr, 2835 (sizeof(*msdu_link_ptr) * size)); 2836 } 2837 2838 /* 2839 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2840 * @msdu_link_ptr: msdu link pointer 2841 * @mpdu_desc_info: mpdu descriptor info 2842 * 2843 * Build a list of msdus using msdu link pointer. If the 2844 * number of msdus are more, chain them together 2845 * 2846 * Returns: Number of processed msdus 2847 */ 2848 static inline 2849 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2850 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2851 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2852 { 2853 int j; 2854 struct rx_msdu_link *msdu_link_ptr = 2855 &msdu_link_ptr_info->msdu_link; 2856 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2857 struct rx_msdu_details *msdu_details = 2858 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2859 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2860 struct rx_msdu_desc_info *msdu_desc_info; 2861 uint8_t fragno, more_frag; 2862 uint8_t *rx_desc_info; 2863 struct hal_rx_msdu_list msdu_list; 2864 2865 for (j = 0; j < num_msdus; j++) { 2866 msdu_desc_info = 2867 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2868 hal_soc); 2869 msdu_list.msdu_info[j].msdu_flags = 2870 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2871 msdu_list.msdu_info[j].msdu_len = 2872 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2873 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2874 &msdu_details[j].buffer_addr_info_details); 2875 } 2876 2877 /* Chain msdu links together */ 2878 if (prev_msdu_link_ptr) { 2879 /* 31-0 bits of the physical address */ 2880 prev_msdu_link_ptr-> 2881 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2882 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2883 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2884 /* 39-32 bits of the physical address */ 2885 prev_msdu_link_ptr-> 2886 next_msdu_link_desc_addr_info.buffer_addr_39_32 2887 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2888 >> 32) & 2889 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2890 prev_msdu_link_ptr-> 2891 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2892 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2893 } 2894 2895 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2896 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2897 /* mark first and last MSDUs */ 2898 rx_desc_info = qdf_nbuf_data(msdu); 2899 fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info); 2900 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2901 2902 /* TODO: create skb->fragslist[] */ 2903 2904 if (more_frag == 0) { 2905 msdu_list.msdu_info[num_msdus].msdu_flags |= 2906 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2907 } else if (fragno == 1) { 2908 msdu_list.msdu_info[num_msdus].msdu_flags |= 2909 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2910 2911 msdu_list.msdu_info[num_msdus].msdu_flags |= 2912 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2913 } 2914 2915 num_msdus++; 2916 2917 /* Number of MSDUs per mpdu descriptor is updated */ 2918 mpdu_desc_info->msdu_count += num_msdus; 2919 } else { 2920 num_msdus = 0; 2921 prev_msdu_link_ptr = msdu_link_ptr; 2922 } 2923 2924 return num_msdus; 2925 } 2926 2927 /* 2928 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2929 * 2930 * @ring_desc: HAL view of ring descriptor 2931 * @mpdu_des_info: saved mpdu desc info 2932 * @msdu_link_ptr: saved msdu link ptr 2933 * 2934 * API used explicitly for rx defrag to update ring desc with 2935 * mpdu desc info and msdu link ptr before reinjecting the 2936 * packet back to REO 2937 * 2938 * Returns: None 2939 */ 2940 static inline 2941 void hal_rx_defrag_update_src_ring_desc( 2942 hal_ring_desc_t ring_desc, 2943 void *saved_mpdu_desc_info, 2944 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 2945 { 2946 struct reo_entrance_ring *reo_ent_ring; 2947 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 2948 struct hal_buf_info buf_info; 2949 2950 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 2951 reo_ring_mpdu_desc_info = &reo_ent_ring-> 2952 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 2953 2954 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 2955 sizeof(*reo_ring_mpdu_desc_info)); 2956 2957 /* 2958 * TODO: Check for additional fields that need configuration in 2959 * reo_ring_mpdu_desc_info 2960 */ 2961 2962 /* Update msdu_link_ptr in the reo entrance ring */ 2963 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 2964 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 2965 buf_info.sw_cookie = 2966 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 2967 } 2968 2969 /* 2970 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 2971 * 2972 * @msdu_link_desc_va: msdu link descriptor handle 2973 * @msdu_link_ptr_info: HAL view of msdu link pointer info 2974 * 2975 * API used to save msdu link information along with physical 2976 * address. The API also copues the sw cookie. 2977 * 2978 * Returns: None 2979 */ 2980 static inline 2981 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 2982 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2983 struct hal_buf_info *hbi) 2984 { 2985 struct rx_msdu_link *msdu_link_ptr = 2986 (struct rx_msdu_link *)msdu_link_desc_va; 2987 2988 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 2989 sizeof(struct rx_msdu_link)); 2990 2991 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 2992 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 2993 } 2994 2995 /* 2996 * hal_rx_get_desc_len(): Returns rx descriptor length 2997 * 2998 * Returns the size of rx_pkt_tlvs which follows the 2999 * data in the nbuf 3000 * 3001 * Returns: Length of rx descriptor 3002 */ 3003 static inline 3004 uint16_t hal_rx_get_desc_len(void) 3005 { 3006 return SIZE_OF_DATA_RX_TLV; 3007 } 3008 3009 /* 3010 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 3011 * reo_entrance_ring descriptor 3012 * 3013 * @reo_ent_desc: reo_entrance_ring descriptor 3014 * Returns: value of rxdma_push_reason 3015 */ 3016 static inline 3017 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 3018 { 3019 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3020 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 3021 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 3022 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 3023 } 3024 3025 /** 3026 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 3027 * reo_entrance_ring descriptor 3028 * @reo_ent_desc: reo_entrance_ring descriptor 3029 * Return: value of rxdma_error_code 3030 */ 3031 static inline 3032 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 3033 { 3034 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3035 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 3036 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 3037 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 3038 } 3039 3040 /** 3041 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 3042 * save it to hal_wbm_err_desc_info structure passed by caller 3043 * @wbm_desc: wbm ring descriptor 3044 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3045 * Return: void 3046 */ 3047 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 3048 struct hal_wbm_err_desc_info *wbm_er_info, 3049 hal_soc_handle_t hal_soc_hdl) 3050 { 3051 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3052 3053 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 3054 } 3055 3056 /** 3057 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 3058 * the reserved bytes of rx_tlv_hdr 3059 * @buf: start of rx_tlv_hdr 3060 * @wbm_er_info: hal_wbm_err_desc_info structure 3061 * Return: void 3062 */ 3063 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 3064 struct hal_wbm_err_desc_info *wbm_er_info) 3065 { 3066 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3067 3068 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 3069 sizeof(struct hal_wbm_err_desc_info)); 3070 } 3071 3072 /** 3073 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 3074 * the reserved bytes of rx_tlv_hdr. 3075 * @buf: start of rx_tlv_hdr 3076 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3077 * Return: void 3078 */ 3079 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 3080 struct hal_wbm_err_desc_info *wbm_er_info) 3081 { 3082 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3083 3084 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 3085 sizeof(struct hal_wbm_err_desc_info)); 3086 } 3087 3088 /** 3089 * hal_rx_mon_dest_set_buffer_info_to_tlv(): Save the mon dest frame info 3090 * into the reserved bytes of rx_tlv_hdr. 3091 * @buf: start of rx_tlv_hdr 3092 * @buf_info: hal_rx_mon_dest_buf_info structure 3093 * 3094 * Return: void 3095 */ 3096 static inline 3097 void hal_rx_mon_dest_set_buffer_info_to_tlv(uint8_t *buf, 3098 struct hal_rx_mon_dest_buf_info *buf_info) 3099 { 3100 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3101 3102 qdf_mem_copy(pkt_tlvs->rx_padding0, buf_info, 3103 sizeof(struct hal_rx_mon_dest_buf_info)); 3104 } 3105 3106 /** 3107 * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info 3108 * from the reserved bytes of rx_tlv_hdr. 3109 * @buf: start of rx_tlv_hdr 3110 * @buf_info: hal_rx_mon_dest_buf_info structure 3111 * 3112 * Return: void 3113 */ 3114 static inline 3115 void hal_rx_mon_dest_get_buffer_info_from_tlv(uint8_t *buf, 3116 struct hal_rx_mon_dest_buf_info *buf_info) 3117 { 3118 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3119 3120 qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0, 3121 sizeof(struct hal_rx_mon_dest_buf_info)); 3122 } 3123 3124 /** 3125 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 3126 * bit from wbm release ring descriptor 3127 * @wbm_desc: wbm ring descriptor 3128 * Return: uint8_t 3129 */ 3130 static inline 3131 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 3132 void *wbm_desc) 3133 { 3134 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3135 3136 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 3137 } 3138 3139 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 3140 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 3141 RX_MSDU_START_5_NSS_OFFSET)), \ 3142 RX_MSDU_START_5_NSS_MASK, \ 3143 RX_MSDU_START_5_NSS_LSB)) 3144 3145 /** 3146 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 3147 * 3148 * @ hal_soc: HAL version of the SOC pointer 3149 * @ hw_desc_addr: Start address of Rx HW TLVs 3150 * @ rs: Status for monitor mode 3151 * 3152 * Return: void 3153 */ 3154 static inline 3155 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 3156 void *hw_desc_addr, 3157 struct mon_rx_status *rs) 3158 { 3159 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3160 3161 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 3162 } 3163 3164 /* 3165 * hal_rx_get_tlv(): API to get the tlv 3166 * 3167 * @hal_soc: HAL version of the SOC pointer 3168 * @rx_tlv: TLV data extracted from the rx packet 3169 * Return: uint8_t 3170 */ 3171 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 3172 { 3173 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 3174 } 3175 3176 /* 3177 * hal_rx_msdu_start_nss_get(): API to get the NSS 3178 * Interval from rx_msdu_start 3179 * 3180 * @hal_soc: HAL version of the SOC pointer 3181 * @buf: pointer to the start of RX PKT TLV header 3182 * Return: uint32_t(nss) 3183 */ 3184 static inline 3185 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3186 { 3187 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3188 3189 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3190 } 3191 3192 /** 3193 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3194 * human readable format. 3195 * @ msdu_start: pointer the msdu_start TLV in pkt. 3196 * @ dbg_level: log level. 3197 * 3198 * Return: void 3199 */ 3200 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3201 struct rx_msdu_start *msdu_start, 3202 uint8_t dbg_level) 3203 { 3204 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3205 } 3206 3207 /** 3208 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3209 * info details 3210 * 3211 * @ buf - Pointer to buffer containing rx pkt tlvs. 3212 * 3213 * 3214 */ 3215 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 3216 uint8_t *buf) 3217 { 3218 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3219 3220 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3221 } 3222 3223 /* 3224 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3225 * Interval from rx_msdu_start 3226 * 3227 * @buf: pointer to the start of RX PKT TLV header 3228 * Return: uint32_t(reception_type) 3229 */ 3230 static inline 3231 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 3232 uint8_t *buf) 3233 { 3234 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3235 3236 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3237 } 3238 3239 /** 3240 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3241 * RX TLVs 3242 * @ buf: pointer the pkt buffer. 3243 * @ dbg_level: log level. 3244 * 3245 * Return: void 3246 */ 3247 static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 3248 uint8_t *buf, uint8_t dbg_level) 3249 { 3250 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3251 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3252 struct rx_mpdu_start *mpdu_start = 3253 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3254 struct rx_msdu_start *msdu_start = 3255 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3256 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3257 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3258 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3259 3260 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3261 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3262 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3263 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3264 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3265 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3266 } 3267 3268 3269 /** 3270 * hal_reo_status_get_header_generic - Process reo desc info 3271 * @d - Pointer to reo descriptior 3272 * @b - tlv type info 3273 * @h - Pointer to hal_reo_status_header where info to be stored 3274 * @hal- pointer to hal_soc structure 3275 * Return - none. 3276 * 3277 */ 3278 static inline 3279 void hal_reo_status_get_header(uint32_t *d, int b, 3280 void *h, struct hal_soc *hal_soc) 3281 { 3282 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3283 } 3284 3285 /** 3286 * hal_rx_desc_is_first_msdu() - Check if first msdu 3287 * 3288 * @hal_soc_hdl: hal_soc handle 3289 * @hw_desc_addr: hardware descriptor address 3290 * 3291 * Return: 0 - success/ non-zero failure 3292 */ 3293 static inline 3294 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 3295 void *hw_desc_addr) 3296 { 3297 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3298 3299 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 3300 } 3301 3302 static inline 3303 uint32_t 3304 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3305 struct rx_msdu_start *rx_msdu_start; 3306 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3307 3308 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3309 3310 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3311 } 3312 3313 #ifdef NO_RX_PKT_HDR_TLV 3314 static inline 3315 uint8_t * 3316 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3317 uint8_t *rx_pkt_hdr; 3318 struct rx_mon_pkt_tlvs *rx_desc = 3319 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 3320 3321 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3322 3323 return rx_pkt_hdr; 3324 } 3325 #else 3326 static inline 3327 uint8_t * 3328 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3329 uint8_t *rx_pkt_hdr; 3330 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3331 3332 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3333 3334 return rx_pkt_hdr; 3335 } 3336 #endif 3337 3338 static inline 3339 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3340 uint8_t *rx_tlv_hdr) 3341 { 3342 uint8_t decap_format; 3343 3344 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 3345 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3346 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3347 return true; 3348 } 3349 3350 return false; 3351 } 3352 3353 /** 3354 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 3355 * from rx_msdu_end TLV 3356 * @buf: pointer to the start of RX PKT TLV headers 3357 * 3358 * Return: fse metadata value from MSDU END TLV 3359 */ 3360 static inline uint32_t 3361 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 3362 uint8_t *buf) 3363 { 3364 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3365 3366 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 3367 } 3368 3369 /** 3370 * hal_rx_msdu_flow_idx_get: API to get flow index 3371 * from rx_msdu_end TLV 3372 * @buf: pointer to the start of RX PKT TLV headers 3373 * 3374 * Return: flow index value from MSDU END TLV 3375 */ 3376 static inline uint32_t 3377 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 3378 uint8_t *buf) 3379 { 3380 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3381 3382 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 3383 } 3384 3385 /** 3386 * hal_rx_msdu_get_reo_destination_indication: API to get reo 3387 * destination index from rx_msdu_end TLV 3388 * @buf: pointer to the start of RX PKT TLV headers 3389 * @reo_destination_indication: pointer to return value of 3390 * reo_destination_indication 3391 * 3392 * Return: reo_destination_indication value from MSDU END TLV 3393 */ 3394 static inline void 3395 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 3396 uint8_t *buf, 3397 uint32_t *reo_destination_indication) 3398 { 3399 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3400 3401 if ((!hal_soc) || (!hal_soc->ops)) { 3402 hal_err("hal handle is NULL"); 3403 QDF_BUG(0); 3404 return; 3405 } 3406 3407 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 3408 reo_destination_indication); 3409 } 3410 3411 /** 3412 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 3413 * from rx_msdu_end TLV 3414 * @buf: pointer to the start of RX PKT TLV headers 3415 * 3416 * Return: flow index timeout value from MSDU END TLV 3417 */ 3418 static inline bool 3419 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 3420 uint8_t *buf) 3421 { 3422 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3423 3424 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 3425 } 3426 3427 /** 3428 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 3429 * from rx_msdu_end TLV 3430 * @buf: pointer to the start of RX PKT TLV headers 3431 * 3432 * Return: flow index invalid value from MSDU END TLV 3433 */ 3434 static inline bool 3435 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 3436 uint8_t *buf) 3437 { 3438 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3439 3440 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 3441 } 3442 3443 /** 3444 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 3445 * @hal_soc_hdl: hal_soc handle 3446 * @rx_tlv_hdr: Rx_tlv_hdr 3447 * @rxdma_dst_ring_desc: Rx HW descriptor 3448 * 3449 * Return: ppdu id 3450 */ 3451 static inline 3452 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 3453 void *rx_tlv_hdr, 3454 void *rxdma_dst_ring_desc) 3455 { 3456 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3457 3458 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 3459 rxdma_dst_ring_desc); 3460 } 3461 3462 /** 3463 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 3464 * @hal_soc_hdl: hal_soc handle 3465 * @buf: rx tlv address 3466 * 3467 * Return: sw peer id 3468 */ 3469 static inline 3470 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 3471 uint8_t *buf) 3472 { 3473 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3474 3475 if ((!hal_soc) || (!hal_soc->ops)) { 3476 hal_err("hal handle is NULL"); 3477 QDF_BUG(0); 3478 return QDF_STATUS_E_INVAL; 3479 } 3480 3481 if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get) 3482 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 3483 3484 return QDF_STATUS_E_INVAL; 3485 } 3486 3487 static inline 3488 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 3489 void *link_desc_addr) 3490 { 3491 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3492 3493 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 3494 } 3495 3496 static inline 3497 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 3498 void *msdu_addr) 3499 { 3500 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3501 3502 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 3503 } 3504 3505 static inline 3506 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3507 void *hw_addr) 3508 { 3509 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3510 3511 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 3512 } 3513 3514 static inline 3515 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3516 void *hw_addr) 3517 { 3518 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3519 3520 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 3521 } 3522 3523 static inline 3524 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 3525 uint8_t *buf) 3526 { 3527 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3528 3529 return hal_soc->ops->hal_rx_get_fc_valid(buf); 3530 } 3531 3532 static inline 3533 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3534 { 3535 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3536 3537 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 3538 } 3539 3540 static inline 3541 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 3542 uint8_t *buf) 3543 { 3544 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3545 3546 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 3547 } 3548 3549 static inline 3550 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 3551 uint8_t *buf) 3552 { 3553 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3554 3555 return hal_soc->ops->hal_rx_get_filter_category(buf); 3556 } 3557 3558 static inline 3559 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 3560 uint8_t *buf) 3561 { 3562 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3563 3564 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 3565 } 3566 3567 /** 3568 * hal_reo_config(): Set reo config parameters 3569 * @soc: hal soc handle 3570 * @reg_val: value to be set 3571 * @reo_params: reo parameters 3572 * 3573 * Return: void 3574 */ 3575 static inline 3576 void hal_reo_config(struct hal_soc *hal_soc, 3577 uint32_t reg_val, 3578 struct hal_reo_params *reo_params) 3579 { 3580 hal_soc->ops->hal_reo_config(hal_soc, 3581 reg_val, 3582 reo_params); 3583 } 3584 3585 /** 3586 * hal_rx_msdu_get_flow_params: API to get flow index, 3587 * flow index invalid and flow index timeout from rx_msdu_end TLV 3588 * @buf: pointer to the start of RX PKT TLV headers 3589 * @flow_invalid: pointer to return value of flow_idx_valid 3590 * @flow_timeout: pointer to return value of flow_idx_timeout 3591 * @flow_index: pointer to return value of flow_idx 3592 * 3593 * Return: none 3594 */ 3595 static inline void 3596 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 3597 uint8_t *buf, 3598 bool *flow_invalid, 3599 bool *flow_timeout, 3600 uint32_t *flow_index) 3601 { 3602 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3603 3604 if ((!hal_soc) || (!hal_soc->ops)) { 3605 hal_err("hal handle is NULL"); 3606 QDF_BUG(0); 3607 return; 3608 } 3609 3610 if (hal_soc->ops->hal_rx_msdu_get_flow_params) 3611 hal_soc->ops-> 3612 hal_rx_msdu_get_flow_params(buf, 3613 flow_invalid, 3614 flow_timeout, 3615 flow_index); 3616 } 3617 3618 static inline 3619 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 3620 uint8_t *buf) 3621 { 3622 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3623 3624 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 3625 } 3626 3627 static inline 3628 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 3629 uint8_t *buf) 3630 { 3631 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3632 3633 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 3634 } 3635 3636 static inline void 3637 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 3638 void *rx_tlv, 3639 void *ppdu_info) 3640 { 3641 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3642 3643 if (hal_soc->ops->hal_rx_get_bb_info) 3644 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 3645 } 3646 3647 static inline void 3648 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 3649 void *rx_tlv, 3650 void *ppdu_info) 3651 { 3652 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3653 3654 if (hal_soc->ops->hal_rx_get_rtt_info) 3655 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 3656 } 3657 3658 /** 3659 * hal_rx_msdu_metadata_get(): API to get the 3660 * fast path information from rx_msdu_end TLV 3661 * 3662 * @ hal_soc_hdl: DP soc handle 3663 * @ buf: pointer to the start of RX PKT TLV headers 3664 * @ msdu_metadata: Structure to hold msdu end information 3665 * Return: none 3666 */ 3667 static inline void 3668 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 3669 struct hal_rx_msdu_metadata *msdu_md) 3670 { 3671 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3672 3673 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 3674 } 3675 3676 /** 3677 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 3678 * from rx_msdu_end TLV 3679 * @buf: pointer to the start of RX PKT TLV headers 3680 * 3681 * Return: cumulative_l4_checksum 3682 */ 3683 static inline uint16_t 3684 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 3685 uint8_t *buf) 3686 { 3687 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3688 3689 if (!hal_soc || !hal_soc->ops) { 3690 hal_err("hal handle is NULL"); 3691 QDF_BUG(0); 3692 return 0; 3693 } 3694 3695 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 3696 return 0; 3697 3698 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 3699 } 3700 3701 /** 3702 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 3703 * from rx_msdu_end TLV 3704 * @buf: pointer to the start of RX PKT TLV headers 3705 * 3706 * Return: cumulative_ip_length 3707 */ 3708 static inline uint16_t 3709 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 3710 uint8_t *buf) 3711 { 3712 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3713 3714 if (!hal_soc || !hal_soc->ops) { 3715 hal_err("hal handle is NULL"); 3716 QDF_BUG(0); 3717 return 0; 3718 } 3719 3720 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 3721 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 3722 3723 return 0; 3724 } 3725 3726 /** 3727 * hal_rx_get_udp_proto: API to get UDP proto field 3728 * from rx_msdu_start TLV 3729 * @buf: pointer to the start of RX PKT TLV headers 3730 * 3731 * Return: UDP proto field value 3732 */ 3733 static inline bool 3734 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3735 { 3736 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3737 3738 if (!hal_soc || !hal_soc->ops) { 3739 hal_err("hal handle is NULL"); 3740 QDF_BUG(0); 3741 return 0; 3742 } 3743 3744 if (hal_soc->ops->hal_rx_get_udp_proto) 3745 return hal_soc->ops->hal_rx_get_udp_proto(buf); 3746 3747 return 0; 3748 } 3749 3750 /** 3751 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 3752 * from rx_msdu_end TLV 3753 * @buf: pointer to the start of RX PKT TLV headers 3754 * 3755 * Return: flow_agg_continuation bit field value 3756 */ 3757 static inline bool 3758 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 3759 uint8_t *buf) 3760 { 3761 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3762 3763 if (!hal_soc || !hal_soc->ops) { 3764 hal_err("hal handle is NULL"); 3765 QDF_BUG(0); 3766 return 0; 3767 } 3768 3769 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 3770 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 3771 3772 return 0; 3773 } 3774 3775 /** 3776 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 3777 * rx_msdu_end TLV 3778 * @buf: pointer to the start of RX PKT TLV headers 3779 * 3780 * Return: flow_agg count value 3781 */ 3782 static inline uint8_t 3783 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 3784 uint8_t *buf) 3785 { 3786 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3787 3788 if (!hal_soc || !hal_soc->ops) { 3789 hal_err("hal handle is NULL"); 3790 QDF_BUG(0); 3791 return 0; 3792 } 3793 3794 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 3795 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 3796 3797 return 0; 3798 } 3799 3800 /** 3801 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 3802 * @buf: pointer to the start of RX PKT TLV headers 3803 * 3804 * Return: fisa flow_agg timeout bit value 3805 */ 3806 static inline bool 3807 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3808 { 3809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3810 3811 if (!hal_soc || !hal_soc->ops) { 3812 hal_err("hal handle is NULL"); 3813 QDF_BUG(0); 3814 return 0; 3815 } 3816 3817 if (hal_soc->ops->hal_rx_get_fisa_timeout) 3818 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 3819 3820 return 0; 3821 } 3822 3823 /** 3824 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 3825 * tag is valid 3826 * 3827 * @hal_soc_hdl: HAL SOC handle 3828 * @rx_tlv_hdr: start address of rx_pkt_tlvs 3829 * 3830 * Return: true if RX_MPDU_START tlv tag is valid, else false 3831 */ 3832 3833 static inline uint8_t 3834 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 3835 void *rx_tlv_hdr) 3836 { 3837 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3838 3839 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 3840 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 3841 3842 return 0; 3843 } 3844 3845 /** 3846 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 3847 * <struct buffer_addr_info> structure 3848 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 3849 * @buf_info: structure to return the buffer information including 3850 * paddr/cookie 3851 * 3852 * return: None 3853 */ 3854 static inline 3855 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 3856 struct hal_buf_info *buf_info) 3857 { 3858 buf_info->paddr = 3859 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 3860 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 3861 3862 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 3863 } 3864 3865 /** 3866 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 3867 * buffer addr info 3868 * @link_desc_va: pointer to current msdu link Desc 3869 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 3870 * 3871 * return: None 3872 */ 3873 static inline 3874 void hal_rx_get_next_msdu_link_desc_buf_addr_info( 3875 void *link_desc_va, 3876 struct buffer_addr_info *next_addr_info) 3877 { 3878 struct rx_msdu_link *msdu_link = link_desc_va; 3879 3880 if (!msdu_link) { 3881 qdf_mem_zero(next_addr_info, 3882 sizeof(struct buffer_addr_info)); 3883 return; 3884 } 3885 3886 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 3887 } 3888 3889 /** 3890 * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc 3891 * buffer addr info 3892 * @link_desc_va: pointer to current msdu link Desc 3893 * 3894 * return: None 3895 */ 3896 static inline 3897 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 3898 { 3899 struct rx_msdu_link *msdu_link = link_desc_va; 3900 3901 if (msdu_link) 3902 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 3903 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 3904 } 3905 3906 /** 3907 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 3908 * 3909 * @buf_addr_info: pointer to buf_addr_info structure 3910 * 3911 * return: true: has valid paddr, false: not. 3912 */ 3913 static inline 3914 bool hal_rx_is_buf_addr_info_valid( 3915 struct buffer_addr_info *buf_addr_info) 3916 { 3917 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 3918 false : true; 3919 } 3920 3921 /** 3922 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 3923 * rx_pkt_tlvs structure 3924 * 3925 * @hal_soc_hdl: HAL SOC handle 3926 * return: msdu_end_tlv offset value 3927 */ 3928 static inline 3929 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 3930 { 3931 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3932 3933 if (!hal_soc || !hal_soc->ops) { 3934 hal_err("hal handle is NULL"); 3935 QDF_BUG(0); 3936 return 0; 3937 } 3938 3939 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 3940 } 3941 3942 /** 3943 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 3944 * rx_pkt_tlvs structure 3945 * 3946 * @hal_soc_hdl: HAL SOC handle 3947 * return: msdu_start_tlv offset value 3948 */ 3949 static inline 3950 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 3951 { 3952 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3953 3954 if (!hal_soc || !hal_soc->ops) { 3955 hal_err("hal handle is NULL"); 3956 QDF_BUG(0); 3957 return 0; 3958 } 3959 3960 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 3961 } 3962 3963 /** 3964 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 3965 * rx_pkt_tlvs structure 3966 * 3967 * @hal_soc_hdl: HAL SOC handle 3968 * return: mpdu_start_tlv offset value 3969 */ 3970 static inline 3971 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 3972 { 3973 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3974 3975 if (!hal_soc || !hal_soc->ops) { 3976 hal_err("hal handle is NULL"); 3977 QDF_BUG(0); 3978 return 0; 3979 } 3980 3981 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 3982 } 3983 3984 /** 3985 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 3986 * rx_pkt_tlvs structure 3987 * 3988 * @hal_soc_hdl: HAL SOC handle 3989 * return: mpdu_end_tlv offset value 3990 */ 3991 static inline 3992 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 3993 { 3994 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3995 3996 if (!hal_soc || !hal_soc->ops) { 3997 hal_err("hal handle is NULL"); 3998 QDF_BUG(0); 3999 return 0; 4000 } 4001 4002 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 4003 } 4004 4005 /** 4006 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 4007 * rx_pkt_tlvs structure 4008 * 4009 * @hal_soc_hdl: HAL SOC handle 4010 * return: attn_tlv offset value 4011 */ 4012 static inline 4013 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 4014 { 4015 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 4016 4017 if (!hal_soc || !hal_soc->ops) { 4018 hal_err("hal handle is NULL"); 4019 QDF_BUG(0); 4020 return 0; 4021 } 4022 4023 return hal_soc->ops->hal_rx_attn_offset_get(); 4024 } 4025 #endif /* _HAL_RX_H */ 4026