1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_RX_H_ 21 #define _HAL_RX_H_ 22 23 #include <hal_api.h> 24 #include "hal_rx_hw_defines.h" 25 #include "hal_hw_headers.h" 26 27 /************************************* 28 * Ring desc offset/shift/masks 29 *************************************/ 30 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 31 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 32 #define HAL_RX_LSB(block, field) block##_##field##_LSB 33 #define HAL_RX_MASK(block, field) block##_##field##_MASK 34 #define HAL_RX_TLV_L3_TYPE_INVALID 0xFFFF 35 36 #define HAL_RX_GET(_ptr, block, field) \ 37 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 38 HAL_RX_MASK(block, field)) >> \ 39 HAL_RX_LSB(block, field)) 40 41 #define HAL_RX_GET_64(_ptr, block, field) \ 42 (((*((volatile uint64_t *)(_ptr) + \ 43 (HAL_RX_OFFSET(block, field) >> 3))) & \ 44 HAL_RX_MASK(block, field)) >> \ 45 HAL_RX_LSB(block, field)) 46 47 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 48 (*(uint32_t *)(((uint8_t *)_ptr) + \ 49 _wrd ## _ ## _field ## _OFFSET) |= \ 50 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 51 _wrd ## _ ## _field ## _MASK)) 52 53 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 54 #ifndef RX_DATA_BUFFER_SIZE 55 #define RX_DATA_BUFFER_SIZE 2048 56 #endif 57 58 #ifndef RX_MONITOR_BUFFER_SIZE 59 #define RX_MONITOR_BUFFER_SIZE 2048 60 #endif 61 62 #define RXDMA_OPTIMIZATION 63 64 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 65 * including buffer reservation, buffer alignment and skb shared info size. 66 */ 67 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 68 #define RX_MON_STATUS_BUF_ALIGN 128 69 #define RX_MON_STATUS_BUF_RESERVATION 128 70 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 71 (RX_MON_STATUS_BUF_RESERVATION + \ 72 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 73 74 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 75 76 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 77 #define HAL_RX_NON_QOS_TID 16 78 79 enum { 80 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 81 HAL_HW_RX_DECAP_FORMAT_NWIFI, 82 HAL_HW_RX_DECAP_FORMAT_ETH2, 83 HAL_HW_RX_DECAP_FORMAT_8023, 84 }; 85 86 /** 87 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 88 * 89 * @reo_psh_rsn: REO push reason 90 * @reo_err_code: REO Error code 91 * @rxdma_psh_rsn: RXDMA push reason 92 * @rxdma_err_code: RXDMA Error code 93 * @reserved_1: Reserved bits 94 * @wbm_err_src: WBM error source 95 * @pool_id: pool ID, indicates which rxdma pool 96 * @reserved_2: Reserved bits 97 */ 98 struct hal_wbm_err_desc_info { 99 uint16_t reo_psh_rsn:2, 100 reo_err_code:5, 101 rxdma_psh_rsn:2, 102 rxdma_err_code:5, 103 reserved_1:2; 104 uint8_t wbm_err_src:3, 105 pool_id:2, 106 msdu_continued:1, 107 reserved_2:2; 108 }; 109 110 /** 111 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 112 * @first_buffer: First buffer of MSDU 113 * @last_buffer: Last buffer of MSDU 114 * @is_decap_raw: Is RAW Frame 115 * @reserved_1: Reserved 116 * 117 * MSDU with continuation: 118 * ----------------------------------------------------------- 119 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 120 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 121 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 122 * ----------------------------------------------------------- 123 * 124 * Single buffer MSDU: 125 * ------------------ 126 * | first_buffer:1 | 127 * | last_buffer :1 | 128 * | is_decap_raw:1/0 | 129 * ------------------ 130 */ 131 struct hal_rx_mon_dest_buf_info { 132 uint8_t first_buffer:1, 133 last_buffer:1, 134 is_decap_raw:1, 135 mpdu_len_err:1, 136 l2_hdr_pad:2, 137 reserved_1:2; 138 }; 139 140 /** 141 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 142 * 143 * @l3_hdr_pad: l3 header padding 144 * @reserved: Reserved bits 145 * @sa_sw_peer_id: sa sw peer id 146 * @sa_idx: sa index 147 * @da_idx: da index 148 */ 149 struct hal_rx_msdu_metadata { 150 uint32_t l3_hdr_pad:16, 151 sa_sw_peer_id:16; 152 uint32_t sa_idx:16, 153 da_idx:16; 154 }; 155 156 struct hal_proto_params { 157 uint8_t tcp_proto; 158 uint8_t udp_proto; 159 uint8_t ipv6_proto; 160 }; 161 162 /** 163 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 164 * 165 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 166 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 167 */ 168 enum hal_reo_error_status { 169 HAL_REO_ERROR_DETECTED = 0, 170 HAL_REO_ROUTING_INSTRUCTION = 1, 171 }; 172 173 /** 174 * @msdu_flags: [0] first_msdu_in_mpdu 175 * [1] last_msdu_in_mpdu 176 * [2] msdu_continuation - MSDU spread across buffers 177 * [23] sa_is_valid - SA match in peer table 178 * [24] sa_idx_timeout - Timeout while searching for SA match 179 * [25] da_is_valid - Used to identtify intra-bss forwarding 180 * [26] da_is_MCBC 181 * [27] da_idx_timeout - Timeout while searching for DA match 182 * 183 */ 184 struct hal_rx_msdu_desc_info { 185 uint32_t msdu_flags; 186 uint16_t msdu_len; /* 14 bits for length */ 187 }; 188 189 /** 190 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 191 * 192 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 193 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 194 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 195 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 196 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 197 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 198 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 199 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 200 * @ HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 201 */ 202 enum hal_rx_msdu_desc_flags { 203 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 204 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 205 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 206 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 207 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 208 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 209 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 210 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 211 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 212 }; 213 214 /* 215 * @msdu_count: no. of msdus in the MPDU 216 * @mpdu_seq: MPDU sequence number 217 * @mpdu_flags [0] Fragment flag 218 * [1] MPDU_retry_bit 219 * [2] AMPDU flag 220 * [3] raw_ampdu 221 * @peer_meta_data: Upper bits containing peer id, vdev id 222 * @bar_frame: indicates if received frame is a bar frame 223 * @tid: tid value of received MPDU 224 */ 225 struct hal_rx_mpdu_desc_info { 226 uint16_t msdu_count; 227 uint16_t mpdu_seq; /* 12 bits for length */ 228 uint32_t mpdu_flags; 229 uint32_t peer_meta_data; /* sw programmed meta-data:MAC Id & peer Id */ 230 uint16_t bar_frame; 231 uint8_t tid:4, 232 reserved:4; 233 }; 234 235 /** 236 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 237 * 238 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 239 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 240 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 241 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 242 * @ HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field 243 */ 244 enum hal_rx_mpdu_desc_flags { 245 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 246 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 247 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 248 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30), 249 HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31) 250 }; 251 252 /* Return Buffer manager ID */ 253 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 254 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 255 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 256 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 257 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 258 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 259 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 260 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 261 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 262 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 263 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 264 265 #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id) 266 267 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 268 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 269 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 270 271 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 272 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 273 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 274 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 275 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 276 277 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 278 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 279 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 280 281 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 282 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 283 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 284 285 /* 286 * macro to set the LSW of the nbuf data physical address 287 * to the rxdma ring entry 288 */ 289 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 290 ((*(((unsigned int *) buff_addr_info) + \ 291 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 292 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 293 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 294 295 /* 296 * macro to set the LSB of MSW of the nbuf data physical address 297 * to the rxdma ring entry 298 */ 299 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 300 ((*(((unsigned int *) buff_addr_info) + \ 301 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 302 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 303 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 304 305 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 306 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 307 308 /* 309 * macro to get the invalid bit for sw cookie 310 */ 311 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 312 ((*(((unsigned int *)buff_addr_info) + \ 313 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 314 HAL_RX_COOKIE_INVALID_MASK) 315 316 /* 317 * macro to set the invalid bit for sw cookie 318 */ 319 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 320 ((*(((unsigned int *)buff_addr_info) + \ 321 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 322 HAL_RX_COOKIE_INVALID_MASK) 323 324 /* 325 * macro to reset the invalid bit for sw cookie 326 */ 327 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 328 ((*(((unsigned int *)buff_addr_info) + \ 329 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 330 ~HAL_RX_COOKIE_INVALID_MASK) 331 332 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 333 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 334 (((struct reo_destination_ring *) \ 335 reo_desc)->buf_or_link_desc_addr_info))) 336 337 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 338 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 339 (((struct reo_destination_ring *) \ 340 reo_desc)->buf_or_link_desc_addr_info))) 341 342 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 343 344 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 345 ((*(((unsigned int *)buff_addr_info) + \ 346 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 347 HAL_RX_LINK_COOKIE_INVALID_MASK) 348 349 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 350 ((*(((unsigned int *)buff_addr_info) + \ 351 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 352 HAL_RX_LINK_COOKIE_INVALID_MASK) 353 354 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 355 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 356 (((struct reo_destination_ring *) \ 357 reo_desc)->buf_or_link_desc_addr_info))) 358 359 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 360 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 361 (((struct reo_destination_ring *) \ 362 reo_desc)->buf_or_link_desc_addr_info))) 363 #endif 364 365 /* TODO: Convert the following structure fields accesseses to offsets */ 366 367 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 368 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 369 (((struct reo_destination_ring *) \ 370 reo_desc)->buf_or_link_desc_addr_info))) 371 372 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 373 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 374 (((struct reo_destination_ring *) \ 375 reo_desc)->buf_or_link_desc_addr_info))) 376 377 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 378 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 379 (((struct reo_destination_ring *) \ 380 reo_desc)->buf_or_link_desc_addr_info))) 381 382 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 383 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 384 _field, _val) 385 386 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 387 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 388 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 389 390 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 391 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 392 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 393 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 394 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 395 396 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 397 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 398 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 399 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 400 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 401 402 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 403 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 404 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 405 406 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 407 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 408 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 409 410 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 411 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 412 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 413 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 414 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 415 416 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 417 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 418 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 419 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 420 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 421 422 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 423 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 424 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 425 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 426 427 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 428 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 429 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 430 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 431 432 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 433 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 434 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 435 436 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 437 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 438 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 439 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 440 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 441 442 static inline uint32_t 443 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 444 rx_msdu_desc_info_t msdu_desc_info_hdl) 445 { 446 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 447 448 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 449 } 450 451 /* 452 * Structures & Macros to obtain fields from the TLV's in the Rx packet 453 * pre-header. 454 */ 455 456 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 457 void *hw_desc_addr) 458 { 459 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 460 461 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 462 } 463 464 /** 465 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 466 * @hal_soc_hdl: hal soc handle 467 * @desc_addr: ring descriptor 468 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 469 * 470 * Return: None 471 */ 472 static inline void 473 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 474 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 475 { 476 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 477 478 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 479 mpdu_desc_info); 480 } 481 482 #define HAL_RX_NUM_MSDU_DESC 6 483 #define HAL_RX_MAX_SAVED_RING_DESC 16 484 485 /* TODO: rework the structure */ 486 struct hal_rx_msdu_list { 487 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 488 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 489 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 490 /* physical address of the msdu */ 491 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 492 }; 493 494 struct hal_buf_info { 495 uint64_t paddr; 496 uint32_t sw_cookie; 497 uint8_t rbm; 498 }; 499 500 /* This special cookie value will be used to indicate FW allocated buffers 501 * received through RXDMA2SW ring for RXDMA WARs 502 */ 503 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 504 505 /** 506 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 507 * 508 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 509 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 510 * descriptor 511 */ 512 enum hal_rx_reo_buf_type { 513 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 514 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 515 }; 516 517 /** 518 * enum hal_reo_error_code: Error code describing the type of error detected 519 * 520 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 521 * REO_ENTRANCE ring is set to 0 522 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 523 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 524 * having been setup 525 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 526 * Retry bit set: duplicate frame 527 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 528 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 529 * received with 2K jump in SN 530 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 531 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 532 * with SN falling within the OOR window 533 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 534 * OOR window 535 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 536 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 537 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 538 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 539 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 540 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 541 * of the pn_error_detected_flag been set in the REO Queue descriptor 542 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 543 * the queue descriptor(address) being blocked as SW/FW seems to be currently 544 * in the process of making updates to this descriptor 545 */ 546 enum hal_reo_error_code { 547 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 548 HAL_REO_ERR_QUEUE_DESC_INVALID, 549 HAL_REO_ERR_AMPDU_IN_NON_BA, 550 HAL_REO_ERR_NON_BA_DUPLICATE, 551 HAL_REO_ERR_BA_DUPLICATE, 552 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 553 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 554 HAL_REO_ERR_REGULAR_FRAME_OOR, 555 HAL_REO_ERR_BAR_FRAME_OOR, 556 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 557 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 558 HAL_REO_ERR_PN_CHECK_FAILED, 559 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 560 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 561 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 562 HAL_REO_ERR_MAX 563 }; 564 565 /** 566 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 567 * 568 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 569 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 570 * overflow 571 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 572 * incomplete 573 * MPDU from the PHY 574 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 575 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 576 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 577 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 578 * encrypted but wasn’t 579 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 580 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 581 * the max allowed 582 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 583 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 584 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 585 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 586 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 587 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 588 * @ HAL_RXDMA_AMSDU_FRAGMENT : Rx PCU reported A-MSDU 589 * present as well as a fragmented MPDU 590 * @ HAL_RXDMA_MULTICAST_ECHO : RX OLE reported a multicast echo 591 * @ HAL_RXDMA_AMSDU_ADDR_MISMATCH : RX OLE reported AMSDU address mismatch 592 * @ HAL_RXDMA_UNAUTHORIZED_WDS : RX PCU reported unauthorized wds 593 * @ HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS :RX PCU reported group cast AMSDU or WDS 594 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 595 */ 596 enum hal_rxdma_error_code { 597 HAL_RXDMA_ERR_OVERFLOW = 0, 598 HAL_RXDMA_ERR_MPDU_LENGTH, 599 HAL_RXDMA_ERR_FCS, 600 HAL_RXDMA_ERR_DECRYPT, 601 HAL_RXDMA_ERR_TKIP_MIC, 602 HAL_RXDMA_ERR_UNENCRYPTED, 603 HAL_RXDMA_ERR_MSDU_LEN, 604 HAL_RXDMA_ERR_MSDU_LIMIT, 605 HAL_RXDMA_ERR_WIFI_PARSE, 606 HAL_RXDMA_ERR_AMSDU_PARSE, 607 HAL_RXDMA_ERR_SA_TIMEOUT, 608 HAL_RXDMA_ERR_DA_TIMEOUT, 609 HAL_RXDMA_ERR_FLOW_TIMEOUT, 610 HAL_RXDMA_ERR_FLUSH_REQUEST, 611 HAL_RXDMA_AMSDU_FRAGMENT, 612 HAL_RXDMA_MULTICAST_ECHO, 613 HAL_RXDMA_AMSDU_ADDR_MISMATCH, 614 HAL_RXDMA_UNAUTHORIZED_WDS, 615 HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS, 616 HAL_RXDMA_ERR_WAR = 31, 617 HAL_RXDMA_ERR_MAX 618 }; 619 620 /** 621 * HW BM action settings in WBM release ring 622 */ 623 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 624 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 625 626 /** 627 * enum hal_rx_wbm_error_source: Indicates which module initiated the 628 * release of this buffer or descriptor 629 * 630 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 631 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 632 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 633 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 634 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 635 */ 636 enum hal_rx_wbm_error_source { 637 HAL_RX_WBM_ERR_SRC_TQM = 0, 638 HAL_RX_WBM_ERR_SRC_RXDMA, 639 HAL_RX_WBM_ERR_SRC_REO, 640 HAL_RX_WBM_ERR_SRC_FW, 641 HAL_RX_WBM_ERR_SRC_SW, 642 }; 643 644 /** 645 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 646 * released 647 * 648 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 649 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 650 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 651 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 652 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 653 */ 654 enum hal_rx_wbm_buf_type { 655 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 656 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 657 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 658 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 659 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 660 }; 661 662 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 663 664 //#include "hal_rx_be.h" 665 666 /* 667 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 668 * 669 * @nbuf: Network buffer 670 * Returns: flag to indicate whether the nbuf has MC/BC address 671 */ 672 static inline uint32_t 673 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 674 qdf_nbuf_t nbuf) 675 { 676 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 677 678 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 679 } 680 681 /** 682 * hal_rx_priv_info_set_in_tlv(): Save the private info to 683 * the reserved bytes of rx_tlv_hdr 684 * @buf: start of rx_tlv_hdr 685 * @wbm_er_info: hal_wbm_err_desc_info structure 686 * Return: void 687 */ 688 static inline void 689 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 690 uint8_t *buf, uint8_t *priv_data, 691 uint32_t len) 692 { 693 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 694 695 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 696 priv_data, 697 len); 698 } 699 700 /* 701 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 702 * reo_entrance_ring descriptor 703 * 704 * @reo_ent_desc: reo_entrance_ring descriptor 705 * Returns: value of rxdma_push_reason 706 */ 707 static inline 708 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 709 { 710 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 711 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 712 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 713 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 714 } 715 716 /** 717 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 718 * reo_entrance_ring descriptor 719 * @reo_ent_desc: reo_entrance_ring descriptor 720 * Return: value of rxdma_error_code 721 */ 722 static inline 723 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 724 { 725 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 726 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 727 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 728 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 729 } 730 731 /** 732 * hal_rx_priv_info_get_from_tlv(): retrieve the private data from 733 * the reserved bytes of rx_tlv_hdr. 734 * @buf: start of rx_tlv_hdr 735 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 736 * Return: void 737 */ 738 static inline void 739 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 740 uint8_t *buf, uint8_t *wbm_er_info, 741 uint32_t len) 742 { 743 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 744 745 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 746 wbm_er_info, 747 len); 748 } 749 750 static inline void 751 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 752 uint16_t *rx_mon_pkt_tlv_size) 753 { 754 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 755 756 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 757 rx_mon_pkt_tlv_size); 758 } 759 760 /* 761 * hal_rx_encryption_info_valid(): Returns encryption type. 762 * 763 * @hal_soc_hdl: hal soc handle 764 * @buf: rx_tlv_hdr of the received packet 765 * 766 * Return: encryption type 767 */ 768 static inline uint32_t 769 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 770 { 771 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 772 773 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 774 } 775 776 /* 777 * hal_rx_print_pn: Prints the PN of rx packet. 778 * @hal_soc_hdl: hal soc handle 779 * @buf: rx_tlv_hdr of the received packet 780 * 781 * Return: void 782 */ 783 static inline void 784 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 785 { 786 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 787 788 hal_soc->ops->hal_rx_print_pn(buf); 789 } 790 791 /** 792 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 793 * l3_header padding from rx_msdu_end TLV 794 * 795 * @buf: pointer to the start of RX PKT TLV headers 796 * Return: number of l3 header padding bytes 797 */ 798 static inline uint32_t 799 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 800 uint8_t *buf) 801 { 802 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 803 804 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 805 } 806 807 /** 808 * hal_rx_msdu_end_sa_idx_get(): API to get the 809 * sa_idx from rx_msdu_end TLV 810 * 811 * @ buf: pointer to the start of RX PKT TLV headers 812 * Return: sa_idx (SA AST index) 813 */ 814 static inline uint16_t 815 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 816 uint8_t *buf) 817 { 818 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 819 820 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 821 } 822 823 /** 824 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 825 * sa_is_valid bit from rx_msdu_end TLV 826 * 827 * @ buf: pointer to the start of RX PKT TLV headers 828 * Return: sa_is_valid bit 829 */ 830 static inline uint8_t 831 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 832 uint8_t *buf) 833 { 834 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 835 836 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 837 } 838 839 /** 840 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 841 * from rx_msdu_start TLV 842 * 843 * @buf: pointer to the start of RX PKT TLV headers 844 * @len: msdu length 845 * 846 * Return: none 847 */ 848 static inline void 849 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 850 uint32_t len) 851 { 852 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 853 854 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 855 } 856 857 /** 858 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 859 * 860 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 861 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 862 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 863 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 864 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 865 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 866 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 867 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 868 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 869 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 870 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 871 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 872 */ 873 enum hal_rx_mpdu_info_sw_frame_group_id_type { 874 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 875 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 876 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 877 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 878 HAL_MPDU_SW_FRAME_GROUP_MGMT, 879 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 880 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 881 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 882 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 883 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 884 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 885 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 886 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 887 }; 888 889 /** 890 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 891 * Retrieve qos control valid bit from the tlv. 892 * @hal_soc_hdl: hal_soc handle 893 * @buf: pointer to rx pkt TLV. 894 * 895 * Return: qos control value. 896 */ 897 static inline uint32_t 898 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 899 hal_soc_handle_t hal_soc_hdl, 900 uint8_t *buf) 901 { 902 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 903 904 if ((!hal_soc) || (!hal_soc->ops)) { 905 hal_err("hal handle is NULL"); 906 QDF_BUG(0); 907 return QDF_STATUS_E_INVAL; 908 } 909 910 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 911 return hal_soc->ops-> 912 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 913 914 return QDF_STATUS_E_INVAL; 915 } 916 917 /** 918 * hal_rx_is_unicast: check packet is unicast frame or not. 919 * @hal_soc_hdl: hal_soc handle 920 * @buf: pointer to rx pkt TLV. 921 * 922 * Return: true on unicast. 923 */ 924 static inline bool 925 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 926 { 927 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 928 929 return hal_soc->ops->hal_rx_is_unicast(buf); 930 } 931 932 /** 933 * hal_rx_tid_get: get tid based on qos control valid. 934 * @hal_soc_hdl: hal soc handle 935 * @buf: pointer to rx pkt TLV. 936 * 937 * Return: tid 938 */ 939 static inline uint32_t 940 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 941 { 942 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 943 944 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 945 } 946 947 /** 948 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 949 * @hal_soc_hdl: hal soc handle 950 * @buf: pointer to rx pkt TLV. 951 * 952 * Return: sw peer_id 953 */ 954 static inline uint32_t 955 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 956 uint8_t *buf) 957 { 958 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 959 960 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 961 } 962 963 /** 964 * hal_rx_tlv_peer_meta_data_get() - Retrieve PEER_META_DATA 965 * @hal_soc_hdl: hal soc handle 966 * @buf: pointer to rx pkt TLV. 967 * 968 * Return: peer meta data 969 */ 970 static inline uint32_t 971 hal_rx_tlv_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl, 972 uint8_t *buf) 973 { 974 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 975 976 return hal_soc->ops->hal_rx_tlv_peer_meta_data_get(buf); 977 } 978 979 /* 980 * hal_rx_mpdu_get_tods(): API to get the tods info 981 * from rx_mpdu_start 982 * 983 * @buf: pointer to the start of RX PKT TLV header 984 * Return: uint32_t(to_ds) 985 */ 986 987 static inline uint32_t 988 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 989 { 990 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 991 992 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 993 } 994 995 996 /* 997 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 998 * from rx_mpdu_start 999 * @hal_soc_hdl: hal soc handle 1000 * @buf: pointer to the start of RX PKT TLV header 1001 * 1002 * Return: uint32_t(fr_ds) 1003 */ 1004 static inline uint32_t 1005 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1006 { 1007 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1008 1009 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1010 } 1011 1012 /* 1013 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1014 * @hal_soc_hdl: hal soc handle 1015 * @buf: pointer to the start of RX PKT TLV headera 1016 * @mac_addr: pointer to mac address 1017 * 1018 * Return: success/failure 1019 */ 1020 static inline 1021 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1022 uint8_t *buf, uint8_t *mac_addr) 1023 { 1024 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1025 1026 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1027 } 1028 1029 /* 1030 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1031 * in the packet 1032 * @hal_soc_hdl: hal soc handle 1033 * @buf: pointer to the start of RX PKT TLV header 1034 * @mac_addr: pointer to mac address 1035 * 1036 * Return: success/failure 1037 */ 1038 static inline 1039 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1040 uint8_t *buf, uint8_t *mac_addr) 1041 { 1042 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1043 1044 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1045 } 1046 1047 /* 1048 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1049 * in the packet 1050 * @hal_soc_hdl: hal soc handle 1051 * @buf: pointer to the start of RX PKT TLV header 1052 * @mac_addr: pointer to mac address 1053 * 1054 * Return: success/failure 1055 */ 1056 static inline 1057 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1058 uint8_t *buf, uint8_t *mac_addr) 1059 { 1060 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1061 1062 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1063 } 1064 1065 /* 1066 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1067 * in the packet 1068 * @hal_soc_hdl: hal_soc handle 1069 * @buf: pointer to the start of RX PKT TLV header 1070 * @mac_addr: pointer to mac address 1071 * Return: success/failure 1072 */ 1073 static inline 1074 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1075 uint8_t *buf, uint8_t *mac_addr) 1076 { 1077 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1078 1079 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1080 } 1081 1082 /** 1083 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1084 * from rx_msdu_end TLV 1085 * 1086 * @ buf: pointer to the start of RX PKT TLV headers 1087 * Return: da index 1088 */ 1089 static inline uint16_t 1090 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1091 { 1092 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1093 1094 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1095 } 1096 1097 /** 1098 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1099 * from rx_msdu_end TLV 1100 * @hal_soc_hdl: hal soc handle 1101 * @ buf: pointer to the start of RX PKT TLV headers 1102 * 1103 * Return: da_is_valid 1104 */ 1105 static inline uint8_t 1106 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1107 uint8_t *buf) 1108 { 1109 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1110 1111 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1112 } 1113 1114 /** 1115 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1116 * from rx_msdu_end TLV 1117 * 1118 * @buf: pointer to the start of RX PKT TLV headers 1119 * 1120 * Return: da_is_mcbc 1121 */ 1122 static inline uint8_t 1123 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1124 { 1125 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1126 1127 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1128 } 1129 1130 /** 1131 * hal_rx_msdu_end_is_tkip_mic_err: API to check if pkt has mic error 1132 * from rx_msdu_end TLV 1133 * 1134 * @buf: pointer to the start of RX PKT TLV headers 1135 * 1136 * Return: tkip_mic_err 1137 */ 1138 static inline uint8_t 1139 hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl, 1140 uint8_t *buf) 1141 { 1142 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1143 1144 if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err) 1145 return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf); 1146 else 1147 return 0; 1148 } 1149 1150 /** 1151 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1152 * from rx_msdu_end TLV 1153 * @hal_soc_hdl: hal soc handle 1154 * @buf: pointer to the start of RX PKT TLV headers 1155 * 1156 * Return: first_msdu 1157 */ 1158 static inline uint8_t 1159 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1160 uint8_t *buf) 1161 { 1162 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1163 1164 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1165 } 1166 1167 /** 1168 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1169 * from rx_msdu_end TLV 1170 * @hal_soc_hdl: hal soc handle 1171 * @buf: pointer to the start of RX PKT TLV headers 1172 * 1173 * Return: last_msdu 1174 */ 1175 static inline uint8_t 1176 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1177 uint8_t *buf) 1178 { 1179 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1180 1181 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1182 } 1183 1184 /** 1185 * hal_rx_msdu_cce_match_get: API to get CCE match 1186 * from rx_msdu_end TLV 1187 * @buf: pointer to the start of RX PKT TLV headers 1188 * Return: cce_meta_data 1189 */ 1190 static inline bool 1191 hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl, 1192 uint8_t *buf) 1193 { 1194 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1195 1196 return hal_soc->ops->hal_rx_msdu_cce_match_get(buf); 1197 } 1198 1199 /** 1200 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1201 * from rx_msdu_end TLV 1202 * @buf: pointer to the start of RX PKT TLV headers 1203 * Return: cce_meta_data 1204 */ 1205 static inline uint16_t 1206 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1207 uint8_t *buf) 1208 { 1209 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1210 1211 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1212 } 1213 1214 /******************************************************************************* 1215 * RX REO ERROR APIS 1216 ******************************************************************************/ 1217 1218 /** 1219 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1220 * @msdu_link_ptr - msdu link ptr 1221 * @hal - pointer to hal_soc 1222 * Return - Pointer to rx_msdu_details structure 1223 * 1224 */ 1225 static inline 1226 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1227 struct hal_soc *hal_soc) 1228 { 1229 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1230 } 1231 1232 /** 1233 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1234 * @msdu_details_ptr - Pointer to msdu_details_ptr 1235 * @hal - pointer to hal_soc 1236 * Return - Pointer to rx_msdu_desc_info structure. 1237 * 1238 */ 1239 static inline 1240 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1241 struct hal_soc *hal_soc) 1242 { 1243 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1244 } 1245 1246 /** 1247 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1248 * cookie from the REO destination ring element 1249 * 1250 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1251 * the current descriptor 1252 * @ buf_info: structure to return the buffer information 1253 * Return: void 1254 */ 1255 static inline 1256 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1257 hal_ring_desc_t rx_desc, 1258 struct hal_buf_info *buf_info) 1259 { 1260 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1261 1262 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1263 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1264 rx_desc, 1265 buf_info); 1266 1267 } 1268 1269 /** 1270 * hal_rx_wbm_rel_buf_paddr_get: Gets the physical address and 1271 * cookie from the WBM release ring element 1272 * 1273 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1274 * the current descriptor 1275 * @ buf_info: structure to return the buffer information 1276 * Return: void 1277 */ 1278 static inline 1279 void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1280 hal_ring_desc_t rx_desc, 1281 struct hal_buf_info *buf_info) 1282 { 1283 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1284 1285 if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get) 1286 return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc, 1287 buf_info); 1288 } 1289 1290 /** 1291 * hal_rx_buf_cookie_rbm_get: Gets the physical address and 1292 * cookie from the REO entrance ring element 1293 * 1294 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1295 * the current descriptor 1296 * @ buf_info: structure to return the buffer information 1297 * @ msdu_cnt: pointer to msdu count in MPDU 1298 * Return: void 1299 */ 1300 static inline 1301 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1302 uint32_t *buf_addr_info, 1303 struct hal_buf_info *buf_info) 1304 { 1305 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1306 1307 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1308 buf_addr_info, 1309 buf_info); 1310 } 1311 1312 /** 1313 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1314 * from the MSDU link descriptor 1315 * 1316 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1317 * MSDU link descriptor (struct rx_msdu_link) 1318 * 1319 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1320 * 1321 * @num_msdus: Number of MSDUs in the MPDU 1322 * 1323 * Return: void 1324 */ 1325 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1326 void *msdu_link_desc, 1327 struct hal_rx_msdu_list *msdu_list, 1328 uint16_t *num_msdus) 1329 { 1330 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1331 struct rx_msdu_details *msdu_details; 1332 struct rx_msdu_desc_info *msdu_desc_info; 1333 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1334 int i; 1335 struct hal_buf_info buf_info; 1336 1337 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1338 1339 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1340 __func__, __LINE__, msdu_link, msdu_details); 1341 1342 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1343 /* num_msdus received in mpdu descriptor may be incorrect 1344 * sometimes due to HW issue. Check msdu buffer address also 1345 */ 1346 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1347 &msdu_details[i].buffer_addr_info_details) == 0)) 1348 break; 1349 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1350 &msdu_details[i].buffer_addr_info_details) == 0) { 1351 /* set the last msdu bit in the prev msdu_desc_info */ 1352 msdu_desc_info = 1353 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1354 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1355 break; 1356 } 1357 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1358 hal_soc); 1359 1360 /* set first MSDU bit or the last MSDU bit */ 1361 if (!i) 1362 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1363 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1364 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1365 1366 msdu_list->msdu_info[i].msdu_flags = 1367 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1368 msdu_list->msdu_info[i].msdu_len = 1369 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1370 1371 /* addr field in buf_info will not be valid */ 1372 hal_rx_buf_cookie_rbm_get( 1373 hal_soc_hdl, 1374 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1375 &buf_info); 1376 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1377 msdu_list->rbm[i] = buf_info.rbm; 1378 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1379 &msdu_details[i].buffer_addr_info_details) | 1380 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1381 &msdu_details[i].buffer_addr_info_details) << 32; 1382 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1383 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1384 } 1385 *num_msdus = i; 1386 } 1387 1388 /** 1389 * hal_rx_is_pn_error() - Indicate if this error was caused by a 1390 * PN check failure 1391 * 1392 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 1393 * 1394 * Return: true: error caused by PN check, false: other error 1395 */ 1396 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1397 { 1398 1399 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1400 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1401 true : false; 1402 } 1403 1404 /** 1405 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1406 * the sequence number 1407 * 1408 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1409 * 1410 * Return: true: error caused by 2K jump, false: other error 1411 */ 1412 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1413 { 1414 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1415 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1416 true : false; 1417 } 1418 1419 /** 1420 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1421 * 1422 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1423 * 1424 * Return: true: error caused by OOR, false: other error 1425 */ 1426 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1427 { 1428 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1429 true : false; 1430 } 1431 1432 /** 1433 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1434 * @error_code: error code obtained from ring descriptor. 1435 * 1436 * Return: true, if the error code is 2k-jump or OOR 1437 * false, for other error codes. 1438 */ 1439 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1440 { 1441 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1442 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1443 true : false; 1444 } 1445 1446 /** 1447 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1448 * @hal_desc: hardware descriptor pointer 1449 * 1450 * This function will print wbm release descriptor 1451 * 1452 * Return: none 1453 */ 1454 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1455 { 1456 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1457 uint32_t i; 1458 1459 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1460 "Current Rx wbm release descriptor is"); 1461 1462 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1463 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1464 "DWORD[i] = 0x%x", wbm_comp[i]); 1465 } 1466 } 1467 1468 /** 1469 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 1470 * 1471 * @ hal_soc_hdl : HAL version of the SOC pointer 1472 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 1473 * @ buf_addr_info : void pointer to the buffer_addr_info 1474 * @ bm_action : put in IDLE list or release to MSDU_LIST 1475 * 1476 * Return: void 1477 */ 1478 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1479 static inline 1480 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1481 void *src_srng_desc, 1482 hal_buff_addrinfo_t buf_addr_info, 1483 uint8_t bm_action) 1484 { 1485 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1486 1487 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1488 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1489 src_srng_desc, 1490 buf_addr_info, 1491 bm_action); 1492 } 1493 1494 /** 1495 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 1496 * BUFFER_ADDR_INFO, give the RX descriptor 1497 * (Assumption -- BUFFER_ADDR_INFO is the 1498 * first field in the descriptor structure) 1499 */ 1500 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1501 ((hal_link_desc_t)(ring_desc)) 1502 1503 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1504 1505 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1506 1507 /******************************************************************************* 1508 * RX WBM ERROR APIS 1509 ******************************************************************************/ 1510 1511 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1512 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1513 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1514 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1515 /** 1516 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 1517 * the frame to this release ring 1518 * 1519 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1520 * frame to this queue 1521 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1522 * received routing instructions. No error within REO was detected 1523 */ 1524 enum hal_rx_wbm_reo_push_reason { 1525 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1526 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1527 }; 1528 1529 1530 /** 1531 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 1532 * this release ring 1533 * 1534 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1535 * this frame to this queue 1536 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1537 * per received routing instructions. No error within RXDMA was detected 1538 */ 1539 enum hal_rx_wbm_rxdma_push_reason { 1540 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1541 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1542 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1543 }; 1544 1545 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 1546 uint8_t dbg_level, 1547 struct hal_soc *hal) 1548 { 1549 1550 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 1551 } 1552 1553 /** 1554 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 1555 * human readable format. 1556 * @ msdu_end: pointer the msdu_end TLV in pkt. 1557 * @ dbg_level: log level. 1558 * 1559 * Return: void 1560 */ 1561 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1562 struct rx_msdu_end *msdu_end, 1563 uint8_t dbg_level) 1564 { 1565 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 1566 } 1567 1568 /** 1569 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 1570 * structure 1571 * @hal_ring: pointer to hal_srng structure 1572 * 1573 * Return: ring_id 1574 */ 1575 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1576 { 1577 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1578 } 1579 1580 #define DOT11_SEQ_FRAG_MASK 0x000f 1581 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1582 1583 /** 1584 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 1585 * 1586 * @nbuf: Network buffer 1587 * Returns: rx fragment number 1588 */ 1589 static inline 1590 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1591 uint8_t *buf) 1592 { 1593 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1594 } 1595 1596 /* 1597 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 1598 * @hal_soc_hdl: hal soc handle 1599 * @nbuf: Network buffer 1600 * 1601 * Return: value of sequence control valid field 1602 */ 1603 static inline 1604 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1605 uint8_t *buf) 1606 { 1607 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1608 1609 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1610 } 1611 1612 /* 1613 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 1614 * @hal_soc_hdl: hal soc handle 1615 * @nbuf: Network buffer 1616 * 1617 * Returns: value of frame control valid field 1618 */ 1619 static inline 1620 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1621 uint8_t *buf) 1622 { 1623 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1624 1625 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1626 } 1627 1628 /** 1629 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 1630 * @hal_soc_hdl: hal soc handle 1631 * @nbuf: Network buffer 1632 * Returns: value of mpdu 4th address valid field 1633 */ 1634 static inline 1635 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1636 uint8_t *buf) 1637 { 1638 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1639 1640 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1641 } 1642 1643 /* 1644 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 1645 * 1646 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1647 * Returns: None 1648 */ 1649 static inline void 1650 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1651 { 1652 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1653 } 1654 1655 /** 1656 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 1657 * save it to hal_wbm_err_desc_info structure passed by caller 1658 * @wbm_desc: wbm ring descriptor 1659 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1660 * Return: void 1661 */ 1662 static inline 1663 void hal_rx_wbm_err_info_get(void *wbm_desc, 1664 struct hal_wbm_err_desc_info *wbm_er_info, 1665 hal_soc_handle_t hal_soc_hdl) 1666 { 1667 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1668 1669 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1670 } 1671 1672 /** 1673 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 1674 * bit from wbm release ring descriptor 1675 * @wbm_desc: wbm ring descriptor 1676 * Return: uint8_t 1677 */ 1678 static inline 1679 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1680 void *wbm_desc) 1681 { 1682 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1683 1684 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1685 } 1686 1687 /** 1688 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 1689 * 1690 * @ hal_soc: HAL version of the SOC pointer 1691 * @ hw_desc_addr: Start address of Rx HW TLVs 1692 * @ rs: Status for monitor mode 1693 * 1694 * Return: void 1695 */ 1696 static inline 1697 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1698 void *hw_desc_addr, 1699 struct mon_rx_status *rs) 1700 { 1701 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1702 1703 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1704 } 1705 1706 /* 1707 * hal_rx_get_tlv(): API to get the tlv 1708 * 1709 * @hal_soc: HAL version of the SOC pointer 1710 * @rx_tlv: TLV data extracted from the rx packet 1711 * Return: uint8_t 1712 */ 1713 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1714 { 1715 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1716 } 1717 1718 /* 1719 * hal_rx_msdu_start_nss_get(): API to get the NSS 1720 * Interval from rx_msdu_start 1721 * 1722 * @hal_soc: HAL version of the SOC pointer 1723 * @buf: pointer to the start of RX PKT TLV header 1724 * Return: uint32_t(nss) 1725 */ 1726 static inline 1727 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1728 { 1729 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1730 1731 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1732 } 1733 1734 /** 1735 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 1736 * human readable format. 1737 * @ msdu_start: pointer the msdu_start TLV in pkt. 1738 * @ dbg_level: log level. 1739 * 1740 * Return: void 1741 */ 1742 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1743 struct rx_msdu_start *msdu_start, 1744 uint8_t dbg_level) 1745 { 1746 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 1747 } 1748 1749 /** 1750 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 1751 * info details 1752 * 1753 * @ buf - Pointer to buffer containing rx pkt tlvs. 1754 * 1755 * 1756 */ 1757 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1758 uint8_t *buf) 1759 { 1760 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1761 1762 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1763 } 1764 1765 /* 1766 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 1767 * Interval from rx_msdu_start 1768 * 1769 * @buf: pointer to the start of RX PKT TLV header 1770 * Return: uint32_t(reception_type) 1771 */ 1772 static inline 1773 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1774 uint8_t *buf) 1775 { 1776 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1777 1778 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1779 } 1780 1781 /** 1782 * hal_reo_status_get_header_generic - Process reo desc info 1783 * @d - Pointer to reo descriptor 1784 * @b - tlv type info 1785 * @h - Pointer to hal_reo_status_header where info to be stored 1786 * @hal- pointer to hal_soc structure 1787 * Return - none. 1788 * 1789 */ 1790 static inline 1791 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1792 void *h, struct hal_soc *hal_soc) 1793 { 1794 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1795 } 1796 1797 /** 1798 * hal_rx_desc_is_first_msdu() - Check if first msdu 1799 * 1800 * @hal_soc_hdl: hal_soc handle 1801 * @hw_desc_addr: hardware descriptor address 1802 * 1803 * Return: 0 - success/ non-zero failure 1804 */ 1805 static inline 1806 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1807 void *hw_desc_addr) 1808 { 1809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1810 1811 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1812 } 1813 1814 /** 1815 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1816 * the rx tlv fields. 1817 * @hal_soc_hdl: HAL SoC handle 1818 * @buf: rx tlv start address [To be validated by caller] 1819 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1820 * 1821 * Return: None 1822 */ 1823 static inline void 1824 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1825 uint8_t *buf, 1826 void *mpdu_desc_info_hdl) 1827 { 1828 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1829 1830 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1831 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1832 mpdu_desc_info_hdl); 1833 } 1834 1835 static inline uint32_t 1836 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1837 { 1838 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1839 1840 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1841 } 1842 1843 static inline 1844 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1845 uint8_t *rx_tlv_hdr) 1846 { 1847 uint8_t decap_format; 1848 1849 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1850 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1851 rx_tlv_hdr); 1852 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1853 return true; 1854 } 1855 1856 return false; 1857 } 1858 1859 /** 1860 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 1861 * from rx_msdu_end TLV 1862 * @buf: pointer to the start of RX PKT TLV headers 1863 * 1864 * Return: fse metadata value from MSDU END TLV 1865 */ 1866 static inline uint32_t 1867 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1868 uint8_t *buf) 1869 { 1870 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1871 1872 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1873 } 1874 1875 /** 1876 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 1877 * <struct buffer_addr_info> structure 1878 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1879 * @buf_info: structure to return the buffer information including 1880 * paddr/cookie 1881 * 1882 * return: None 1883 */ 1884 static inline 1885 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 1886 struct hal_buf_info *buf_info) 1887 { 1888 buf_info->paddr = 1889 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 1890 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 1891 } 1892 1893 /** 1894 * hal_rx_msdu_flow_idx_get: API to get flow index 1895 * from rx_msdu_end TLV 1896 * @buf: pointer to the start of RX PKT TLV headers 1897 * 1898 * Return: flow index value from MSDU END TLV 1899 */ 1900 static inline uint32_t 1901 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 1902 uint8_t *buf) 1903 { 1904 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1905 1906 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 1907 } 1908 1909 /** 1910 * hal_rx_msdu_get_reo_destination_indication: API to get reo 1911 * destination index from rx_msdu_end TLV 1912 * @buf: pointer to the start of RX PKT TLV headers 1913 * @reo_destination_indication: pointer to return value of 1914 * reo_destination_indication 1915 * 1916 * Return: reo_destination_indication value from MSDU END TLV 1917 */ 1918 static inline void 1919 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 1920 uint8_t *buf, 1921 uint32_t *reo_destination_indication) 1922 { 1923 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1924 1925 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 1926 reo_destination_indication); 1927 } 1928 1929 /** 1930 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 1931 * from rx_msdu_end TLV 1932 * @buf: pointer to the start of RX PKT TLV headers 1933 * 1934 * Return: flow index timeout value from MSDU END TLV 1935 */ 1936 static inline bool 1937 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 1938 uint8_t *buf) 1939 { 1940 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1941 1942 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 1943 } 1944 1945 /** 1946 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 1947 * from rx_msdu_end TLV 1948 * @buf: pointer to the start of RX PKT TLV headers 1949 * 1950 * Return: flow index invalid value from MSDU END TLV 1951 */ 1952 static inline bool 1953 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 1954 uint8_t *buf) 1955 { 1956 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1957 1958 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 1959 } 1960 1961 /** 1962 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 1963 * @hal_soc_hdl: hal_soc handle 1964 * @rx_tlv_hdr: Rx_tlv_hdr 1965 * @rxdma_dst_ring_desc: Rx HW descriptor 1966 * 1967 * Return: ppdu id 1968 */ 1969 static inline 1970 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 1971 void *rx_tlv_hdr, 1972 void *rxdma_dst_ring_desc) 1973 { 1974 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1975 1976 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 1977 rxdma_dst_ring_desc); 1978 } 1979 1980 /** 1981 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 1982 * @hal_soc_hdl: hal_soc handle 1983 * @buf: rx tlv address 1984 * 1985 * Return: sw peer id 1986 */ 1987 static inline 1988 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1989 uint8_t *buf) 1990 { 1991 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1992 1993 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 1994 } 1995 1996 static inline 1997 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 1998 void *link_desc_addr) 1999 { 2000 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2001 2002 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 2003 } 2004 2005 static inline 2006 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 2007 void *msdu_addr) 2008 { 2009 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2010 2011 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 2012 } 2013 2014 static inline 2015 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2016 void *hw_addr) 2017 { 2018 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2019 2020 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 2021 } 2022 2023 static inline 2024 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2025 void *hw_addr) 2026 { 2027 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2028 2029 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 2030 } 2031 2032 static inline 2033 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 2034 uint8_t *buf) 2035 { 2036 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2037 2038 return hal_soc->ops->hal_rx_get_fc_valid(buf); 2039 } 2040 2041 static inline 2042 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2043 { 2044 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2045 2046 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 2047 } 2048 2049 static inline 2050 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 2051 uint8_t *buf) 2052 { 2053 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2054 2055 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 2056 } 2057 2058 static inline 2059 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 2060 uint8_t *buf) 2061 { 2062 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2063 2064 return hal_soc->ops->hal_rx_get_filter_category(buf); 2065 } 2066 2067 static inline 2068 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 2069 uint8_t *buf) 2070 { 2071 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2072 2073 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 2074 } 2075 2076 /** 2077 * hal_reo_config(): Set reo config parameters 2078 * @soc: hal soc handle 2079 * @reg_val: value to be set 2080 * @reo_params: reo parameters 2081 * 2082 * Return: void 2083 */ 2084 static inline 2085 void hal_reo_config(struct hal_soc *hal_soc, 2086 uint32_t reg_val, 2087 struct hal_reo_params *reo_params) 2088 { 2089 hal_soc->ops->hal_reo_config(hal_soc, 2090 reg_val, 2091 reo_params); 2092 } 2093 2094 /** 2095 * hal_rx_msdu_get_flow_params: API to get flow index, 2096 * flow index invalid and flow index timeout from rx_msdu_end TLV 2097 * @buf: pointer to the start of RX PKT TLV headers 2098 * @flow_invalid: pointer to return value of flow_idx_valid 2099 * @flow_timeout: pointer to return value of flow_idx_timeout 2100 * @flow_index: pointer to return value of flow_idx 2101 * 2102 * Return: none 2103 */ 2104 static inline void 2105 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2106 uint8_t *buf, 2107 bool *flow_invalid, 2108 bool *flow_timeout, 2109 uint32_t *flow_index) 2110 { 2111 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2112 2113 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2114 flow_invalid, 2115 flow_timeout, 2116 flow_index); 2117 } 2118 2119 static inline 2120 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2121 uint8_t *buf) 2122 { 2123 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2124 2125 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2126 } 2127 2128 static inline 2129 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2130 uint8_t *buf) 2131 { 2132 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2133 2134 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2135 } 2136 2137 static inline void 2138 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2139 void *rx_tlv, 2140 void *ppdu_info) 2141 { 2142 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2143 2144 if (hal_soc->ops->hal_rx_get_bb_info) 2145 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2146 } 2147 2148 static inline void 2149 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2150 void *rx_tlv, 2151 void *ppdu_info) 2152 { 2153 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2154 2155 if (hal_soc->ops->hal_rx_get_rtt_info) 2156 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2157 } 2158 2159 /** 2160 * hal_rx_msdu_metadata_get(): API to get the 2161 * fast path information from rx_msdu_end TLV 2162 * 2163 * @ hal_soc_hdl: DP soc handle 2164 * @ buf: pointer to the start of RX PKT TLV headers 2165 * @ msdu_metadata: Structure to hold msdu end information 2166 * Return: none 2167 */ 2168 static inline void 2169 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2170 struct hal_rx_msdu_metadata *msdu_md) 2171 { 2172 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2173 2174 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2175 } 2176 2177 /** 2178 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 2179 * from rx_msdu_end TLV 2180 * @buf: pointer to the start of RX PKT TLV headers 2181 * 2182 * Return: cumulative_l4_checksum 2183 */ 2184 static inline uint16_t 2185 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2186 uint8_t *buf) 2187 { 2188 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2189 2190 if (!hal_soc || !hal_soc->ops) { 2191 hal_err("hal handle is NULL"); 2192 QDF_BUG(0); 2193 return 0; 2194 } 2195 2196 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2197 return 0; 2198 2199 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2200 } 2201 2202 /** 2203 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 2204 * from rx_msdu_end TLV 2205 * @buf: pointer to the start of RX PKT TLV headers 2206 * 2207 * Return: cumulative_ip_length 2208 */ 2209 static inline uint16_t 2210 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2211 uint8_t *buf) 2212 { 2213 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2214 2215 if (!hal_soc || !hal_soc->ops) { 2216 hal_err("hal handle is NULL"); 2217 QDF_BUG(0); 2218 return 0; 2219 } 2220 2221 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2222 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2223 2224 return 0; 2225 } 2226 2227 /** 2228 * hal_rx_get_udp_proto: API to get UDP proto field 2229 * from rx_msdu_start TLV 2230 * @buf: pointer to the start of RX PKT TLV headers 2231 * 2232 * Return: UDP proto field value 2233 */ 2234 static inline bool 2235 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2236 { 2237 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2238 2239 if (!hal_soc || !hal_soc->ops) { 2240 hal_err("hal handle is NULL"); 2241 QDF_BUG(0); 2242 return 0; 2243 } 2244 2245 if (hal_soc->ops->hal_rx_get_udp_proto) 2246 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2247 2248 return 0; 2249 } 2250 2251 /** 2252 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 2253 * from rx_msdu_end TLV 2254 * @buf: pointer to the start of RX PKT TLV headers 2255 * 2256 * Return: flow_agg_continuation bit field value 2257 */ 2258 static inline bool 2259 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2260 uint8_t *buf) 2261 { 2262 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2263 2264 if (!hal_soc || !hal_soc->ops) { 2265 hal_err("hal handle is NULL"); 2266 QDF_BUG(0); 2267 return 0; 2268 } 2269 2270 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2271 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2272 2273 return 0; 2274 } 2275 2276 /** 2277 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 2278 * rx_msdu_end TLV 2279 * @buf: pointer to the start of RX PKT TLV headers 2280 * 2281 * Return: flow_agg count value 2282 */ 2283 static inline uint8_t 2284 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2285 uint8_t *buf) 2286 { 2287 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2288 2289 if (!hal_soc || !hal_soc->ops) { 2290 hal_err("hal handle is NULL"); 2291 QDF_BUG(0); 2292 return 0; 2293 } 2294 2295 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2296 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2297 2298 return 0; 2299 } 2300 2301 /** 2302 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 2303 * @buf: pointer to the start of RX PKT TLV headers 2304 * 2305 * Return: fisa flow_agg timeout bit value 2306 */ 2307 static inline bool 2308 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2309 { 2310 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2311 2312 if (!hal_soc || !hal_soc->ops) { 2313 hal_err("hal handle is NULL"); 2314 QDF_BUG(0); 2315 return 0; 2316 } 2317 2318 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2319 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2320 2321 return 0; 2322 } 2323 2324 /** 2325 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 2326 * tag is valid 2327 * 2328 * @hal_soc_hdl: HAL SOC handle 2329 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2330 * 2331 * Return: true if RX_MPDU_START tlv tag is valid, else false 2332 */ 2333 2334 static inline uint8_t 2335 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2336 void *rx_tlv_hdr) 2337 { 2338 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2339 2340 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2341 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2342 2343 return 0; 2344 } 2345 2346 /** 2347 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 2348 * buffer addr info 2349 * @link_desc_va: pointer to current msdu link Desc 2350 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2351 * 2352 * return: None 2353 */ 2354 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2355 void *link_desc_va, 2356 struct buffer_addr_info *next_addr_info) 2357 { 2358 struct rx_msdu_link *msdu_link = link_desc_va; 2359 2360 if (!msdu_link) { 2361 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2362 return; 2363 } 2364 2365 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2366 } 2367 2368 /** 2369 * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc 2370 * buffer addr info 2371 * @link_desc_va: pointer to current msdu link Desc 2372 * 2373 * return: None 2374 */ 2375 static inline 2376 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2377 { 2378 struct rx_msdu_link *msdu_link = link_desc_va; 2379 2380 if (msdu_link) 2381 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2382 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2383 } 2384 2385 /** 2386 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 2387 * 2388 * @buf_addr_info: pointer to buf_addr_info structure 2389 * 2390 * return: true: has valid paddr, false: not. 2391 */ 2392 static inline 2393 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2394 { 2395 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2396 false : true; 2397 } 2398 2399 /** 2400 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 2401 * rx_pkt_tlvs structure 2402 * 2403 * @hal_soc_hdl: HAL SOC handle 2404 * return: msdu_end_tlv offset value 2405 */ 2406 static inline 2407 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2408 { 2409 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2410 2411 if (!hal_soc || !hal_soc->ops) { 2412 hal_err("hal handle is NULL"); 2413 QDF_BUG(0); 2414 return 0; 2415 } 2416 2417 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2418 } 2419 2420 /** 2421 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 2422 * rx_pkt_tlvs structure 2423 * 2424 * @hal_soc_hdl: HAL SOC handle 2425 * return: msdu_start_tlv offset value 2426 */ 2427 static inline 2428 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2429 { 2430 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2431 2432 if (!hal_soc || !hal_soc->ops) { 2433 hal_err("hal handle is NULL"); 2434 QDF_BUG(0); 2435 return 0; 2436 } 2437 2438 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2439 } 2440 2441 /** 2442 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 2443 * rx_pkt_tlvs structure 2444 * 2445 * @hal_soc_hdl: HAL SOC handle 2446 * return: mpdu_start_tlv offset value 2447 */ 2448 static inline 2449 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2450 { 2451 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2452 2453 if (!hal_soc || !hal_soc->ops) { 2454 hal_err("hal handle is NULL"); 2455 QDF_BUG(0); 2456 return 0; 2457 } 2458 2459 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2460 } 2461 2462 static inline 2463 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2464 { 2465 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2466 2467 if (!hal_soc || !hal_soc->ops) { 2468 hal_err("hal handle is NULL"); 2469 QDF_BUG(0); 2470 return 0; 2471 } 2472 2473 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2474 } 2475 2476 /** 2477 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 2478 * rx_pkt_tlvs structure 2479 * 2480 * @hal_soc_hdl: HAL SOC handle 2481 * return: mpdu_end_tlv offset value 2482 */ 2483 static inline 2484 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2485 { 2486 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2487 2488 if (!hal_soc || !hal_soc->ops) { 2489 hal_err("hal handle is NULL"); 2490 QDF_BUG(0); 2491 return 0; 2492 } 2493 2494 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2495 } 2496 2497 #ifdef CONFIG_WORD_BASED_TLV 2498 /** 2499 * hal_rx_mpdu_start_wmask_get(): Get the MPDU start word mask 2500 * 2501 * @hal_soc_hdl: HAL SOC handle 2502 * return: mpdu_start_tlv word mask value 2503 */ 2504 static inline 2505 uint32_t hal_rx_mpdu_start_wmask_get(hal_soc_handle_t hal_soc_hdl) 2506 { 2507 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2508 2509 if (!hal_soc || !hal_soc->ops) { 2510 hal_err("hal handle is NULL"); 2511 QDF_BUG(0); 2512 return 0; 2513 } 2514 2515 return hal_soc->ops->hal_rx_mpdu_start_wmask_get(); 2516 } 2517 2518 /** 2519 * hal_rx_msdu_end_wmask_get(): Get the MSDU END word mask 2520 * 2521 * @hal_soc_hdl: HAL SOC handle 2522 * return: msdu_end_tlv word mask value 2523 */ 2524 static inline 2525 uint32_t hal_rx_msdu_end_wmask_get(hal_soc_handle_t hal_soc_hdl) 2526 { 2527 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2528 2529 if (!hal_soc || !hal_soc->ops) { 2530 hal_err("hal handle is NULL"); 2531 QDF_BUG(0); 2532 return 0; 2533 } 2534 2535 return hal_soc->ops->hal_rx_msdu_end_wmask_get(); 2536 } 2537 #endif 2538 2539 /** 2540 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 2541 * rx_pkt_tlvs structure 2542 * 2543 * @hal_soc_hdl: HAL SOC handle 2544 * return: attn_tlv offset value 2545 */ 2546 static inline 2547 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2548 { 2549 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2550 2551 if (!hal_soc || !hal_soc->ops) { 2552 hal_err("hal handle is NULL"); 2553 QDF_BUG(0); 2554 return 0; 2555 } 2556 2557 return hal_soc->ops->hal_rx_attn_offset_get(); 2558 } 2559 2560 /** 2561 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 2562 * @msdu_details_ptr - Pointer to msdu_details_ptr 2563 * @hal - pointer to hal_soc 2564 * Return - Pointer to rx_msdu_desc_info structure. 2565 * 2566 */ 2567 static inline 2568 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2569 struct hal_soc *hal_soc) 2570 { 2571 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2572 msdu_details_ptr); 2573 } 2574 2575 static inline void 2576 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2577 uint8_t *buf, uint8_t dbg_level) 2578 { 2579 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2580 2581 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2582 } 2583 2584 //TODO - Change the names to not include tlv names 2585 static inline uint16_t 2586 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2587 { 2588 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2589 2590 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2591 } 2592 2593 static inline uint32_t 2594 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2595 { 2596 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2597 2598 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2599 } 2600 2601 static inline uint32_t 2602 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2603 { 2604 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2605 2606 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2607 } 2608 2609 static inline uint16_t 2610 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2611 { 2612 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2613 2614 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2615 } 2616 2617 static inline int 2618 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2619 uint8_t *rx_pkt_tlv, 2620 struct hal_offload_info *offload_info) 2621 { 2622 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2623 2624 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2625 offload_info); 2626 2627 } 2628 2629 static inline int 2630 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2631 void *proto_params) 2632 { 2633 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2634 2635 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2636 } 2637 2638 static inline int 2639 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2640 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2641 { 2642 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2643 2644 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2645 l3_hdr_offset, 2646 l4_hdr_offset); 2647 } 2648 2649 static inline uint32_t 2650 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2651 { 2652 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2653 2654 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2655 } 2656 2657 /* 2658 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 2659 * from rx_msdu_start 2660 * 2661 * @buf: pointer to the start of RX PKT TLV header 2662 * Return: uint32_t(pkt type) 2663 */ 2664 2665 static inline uint32_t 2666 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2667 { 2668 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2669 2670 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2671 } 2672 2673 static inline void 2674 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2675 uint8_t *buf, uint64_t *pn_num) 2676 { 2677 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2678 2679 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2680 } 2681 2682 static inline uint8_t * 2683 hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc) 2684 { 2685 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2686 2687 if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr) 2688 return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc); 2689 2690 return NULL; 2691 } 2692 2693 static inline uint64_t 2694 hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc, 2695 uint8_t *buf) 2696 { 2697 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2698 2699 if (hal_soc->ops->hal_rx_get_qdesc_addr) 2700 return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf); 2701 2702 return 0; 2703 } 2704 2705 static inline void 2706 hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl, 2707 uint8_t *desc, uint32_t dst_ind) 2708 { 2709 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2710 2711 if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind) 2712 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind); 2713 } 2714 2715 static inline uint32_t 2716 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2717 { 2718 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2719 2720 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2721 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2722 2723 return 0; 2724 } 2725 2726 static inline uint8_t * 2727 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2728 { 2729 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2730 2731 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2732 } 2733 2734 static inline uint8_t 2735 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2736 { 2737 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2738 2739 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2740 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2741 2742 return 0; 2743 } 2744 2745 static inline uint32_t 2746 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2747 { 2748 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2749 2750 if (hal_soc->ops->hal_rx_tlv_get_freq) 2751 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2752 2753 return 0; 2754 } 2755 2756 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2757 void *desc, 2758 void *mpdu_desc_info, 2759 uint32_t val) 2760 { 2761 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2762 2763 if (hal_soc->ops->hal_mpdu_desc_info_set) 2764 return hal_soc->ops->hal_mpdu_desc_info_set( 2765 hal_soc_hdl, desc, mpdu_desc_info, val); 2766 } 2767 2768 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2769 void *msdu_desc_info, 2770 uint32_t val, uint32_t nbuf_len) 2771 { 2772 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2773 2774 if (hal_soc->ops->hal_msdu_desc_info_set) 2775 return hal_soc->ops->hal_msdu_desc_info_set( 2776 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2777 } 2778 2779 static inline uint32_t 2780 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2781 { 2782 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2783 2784 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2785 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2786 hal_soc_hdl, msdu_link_desc); 2787 2788 return 0; 2789 } 2790 2791 static inline uint32_t 2792 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2793 { 2794 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2795 2796 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2797 } 2798 2799 static inline uint32_t 2800 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2801 { 2802 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2803 2804 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2805 } 2806 2807 static inline uint32_t 2808 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2809 { 2810 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2811 2812 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2813 } 2814 2815 static inline uint32_t 2816 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2817 { 2818 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2819 2820 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2821 } 2822 2823 static inline uint32_t 2824 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2825 { 2826 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2827 2828 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2829 } 2830 2831 static inline uint32_t 2832 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2833 hal_ring_desc_t ring_desc) 2834 { 2835 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2836 2837 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2838 } 2839 2840 /** 2841 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2842 * from the BUFFER_ADDR_INFO structure 2843 * given a REO destination ring descriptor. 2844 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2845 * 2846 * Return: uint8_t (value of the return_buffer_manager) 2847 */ 2848 static inline uint8_t 2849 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2850 hal_ring_desc_t ring_desc) 2851 { 2852 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2853 2854 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2855 } 2856 2857 /* 2858 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2859 * rxdma ring entry. 2860 * @rxdma_entry: descriptor entry 2861 * @paddr: physical address of nbuf data pointer. 2862 * @cookie: SW cookie used as a index to SW rx desc. 2863 * @manager: who owns the nbuf (host, NSS, etc...). 2864 * 2865 */ 2866 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 2867 void *rxdma_entry, 2868 qdf_dma_addr_t paddr, 2869 uint32_t cookie, 2870 uint8_t manager) 2871 { 2872 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2873 2874 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 2875 paddr, 2876 cookie, 2877 manager); 2878 } 2879 2880 static inline uint32_t 2881 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2882 { 2883 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2884 2885 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 2886 } 2887 2888 static inline void 2889 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 2890 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 2891 { 2892 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2893 2894 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 2895 ip_csum_err, 2896 tcp_udp_csum_err); 2897 } 2898 2899 static inline void 2900 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 2901 uint8_t *rx_tlv_hdr, 2902 struct hal_rx_pkt_capture_flags *flags) 2903 { 2904 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2905 2906 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 2907 flags); 2908 } 2909 2910 static inline uint8_t 2911 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2912 { 2913 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2914 2915 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 2916 } 2917 2918 static inline uint8_t 2919 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2920 { 2921 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2922 2923 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 2924 } 2925 2926 /** 2927 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 2928 * @hal_soc_hdl: HAL SoC handle 2929 * @ring_desc: REO ring descriptor 2930 * @prev_pn: Buffer to populate the previous PN 2931 * 2932 * Return: None 2933 */ 2934 static inline void 2935 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 2936 uint64_t *prev_pn) 2937 { 2938 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2939 2940 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 2941 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 2942 } 2943 2944 /** 2945 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 2946 * from rx mpdu info 2947 * @buf: pointer to rx_pkt_tlvs 2948 * 2949 * No input validdataion, since this function is supposed to be 2950 * called from fastpath. 2951 * 2952 * Return: ampdu flag 2953 */ 2954 static inline bool 2955 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2956 { 2957 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2958 2959 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 2960 } 2961 2962 #ifdef REO_SHARED_QREF_TABLE_EN 2963 /** 2964 * hal_reo_shared_qaddr_write(): Write REo tid queue addr 2965 * LUT shared by SW and HW at the index given by peer id 2966 * and tid. 2967 * 2968 * @hal_soc: hal soc pointer 2969 * @reo_qref_addr: pointer to index pointed to be peer_id 2970 * and tid 2971 * @tid: tid queue number 2972 * @hw_qdesc_paddr: reo queue addr 2973 */ 2974 static inline void 2975 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 2976 uint16_t peer_id, 2977 int tid, 2978 qdf_dma_addr_t hw_qdesc_paddr) 2979 { 2980 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2981 2982 if (hal_soc->ops->hal_reo_shared_qaddr_write) 2983 return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl, 2984 peer_id, tid, hw_qdesc_paddr); 2985 } 2986 2987 /** 2988 * hal_reo_shared_qaddr_init(): Initialize reo qref LUT 2989 * @hal_soc: Hal soc pointer 2990 * @qref_reset: reset qref LUT 2991 * 2992 * Write MLO and Non MLO table start addr to HW reg 2993 * 2994 * Return: void 2995 */ 2996 static inline void 2997 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) 2998 { 2999 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3000 3001 if (hal_soc->ops->hal_reo_shared_qaddr_init) 3002 return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl, 3003 qref_reset); 3004 } 3005 3006 /** 3007 * hal_reo_shared_qaddr_cache_clear(): Set and unset 'clear_qdesc_array' 3008 * bit in reo reg for shared qref feature. This is done for every MLO 3009 * connection to clear HW reo internal storage for clearing stale entry 3010 * of prev peer having same peer id 3011 * 3012 * @hal_soc: Hal soc pointer 3013 * 3014 * Write MLO and Non MLO table start addr to HW reg 3015 * 3016 * Return: void 3017 */ 3018 static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) 3019 { 3020 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3021 3022 if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear) 3023 return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl); 3024 } 3025 3026 #else 3027 static inline void 3028 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 3029 uint16_t peer_id, 3030 int tid, 3031 qdf_dma_addr_t hw_qdesc_paddr) {} 3032 static inline void 3033 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {} 3034 3035 static inline void 3036 hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {} 3037 3038 #endif /* REO_SHARED_QREF_TABLE_EN */ 3039 3040 static inline uint8_t 3041 hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl) 3042 { 3043 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3044 3045 return hal->reo_qref.reo_qref_table_en; 3046 } 3047 3048 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3049 static inline uint8_t 3050 hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3051 { 3052 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3053 3054 return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf); 3055 } 3056 #endif 3057 3058 static inline uint32_t 3059 hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3060 { 3061 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3062 3063 return hal_soc->ops->hal_rx_tlv_l3_type_get ? 3064 hal_soc->ops->hal_rx_tlv_l3_type_get(buf) : 3065 HAL_RX_TLV_L3_TYPE_INVALID; 3066 } 3067 3068 /** 3069 * hal_get_tsf_time() - Get tsf time 3070 * @hal_soc_hdl: HAL soc handle 3071 * @mac_id: mac_id 3072 * @tsf: pointer to update tsf value 3073 * @tsf_sync_soc_time: pointer to update tsf sync time 3074 * 3075 * Return: None. 3076 */ 3077 static inline void 3078 hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 3079 uint32_t mac_id, uint64_t *tsf, 3080 uint64_t *tsf_sync_soc_time) 3081 { 3082 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3083 3084 if (hal_soc->ops->hal_get_tsf_time) 3085 hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id, 3086 tsf, tsf_sync_soc_time); 3087 } 3088 #endif /* _HAL_RX_H */ 3089