1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_RX_H_ 21 #define _HAL_RX_H_ 22 23 #include <hal_api.h> 24 #include "hal_rx_hw_defines.h" 25 #include "hal_hw_headers.h" 26 27 /************************************* 28 * Ring desc offset/shift/masks 29 *************************************/ 30 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 31 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 32 #define HAL_RX_LSB(block, field) block##_##field##_LSB 33 #define HAL_RX_MASK(block, field) block##_##field##_MASK 34 #define HAL_RX_TLV_L3_TYPE_INVALID 0xFFFF 35 36 #define HAL_RX_GET(_ptr, block, field) \ 37 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 38 HAL_RX_MASK(block, field)) >> \ 39 HAL_RX_LSB(block, field)) 40 41 #define HAL_RX_GET_64(_ptr, block, field) \ 42 (((*((volatile uint64_t *)(_ptr) + \ 43 (HAL_RX_OFFSET(block, field) >> 3))) & \ 44 HAL_RX_MASK(block, field)) >> \ 45 HAL_RX_LSB(block, field)) 46 47 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 48 (*(uint32_t *)(((uint8_t *)_ptr) + \ 49 _wrd ## _ ## _field ## _OFFSET) |= \ 50 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 51 _wrd ## _ ## _field ## _MASK)) 52 53 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 54 #ifndef RX_DATA_BUFFER_SIZE 55 #define RX_DATA_BUFFER_SIZE 2048 56 #endif 57 58 #ifndef RX_MONITOR_BUFFER_SIZE 59 #define RX_MONITOR_BUFFER_SIZE 2048 60 #endif 61 62 #define RXDMA_OPTIMIZATION 63 64 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 65 * including buffer reservation, buffer alignment and skb shared info size. 66 */ 67 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 68 #define RX_MON_STATUS_BUF_ALIGN 128 69 #define RX_MON_STATUS_BUF_RESERVATION 128 70 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 71 (RX_MON_STATUS_BUF_RESERVATION + \ 72 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 73 74 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 75 76 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 77 #define HAL_RX_NON_QOS_TID 16 78 79 enum { 80 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 81 HAL_HW_RX_DECAP_FORMAT_NWIFI, 82 HAL_HW_RX_DECAP_FORMAT_ETH2, 83 HAL_HW_RX_DECAP_FORMAT_8023, 84 }; 85 86 /** 87 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 88 * 89 * @reo_psh_rsn: REO push reason 90 * @reo_err_code: REO Error code 91 * @rxdma_psh_rsn: RXDMA push reason 92 * @rxdma_err_code: RXDMA Error code 93 * @reserved_1: Reserved bits 94 * @wbm_err_src: WBM error source 95 * @pool_id: pool ID, indicates which rxdma pool 96 * @reserved_2: Reserved bits 97 */ 98 struct hal_wbm_err_desc_info { 99 uint16_t reo_psh_rsn:2, 100 reo_err_code:5, 101 rxdma_psh_rsn:2, 102 rxdma_err_code:5, 103 reserved_1:2; 104 uint8_t wbm_err_src:3, 105 pool_id:2, 106 msdu_continued:1, 107 reserved_2:2; 108 }; 109 110 /** 111 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 112 * @first_buffer: First buffer of MSDU 113 * @last_buffer: Last buffer of MSDU 114 * @is_decap_raw: Is RAW Frame 115 * @reserved_1: Reserved 116 * 117 * MSDU with continuation: 118 * ----------------------------------------------------------- 119 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 120 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 121 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 122 * ----------------------------------------------------------- 123 * 124 * Single buffer MSDU: 125 * ------------------ 126 * | first_buffer:1 | 127 * | last_buffer :1 | 128 * | is_decap_raw:1/0 | 129 * ------------------ 130 */ 131 struct hal_rx_mon_dest_buf_info { 132 uint8_t first_buffer:1, 133 last_buffer:1, 134 is_decap_raw:1, 135 reserved_1:5; 136 }; 137 138 /** 139 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 140 * 141 * @l3_hdr_pad: l3 header padding 142 * @reserved: Reserved bits 143 * @sa_sw_peer_id: sa sw peer id 144 * @sa_idx: sa index 145 * @da_idx: da index 146 */ 147 struct hal_rx_msdu_metadata { 148 uint32_t l3_hdr_pad:16, 149 sa_sw_peer_id:16; 150 uint32_t sa_idx:16, 151 da_idx:16; 152 }; 153 154 struct hal_proto_params { 155 uint8_t tcp_proto; 156 uint8_t udp_proto; 157 uint8_t ipv6_proto; 158 }; 159 160 /** 161 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 162 * 163 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 164 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 165 */ 166 enum hal_reo_error_status { 167 HAL_REO_ERROR_DETECTED = 0, 168 HAL_REO_ROUTING_INSTRUCTION = 1, 169 }; 170 171 /** 172 * @msdu_flags: [0] first_msdu_in_mpdu 173 * [1] last_msdu_in_mpdu 174 * [2] msdu_continuation - MSDU spread across buffers 175 * [23] sa_is_valid - SA match in peer table 176 * [24] sa_idx_timeout - Timeout while searching for SA match 177 * [25] da_is_valid - Used to identtify intra-bss forwarding 178 * [26] da_is_MCBC 179 * [27] da_idx_timeout - Timeout while searching for DA match 180 * 181 */ 182 struct hal_rx_msdu_desc_info { 183 uint32_t msdu_flags; 184 uint16_t msdu_len; /* 14 bits for length */ 185 }; 186 187 /** 188 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 189 * 190 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 191 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 192 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 193 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 194 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 195 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 196 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 197 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 198 * @ HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 199 */ 200 enum hal_rx_msdu_desc_flags { 201 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 202 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 203 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 204 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 205 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 206 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 207 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 208 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 209 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 210 }; 211 212 /* 213 * @msdu_count: no. of msdus in the MPDU 214 * @mpdu_seq: MPDU sequence number 215 * @mpdu_flags [0] Fragment flag 216 * [1] MPDU_retry_bit 217 * [2] AMPDU flag 218 * [3] raw_ampdu 219 * @peer_meta_data: Upper bits containing peer id, vdev id 220 * @bar_frame: indicates if received frame is a bar frame 221 * @tid: tid value of received MPDU 222 */ 223 struct hal_rx_mpdu_desc_info { 224 uint16_t msdu_count; 225 uint16_t mpdu_seq; /* 12 bits for length */ 226 uint32_t mpdu_flags; 227 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 228 uint16_t bar_frame; 229 uint8_t tid:4, 230 reserved:4; 231 }; 232 233 /** 234 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 235 * 236 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 237 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 238 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 239 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 240 * @ HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field 241 */ 242 enum hal_rx_mpdu_desc_flags { 243 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 244 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 245 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 246 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30), 247 HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31) 248 }; 249 250 /* Return Buffer manager ID */ 251 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 252 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 253 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 254 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 255 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 256 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 257 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 258 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 259 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 260 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 261 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 262 263 #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id) 264 265 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 266 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 267 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 268 269 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 270 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 271 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 272 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 273 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 274 275 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 276 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 277 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 278 279 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 280 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 281 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 282 283 /* 284 * macro to set the LSW of the nbuf data physical address 285 * to the rxdma ring entry 286 */ 287 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 288 ((*(((unsigned int *) buff_addr_info) + \ 289 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 290 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 291 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 292 293 /* 294 * macro to set the LSB of MSW of the nbuf data physical address 295 * to the rxdma ring entry 296 */ 297 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 298 ((*(((unsigned int *) buff_addr_info) + \ 299 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 300 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 301 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 302 303 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 304 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 305 306 /* 307 * macro to get the invalid bit for sw cookie 308 */ 309 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 310 ((*(((unsigned int *)buff_addr_info) + \ 311 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 312 HAL_RX_COOKIE_INVALID_MASK) 313 314 /* 315 * macro to set the invalid bit for sw cookie 316 */ 317 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 318 ((*(((unsigned int *)buff_addr_info) + \ 319 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 320 HAL_RX_COOKIE_INVALID_MASK) 321 322 /* 323 * macro to reset the invalid bit for sw cookie 324 */ 325 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 326 ((*(((unsigned int *)buff_addr_info) + \ 327 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 328 ~HAL_RX_COOKIE_INVALID_MASK) 329 330 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 331 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 332 (((struct reo_destination_ring *) \ 333 reo_desc)->buf_or_link_desc_addr_info))) 334 335 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 336 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 337 (((struct reo_destination_ring *) \ 338 reo_desc)->buf_or_link_desc_addr_info))) 339 340 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 341 342 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 343 ((*(((unsigned int *)buff_addr_info) + \ 344 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 345 HAL_RX_LINK_COOKIE_INVALID_MASK) 346 347 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 348 ((*(((unsigned int *)buff_addr_info) + \ 349 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 350 HAL_RX_LINK_COOKIE_INVALID_MASK) 351 352 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 353 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 354 (((struct reo_destination_ring *) \ 355 reo_desc)->buf_or_link_desc_addr_info))) 356 357 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 358 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 359 (((struct reo_destination_ring *) \ 360 reo_desc)->buf_or_link_desc_addr_info))) 361 #endif 362 363 /* TODO: Convert the following structure fields accesseses to offsets */ 364 365 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 366 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 367 (((struct reo_destination_ring *) \ 368 reo_desc)->buf_or_link_desc_addr_info))) 369 370 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 371 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 372 (((struct reo_destination_ring *) \ 373 reo_desc)->buf_or_link_desc_addr_info))) 374 375 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 376 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 377 (((struct reo_destination_ring *) \ 378 reo_desc)->buf_or_link_desc_addr_info))) 379 380 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 381 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 382 _field, _val) 383 384 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 385 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 386 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 387 388 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 389 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 390 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 391 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 392 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 393 394 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 395 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 396 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 397 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 398 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 399 400 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 401 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 402 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 403 404 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 405 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 406 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 407 408 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 409 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 410 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 411 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 412 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 413 414 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 415 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 416 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 417 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 418 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 419 420 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 421 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 422 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 423 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 424 425 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 426 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 427 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 428 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 429 430 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 431 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 432 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 433 434 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 435 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 436 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 437 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 438 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 439 440 static inline uint32_t 441 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 442 rx_msdu_desc_info_t msdu_desc_info_hdl) 443 { 444 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 445 446 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 447 } 448 449 /* 450 * Structures & Macros to obtain fields from the TLV's in the Rx packet 451 * pre-header. 452 */ 453 454 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 455 void *hw_desc_addr) 456 { 457 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 458 459 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 460 } 461 462 /** 463 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 464 * @hal_soc_hdl: hal soc handle 465 * @desc_addr: ring descriptor 466 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 467 * 468 * Return: None 469 */ 470 static inline void 471 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 472 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 473 { 474 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 475 476 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 477 mpdu_desc_info); 478 } 479 480 #define HAL_RX_NUM_MSDU_DESC 6 481 #define HAL_RX_MAX_SAVED_RING_DESC 16 482 483 /* TODO: rework the structure */ 484 struct hal_rx_msdu_list { 485 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 486 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 487 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 488 /* physical address of the msdu */ 489 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 490 }; 491 492 struct hal_buf_info { 493 uint64_t paddr; 494 uint32_t sw_cookie; 495 uint8_t rbm; 496 }; 497 498 /* This special cookie value will be used to indicate FW allocated buffers 499 * received through RXDMA2SW ring for RXDMA WARs 500 */ 501 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 502 503 /** 504 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 505 * 506 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 507 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 508 * descriptor 509 */ 510 enum hal_rx_reo_buf_type { 511 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 512 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 513 }; 514 515 /** 516 * enum hal_reo_error_code: Error code describing the type of error detected 517 * 518 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 519 * REO_ENTRANCE ring is set to 0 520 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 521 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 522 * having been setup 523 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 524 * Retry bit set: duplicate frame 525 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 526 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 527 * received with 2K jump in SN 528 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 529 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 530 * with SN falling within the OOR window 531 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 532 * OOR window 533 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 534 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 535 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 536 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 537 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 538 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 539 * of the pn_error_detected_flag been set in the REO Queue descriptor 540 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 541 * the queue descriptor(address) being blocked as SW/FW seems to be currently 542 * in the process of making updates to this descriptor 543 */ 544 enum hal_reo_error_code { 545 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 546 HAL_REO_ERR_QUEUE_DESC_INVALID, 547 HAL_REO_ERR_AMPDU_IN_NON_BA, 548 HAL_REO_ERR_NON_BA_DUPLICATE, 549 HAL_REO_ERR_BA_DUPLICATE, 550 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 551 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 552 HAL_REO_ERR_REGULAR_FRAME_OOR, 553 HAL_REO_ERR_BAR_FRAME_OOR, 554 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 555 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 556 HAL_REO_ERR_PN_CHECK_FAILED, 557 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 558 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 559 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 560 HAL_REO_ERR_MAX 561 }; 562 563 /** 564 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 565 * 566 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 567 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 568 * overflow 569 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 570 * incomplete 571 * MPDU from the PHY 572 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 573 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 574 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 575 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 576 * encrypted but wasn’t 577 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 578 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 579 * the max allowed 580 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 581 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 582 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 583 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 584 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 585 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 586 * @ HAL_RXDMA_AMSDU_FRAGMENT : Rx PCU reported A-MSDU 587 * present as well as a fragmented MPDU 588 * @ HAL_RXDMA_MULTICAST_ECHO : RX OLE reported a multicast echo 589 * @ HAL_RXDMA_AMSDU_ADDR_MISMATCH : RX OLE reported AMSDU address mismatch 590 * @ HAL_RXDMA_UNAUTHORIZED_WDS : RX PCU reported unauthorized wds 591 * @ HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS :RX PCU reported group cast AMSDU or WDS 592 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 593 */ 594 enum hal_rxdma_error_code { 595 HAL_RXDMA_ERR_OVERFLOW = 0, 596 HAL_RXDMA_ERR_MPDU_LENGTH, 597 HAL_RXDMA_ERR_FCS, 598 HAL_RXDMA_ERR_DECRYPT, 599 HAL_RXDMA_ERR_TKIP_MIC, 600 HAL_RXDMA_ERR_UNENCRYPTED, 601 HAL_RXDMA_ERR_MSDU_LEN, 602 HAL_RXDMA_ERR_MSDU_LIMIT, 603 HAL_RXDMA_ERR_WIFI_PARSE, 604 HAL_RXDMA_ERR_AMSDU_PARSE, 605 HAL_RXDMA_ERR_SA_TIMEOUT, 606 HAL_RXDMA_ERR_DA_TIMEOUT, 607 HAL_RXDMA_ERR_FLOW_TIMEOUT, 608 HAL_RXDMA_ERR_FLUSH_REQUEST, 609 HAL_RXDMA_AMSDU_FRAGMENT, 610 HAL_RXDMA_MULTICAST_ECHO, 611 HAL_RXDMA_AMSDU_ADDR_MISMATCH, 612 HAL_RXDMA_UNAUTHORIZED_WDS, 613 HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS, 614 HAL_RXDMA_ERR_WAR = 31, 615 HAL_RXDMA_ERR_MAX 616 }; 617 618 /** 619 * HW BM action settings in WBM release ring 620 */ 621 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 622 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 623 624 /** 625 * enum hal_rx_wbm_error_source: Indicates which module initiated the 626 * release of this buffer or descriptor 627 * 628 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 629 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 630 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 631 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 632 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 633 */ 634 enum hal_rx_wbm_error_source { 635 HAL_RX_WBM_ERR_SRC_TQM = 0, 636 HAL_RX_WBM_ERR_SRC_RXDMA, 637 HAL_RX_WBM_ERR_SRC_REO, 638 HAL_RX_WBM_ERR_SRC_FW, 639 HAL_RX_WBM_ERR_SRC_SW, 640 }; 641 642 /** 643 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 644 * released 645 * 646 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 647 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 648 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 649 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 650 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 651 */ 652 enum hal_rx_wbm_buf_type { 653 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 654 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 655 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 656 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 657 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 658 }; 659 660 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 661 662 //#include "hal_rx_be.h" 663 664 /* 665 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 666 * 667 * @nbuf: Network buffer 668 * Returns: flag to indicate whether the nbuf has MC/BC address 669 */ 670 static inline uint32_t 671 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 672 qdf_nbuf_t nbuf) 673 { 674 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 675 676 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 677 } 678 679 /** 680 * hal_rx_priv_info_set_in_tlv(): Save the private info to 681 * the reserved bytes of rx_tlv_hdr 682 * @buf: start of rx_tlv_hdr 683 * @wbm_er_info: hal_wbm_err_desc_info structure 684 * Return: void 685 */ 686 static inline void 687 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 688 uint8_t *buf, uint8_t *priv_data, 689 uint32_t len) 690 { 691 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 692 693 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 694 priv_data, 695 len); 696 } 697 698 /* 699 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 700 * reo_entrance_ring descriptor 701 * 702 * @reo_ent_desc: reo_entrance_ring descriptor 703 * Returns: value of rxdma_push_reason 704 */ 705 static inline 706 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 707 { 708 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 709 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 710 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 711 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 712 } 713 714 /** 715 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 716 * reo_entrance_ring descriptor 717 * @reo_ent_desc: reo_entrance_ring descriptor 718 * Return: value of rxdma_error_code 719 */ 720 static inline 721 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 722 { 723 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 724 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 725 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 726 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 727 } 728 729 /** 730 * hal_rx_priv_info_get_from_tlv(): retrieve the private data from 731 * the reserved bytes of rx_tlv_hdr. 732 * @buf: start of rx_tlv_hdr 733 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 734 * Return: void 735 */ 736 static inline void 737 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 738 uint8_t *buf, uint8_t *wbm_er_info, 739 uint32_t len) 740 { 741 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 742 743 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 744 wbm_er_info, 745 len); 746 } 747 748 static inline void 749 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 750 uint16_t *rx_mon_pkt_tlv_size) 751 { 752 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 753 754 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 755 rx_mon_pkt_tlv_size); 756 } 757 758 /* 759 * hal_rx_encryption_info_valid(): Returns encryption type. 760 * 761 * @hal_soc_hdl: hal soc handle 762 * @buf: rx_tlv_hdr of the received packet 763 * 764 * Return: encryption type 765 */ 766 static inline uint32_t 767 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 768 { 769 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 770 771 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 772 } 773 774 /* 775 * hal_rx_print_pn: Prints the PN of rx packet. 776 * @hal_soc_hdl: hal soc handle 777 * @buf: rx_tlv_hdr of the received packet 778 * 779 * Return: void 780 */ 781 static inline void 782 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 783 { 784 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 785 786 hal_soc->ops->hal_rx_print_pn(buf); 787 } 788 789 /** 790 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 791 * l3_header padding from rx_msdu_end TLV 792 * 793 * @buf: pointer to the start of RX PKT TLV headers 794 * Return: number of l3 header padding bytes 795 */ 796 static inline uint32_t 797 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 798 uint8_t *buf) 799 { 800 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 801 802 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 803 } 804 805 /** 806 * hal_rx_msdu_end_sa_idx_get(): API to get the 807 * sa_idx from rx_msdu_end TLV 808 * 809 * @ buf: pointer to the start of RX PKT TLV headers 810 * Return: sa_idx (SA AST index) 811 */ 812 static inline uint16_t 813 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 814 uint8_t *buf) 815 { 816 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 817 818 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 819 } 820 821 /** 822 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 823 * sa_is_valid bit from rx_msdu_end TLV 824 * 825 * @ buf: pointer to the start of RX PKT TLV headers 826 * Return: sa_is_valid bit 827 */ 828 static inline uint8_t 829 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 830 uint8_t *buf) 831 { 832 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 833 834 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 835 } 836 837 /** 838 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 839 * from rx_msdu_start TLV 840 * 841 * @buf: pointer to the start of RX PKT TLV headers 842 * @len: msdu length 843 * 844 * Return: none 845 */ 846 static inline void 847 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 848 uint32_t len) 849 { 850 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 851 852 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 853 } 854 855 /** 856 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 857 * 858 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 859 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 860 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 861 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 862 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 863 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 864 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 865 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 866 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 867 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 868 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 869 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 870 */ 871 enum hal_rx_mpdu_info_sw_frame_group_id_type { 872 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 873 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 874 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 875 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 876 HAL_MPDU_SW_FRAME_GROUP_MGMT, 877 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 878 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 879 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 880 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 881 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 882 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 883 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 884 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 885 }; 886 887 /** 888 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 889 * Retrieve qos control valid bit from the tlv. 890 * @hal_soc_hdl: hal_soc handle 891 * @buf: pointer to rx pkt TLV. 892 * 893 * Return: qos control value. 894 */ 895 static inline uint32_t 896 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 897 hal_soc_handle_t hal_soc_hdl, 898 uint8_t *buf) 899 { 900 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 901 902 if ((!hal_soc) || (!hal_soc->ops)) { 903 hal_err("hal handle is NULL"); 904 QDF_BUG(0); 905 return QDF_STATUS_E_INVAL; 906 } 907 908 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 909 return hal_soc->ops-> 910 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 911 912 return QDF_STATUS_E_INVAL; 913 } 914 915 /** 916 * hal_rx_is_unicast: check packet is unicast frame or not. 917 * @hal_soc_hdl: hal_soc handle 918 * @buf: pointer to rx pkt TLV. 919 * 920 * Return: true on unicast. 921 */ 922 static inline bool 923 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 924 { 925 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 926 927 return hal_soc->ops->hal_rx_is_unicast(buf); 928 } 929 930 /** 931 * hal_rx_tid_get: get tid based on qos control valid. 932 * @hal_soc_hdl: hal soc handle 933 * @buf: pointer to rx pkt TLV. 934 * 935 * Return: tid 936 */ 937 static inline uint32_t 938 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 939 { 940 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 941 942 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 943 } 944 945 /** 946 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 947 * @hal_soc_hdl: hal soc handle 948 * @buf: pointer to rx pkt TLV. 949 * 950 * Return: sw peer_id 951 */ 952 static inline uint32_t 953 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 954 uint8_t *buf) 955 { 956 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 957 958 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 959 } 960 961 /** 962 * hal_rx_tlv_peer_meta_data_get() - Retrieve PEER_META_DATA 963 * @hal_soc_hdl: hal soc handle 964 * @buf: pointer to rx pkt TLV. 965 * 966 * Return: peer meta data 967 */ 968 static inline uint32_t 969 hal_rx_tlv_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl, 970 uint8_t *buf) 971 { 972 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 973 974 return hal_soc->ops->hal_rx_tlv_peer_meta_data_get(buf); 975 } 976 977 /* 978 * hal_rx_mpdu_get_tods(): API to get the tods info 979 * from rx_mpdu_start 980 * 981 * @buf: pointer to the start of RX PKT TLV header 982 * Return: uint32_t(to_ds) 983 */ 984 985 static inline uint32_t 986 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 987 { 988 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 989 990 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 991 } 992 993 994 /* 995 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 996 * from rx_mpdu_start 997 * @hal_soc_hdl: hal soc handle 998 * @buf: pointer to the start of RX PKT TLV header 999 * 1000 * Return: uint32_t(fr_ds) 1001 */ 1002 static inline uint32_t 1003 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1004 { 1005 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1006 1007 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1008 } 1009 1010 /* 1011 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1012 * @hal_soc_hdl: hal soc handle 1013 * @buf: pointer to the start of RX PKT TLV headera 1014 * @mac_addr: pointer to mac address 1015 * 1016 * Return: success/failure 1017 */ 1018 static inline 1019 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1020 uint8_t *buf, uint8_t *mac_addr) 1021 { 1022 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1023 1024 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1025 } 1026 1027 /* 1028 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1029 * in the packet 1030 * @hal_soc_hdl: hal soc handle 1031 * @buf: pointer to the start of RX PKT TLV header 1032 * @mac_addr: pointer to mac address 1033 * 1034 * Return: success/failure 1035 */ 1036 static inline 1037 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1038 uint8_t *buf, uint8_t *mac_addr) 1039 { 1040 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1041 1042 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1043 } 1044 1045 /* 1046 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1047 * in the packet 1048 * @hal_soc_hdl: hal soc handle 1049 * @buf: pointer to the start of RX PKT TLV header 1050 * @mac_addr: pointer to mac address 1051 * 1052 * Return: success/failure 1053 */ 1054 static inline 1055 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1056 uint8_t *buf, uint8_t *mac_addr) 1057 { 1058 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1059 1060 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1061 } 1062 1063 /* 1064 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1065 * in the packet 1066 * @hal_soc_hdl: hal_soc handle 1067 * @buf: pointer to the start of RX PKT TLV header 1068 * @mac_addr: pointer to mac address 1069 * Return: success/failure 1070 */ 1071 static inline 1072 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1073 uint8_t *buf, uint8_t *mac_addr) 1074 { 1075 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1076 1077 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1078 } 1079 1080 /** 1081 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1082 * from rx_msdu_end TLV 1083 * 1084 * @ buf: pointer to the start of RX PKT TLV headers 1085 * Return: da index 1086 */ 1087 static inline uint16_t 1088 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1089 { 1090 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1091 1092 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1093 } 1094 1095 /** 1096 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1097 * from rx_msdu_end TLV 1098 * @hal_soc_hdl: hal soc handle 1099 * @ buf: pointer to the start of RX PKT TLV headers 1100 * 1101 * Return: da_is_valid 1102 */ 1103 static inline uint8_t 1104 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1105 uint8_t *buf) 1106 { 1107 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1108 1109 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1110 } 1111 1112 /** 1113 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1114 * from rx_msdu_end TLV 1115 * 1116 * @buf: pointer to the start of RX PKT TLV headers 1117 * 1118 * Return: da_is_mcbc 1119 */ 1120 static inline uint8_t 1121 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1122 { 1123 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1124 1125 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1126 } 1127 1128 /** 1129 * hal_rx_msdu_end_is_tkip_mic_err: API to check if pkt has mic error 1130 * from rx_msdu_end TLV 1131 * 1132 * @buf: pointer to the start of RX PKT TLV headers 1133 * 1134 * Return: tkip_mic_err 1135 */ 1136 static inline uint8_t 1137 hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl, 1138 uint8_t *buf) 1139 { 1140 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1141 1142 if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err) 1143 return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf); 1144 else 1145 return 0; 1146 } 1147 1148 /** 1149 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1150 * from rx_msdu_end TLV 1151 * @hal_soc_hdl: hal soc handle 1152 * @buf: pointer to the start of RX PKT TLV headers 1153 * 1154 * Return: first_msdu 1155 */ 1156 static inline uint8_t 1157 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1158 uint8_t *buf) 1159 { 1160 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1161 1162 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1163 } 1164 1165 /** 1166 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1167 * from rx_msdu_end TLV 1168 * @hal_soc_hdl: hal soc handle 1169 * @buf: pointer to the start of RX PKT TLV headers 1170 * 1171 * Return: last_msdu 1172 */ 1173 static inline uint8_t 1174 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1175 uint8_t *buf) 1176 { 1177 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1178 1179 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1180 } 1181 1182 /** 1183 * hal_rx_msdu_cce_match_get: API to get CCE match 1184 * from rx_msdu_end TLV 1185 * @buf: pointer to the start of RX PKT TLV headers 1186 * Return: cce_meta_data 1187 */ 1188 static inline bool 1189 hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl, 1190 uint8_t *buf) 1191 { 1192 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1193 1194 return hal_soc->ops->hal_rx_msdu_cce_match_get(buf); 1195 } 1196 1197 /** 1198 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1199 * from rx_msdu_end TLV 1200 * @buf: pointer to the start of RX PKT TLV headers 1201 * Return: cce_meta_data 1202 */ 1203 static inline uint16_t 1204 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1205 uint8_t *buf) 1206 { 1207 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1208 1209 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1210 } 1211 1212 /******************************************************************************* 1213 * RX REO ERROR APIS 1214 ******************************************************************************/ 1215 1216 /** 1217 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1218 * @msdu_link_ptr - msdu link ptr 1219 * @hal - pointer to hal_soc 1220 * Return - Pointer to rx_msdu_details structure 1221 * 1222 */ 1223 static inline 1224 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1225 struct hal_soc *hal_soc) 1226 { 1227 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1228 } 1229 1230 /** 1231 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1232 * @msdu_details_ptr - Pointer to msdu_details_ptr 1233 * @hal - pointer to hal_soc 1234 * Return - Pointer to rx_msdu_desc_info structure. 1235 * 1236 */ 1237 static inline 1238 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1239 struct hal_soc *hal_soc) 1240 { 1241 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1242 } 1243 1244 /** 1245 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1246 * cookie from the REO destination ring element 1247 * 1248 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1249 * the current descriptor 1250 * @ buf_info: structure to return the buffer information 1251 * Return: void 1252 */ 1253 static inline 1254 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1255 hal_ring_desc_t rx_desc, 1256 struct hal_buf_info *buf_info) 1257 { 1258 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1259 1260 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1261 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1262 rx_desc, 1263 buf_info); 1264 1265 } 1266 1267 /** 1268 * hal_rx_wbm_rel_buf_paddr_get: Gets the physical address and 1269 * cookie from the WBM release ring element 1270 * 1271 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1272 * the current descriptor 1273 * @ buf_info: structure to return the buffer information 1274 * Return: void 1275 */ 1276 static inline 1277 void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1278 hal_ring_desc_t rx_desc, 1279 struct hal_buf_info *buf_info) 1280 { 1281 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1282 1283 if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get) 1284 return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc, 1285 buf_info); 1286 } 1287 1288 /** 1289 * hal_rx_buf_cookie_rbm_get: Gets the physical address and 1290 * cookie from the REO entrance ring element 1291 * 1292 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1293 * the current descriptor 1294 * @ buf_info: structure to return the buffer information 1295 * @ msdu_cnt: pointer to msdu count in MPDU 1296 * Return: void 1297 */ 1298 static inline 1299 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1300 uint32_t *buf_addr_info, 1301 struct hal_buf_info *buf_info) 1302 { 1303 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1304 1305 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1306 buf_addr_info, 1307 buf_info); 1308 } 1309 1310 /** 1311 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1312 * from the MSDU link descriptor 1313 * 1314 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1315 * MSDU link descriptor (struct rx_msdu_link) 1316 * 1317 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1318 * 1319 * @num_msdus: Number of MSDUs in the MPDU 1320 * 1321 * Return: void 1322 */ 1323 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1324 void *msdu_link_desc, 1325 struct hal_rx_msdu_list *msdu_list, 1326 uint16_t *num_msdus) 1327 { 1328 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1329 struct rx_msdu_details *msdu_details; 1330 struct rx_msdu_desc_info *msdu_desc_info; 1331 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1332 int i; 1333 struct hal_buf_info buf_info; 1334 1335 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1336 1337 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1338 __func__, __LINE__, msdu_link, msdu_details); 1339 1340 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1341 /* num_msdus received in mpdu descriptor may be incorrect 1342 * sometimes due to HW issue. Check msdu buffer address also 1343 */ 1344 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1345 &msdu_details[i].buffer_addr_info_details) == 0)) 1346 break; 1347 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1348 &msdu_details[i].buffer_addr_info_details) == 0) { 1349 /* set the last msdu bit in the prev msdu_desc_info */ 1350 msdu_desc_info = 1351 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1352 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1353 break; 1354 } 1355 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1356 hal_soc); 1357 1358 /* set first MSDU bit or the last MSDU bit */ 1359 if (!i) 1360 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1361 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1362 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1363 1364 msdu_list->msdu_info[i].msdu_flags = 1365 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1366 msdu_list->msdu_info[i].msdu_len = 1367 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1368 1369 /* addr field in buf_info will not be valid */ 1370 hal_rx_buf_cookie_rbm_get( 1371 hal_soc_hdl, 1372 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1373 &buf_info); 1374 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1375 msdu_list->rbm[i] = buf_info.rbm; 1376 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1377 &msdu_details[i].buffer_addr_info_details) | 1378 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1379 &msdu_details[i].buffer_addr_info_details) << 32; 1380 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1381 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1382 } 1383 *num_msdus = i; 1384 } 1385 1386 /** 1387 * hal_rx_is_pn_error() - Indicate if this error was caused by a 1388 * PN check failure 1389 * 1390 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 1391 * 1392 * Return: true: error caused by PN check, false: other error 1393 */ 1394 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1395 { 1396 1397 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1398 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1399 true : false; 1400 } 1401 1402 /** 1403 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1404 * the sequence number 1405 * 1406 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1407 * 1408 * Return: true: error caused by 2K jump, false: other error 1409 */ 1410 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1411 { 1412 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1413 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1414 true : false; 1415 } 1416 1417 /** 1418 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1419 * 1420 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1421 * 1422 * Return: true: error caused by OOR, false: other error 1423 */ 1424 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1425 { 1426 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1427 true : false; 1428 } 1429 1430 /** 1431 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1432 * @error_code: error code obtained from ring descriptor. 1433 * 1434 * Return: true, if the error code is 2k-jump or OOR 1435 * false, for other error codes. 1436 */ 1437 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1438 { 1439 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1440 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1441 true : false; 1442 } 1443 1444 /** 1445 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1446 * @hal_desc: hardware descriptor pointer 1447 * 1448 * This function will print wbm release descriptor 1449 * 1450 * Return: none 1451 */ 1452 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1453 { 1454 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1455 uint32_t i; 1456 1457 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1458 "Current Rx wbm release descriptor is"); 1459 1460 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1461 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1462 "DWORD[i] = 0x%x", wbm_comp[i]); 1463 } 1464 } 1465 1466 /** 1467 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 1468 * 1469 * @ hal_soc_hdl : HAL version of the SOC pointer 1470 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 1471 * @ buf_addr_info : void pointer to the buffer_addr_info 1472 * @ bm_action : put in IDLE list or release to MSDU_LIST 1473 * 1474 * Return: void 1475 */ 1476 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1477 static inline 1478 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1479 void *src_srng_desc, 1480 hal_buff_addrinfo_t buf_addr_info, 1481 uint8_t bm_action) 1482 { 1483 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1484 1485 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1486 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1487 src_srng_desc, 1488 buf_addr_info, 1489 bm_action); 1490 } 1491 1492 /** 1493 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 1494 * BUFFER_ADDR_INFO, give the RX descriptor 1495 * (Assumption -- BUFFER_ADDR_INFO is the 1496 * first field in the descriptor structure) 1497 */ 1498 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1499 ((hal_link_desc_t)(ring_desc)) 1500 1501 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1502 1503 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1504 1505 /******************************************************************************* 1506 * RX WBM ERROR APIS 1507 ******************************************************************************/ 1508 1509 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1510 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1511 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1512 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1513 /** 1514 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 1515 * the frame to this release ring 1516 * 1517 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1518 * frame to this queue 1519 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1520 * received routing instructions. No error within REO was detected 1521 */ 1522 enum hal_rx_wbm_reo_push_reason { 1523 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1524 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1525 }; 1526 1527 1528 /** 1529 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 1530 * this release ring 1531 * 1532 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1533 * this frame to this queue 1534 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1535 * per received routing instructions. No error within RXDMA was detected 1536 */ 1537 enum hal_rx_wbm_rxdma_push_reason { 1538 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1539 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1540 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1541 }; 1542 1543 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 1544 uint8_t dbg_level, 1545 struct hal_soc *hal) 1546 { 1547 1548 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 1549 } 1550 1551 /** 1552 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 1553 * human readable format. 1554 * @ msdu_end: pointer the msdu_end TLV in pkt. 1555 * @ dbg_level: log level. 1556 * 1557 * Return: void 1558 */ 1559 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1560 struct rx_msdu_end *msdu_end, 1561 uint8_t dbg_level) 1562 { 1563 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 1564 } 1565 1566 /** 1567 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 1568 * structure 1569 * @hal_ring: pointer to hal_srng structure 1570 * 1571 * Return: ring_id 1572 */ 1573 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1574 { 1575 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1576 } 1577 1578 #define DOT11_SEQ_FRAG_MASK 0x000f 1579 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1580 1581 /** 1582 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 1583 * 1584 * @nbuf: Network buffer 1585 * Returns: rx fragment number 1586 */ 1587 static inline 1588 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1589 uint8_t *buf) 1590 { 1591 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1592 } 1593 1594 /* 1595 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 1596 * @hal_soc_hdl: hal soc handle 1597 * @nbuf: Network buffer 1598 * 1599 * Return: value of sequence control valid field 1600 */ 1601 static inline 1602 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1603 uint8_t *buf) 1604 { 1605 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1606 1607 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1608 } 1609 1610 /* 1611 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 1612 * @hal_soc_hdl: hal soc handle 1613 * @nbuf: Network buffer 1614 * 1615 * Returns: value of frame control valid field 1616 */ 1617 static inline 1618 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1619 uint8_t *buf) 1620 { 1621 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1622 1623 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1624 } 1625 1626 /** 1627 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 1628 * @hal_soc_hdl: hal soc handle 1629 * @nbuf: Network buffer 1630 * Returns: value of mpdu 4th address valid field 1631 */ 1632 static inline 1633 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1634 uint8_t *buf) 1635 { 1636 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1637 1638 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1639 } 1640 1641 /* 1642 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 1643 * 1644 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1645 * Returns: None 1646 */ 1647 static inline void 1648 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1649 { 1650 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1651 } 1652 1653 /** 1654 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 1655 * save it to hal_wbm_err_desc_info structure passed by caller 1656 * @wbm_desc: wbm ring descriptor 1657 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1658 * Return: void 1659 */ 1660 static inline 1661 void hal_rx_wbm_err_info_get(void *wbm_desc, 1662 struct hal_wbm_err_desc_info *wbm_er_info, 1663 hal_soc_handle_t hal_soc_hdl) 1664 { 1665 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1666 1667 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1668 } 1669 1670 /** 1671 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 1672 * bit from wbm release ring descriptor 1673 * @wbm_desc: wbm ring descriptor 1674 * Return: uint8_t 1675 */ 1676 static inline 1677 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1678 void *wbm_desc) 1679 { 1680 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1681 1682 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1683 } 1684 1685 /** 1686 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 1687 * 1688 * @ hal_soc: HAL version of the SOC pointer 1689 * @ hw_desc_addr: Start address of Rx HW TLVs 1690 * @ rs: Status for monitor mode 1691 * 1692 * Return: void 1693 */ 1694 static inline 1695 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1696 void *hw_desc_addr, 1697 struct mon_rx_status *rs) 1698 { 1699 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1700 1701 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1702 } 1703 1704 /* 1705 * hal_rx_get_tlv(): API to get the tlv 1706 * 1707 * @hal_soc: HAL version of the SOC pointer 1708 * @rx_tlv: TLV data extracted from the rx packet 1709 * Return: uint8_t 1710 */ 1711 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1712 { 1713 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1714 } 1715 1716 /* 1717 * hal_rx_msdu_start_nss_get(): API to get the NSS 1718 * Interval from rx_msdu_start 1719 * 1720 * @hal_soc: HAL version of the SOC pointer 1721 * @buf: pointer to the start of RX PKT TLV header 1722 * Return: uint32_t(nss) 1723 */ 1724 static inline 1725 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1726 { 1727 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1728 1729 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1730 } 1731 1732 /** 1733 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 1734 * human readable format. 1735 * @ msdu_start: pointer the msdu_start TLV in pkt. 1736 * @ dbg_level: log level. 1737 * 1738 * Return: void 1739 */ 1740 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1741 struct rx_msdu_start *msdu_start, 1742 uint8_t dbg_level) 1743 { 1744 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 1745 } 1746 1747 /** 1748 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 1749 * info details 1750 * 1751 * @ buf - Pointer to buffer containing rx pkt tlvs. 1752 * 1753 * 1754 */ 1755 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1756 uint8_t *buf) 1757 { 1758 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1759 1760 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1761 } 1762 1763 /* 1764 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 1765 * Interval from rx_msdu_start 1766 * 1767 * @buf: pointer to the start of RX PKT TLV header 1768 * Return: uint32_t(reception_type) 1769 */ 1770 static inline 1771 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1772 uint8_t *buf) 1773 { 1774 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1775 1776 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1777 } 1778 1779 /** 1780 * hal_reo_status_get_header_generic - Process reo desc info 1781 * @d - Pointer to reo descriptior 1782 * @b - tlv type info 1783 * @h - Pointer to hal_reo_status_header where info to be stored 1784 * @hal- pointer to hal_soc structure 1785 * Return - none. 1786 * 1787 */ 1788 static inline 1789 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1790 void *h, struct hal_soc *hal_soc) 1791 { 1792 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1793 } 1794 1795 /** 1796 * hal_rx_desc_is_first_msdu() - Check if first msdu 1797 * 1798 * @hal_soc_hdl: hal_soc handle 1799 * @hw_desc_addr: hardware descriptor address 1800 * 1801 * Return: 0 - success/ non-zero failure 1802 */ 1803 static inline 1804 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1805 void *hw_desc_addr) 1806 { 1807 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1808 1809 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1810 } 1811 1812 /** 1813 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1814 * the rx tlv fields. 1815 * @hal_soc_hdl: HAL SoC handle 1816 * @buf: rx tlv start address [To be validated by caller] 1817 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1818 * 1819 * Return: None 1820 */ 1821 static inline void 1822 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1823 uint8_t *buf, 1824 void *mpdu_desc_info_hdl) 1825 { 1826 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1827 1828 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1829 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1830 mpdu_desc_info_hdl); 1831 } 1832 1833 static inline uint32_t 1834 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1835 { 1836 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1837 1838 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1839 } 1840 1841 static inline 1842 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1843 uint8_t *rx_tlv_hdr) 1844 { 1845 uint8_t decap_format; 1846 1847 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1848 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1849 rx_tlv_hdr); 1850 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1851 return true; 1852 } 1853 1854 return false; 1855 } 1856 1857 /** 1858 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 1859 * from rx_msdu_end TLV 1860 * @buf: pointer to the start of RX PKT TLV headers 1861 * 1862 * Return: fse metadata value from MSDU END TLV 1863 */ 1864 static inline uint32_t 1865 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1866 uint8_t *buf) 1867 { 1868 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1869 1870 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1871 } 1872 1873 /** 1874 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 1875 * <struct buffer_addr_info> structure 1876 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1877 * @buf_info: structure to return the buffer information including 1878 * paddr/cookie 1879 * 1880 * return: None 1881 */ 1882 static inline 1883 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 1884 struct hal_buf_info *buf_info) 1885 { 1886 buf_info->paddr = 1887 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 1888 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 1889 } 1890 1891 /** 1892 * hal_rx_msdu_flow_idx_get: API to get flow index 1893 * from rx_msdu_end TLV 1894 * @buf: pointer to the start of RX PKT TLV headers 1895 * 1896 * Return: flow index value from MSDU END TLV 1897 */ 1898 static inline uint32_t 1899 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 1900 uint8_t *buf) 1901 { 1902 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1903 1904 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 1905 } 1906 1907 /** 1908 * hal_rx_msdu_get_reo_destination_indication: API to get reo 1909 * destination index from rx_msdu_end TLV 1910 * @buf: pointer to the start of RX PKT TLV headers 1911 * @reo_destination_indication: pointer to return value of 1912 * reo_destination_indication 1913 * 1914 * Return: reo_destination_indication value from MSDU END TLV 1915 */ 1916 static inline void 1917 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 1918 uint8_t *buf, 1919 uint32_t *reo_destination_indication) 1920 { 1921 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1922 1923 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 1924 reo_destination_indication); 1925 } 1926 1927 /** 1928 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 1929 * from rx_msdu_end TLV 1930 * @buf: pointer to the start of RX PKT TLV headers 1931 * 1932 * Return: flow index timeout value from MSDU END TLV 1933 */ 1934 static inline bool 1935 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 1936 uint8_t *buf) 1937 { 1938 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1939 1940 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 1941 } 1942 1943 /** 1944 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 1945 * from rx_msdu_end TLV 1946 * @buf: pointer to the start of RX PKT TLV headers 1947 * 1948 * Return: flow index invalid value from MSDU END TLV 1949 */ 1950 static inline bool 1951 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 1952 uint8_t *buf) 1953 { 1954 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1955 1956 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 1957 } 1958 1959 /** 1960 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 1961 * @hal_soc_hdl: hal_soc handle 1962 * @rx_tlv_hdr: Rx_tlv_hdr 1963 * @rxdma_dst_ring_desc: Rx HW descriptor 1964 * 1965 * Return: ppdu id 1966 */ 1967 static inline 1968 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 1969 void *rx_tlv_hdr, 1970 void *rxdma_dst_ring_desc) 1971 { 1972 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1973 1974 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 1975 rxdma_dst_ring_desc); 1976 } 1977 1978 /** 1979 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 1980 * @hal_soc_hdl: hal_soc handle 1981 * @buf: rx tlv address 1982 * 1983 * Return: sw peer id 1984 */ 1985 static inline 1986 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1987 uint8_t *buf) 1988 { 1989 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1990 1991 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 1992 } 1993 1994 static inline 1995 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 1996 void *link_desc_addr) 1997 { 1998 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1999 2000 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 2001 } 2002 2003 static inline 2004 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 2005 void *msdu_addr) 2006 { 2007 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2008 2009 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 2010 } 2011 2012 static inline 2013 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2014 void *hw_addr) 2015 { 2016 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2017 2018 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 2019 } 2020 2021 static inline 2022 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2023 void *hw_addr) 2024 { 2025 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2026 2027 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 2028 } 2029 2030 static inline 2031 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 2032 uint8_t *buf) 2033 { 2034 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2035 2036 return hal_soc->ops->hal_rx_get_fc_valid(buf); 2037 } 2038 2039 static inline 2040 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2041 { 2042 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2043 2044 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 2045 } 2046 2047 static inline 2048 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 2049 uint8_t *buf) 2050 { 2051 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2052 2053 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 2054 } 2055 2056 static inline 2057 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 2058 uint8_t *buf) 2059 { 2060 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2061 2062 return hal_soc->ops->hal_rx_get_filter_category(buf); 2063 } 2064 2065 static inline 2066 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 2067 uint8_t *buf) 2068 { 2069 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2070 2071 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 2072 } 2073 2074 /** 2075 * hal_reo_config(): Set reo config parameters 2076 * @soc: hal soc handle 2077 * @reg_val: value to be set 2078 * @reo_params: reo parameters 2079 * 2080 * Return: void 2081 */ 2082 static inline 2083 void hal_reo_config(struct hal_soc *hal_soc, 2084 uint32_t reg_val, 2085 struct hal_reo_params *reo_params) 2086 { 2087 hal_soc->ops->hal_reo_config(hal_soc, 2088 reg_val, 2089 reo_params); 2090 } 2091 2092 /** 2093 * hal_rx_msdu_get_flow_params: API to get flow index, 2094 * flow index invalid and flow index timeout from rx_msdu_end TLV 2095 * @buf: pointer to the start of RX PKT TLV headers 2096 * @flow_invalid: pointer to return value of flow_idx_valid 2097 * @flow_timeout: pointer to return value of flow_idx_timeout 2098 * @flow_index: pointer to return value of flow_idx 2099 * 2100 * Return: none 2101 */ 2102 static inline void 2103 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2104 uint8_t *buf, 2105 bool *flow_invalid, 2106 bool *flow_timeout, 2107 uint32_t *flow_index) 2108 { 2109 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2110 2111 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2112 flow_invalid, 2113 flow_timeout, 2114 flow_index); 2115 } 2116 2117 static inline 2118 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2119 uint8_t *buf) 2120 { 2121 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2122 2123 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2124 } 2125 2126 static inline 2127 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2128 uint8_t *buf) 2129 { 2130 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2131 2132 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2133 } 2134 2135 static inline void 2136 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2137 void *rx_tlv, 2138 void *ppdu_info) 2139 { 2140 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2141 2142 if (hal_soc->ops->hal_rx_get_bb_info) 2143 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2144 } 2145 2146 static inline void 2147 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2148 void *rx_tlv, 2149 void *ppdu_info) 2150 { 2151 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2152 2153 if (hal_soc->ops->hal_rx_get_rtt_info) 2154 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2155 } 2156 2157 /** 2158 * hal_rx_msdu_metadata_get(): API to get the 2159 * fast path information from rx_msdu_end TLV 2160 * 2161 * @ hal_soc_hdl: DP soc handle 2162 * @ buf: pointer to the start of RX PKT TLV headers 2163 * @ msdu_metadata: Structure to hold msdu end information 2164 * Return: none 2165 */ 2166 static inline void 2167 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2168 struct hal_rx_msdu_metadata *msdu_md) 2169 { 2170 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2171 2172 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2173 } 2174 2175 /** 2176 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 2177 * from rx_msdu_end TLV 2178 * @buf: pointer to the start of RX PKT TLV headers 2179 * 2180 * Return: cumulative_l4_checksum 2181 */ 2182 static inline uint16_t 2183 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2184 uint8_t *buf) 2185 { 2186 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2187 2188 if (!hal_soc || !hal_soc->ops) { 2189 hal_err("hal handle is NULL"); 2190 QDF_BUG(0); 2191 return 0; 2192 } 2193 2194 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2195 return 0; 2196 2197 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2198 } 2199 2200 /** 2201 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 2202 * from rx_msdu_end TLV 2203 * @buf: pointer to the start of RX PKT TLV headers 2204 * 2205 * Return: cumulative_ip_length 2206 */ 2207 static inline uint16_t 2208 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2209 uint8_t *buf) 2210 { 2211 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2212 2213 if (!hal_soc || !hal_soc->ops) { 2214 hal_err("hal handle is NULL"); 2215 QDF_BUG(0); 2216 return 0; 2217 } 2218 2219 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2220 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2221 2222 return 0; 2223 } 2224 2225 /** 2226 * hal_rx_get_udp_proto: API to get UDP proto field 2227 * from rx_msdu_start TLV 2228 * @buf: pointer to the start of RX PKT TLV headers 2229 * 2230 * Return: UDP proto field value 2231 */ 2232 static inline bool 2233 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2234 { 2235 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2236 2237 if (!hal_soc || !hal_soc->ops) { 2238 hal_err("hal handle is NULL"); 2239 QDF_BUG(0); 2240 return 0; 2241 } 2242 2243 if (hal_soc->ops->hal_rx_get_udp_proto) 2244 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2245 2246 return 0; 2247 } 2248 2249 /** 2250 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 2251 * from rx_msdu_end TLV 2252 * @buf: pointer to the start of RX PKT TLV headers 2253 * 2254 * Return: flow_agg_continuation bit field value 2255 */ 2256 static inline bool 2257 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2258 uint8_t *buf) 2259 { 2260 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2261 2262 if (!hal_soc || !hal_soc->ops) { 2263 hal_err("hal handle is NULL"); 2264 QDF_BUG(0); 2265 return 0; 2266 } 2267 2268 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2269 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2270 2271 return 0; 2272 } 2273 2274 /** 2275 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 2276 * rx_msdu_end TLV 2277 * @buf: pointer to the start of RX PKT TLV headers 2278 * 2279 * Return: flow_agg count value 2280 */ 2281 static inline uint8_t 2282 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2283 uint8_t *buf) 2284 { 2285 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2286 2287 if (!hal_soc || !hal_soc->ops) { 2288 hal_err("hal handle is NULL"); 2289 QDF_BUG(0); 2290 return 0; 2291 } 2292 2293 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2294 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2295 2296 return 0; 2297 } 2298 2299 /** 2300 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 2301 * @buf: pointer to the start of RX PKT TLV headers 2302 * 2303 * Return: fisa flow_agg timeout bit value 2304 */ 2305 static inline bool 2306 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2307 { 2308 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2309 2310 if (!hal_soc || !hal_soc->ops) { 2311 hal_err("hal handle is NULL"); 2312 QDF_BUG(0); 2313 return 0; 2314 } 2315 2316 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2317 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2318 2319 return 0; 2320 } 2321 2322 /** 2323 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 2324 * tag is valid 2325 * 2326 * @hal_soc_hdl: HAL SOC handle 2327 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2328 * 2329 * Return: true if RX_MPDU_START tlv tag is valid, else false 2330 */ 2331 2332 static inline uint8_t 2333 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2334 void *rx_tlv_hdr) 2335 { 2336 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2337 2338 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2339 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2340 2341 return 0; 2342 } 2343 2344 /** 2345 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 2346 * buffer addr info 2347 * @link_desc_va: pointer to current msdu link Desc 2348 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2349 * 2350 * return: None 2351 */ 2352 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2353 void *link_desc_va, 2354 struct buffer_addr_info *next_addr_info) 2355 { 2356 struct rx_msdu_link *msdu_link = link_desc_va; 2357 2358 if (!msdu_link) { 2359 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2360 return; 2361 } 2362 2363 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2364 } 2365 2366 /** 2367 * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc 2368 * buffer addr info 2369 * @link_desc_va: pointer to current msdu link Desc 2370 * 2371 * return: None 2372 */ 2373 static inline 2374 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2375 { 2376 struct rx_msdu_link *msdu_link = link_desc_va; 2377 2378 if (msdu_link) 2379 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2380 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2381 } 2382 2383 /** 2384 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 2385 * 2386 * @buf_addr_info: pointer to buf_addr_info structure 2387 * 2388 * return: true: has valid paddr, false: not. 2389 */ 2390 static inline 2391 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2392 { 2393 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2394 false : true; 2395 } 2396 2397 /** 2398 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 2399 * rx_pkt_tlvs structure 2400 * 2401 * @hal_soc_hdl: HAL SOC handle 2402 * return: msdu_end_tlv offset value 2403 */ 2404 static inline 2405 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2406 { 2407 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2408 2409 if (!hal_soc || !hal_soc->ops) { 2410 hal_err("hal handle is NULL"); 2411 QDF_BUG(0); 2412 return 0; 2413 } 2414 2415 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2416 } 2417 2418 /** 2419 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 2420 * rx_pkt_tlvs structure 2421 * 2422 * @hal_soc_hdl: HAL SOC handle 2423 * return: msdu_start_tlv offset value 2424 */ 2425 static inline 2426 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2427 { 2428 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2429 2430 if (!hal_soc || !hal_soc->ops) { 2431 hal_err("hal handle is NULL"); 2432 QDF_BUG(0); 2433 return 0; 2434 } 2435 2436 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2437 } 2438 2439 /** 2440 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 2441 * rx_pkt_tlvs structure 2442 * 2443 * @hal_soc_hdl: HAL SOC handle 2444 * return: mpdu_start_tlv offset value 2445 */ 2446 static inline 2447 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2448 { 2449 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2450 2451 if (!hal_soc || !hal_soc->ops) { 2452 hal_err("hal handle is NULL"); 2453 QDF_BUG(0); 2454 return 0; 2455 } 2456 2457 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2458 } 2459 2460 static inline 2461 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2462 { 2463 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2464 2465 if (!hal_soc || !hal_soc->ops) { 2466 hal_err("hal handle is NULL"); 2467 QDF_BUG(0); 2468 return 0; 2469 } 2470 2471 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2472 } 2473 2474 /** 2475 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 2476 * rx_pkt_tlvs structure 2477 * 2478 * @hal_soc_hdl: HAL SOC handle 2479 * return: mpdu_end_tlv offset value 2480 */ 2481 static inline 2482 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2483 { 2484 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2485 2486 if (!hal_soc || !hal_soc->ops) { 2487 hal_err("hal handle is NULL"); 2488 QDF_BUG(0); 2489 return 0; 2490 } 2491 2492 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2493 } 2494 2495 /** 2496 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 2497 * rx_pkt_tlvs structure 2498 * 2499 * @hal_soc_hdl: HAL SOC handle 2500 * return: attn_tlv offset value 2501 */ 2502 static inline 2503 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2504 { 2505 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2506 2507 if (!hal_soc || !hal_soc->ops) { 2508 hal_err("hal handle is NULL"); 2509 QDF_BUG(0); 2510 return 0; 2511 } 2512 2513 return hal_soc->ops->hal_rx_attn_offset_get(); 2514 } 2515 2516 /** 2517 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 2518 * @msdu_details_ptr - Pointer to msdu_details_ptr 2519 * @hal - pointer to hal_soc 2520 * Return - Pointer to rx_msdu_desc_info structure. 2521 * 2522 */ 2523 static inline 2524 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2525 struct hal_soc *hal_soc) 2526 { 2527 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2528 msdu_details_ptr); 2529 } 2530 2531 static inline void 2532 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2533 uint8_t *buf, uint8_t dbg_level) 2534 { 2535 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2536 2537 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2538 } 2539 2540 //TODO - Change the names to not include tlv names 2541 static inline uint16_t 2542 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2543 { 2544 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2545 2546 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2547 } 2548 2549 static inline uint32_t 2550 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2551 { 2552 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2553 2554 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2555 } 2556 2557 static inline uint32_t 2558 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2559 { 2560 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2561 2562 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2563 } 2564 2565 static inline uint16_t 2566 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2567 { 2568 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2569 2570 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2571 } 2572 2573 static inline int 2574 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2575 uint8_t *rx_pkt_tlv, 2576 struct hal_offload_info *offload_info) 2577 { 2578 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2579 2580 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2581 offload_info); 2582 2583 } 2584 2585 static inline int 2586 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2587 void *proto_params) 2588 { 2589 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2590 2591 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2592 } 2593 2594 static inline int 2595 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2596 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2597 { 2598 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2599 2600 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2601 l3_hdr_offset, 2602 l4_hdr_offset); 2603 } 2604 2605 static inline uint32_t 2606 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2607 { 2608 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2609 2610 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2611 } 2612 2613 /* 2614 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 2615 * from rx_msdu_start 2616 * 2617 * @buf: pointer to the start of RX PKT TLV header 2618 * Return: uint32_t(pkt type) 2619 */ 2620 2621 static inline uint32_t 2622 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2623 { 2624 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2625 2626 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2627 } 2628 2629 static inline void 2630 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2631 uint8_t *buf, uint64_t *pn_num) 2632 { 2633 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2634 2635 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2636 } 2637 2638 static inline uint8_t * 2639 hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc) 2640 { 2641 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2642 2643 if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr) 2644 return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc); 2645 2646 return NULL; 2647 } 2648 2649 static inline uint64_t 2650 hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc, 2651 uint8_t *buf) 2652 { 2653 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2654 2655 if (hal_soc->ops->hal_rx_get_qdesc_addr) 2656 return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf); 2657 2658 return 0; 2659 } 2660 2661 static inline void 2662 hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl, 2663 uint8_t *desc, uint32_t dst_ind) 2664 { 2665 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2666 2667 if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind) 2668 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind); 2669 } 2670 2671 static inline uint32_t 2672 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2673 { 2674 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2675 2676 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2677 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2678 2679 return 0; 2680 } 2681 2682 static inline uint8_t * 2683 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2684 { 2685 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2686 2687 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2688 } 2689 2690 static inline uint8_t 2691 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2692 { 2693 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2694 2695 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2696 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2697 2698 return 0; 2699 } 2700 2701 static inline uint32_t 2702 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2703 { 2704 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2705 2706 if (hal_soc->ops->hal_rx_tlv_get_freq) 2707 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2708 2709 return 0; 2710 } 2711 2712 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2713 void *desc, 2714 void *mpdu_desc_info, 2715 uint32_t val) 2716 { 2717 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2718 2719 if (hal_soc->ops->hal_mpdu_desc_info_set) 2720 return hal_soc->ops->hal_mpdu_desc_info_set( 2721 hal_soc_hdl, desc, mpdu_desc_info, val); 2722 } 2723 2724 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2725 void *msdu_desc_info, 2726 uint32_t val, uint32_t nbuf_len) 2727 { 2728 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2729 2730 if (hal_soc->ops->hal_msdu_desc_info_set) 2731 return hal_soc->ops->hal_msdu_desc_info_set( 2732 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2733 } 2734 2735 static inline uint32_t 2736 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2737 { 2738 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2739 2740 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2741 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2742 hal_soc_hdl, msdu_link_desc); 2743 2744 return 0; 2745 } 2746 2747 static inline uint32_t 2748 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2749 { 2750 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2751 2752 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2753 } 2754 2755 static inline uint32_t 2756 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2757 { 2758 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2759 2760 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2761 } 2762 2763 static inline uint32_t 2764 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2765 { 2766 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2767 2768 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2769 } 2770 2771 static inline uint32_t 2772 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2773 { 2774 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2775 2776 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2777 } 2778 2779 static inline uint32_t 2780 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2781 { 2782 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2783 2784 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2785 } 2786 2787 static inline uint32_t 2788 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2789 hal_ring_desc_t ring_desc) 2790 { 2791 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2792 2793 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2794 } 2795 2796 /** 2797 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2798 * from the BUFFER_ADDR_INFO structure 2799 * given a REO destination ring descriptor. 2800 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2801 * 2802 * Return: uint8_t (value of the return_buffer_manager) 2803 */ 2804 static inline uint8_t 2805 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2806 hal_ring_desc_t ring_desc) 2807 { 2808 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2809 2810 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2811 } 2812 2813 /* 2814 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2815 * rxdma ring entry. 2816 * @rxdma_entry: descriptor entry 2817 * @paddr: physical address of nbuf data pointer. 2818 * @cookie: SW cookie used as a index to SW rx desc. 2819 * @manager: who owns the nbuf (host, NSS, etc...). 2820 * 2821 */ 2822 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 2823 void *rxdma_entry, 2824 qdf_dma_addr_t paddr, 2825 uint32_t cookie, 2826 uint8_t manager) 2827 { 2828 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2829 2830 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 2831 paddr, 2832 cookie, 2833 manager); 2834 } 2835 2836 static inline uint32_t 2837 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2838 { 2839 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2840 2841 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 2842 } 2843 2844 static inline void 2845 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 2846 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 2847 { 2848 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2849 2850 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 2851 ip_csum_err, 2852 tcp_udp_csum_err); 2853 } 2854 2855 static inline void 2856 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 2857 uint8_t *rx_tlv_hdr, 2858 struct hal_rx_pkt_capture_flags *flags) 2859 { 2860 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2861 2862 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 2863 flags); 2864 } 2865 2866 static inline uint8_t 2867 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2868 { 2869 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2870 2871 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 2872 } 2873 2874 static inline uint8_t 2875 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2876 { 2877 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2878 2879 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 2880 } 2881 2882 /** 2883 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 2884 * @hal_soc_hdl: HAL SoC handle 2885 * @ring_desc: REO ring descriptor 2886 * @prev_pn: Buffer to populate the previos PN 2887 * 2888 * Return: None 2889 */ 2890 static inline void 2891 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 2892 uint64_t *prev_pn) 2893 { 2894 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2895 2896 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 2897 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 2898 } 2899 2900 /** 2901 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 2902 * from rx mpdu info 2903 * @buf: pointer to rx_pkt_tlvs 2904 * 2905 * No input validdataion, since this function is supposed to be 2906 * called from fastpath. 2907 * 2908 * Return: ampdu flag 2909 */ 2910 static inline bool 2911 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2912 { 2913 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2914 2915 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 2916 } 2917 2918 #ifdef REO_SHARED_QREF_TABLE_EN 2919 /** 2920 * hal_reo_shared_qaddr_write(): Write REo tid queue addr 2921 * LUT shared by SW and HW at the index given by peer id 2922 * and tid. 2923 * 2924 * @hal_soc: hal soc pointer 2925 * @reo_qref_addr: pointer to index pointed to be peer_id 2926 * and tid 2927 * @tid: tid queue number 2928 * @hw_qdesc_paddr: reo queue addr 2929 */ 2930 static inline void 2931 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 2932 uint16_t peer_id, 2933 int tid, 2934 qdf_dma_addr_t hw_qdesc_paddr) 2935 { 2936 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2937 2938 if (hal_soc->ops->hal_reo_shared_qaddr_write) 2939 return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl, 2940 peer_id, tid, hw_qdesc_paddr); 2941 } 2942 2943 /** 2944 * hal_reo_shared_qaddr_init(): Initialize reo qref LUT 2945 * @hal_soc: Hal soc pointer 2946 * @qref_reset: reset qref LUT 2947 * 2948 * Write MLO and Non MLO table start addr to HW reg 2949 * 2950 * Return: void 2951 */ 2952 static inline void 2953 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) 2954 { 2955 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2956 2957 if (hal_soc->ops->hal_reo_shared_qaddr_init) 2958 return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl, 2959 qref_reset); 2960 } 2961 2962 /** 2963 * hal_reo_shared_qaddr_cache_clear(): Set and unset 'clear_qdesc_array' 2964 * bit in reo reg for shared qref feature. This is done for every MLO 2965 * connection to clear HW reo internal storage for clearing stale entry 2966 * of prev peer having same peer id 2967 * 2968 * @hal_soc: Hal soc pointer 2969 * 2970 * Write MLO and Non MLO table start addr to HW reg 2971 * 2972 * Return: void 2973 */ 2974 static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) 2975 { 2976 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2977 2978 if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear) 2979 return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl); 2980 } 2981 2982 #else 2983 static inline void 2984 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 2985 uint16_t peer_id, 2986 int tid, 2987 qdf_dma_addr_t hw_qdesc_paddr) {} 2988 static inline void 2989 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {} 2990 2991 static inline void 2992 hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {} 2993 2994 #endif /* REO_SHARED_QREF_TABLE_EN */ 2995 2996 static inline uint8_t 2997 hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl) 2998 { 2999 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3000 3001 return hal->reo_qref.reo_qref_table_en; 3002 } 3003 3004 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3005 static inline uint8_t 3006 hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3007 { 3008 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3009 3010 return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf); 3011 } 3012 #endif 3013 3014 static inline uint32_t 3015 hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3016 { 3017 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3018 3019 return hal_soc->ops->hal_rx_tlv_l3_type_get ? 3020 hal_soc->ops->hal_rx_tlv_l3_type_get(buf) : 3021 HAL_RX_TLV_L3_TYPE_INVALID; 3022 } 3023 3024 /** 3025 * hal_get_tsf_time() - Get tsf time 3026 * @hal_soc_hdl: HAL soc handle 3027 * @mac_id: mac_id 3028 * @tsf: pointer to update tsf value 3029 * @tsf_sync_soc_time: pointer to update tsf sync time 3030 * 3031 * Return: None. 3032 */ 3033 static inline void 3034 hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 3035 uint32_t mac_id, uint64_t *tsf, 3036 uint64_t *tsf_sync_soc_time) 3037 { 3038 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3039 3040 if (hal_soc->ops->hal_get_tsf_time) 3041 hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id, 3042 tsf, tsf_sync_soc_time); 3043 } 3044 #endif /* _HAL_RX_H */ 3045