1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 24 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 25 #define HAL_RX_LSB(block, field) block##_##field##_LSB 26 #define HAL_RX_MASk(block, field) block##_##field##_MASK 27 28 #define HAL_RX_GET(_ptr, block, field) \ 29 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 30 HAL_RX_MASk(block, field)) >> \ 31 HAL_RX_LSB(block, field)) 32 33 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 34 #ifndef RX_DATA_BUFFER_SIZE 35 #define RX_DATA_BUFFER_SIZE 2048 36 #endif 37 38 #ifndef RX_MONITOR_BUFFER_SIZE 39 #define RX_MONITOR_BUFFER_SIZE 2048 40 #endif 41 42 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 43 #define HAL_RX_NON_QOS_TID 16 44 45 enum { 46 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 47 HAL_HW_RX_DECAP_FORMAT_NWIFI, 48 HAL_HW_RX_DECAP_FORMAT_ETH2, 49 HAL_HW_RX_DECAP_FORMAT_8023, 50 }; 51 52 /** 53 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 54 * 55 * @reo_psh_rsn: REO push reason 56 * @reo_err_code: REO Error code 57 * @rxdma_psh_rsn: RXDMA push reason 58 * @rxdma_err_code: RXDMA Error code 59 * @reserved_1: Reserved bits 60 * @wbm_err_src: WBM error source 61 * @pool_id: pool ID, indicates which rxdma pool 62 * @reserved_2: Reserved bits 63 */ 64 struct hal_wbm_err_desc_info { 65 uint16_t reo_psh_rsn:2, 66 reo_err_code:5, 67 rxdma_psh_rsn:2, 68 rxdma_err_code:5, 69 reserved_1:2; 70 uint8_t wbm_err_src:3, 71 pool_id:2, 72 msdu_continued:1, 73 reserved_2:2; 74 }; 75 76 /** 77 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 78 * 79 * @l3_hdr_pad: l3 header padding 80 * @reserved: Reserved bits 81 * @sa_sw_peer_id: sa sw peer id 82 * @sa_idx: sa index 83 * @da_idx: da index 84 */ 85 struct hal_rx_msdu_metadata { 86 uint32_t l3_hdr_pad:16, 87 sa_sw_peer_id:16; 88 uint32_t sa_idx:16, 89 da_idx:16; 90 }; 91 92 /** 93 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 94 * 95 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 96 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 97 */ 98 enum hal_reo_error_status { 99 HAL_REO_ERROR_DETECTED = 0, 100 HAL_REO_ROUTING_INSTRUCTION = 1, 101 }; 102 103 /** 104 * @msdu_flags: [0] first_msdu_in_mpdu 105 * [1] last_msdu_in_mpdu 106 * [2] msdu_continuation - MSDU spread across buffers 107 * [23] sa_is_valid - SA match in peer table 108 * [24] sa_idx_timeout - Timeout while searching for SA match 109 * [25] da_is_valid - Used to identtify intra-bss forwarding 110 * [26] da_is_MCBC 111 * [27] da_idx_timeout - Timeout while searching for DA match 112 * 113 */ 114 struct hal_rx_msdu_desc_info { 115 uint32_t msdu_flags; 116 uint16_t msdu_len; /* 14 bits for length */ 117 }; 118 119 /** 120 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 121 * 122 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 123 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 124 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 125 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 126 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 127 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 128 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 129 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 130 */ 131 enum hal_rx_msdu_desc_flags { 132 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 133 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 134 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 135 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 136 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 137 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 138 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 139 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 140 }; 141 142 /* 143 * @msdu_count: no. of msdus in the MPDU 144 * @mpdu_seq: MPDU sequence number 145 * @mpdu_flags [0] Fragment flag 146 * [1] MPDU_retry_bit 147 * [2] AMPDU flag 148 * [3] raw_ampdu 149 * @peer_meta_data: Upper bits containing peer id, vdev id 150 */ 151 struct hal_rx_mpdu_desc_info { 152 uint16_t msdu_count; 153 uint16_t mpdu_seq; /* 12 bits for length */ 154 uint32_t mpdu_flags; 155 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 156 }; 157 158 /** 159 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 160 * 161 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 162 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 163 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 164 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 165 */ 166 enum hal_rx_mpdu_desc_flags { 167 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 168 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 169 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 170 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 171 }; 172 173 /** 174 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 175 * BUFFER_ADDR_INFO structure 176 * 177 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 178 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 179 * descriptor list 180 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 181 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 182 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 183 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 184 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 185 */ 186 enum hal_rx_ret_buf_manager { 187 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 188 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 189 HAL_RX_BUF_RBM_FW_BM = 2, 190 HAL_RX_BUF_RBM_SW0_BM = 3, 191 HAL_RX_BUF_RBM_SW1_BM = 4, 192 HAL_RX_BUF_RBM_SW2_BM = 5, 193 HAL_RX_BUF_RBM_SW3_BM = 6, 194 }; 195 196 /* 197 * Given the offset of a field in bytes, returns uint8_t * 198 */ 199 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 200 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 201 202 /* 203 * Given the offset of a field in bytes, returns uint32_t * 204 */ 205 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 206 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 207 208 #define _HAL_MS(_word, _mask, _shift) \ 209 (((_word) & (_mask)) >> (_shift)) 210 211 /* 212 * macro to set the LSW of the nbuf data physical address 213 * to the rxdma ring entry 214 */ 215 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 216 ((*(((unsigned int *) buff_addr_info) + \ 217 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 218 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 219 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 220 221 /* 222 * macro to set the LSB of MSW of the nbuf data physical address 223 * to the rxdma ring entry 224 */ 225 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 226 ((*(((unsigned int *) buff_addr_info) + \ 227 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 228 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 229 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 230 231 /* 232 * macro to set the cookie into the rxdma ring entry 233 */ 234 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 235 ((*(((unsigned int *) buff_addr_info) + \ 236 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 237 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 238 ((*(((unsigned int *) buff_addr_info) + \ 239 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 240 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 241 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 242 243 /* 244 * macro to set the manager into the rxdma ring entry 245 */ 246 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 247 ((*(((unsigned int *) buff_addr_info) + \ 248 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 249 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 250 ((*(((unsigned int *) buff_addr_info) + \ 251 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 252 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 253 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 254 255 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 256 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 257 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 258 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 259 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 260 261 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 262 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 263 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 264 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 265 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 266 267 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 268 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 269 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 270 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 271 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 272 273 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 274 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 275 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 276 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 277 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 278 279 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 280 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 281 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 282 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 283 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 284 285 /* TODO: Convert the following structure fields accesseses to offsets */ 286 287 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 288 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 289 (((struct reo_destination_ring *) \ 290 reo_desc)->buf_or_link_desc_addr_info))) 291 292 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 293 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 294 (((struct reo_destination_ring *) \ 295 reo_desc)->buf_or_link_desc_addr_info))) 296 297 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 298 (HAL_RX_BUF_COOKIE_GET(& \ 299 (((struct reo_destination_ring *) \ 300 reo_desc)->buf_or_link_desc_addr_info))) 301 302 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 303 ((mpdu_info_ptr \ 304 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 305 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 306 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 307 308 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 309 ((mpdu_info_ptr \ 310 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 311 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 312 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 313 314 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 315 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 316 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 317 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 318 319 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 320 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 321 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 322 323 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 324 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 325 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 326 327 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 328 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 329 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 330 331 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 332 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 333 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 334 335 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 336 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 337 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 338 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 339 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 340 341 342 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 343 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 344 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 345 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 346 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 347 348 /* 349 * NOTE: None of the following _GET macros need a right 350 * shift by the corresponding _LSB. This is because, they are 351 * finally taken and "OR'ed" into a single word again. 352 */ 353 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 354 ((*(((uint32_t *)msdu_info_ptr) + \ 355 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 356 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 357 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 358 359 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 360 ((*(((uint32_t *)msdu_info_ptr) + \ 361 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 362 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 363 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 364 365 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 366 ((*(((uint32_t *)msdu_info_ptr) + \ 367 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 368 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 369 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 370 371 372 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 373 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 374 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 375 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 376 377 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 378 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 379 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 380 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 381 382 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 383 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 384 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 385 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 386 387 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 388 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 389 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 390 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 391 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 392 393 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 394 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 395 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 396 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 397 398 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 399 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 400 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 401 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 402 403 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 404 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 405 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 406 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 407 408 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 409 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 410 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 411 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 412 413 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 414 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 415 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 416 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 417 418 419 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 420 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 421 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 422 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 423 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 424 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 425 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 426 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 427 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 428 429 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 430 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 431 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 432 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 433 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 434 435 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 436 (*(uint32_t *)(((uint8_t *)_ptr) + \ 437 _wrd ## _ ## _field ## _OFFSET) |= \ 438 ((_val << _wrd ## _ ## _field ## _LSB) & \ 439 _wrd ## _ ## _field ## _MASK)) 440 441 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 442 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 443 _field, _val) 444 445 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 446 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 447 _field, _val) 448 449 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 450 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 451 _field, _val) 452 453 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 454 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 455 { 456 struct reo_destination_ring *reo_dst_ring; 457 uint32_t *mpdu_info; 458 459 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 460 461 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 462 463 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 464 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 465 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 466 mpdu_desc_info->peer_meta_data = 467 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 468 } 469 470 /* 471 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 472 * @ Specifically flags needed are: 473 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 474 * @ msdu_continuation, sa_is_valid, 475 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 476 * @ da_is_MCBC 477 * 478 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 479 * @ descriptor 480 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 481 * @ Return: void 482 */ 483 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 484 struct hal_rx_msdu_desc_info *msdu_desc_info) 485 { 486 struct reo_destination_ring *reo_dst_ring; 487 uint32_t *msdu_info; 488 489 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 490 491 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 492 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 493 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 494 } 495 496 /* 497 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 498 * rxdma ring entry. 499 * @rxdma_entry: descriptor entry 500 * @paddr: physical address of nbuf data pointer. 501 * @cookie: SW cookie used as a index to SW rx desc. 502 * @manager: who owns the nbuf (host, NSS, etc...). 503 * 504 */ 505 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 506 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 507 { 508 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 509 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 510 511 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 512 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 513 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 514 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 515 } 516 517 /* 518 * Structures & Macros to obtain fields from the TLV's in the Rx packet 519 * pre-header. 520 */ 521 522 /* 523 * Every Rx packet starts at an offset from the top of the buffer. 524 * If the host hasn't subscribed to any specific TLV, there is 525 * still space reserved for the following TLV's from the start of 526 * the buffer: 527 * -- RX ATTENTION 528 * -- RX MPDU START 529 * -- RX MSDU START 530 * -- RX MSDU END 531 * -- RX MPDU END 532 * -- RX PACKET HEADER (802.11) 533 * If the host subscribes to any of the TLV's above, that TLV 534 * if populated by the HW 535 */ 536 537 #define NUM_DWORDS_TAG 1 538 539 /* By default the packet header TLV is 128 bytes */ 540 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 541 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 542 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 543 544 #define RX_PKT_OFFSET_WORDS \ 545 ( \ 546 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 547 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 548 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 549 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 550 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 551 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 552 ) 553 554 #define RX_PKT_OFFSET_BYTES \ 555 (RX_PKT_OFFSET_WORDS << 2) 556 557 #define RX_PKT_HDR_TLV_LEN 120 558 559 /* 560 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 561 */ 562 struct rx_attention_tlv { 563 uint32_t tag; 564 struct rx_attention rx_attn; 565 }; 566 567 struct rx_mpdu_start_tlv { 568 uint32_t tag; 569 struct rx_mpdu_start rx_mpdu_start; 570 }; 571 572 struct rx_msdu_start_tlv { 573 uint32_t tag; 574 struct rx_msdu_start rx_msdu_start; 575 }; 576 577 struct rx_msdu_end_tlv { 578 uint32_t tag; 579 struct rx_msdu_end rx_msdu_end; 580 }; 581 582 struct rx_mpdu_end_tlv { 583 uint32_t tag; 584 struct rx_mpdu_end rx_mpdu_end; 585 }; 586 587 struct rx_pkt_hdr_tlv { 588 uint32_t tag; /* 4 B */ 589 uint32_t phy_ppdu_id; /* 4 B */ 590 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 591 }; 592 593 594 #define RXDMA_OPTIMIZATION 595 596 /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status 597 * buffers, monitor destination buffers and monitor descriptor buffers. 598 */ 599 #ifdef RXDMA_OPTIMIZATION 600 /* 601 * The RX_PADDING_BYTES is required so that the TLV's don't 602 * spread across the 128 byte boundary 603 * RXDMA optimization requires: 604 * 1) MSDU_END & ATTENTION TLV's follow in that order 605 * 2) TLV's don't span across 128 byte lines 606 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 607 */ 608 #define RX_PADDING0_BYTES 4 609 #define RX_PADDING1_BYTES 16 610 struct rx_pkt_tlvs { 611 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 612 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 613 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 614 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 615 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 616 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 617 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 618 #ifndef NO_RX_PKT_HDR_TLV 619 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 620 #endif 621 }; 622 #else /* RXDMA_OPTIMIZATION */ 623 struct rx_pkt_tlvs { 624 struct rx_attention_tlv attn_tlv; 625 struct rx_mpdu_start_tlv mpdu_start_tlv; 626 struct rx_msdu_start_tlv msdu_start_tlv; 627 struct rx_msdu_end_tlv msdu_end_tlv; 628 struct rx_mpdu_end_tlv mpdu_end_tlv; 629 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 630 }; 631 #endif /* RXDMA_OPTIMIZATION */ 632 633 /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */ 634 #ifdef RXDMA_OPTIMIZATION 635 struct rx_mon_pkt_tlvs { 636 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 637 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 638 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 639 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 640 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 641 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 642 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 643 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 644 }; 645 #else /* RXDMA_OPTIMIZATION */ 646 struct rx_mon_pkt_tlvs { 647 struct rx_attention_tlv attn_tlv; 648 struct rx_mpdu_start_tlv mpdu_start_tlv; 649 struct rx_msdu_start_tlv msdu_start_tlv; 650 struct rx_msdu_end_tlv msdu_end_tlv; 651 struct rx_mpdu_end_tlv mpdu_end_tlv; 652 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 653 }; 654 #endif 655 656 #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs) 657 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 658 659 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 660 661 #ifdef NO_RX_PKT_HDR_TLV 662 static inline uint8_t 663 *hal_rx_pkt_hdr_get(uint8_t *buf) 664 { 665 return buf + RX_PKT_TLVS_LEN; 666 } 667 #else 668 static inline uint8_t 669 *hal_rx_pkt_hdr_get(uint8_t *buf) 670 { 671 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 672 673 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 674 675 } 676 #endif 677 678 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 679 680 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 681 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 682 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 683 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 684 RX_PKT_TLV_OFFSET(msdu_start_tlv) 685 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 686 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 687 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 688 689 static inline uint8_t 690 *hal_rx_padding0_get(uint8_t *buf) 691 { 692 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 693 694 return pkt_tlvs->rx_padding0; 695 } 696 697 /* 698 * hal_rx_encryption_info_valid(): Returns encryption type. 699 * 700 * @hal_soc_hdl: hal soc handle 701 * @buf: rx_tlv_hdr of the received packet 702 * 703 * Return: encryption type 704 */ 705 static inline uint32_t 706 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 707 { 708 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 709 710 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 711 712 } 713 714 /* 715 * hal_rx_print_pn: Prints the PN of rx packet. 716 * @hal_soc_hdl: hal soc handle 717 * @buf: rx_tlv_hdr of the received packet 718 * 719 * Return: void 720 */ 721 static inline void 722 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 723 { 724 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 725 726 hal_soc->ops->hal_rx_print_pn(buf); 727 } 728 729 /* 730 * Get msdu_done bit from the RX_ATTENTION TLV 731 */ 732 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 733 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 734 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 735 RX_ATTENTION_2_MSDU_DONE_MASK, \ 736 RX_ATTENTION_2_MSDU_DONE_LSB)) 737 738 static inline uint32_t 739 hal_rx_attn_msdu_done_get(uint8_t *buf) 740 { 741 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 742 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 743 uint32_t msdu_done; 744 745 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 746 747 return msdu_done; 748 } 749 750 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 751 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 752 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 753 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 754 RX_ATTENTION_1_FIRST_MPDU_LSB)) 755 756 /* 757 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 758 * @buf: pointer to rx_pkt_tlvs 759 * 760 * reutm: uint32_t(first_msdu) 761 */ 762 static inline uint32_t 763 hal_rx_attn_first_mpdu_get(uint8_t *buf) 764 { 765 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 766 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 767 uint32_t first_mpdu; 768 769 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 770 771 return first_mpdu; 772 } 773 774 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 775 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 776 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 777 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 778 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 779 780 /* 781 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 782 * from rx attention 783 * @buf: pointer to rx_pkt_tlvs 784 * 785 * Return: tcp_udp_cksum_fail 786 */ 787 static inline bool 788 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 789 { 790 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 791 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 792 bool tcp_udp_cksum_fail; 793 794 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 795 796 return tcp_udp_cksum_fail; 797 } 798 799 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 800 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 801 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 802 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 803 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 804 805 /* 806 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 807 * from rx attention 808 * @buf: pointer to rx_pkt_tlvs 809 * 810 * Return: ip_cksum_fail 811 */ 812 static inline bool 813 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 814 { 815 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 816 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 817 bool ip_cksum_fail; 818 819 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 820 821 return ip_cksum_fail; 822 } 823 824 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 825 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 826 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 827 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 828 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 829 830 /* 831 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 832 * from rx attention 833 * @buf: pointer to rx_pkt_tlvs 834 * 835 * Return: phy_ppdu_id 836 */ 837 static inline uint16_t 838 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 839 { 840 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 841 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 842 uint16_t phy_ppdu_id; 843 844 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 845 846 return phy_ppdu_id; 847 } 848 849 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 850 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 851 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 852 RX_ATTENTION_1_CCE_MATCH_MASK, \ 853 RX_ATTENTION_1_CCE_MATCH_LSB)) 854 855 /* 856 * hal_rx_msdu_cce_match_get(): get CCE match bit 857 * from rx attention 858 * @buf: pointer to rx_pkt_tlvs 859 * Return: CCE match value 860 */ 861 static inline bool 862 hal_rx_msdu_cce_match_get(uint8_t *buf) 863 { 864 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 865 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 866 bool cce_match_val; 867 868 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 869 return cce_match_val; 870 } 871 872 /* 873 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 874 */ 875 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 876 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 877 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 878 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 879 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 880 881 static inline uint32_t 882 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 883 { 884 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 885 struct rx_mpdu_start *mpdu_start = 886 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 887 888 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 889 uint32_t peer_meta_data; 890 891 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 892 893 return peer_meta_data; 894 } 895 896 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 897 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 898 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 899 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 900 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 901 /** 902 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 903 * from rx mpdu info 904 * @buf: pointer to rx_pkt_tlvs 905 * 906 * Return: ampdu flag 907 */ 908 static inline bool 909 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 910 { 911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 912 struct rx_mpdu_start *mpdu_start = 913 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 914 915 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 916 bool ampdu_flag; 917 918 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 919 920 return ampdu_flag; 921 } 922 923 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 924 ((*(((uint32_t *)_rx_mpdu_info) + \ 925 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 926 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 927 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 928 929 /* 930 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 931 * 932 * @ buf: rx_tlv_hdr of the received packet 933 * @ peer_mdata: peer meta data to be set. 934 * @ Return: void 935 */ 936 static inline void 937 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 938 { 939 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 940 struct rx_mpdu_start *mpdu_start = 941 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 942 943 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 944 945 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 946 } 947 948 /** 949 * LRO information needed from the TLVs 950 */ 951 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 952 (_HAL_MS( \ 953 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 954 msdu_end_tlv.rx_msdu_end), \ 955 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 956 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 957 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 958 959 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 960 (_HAL_MS( \ 961 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 962 msdu_end_tlv.rx_msdu_end), \ 963 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 964 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 965 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 966 967 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 968 (_HAL_MS( \ 969 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 970 msdu_end_tlv.rx_msdu_end), \ 971 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 972 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 973 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 974 975 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 976 (_HAL_MS( \ 977 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 978 msdu_end_tlv.rx_msdu_end), \ 979 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 980 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 981 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 982 983 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 984 (_HAL_MS( \ 985 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 986 msdu_start_tlv.rx_msdu_start), \ 987 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 988 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 989 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 990 991 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 992 (_HAL_MS( \ 993 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 994 msdu_start_tlv.rx_msdu_start), \ 995 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 996 RX_MSDU_START_2_TCP_PROTO_MASK, \ 997 RX_MSDU_START_2_TCP_PROTO_LSB)) 998 999 #define HAL_RX_TLV_GET_UDP_PROTO(buf) \ 1000 (_HAL_MS( \ 1001 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1002 msdu_start_tlv.rx_msdu_start), \ 1003 RX_MSDU_START_2_UDP_PROTO_OFFSET)), \ 1004 RX_MSDU_START_2_UDP_PROTO_MASK, \ 1005 RX_MSDU_START_2_UDP_PROTO_LSB)) 1006 1007 #define HAL_RX_TLV_GET_IPV6(buf) \ 1008 (_HAL_MS( \ 1009 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1010 msdu_start_tlv.rx_msdu_start), \ 1011 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 1012 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 1013 RX_MSDU_START_2_IPV6_PROTO_LSB)) 1014 1015 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 1016 (_HAL_MS( \ 1017 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1018 msdu_start_tlv.rx_msdu_start), \ 1019 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 1020 RX_MSDU_START_1_L3_OFFSET_MASK, \ 1021 RX_MSDU_START_1_L3_OFFSET_LSB)) 1022 1023 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 1024 (_HAL_MS( \ 1025 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1026 msdu_start_tlv.rx_msdu_start), \ 1027 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 1028 RX_MSDU_START_1_L4_OFFSET_MASK, \ 1029 RX_MSDU_START_1_L4_OFFSET_LSB)) 1030 1031 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 1032 (_HAL_MS( \ 1033 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1034 msdu_start_tlv.rx_msdu_start), \ 1035 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1036 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1037 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1038 1039 /** 1040 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 1041 * l3_header padding from rx_msdu_end TLV 1042 * 1043 * @buf: pointer to the start of RX PKT TLV headers 1044 * Return: number of l3 header padding bytes 1045 */ 1046 static inline uint32_t 1047 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 1048 uint8_t *buf) 1049 { 1050 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1051 1052 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 1053 } 1054 1055 /** 1056 * hal_rx_msdu_end_sa_idx_get(): API to get the 1057 * sa_idx from rx_msdu_end TLV 1058 * 1059 * @ buf: pointer to the start of RX PKT TLV headers 1060 * Return: sa_idx (SA AST index) 1061 */ 1062 static inline uint16_t 1063 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 1064 uint8_t *buf) 1065 { 1066 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1067 1068 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 1069 } 1070 1071 /** 1072 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1073 * sa_is_valid bit from rx_msdu_end TLV 1074 * 1075 * @ buf: pointer to the start of RX PKT TLV headers 1076 * Return: sa_is_valid bit 1077 */ 1078 static inline uint8_t 1079 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1080 uint8_t *buf) 1081 { 1082 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1083 1084 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 1085 } 1086 1087 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1088 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1089 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1090 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1091 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1092 1093 /** 1094 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1095 * from rx_msdu_start TLV 1096 * 1097 * @ buf: pointer to the start of RX PKT TLV headers 1098 * Return: msdu length 1099 */ 1100 static inline uint32_t 1101 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1102 { 1103 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1104 struct rx_msdu_start *msdu_start = 1105 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1106 uint32_t msdu_len; 1107 1108 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1109 1110 return msdu_len; 1111 } 1112 1113 /** 1114 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1115 * from rx_msdu_start TLV 1116 * 1117 * @buf: pointer to the start of RX PKT TLV headers 1118 * @len: msdu length 1119 * 1120 * Return: none 1121 */ 1122 static inline void 1123 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1124 { 1125 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1126 struct rx_msdu_start *msdu_start = 1127 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1128 void *wrd1; 1129 1130 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1131 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1132 *(uint32_t *)wrd1 |= len; 1133 } 1134 1135 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1136 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1137 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1138 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1139 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1140 1141 /* 1142 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1143 * Interval from rx_msdu_start 1144 * 1145 * @buf: pointer to the start of RX PKT TLV header 1146 * Return: uint32_t(bw) 1147 */ 1148 static inline uint32_t 1149 hal_rx_msdu_start_bw_get(uint8_t *buf) 1150 { 1151 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1152 struct rx_msdu_start *msdu_start = 1153 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1154 uint32_t bw; 1155 1156 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1157 1158 return bw; 1159 } 1160 1161 1162 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1164 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1165 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1166 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1167 1168 /** 1169 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1170 * from rx_msdu_start TLV 1171 * 1172 * @ buf: pointer to the start of RX PKT TLV headers 1173 * Return: toeplitz hash 1174 */ 1175 static inline uint32_t 1176 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1177 { 1178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1179 struct rx_msdu_start *msdu_start = 1180 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1181 1182 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1183 } 1184 1185 /** 1186 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 1187 * 1188 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 1189 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 1190 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 1191 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 1192 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 1193 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 1194 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 1195 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 1196 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 1197 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 1198 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 1199 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 1200 */ 1201 enum hal_rx_mpdu_info_sw_frame_group_id_type { 1202 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 1203 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 1204 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 1205 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 1206 HAL_MPDU_SW_FRAME_GROUP_MGMT, 1207 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 1208 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 1209 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 1210 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 1211 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 1212 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 1213 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 1214 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 1215 }; 1216 1217 /** 1218 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 1219 * Retrieve qos control valid bit from the tlv. 1220 * @hal_soc_hdl: hal_soc handle 1221 * @buf: pointer to rx pkt TLV. 1222 * 1223 * Return: qos control value. 1224 */ 1225 static inline uint32_t 1226 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 1227 hal_soc_handle_t hal_soc_hdl, 1228 uint8_t *buf) 1229 { 1230 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1231 1232 if ((!hal_soc) || (!hal_soc->ops)) { 1233 hal_err("hal handle is NULL"); 1234 QDF_BUG(0); 1235 return QDF_STATUS_E_INVAL; 1236 } 1237 1238 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 1239 return hal_soc->ops-> 1240 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 1241 1242 return QDF_STATUS_E_INVAL; 1243 } 1244 1245 /** 1246 * hal_rx_is_unicast: check packet is unicast frame or not. 1247 * @hal_soc_hdl: hal_soc handle 1248 * @buf: pointer to rx pkt TLV. 1249 * 1250 * Return: true on unicast. 1251 */ 1252 static inline bool 1253 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1254 { 1255 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1256 1257 return hal_soc->ops->hal_rx_is_unicast(buf); 1258 } 1259 1260 /** 1261 * hal_rx_tid_get: get tid based on qos control valid. 1262 * @hal_soc_hdl: hal soc handle 1263 * @buf: pointer to rx pkt TLV. 1264 * 1265 * Return: tid 1266 */ 1267 static inline uint32_t 1268 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1269 { 1270 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1271 1272 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 1273 } 1274 1275 /** 1276 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 1277 * @hal_soc_hdl: hal soc handle 1278 * @buf: pointer to rx pkt TLV. 1279 * 1280 * Return: sw peer_id 1281 */ 1282 static inline uint32_t 1283 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1284 uint8_t *buf) 1285 { 1286 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1287 1288 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1289 } 1290 1291 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1292 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1293 RX_MSDU_START_5_SGI_OFFSET)), \ 1294 RX_MSDU_START_5_SGI_MASK, \ 1295 RX_MSDU_START_5_SGI_LSB)) 1296 /** 1297 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1298 * Interval from rx_msdu_start TLV 1299 * 1300 * @buf: pointer to the start of RX PKT TLV headers 1301 * Return: uint32_t(sgi) 1302 */ 1303 static inline uint32_t 1304 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1305 { 1306 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1307 struct rx_msdu_start *msdu_start = 1308 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1309 uint32_t sgi; 1310 1311 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1312 1313 return sgi; 1314 } 1315 1316 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1317 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1318 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1319 RX_MSDU_START_5_RATE_MCS_MASK, \ 1320 RX_MSDU_START_5_RATE_MCS_LSB)) 1321 /** 1322 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1323 * from rx_msdu_start TLV 1324 * 1325 * @buf: pointer to the start of RX PKT TLV headers 1326 * Return: uint32_t(rate_mcs) 1327 */ 1328 static inline uint32_t 1329 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1330 { 1331 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1332 struct rx_msdu_start *msdu_start = 1333 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1334 uint32_t rate_mcs; 1335 1336 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1337 1338 return rate_mcs; 1339 } 1340 1341 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1342 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1343 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1344 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1345 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1346 1347 /* 1348 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1349 * packet from rx_attention 1350 * 1351 * @buf: pointer to the start of RX PKT TLV header 1352 * Return: uint32_t(decryt status) 1353 */ 1354 1355 static inline uint32_t 1356 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1357 { 1358 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1359 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1360 uint32_t is_decrypt = 0; 1361 uint32_t decrypt_status; 1362 1363 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1364 1365 if (!decrypt_status) 1366 is_decrypt = 1; 1367 1368 return is_decrypt; 1369 } 1370 1371 /* 1372 * Get key index from RX_MSDU_END 1373 */ 1374 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1375 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1376 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1377 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1378 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1379 /* 1380 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1381 * from rx_msdu_end 1382 * 1383 * @buf: pointer to the start of RX PKT TLV header 1384 * Return: uint32_t(key id) 1385 */ 1386 1387 static inline uint32_t 1388 hal_rx_msdu_get_keyid(uint8_t *buf) 1389 { 1390 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1391 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1392 uint32_t keyid_octet; 1393 1394 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1395 1396 return keyid_octet & 0x3; 1397 } 1398 1399 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1400 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1401 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1402 RX_MSDU_START_5_USER_RSSI_MASK, \ 1403 RX_MSDU_START_5_USER_RSSI_LSB)) 1404 /* 1405 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1406 * from rx_msdu_start 1407 * 1408 * @buf: pointer to the start of RX PKT TLV header 1409 * Return: uint32_t(rssi) 1410 */ 1411 1412 static inline uint32_t 1413 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1414 { 1415 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1416 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1417 uint32_t rssi; 1418 1419 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1420 1421 return rssi; 1422 1423 } 1424 1425 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1426 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1427 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1428 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1429 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1430 1431 /* 1432 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1433 * from rx_msdu_start 1434 * 1435 * @buf: pointer to the start of RX PKT TLV header 1436 * Return: uint32_t(frequency) 1437 */ 1438 1439 static inline uint32_t 1440 hal_rx_msdu_start_get_freq(uint8_t *buf) 1441 { 1442 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1443 struct rx_msdu_start *msdu_start = 1444 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1445 uint32_t freq; 1446 1447 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1448 1449 return freq; 1450 } 1451 1452 1453 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1454 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1455 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1456 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1457 RX_MSDU_START_5_PKT_TYPE_LSB)) 1458 1459 /* 1460 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1461 * from rx_msdu_start 1462 * 1463 * @buf: pointer to the start of RX PKT TLV header 1464 * Return: uint32_t(pkt type) 1465 */ 1466 1467 static inline uint32_t 1468 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1469 { 1470 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1471 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1472 uint32_t pkt_type; 1473 1474 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1475 1476 return pkt_type; 1477 } 1478 1479 /* 1480 * hal_rx_mpdu_get_tods(): API to get the tods info 1481 * from rx_mpdu_start 1482 * 1483 * @buf: pointer to the start of RX PKT TLV header 1484 * Return: uint32_t(to_ds) 1485 */ 1486 1487 static inline uint32_t 1488 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1489 { 1490 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1491 1492 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1493 } 1494 1495 1496 /* 1497 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1498 * from rx_mpdu_start 1499 * @hal_soc_hdl: hal soc handle 1500 * @buf: pointer to the start of RX PKT TLV header 1501 * 1502 * Return: uint32_t(fr_ds) 1503 */ 1504 static inline uint32_t 1505 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1506 { 1507 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1508 1509 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1510 } 1511 1512 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1513 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1514 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1515 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1516 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1517 1518 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1519 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1520 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1521 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1522 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1523 1524 /* 1525 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1526 * @hal_soc_hdl: hal soc handle 1527 * @buf: pointer to the start of RX PKT TLV headera 1528 * @mac_addr: pointer to mac address 1529 * 1530 * Return: success/failure 1531 */ 1532 static inline 1533 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1534 uint8_t *buf, uint8_t *mac_addr) 1535 { 1536 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1537 1538 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1539 } 1540 1541 /* 1542 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1543 * in the packet 1544 * @hal_soc_hdl: hal soc handle 1545 * @buf: pointer to the start of RX PKT TLV header 1546 * @mac_addr: pointer to mac address 1547 * 1548 * Return: success/failure 1549 */ 1550 static inline 1551 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1552 uint8_t *buf, uint8_t *mac_addr) 1553 { 1554 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1555 1556 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1557 } 1558 1559 /* 1560 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1561 * in the packet 1562 * @hal_soc_hdl: hal soc handle 1563 * @buf: pointer to the start of RX PKT TLV header 1564 * @mac_addr: pointer to mac address 1565 * 1566 * Return: success/failure 1567 */ 1568 static inline 1569 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1570 uint8_t *buf, uint8_t *mac_addr) 1571 { 1572 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1573 1574 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1575 } 1576 1577 /* 1578 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1579 * in the packet 1580 * @hal_soc_hdl: hal_soc handle 1581 * @buf: pointer to the start of RX PKT TLV header 1582 * @mac_addr: pointer to mac address 1583 * Return: success/failure 1584 */ 1585 static inline 1586 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1587 uint8_t *buf, uint8_t *mac_addr) 1588 { 1589 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1590 1591 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1592 } 1593 1594 /** 1595 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1596 * from rx_msdu_end TLV 1597 * 1598 * @ buf: pointer to the start of RX PKT TLV headers 1599 * Return: da index 1600 */ 1601 static inline uint16_t 1602 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1603 { 1604 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1605 1606 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1607 } 1608 1609 /** 1610 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1611 * from rx_msdu_end TLV 1612 * @hal_soc_hdl: hal soc handle 1613 * @ buf: pointer to the start of RX PKT TLV headers 1614 * 1615 * Return: da_is_valid 1616 */ 1617 static inline uint8_t 1618 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1619 uint8_t *buf) 1620 { 1621 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1622 1623 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1624 } 1625 1626 /** 1627 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1628 * from rx_msdu_end TLV 1629 * 1630 * @buf: pointer to the start of RX PKT TLV headers 1631 * 1632 * Return: da_is_mcbc 1633 */ 1634 static inline uint8_t 1635 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1636 { 1637 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1638 1639 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1640 } 1641 1642 /** 1643 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1644 * from rx_msdu_end TLV 1645 * @hal_soc_hdl: hal soc handle 1646 * @buf: pointer to the start of RX PKT TLV headers 1647 * 1648 * Return: first_msdu 1649 */ 1650 static inline uint8_t 1651 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1652 uint8_t *buf) 1653 { 1654 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1655 1656 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1657 } 1658 1659 /** 1660 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1661 * from rx_msdu_end TLV 1662 * @hal_soc_hdl: hal soc handle 1663 * @buf: pointer to the start of RX PKT TLV headers 1664 * 1665 * Return: last_msdu 1666 */ 1667 static inline uint8_t 1668 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1669 uint8_t *buf) 1670 { 1671 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1672 1673 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1674 } 1675 1676 /** 1677 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1678 * from rx_msdu_end TLV 1679 * @buf: pointer to the start of RX PKT TLV headers 1680 * Return: cce_meta_data 1681 */ 1682 static inline uint16_t 1683 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1684 uint8_t *buf) 1685 { 1686 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1687 1688 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1689 } 1690 1691 /******************************************************************************* 1692 * RX ERROR APIS 1693 ******************************************************************************/ 1694 1695 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1696 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1697 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1698 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1699 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1700 1701 /** 1702 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1703 * from rx_mpdu_end TLV 1704 * 1705 * @buf: pointer to the start of RX PKT TLV headers 1706 * Return: uint32_t(decrypt_err) 1707 */ 1708 static inline uint32_t 1709 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1710 { 1711 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1712 struct rx_mpdu_end *mpdu_end = 1713 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1714 uint32_t decrypt_err; 1715 1716 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1717 1718 return decrypt_err; 1719 } 1720 1721 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1722 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1723 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1724 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1725 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1726 1727 /** 1728 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1729 * from rx_mpdu_end TLV 1730 * 1731 * @buf: pointer to the start of RX PKT TLV headers 1732 * Return: uint32_t(mic_err) 1733 */ 1734 static inline uint32_t 1735 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1736 { 1737 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1738 struct rx_mpdu_end *mpdu_end = 1739 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1740 uint32_t mic_err; 1741 1742 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1743 1744 return mic_err; 1745 } 1746 1747 /******************************************************************************* 1748 * RX REO ERROR APIS 1749 ******************************************************************************/ 1750 1751 #define HAL_RX_NUM_MSDU_DESC 6 1752 #define HAL_RX_MAX_SAVED_RING_DESC 16 1753 1754 /* TODO: rework the structure */ 1755 struct hal_rx_msdu_list { 1756 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1757 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1758 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1759 /* physical address of the msdu */ 1760 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1761 }; 1762 1763 struct hal_buf_info { 1764 uint64_t paddr; 1765 uint32_t sw_cookie; 1766 uint8_t rbm; 1767 }; 1768 1769 /** 1770 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1771 * @msdu_link_ptr - msdu link ptr 1772 * @hal - pointer to hal_soc 1773 * Return - Pointer to rx_msdu_details structure 1774 * 1775 */ 1776 static inline 1777 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1778 struct hal_soc *hal_soc) 1779 { 1780 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1781 } 1782 1783 /** 1784 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1785 * @msdu_details_ptr - Pointer to msdu_details_ptr 1786 * @hal - pointer to hal_soc 1787 * Return - Pointer to rx_msdu_desc_info structure. 1788 * 1789 */ 1790 static inline 1791 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1792 struct hal_soc *hal_soc) 1793 { 1794 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1795 } 1796 1797 /* This special cookie value will be used to indicate FW allocated buffers 1798 * received through RXDMA2SW ring for RXDMA WARs 1799 */ 1800 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1801 1802 /** 1803 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1804 * from the MSDU link descriptor 1805 * 1806 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1807 * MSDU link descriptor (struct rx_msdu_link) 1808 * 1809 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1810 * 1811 * @num_msdus: Number of MSDUs in the MPDU 1812 * 1813 * Return: void 1814 */ 1815 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1816 void *msdu_link_desc, 1817 struct hal_rx_msdu_list *msdu_list, 1818 uint16_t *num_msdus) 1819 { 1820 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1821 struct rx_msdu_details *msdu_details; 1822 struct rx_msdu_desc_info *msdu_desc_info; 1823 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1824 int i; 1825 1826 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1827 1828 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1829 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1830 __func__, __LINE__, msdu_link, msdu_details); 1831 1832 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1833 /* num_msdus received in mpdu descriptor may be incorrect 1834 * sometimes due to HW issue. Check msdu buffer address also 1835 */ 1836 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1837 &msdu_details[i].buffer_addr_info_details) == 0) { 1838 /* set the last msdu bit in the prev msdu_desc_info */ 1839 msdu_desc_info = 1840 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1841 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1842 break; 1843 } 1844 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1845 hal_soc); 1846 1847 /* set first MSDU bit or the last MSDU bit */ 1848 if (!i) 1849 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1850 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1851 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1852 1853 msdu_list->msdu_info[i].msdu_flags = 1854 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1855 msdu_list->msdu_info[i].msdu_len = 1856 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1857 msdu_list->sw_cookie[i] = 1858 HAL_RX_BUF_COOKIE_GET( 1859 &msdu_details[i].buffer_addr_info_details); 1860 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1861 &msdu_details[i].buffer_addr_info_details); 1862 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1863 &msdu_details[i].buffer_addr_info_details) | 1864 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1865 &msdu_details[i].buffer_addr_info_details) << 32; 1866 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1867 "[%s][%d] i=%d sw_cookie=%d", 1868 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1869 } 1870 *num_msdus = i; 1871 } 1872 1873 /** 1874 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1875 * destination ring ID from the msdu desc info 1876 * 1877 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1878 * the current descriptor 1879 * 1880 * Return: dst_ind (REO destination ring ID) 1881 */ 1882 static inline uint32_t 1883 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 1884 { 1885 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1886 struct rx_msdu_details *msdu_details; 1887 struct rx_msdu_desc_info *msdu_desc_info; 1888 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1889 uint32_t dst_ind; 1890 1891 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1892 1893 /* The first msdu in the link should exsist */ 1894 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1895 hal_soc); 1896 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1897 return dst_ind; 1898 } 1899 1900 /** 1901 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1902 * cookie from the REO destination ring element 1903 * 1904 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1905 * the current descriptor 1906 * @ buf_info: structure to return the buffer information 1907 * Return: void 1908 */ 1909 static inline 1910 void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc, 1911 struct hal_buf_info *buf_info) 1912 { 1913 struct reo_destination_ring *reo_ring = 1914 (struct reo_destination_ring *)rx_desc; 1915 1916 buf_info->paddr = 1917 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 1918 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 1919 1920 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 1921 } 1922 1923 /** 1924 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 1925 * 1926 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 1927 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 1928 * descriptor 1929 */ 1930 enum hal_rx_reo_buf_type { 1931 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 1932 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 1933 }; 1934 1935 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 1936 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 1937 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 1938 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 1939 1940 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 1941 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 1942 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 1943 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 1944 1945 /** 1946 * enum hal_reo_error_code: Error code describing the type of error detected 1947 * 1948 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 1949 * REO_ENTRANCE ring is set to 0 1950 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 1951 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 1952 * having been setup 1953 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 1954 * Retry bit set: duplicate frame 1955 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 1956 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 1957 * received with 2K jump in SN 1958 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 1959 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 1960 * with SN falling within the OOR window 1961 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 1962 * OOR window 1963 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 1964 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 1965 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 1966 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1967 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 1968 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1969 * of the pn_error_detected_flag been set in the REO Queue descriptor 1970 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 1971 * the queue descriptor(address) being blocked as SW/FW seems to be currently 1972 * in the process of making updates to this descriptor 1973 */ 1974 enum hal_reo_error_code { 1975 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 1976 HAL_REO_ERR_QUEUE_DESC_INVALID, 1977 HAL_REO_ERR_AMPDU_IN_NON_BA, 1978 HAL_REO_ERR_NON_BA_DUPLICATE, 1979 HAL_REO_ERR_BA_DUPLICATE, 1980 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 1981 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 1982 HAL_REO_ERR_REGULAR_FRAME_OOR, 1983 HAL_REO_ERR_BAR_FRAME_OOR, 1984 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 1985 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 1986 HAL_REO_ERR_PN_CHECK_FAILED, 1987 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 1988 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 1989 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 1990 HAL_REO_ERR_MAX 1991 }; 1992 1993 /** 1994 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 1995 * 1996 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 1997 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 1998 * overflow 1999 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 2000 * incomplete 2001 * MPDU from the PHY 2002 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 2003 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 2004 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 2005 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 2006 * encrypted but wasn’t 2007 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 2008 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 2009 * the max allowed 2010 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2011 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2012 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2013 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2014 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2015 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2016 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2017 */ 2018 enum hal_rxdma_error_code { 2019 HAL_RXDMA_ERR_OVERFLOW = 0, 2020 HAL_RXDMA_ERR_MPDU_LENGTH, 2021 HAL_RXDMA_ERR_FCS, 2022 HAL_RXDMA_ERR_DECRYPT, 2023 HAL_RXDMA_ERR_TKIP_MIC, 2024 HAL_RXDMA_ERR_UNENCRYPTED, 2025 HAL_RXDMA_ERR_MSDU_LEN, 2026 HAL_RXDMA_ERR_MSDU_LIMIT, 2027 HAL_RXDMA_ERR_WIFI_PARSE, 2028 HAL_RXDMA_ERR_AMSDU_PARSE, 2029 HAL_RXDMA_ERR_SA_TIMEOUT, 2030 HAL_RXDMA_ERR_DA_TIMEOUT, 2031 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2032 HAL_RXDMA_ERR_FLUSH_REQUEST, 2033 HAL_RXDMA_ERR_WAR = 31, 2034 HAL_RXDMA_ERR_MAX 2035 }; 2036 2037 /** 2038 * HW BM action settings in WBM release ring 2039 */ 2040 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2041 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2042 2043 /** 2044 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2045 * release of this buffer or descriptor 2046 * 2047 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2048 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2049 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2050 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2051 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2052 */ 2053 enum hal_rx_wbm_error_source { 2054 HAL_RX_WBM_ERR_SRC_TQM = 0, 2055 HAL_RX_WBM_ERR_SRC_RXDMA, 2056 HAL_RX_WBM_ERR_SRC_REO, 2057 HAL_RX_WBM_ERR_SRC_FW, 2058 HAL_RX_WBM_ERR_SRC_SW, 2059 }; 2060 2061 /** 2062 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2063 * released 2064 * 2065 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2066 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2067 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2068 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2069 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2070 */ 2071 enum hal_rx_wbm_buf_type { 2072 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2073 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2074 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2075 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2076 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2077 }; 2078 2079 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2080 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2081 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2082 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2083 2084 /** 2085 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2086 * PN check failure 2087 * 2088 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2089 * 2090 * Return: true: error caused by PN check, false: other error 2091 */ 2092 static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc) 2093 { 2094 struct reo_destination_ring *reo_desc = 2095 (struct reo_destination_ring *)rx_desc; 2096 2097 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2098 HAL_REO_ERR_PN_CHECK_FAILED) | 2099 (HAL_RX_REO_ERROR_GET(reo_desc) == 2100 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2101 true : false; 2102 } 2103 2104 /** 2105 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2106 * the sequence number 2107 * 2108 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2109 * 2110 * Return: true: error caused by 2K jump, false: other error 2111 */ 2112 static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc) 2113 { 2114 struct reo_destination_ring *reo_desc = 2115 (struct reo_destination_ring *)rx_desc; 2116 2117 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2118 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2119 (HAL_RX_REO_ERROR_GET(reo_desc) == 2120 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2121 true : false; 2122 } 2123 2124 /** 2125 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 2126 * 2127 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2128 * 2129 * Return: true: error caused by OOR, false: other error 2130 */ 2131 static inline bool hal_rx_reo_is_oor_error(void *rx_desc) 2132 { 2133 struct reo_destination_ring *reo_desc = 2134 (struct reo_destination_ring *)rx_desc; 2135 2136 return (HAL_RX_REO_ERROR_GET(reo_desc) == 2137 HAL_REO_ERR_REGULAR_FRAME_OOR) ? true : false; 2138 } 2139 2140 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 2141 /** 2142 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 2143 * @hal_desc: hardware descriptor pointer 2144 * 2145 * This function will print wbm release descriptor 2146 * 2147 * Return: none 2148 */ 2149 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 2150 { 2151 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 2152 uint32_t i; 2153 2154 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2155 "Current Rx wbm release descriptor is"); 2156 2157 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 2158 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2159 "DWORD[i] = 0x%x", wbm_comp[i]); 2160 } 2161 } 2162 2163 /** 2164 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2165 * 2166 * @ hal_soc_hdl : HAL version of the SOC pointer 2167 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2168 * @ buf_addr_info : void pointer to the buffer_addr_info 2169 * @ bm_action : put in IDLE list or release to MSDU_LIST 2170 * 2171 * Return: void 2172 */ 2173 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2174 static inline 2175 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 2176 void *src_srng_desc, 2177 hal_buff_addrinfo_t buf_addr_info, 2178 uint8_t bm_action) 2179 { 2180 struct wbm_release_ring *wbm_rel_srng = 2181 (struct wbm_release_ring *)src_srng_desc; 2182 uint32_t addr_31_0; 2183 uint8_t addr_39_32; 2184 2185 /* Structure copy !!! */ 2186 wbm_rel_srng->released_buff_or_desc_addr_info = 2187 *((struct buffer_addr_info *)buf_addr_info); 2188 2189 addr_31_0 = 2190 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 2191 addr_39_32 = 2192 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 2193 2194 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2195 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2196 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2197 bm_action); 2198 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2199 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2200 2201 /* WBM error is indicated when any of the link descriptors given to 2202 * WBM has a NULL address, and one those paths is the link descriptors 2203 * released from host after processing RXDMA errors, 2204 * or from Rx defrag path, and we want to add an assert here to ensure 2205 * host is not releasing descriptors with NULL address. 2206 */ 2207 2208 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 2209 hal_dump_wbm_rel_desc(src_srng_desc); 2210 qdf_assert_always(0); 2211 } 2212 } 2213 2214 /* 2215 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2216 * REO entrance ring 2217 * 2218 * @ soc: HAL version of the SOC pointer 2219 * @ pa: Physical address of the MSDU Link Descriptor 2220 * @ cookie: SW cookie to get to the virtual address 2221 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2222 * to the error enabled REO queue 2223 * 2224 * Return: void 2225 */ 2226 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2227 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2228 { 2229 /* TODO */ 2230 } 2231 2232 /** 2233 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2234 * BUFFER_ADDR_INFO, give the RX descriptor 2235 * (Assumption -- BUFFER_ADDR_INFO is the 2236 * first field in the descriptor structure) 2237 */ 2238 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 2239 ((hal_link_desc_t)(ring_desc)) 2240 2241 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2242 2243 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2244 2245 /** 2246 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2247 * from the BUFFER_ADDR_INFO structure 2248 * given a REO destination ring descriptor. 2249 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2250 * 2251 * Return: uint8_t (value of the return_buffer_manager) 2252 */ 2253 static inline 2254 uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc) 2255 { 2256 /* 2257 * The following macro takes buf_addr_info as argument, 2258 * but since buf_addr_info is the first field in ring_desc 2259 * Hence the following call is OK 2260 */ 2261 return HAL_RX_BUF_RBM_GET(ring_desc); 2262 } 2263 2264 2265 /******************************************************************************* 2266 * RX WBM ERROR APIS 2267 ******************************************************************************/ 2268 2269 2270 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2271 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2272 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2273 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2274 2275 /** 2276 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2277 * the frame to this release ring 2278 * 2279 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2280 * frame to this queue 2281 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2282 * received routing instructions. No error within REO was detected 2283 */ 2284 enum hal_rx_wbm_reo_push_reason { 2285 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2286 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2287 }; 2288 2289 2290 /** 2291 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2292 * this release ring 2293 * 2294 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2295 * this frame to this queue 2296 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2297 * per received routing instructions. No error within RXDMA was detected 2298 */ 2299 enum hal_rx_wbm_rxdma_push_reason { 2300 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2301 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2302 }; 2303 2304 2305 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2306 (((*(((uint32_t *) wbm_desc) + \ 2307 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2308 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2309 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2310 2311 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2312 (((*(((uint32_t *) wbm_desc) + \ 2313 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2314 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2315 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2316 2317 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2318 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2319 wbm_desc)->released_buff_or_desc_addr_info) 2320 2321 /** 2322 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2323 * humman readable format. 2324 * @ rx_attn: pointer the rx_attention TLV in pkt. 2325 * @ dbg_level: log level. 2326 * 2327 * Return: void 2328 */ 2329 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2330 uint8_t dbg_level) 2331 { 2332 hal_verbose_debug( 2333 "rx_attention tlv (1/2) - " 2334 "rxpcu_mpdu_filter_in_category: %x " 2335 "sw_frame_group_id: %x " 2336 "reserved_0: %x " 2337 "phy_ppdu_id: %x " 2338 "first_mpdu : %x " 2339 "reserved_1a: %x " 2340 "mcast_bcast: %x " 2341 "ast_index_not_found: %x " 2342 "ast_index_timeout: %x " 2343 "power_mgmt: %x " 2344 "non_qos: %x " 2345 "null_data: %x " 2346 "mgmt_type: %x " 2347 "ctrl_type: %x " 2348 "more_data: %x " 2349 "eosp: %x " 2350 "a_msdu_error: %x " 2351 "fragment_flag: %x " 2352 "order: %x " 2353 "cce_match: %x " 2354 "overflow_err: %x " 2355 "msdu_length_err: %x " 2356 "tcp_udp_chksum_fail: %x " 2357 "ip_chksum_fail: %x " 2358 "sa_idx_invalid: %x " 2359 "da_idx_invalid: %x " 2360 "reserved_1b: %x " 2361 "rx_in_tx_decrypt_byp: %x ", 2362 rx_attn->rxpcu_mpdu_filter_in_category, 2363 rx_attn->sw_frame_group_id, 2364 rx_attn->reserved_0, 2365 rx_attn->phy_ppdu_id, 2366 rx_attn->first_mpdu, 2367 rx_attn->reserved_1a, 2368 rx_attn->mcast_bcast, 2369 rx_attn->ast_index_not_found, 2370 rx_attn->ast_index_timeout, 2371 rx_attn->power_mgmt, 2372 rx_attn->non_qos, 2373 rx_attn->null_data, 2374 rx_attn->mgmt_type, 2375 rx_attn->ctrl_type, 2376 rx_attn->more_data, 2377 rx_attn->eosp, 2378 rx_attn->a_msdu_error, 2379 rx_attn->fragment_flag, 2380 rx_attn->order, 2381 rx_attn->cce_match, 2382 rx_attn->overflow_err, 2383 rx_attn->msdu_length_err, 2384 rx_attn->tcp_udp_chksum_fail, 2385 rx_attn->ip_chksum_fail, 2386 rx_attn->sa_idx_invalid, 2387 rx_attn->da_idx_invalid, 2388 rx_attn->reserved_1b, 2389 rx_attn->rx_in_tx_decrypt_byp); 2390 2391 hal_verbose_debug( 2392 "rx_attention tlv (2/2) - " 2393 "encrypt_required: %x " 2394 "directed: %x " 2395 "buffer_fragment: %x " 2396 "mpdu_length_err: %x " 2397 "tkip_mic_err: %x " 2398 "decrypt_err: %x " 2399 "unencrypted_frame_err: %x " 2400 "fcs_err: %x " 2401 "flow_idx_timeout: %x " 2402 "flow_idx_invalid: %x " 2403 "wifi_parser_error: %x " 2404 "amsdu_parser_error: %x " 2405 "sa_idx_timeout: %x " 2406 "da_idx_timeout: %x " 2407 "msdu_limit_error: %x " 2408 "da_is_valid: %x " 2409 "da_is_mcbc: %x " 2410 "sa_is_valid: %x " 2411 "decrypt_status_code: %x " 2412 "rx_bitmap_not_updated: %x " 2413 "reserved_2: %x " 2414 "msdu_done: %x ", 2415 rx_attn->encrypt_required, 2416 rx_attn->directed, 2417 rx_attn->buffer_fragment, 2418 rx_attn->mpdu_length_err, 2419 rx_attn->tkip_mic_err, 2420 rx_attn->decrypt_err, 2421 rx_attn->unencrypted_frame_err, 2422 rx_attn->fcs_err, 2423 rx_attn->flow_idx_timeout, 2424 rx_attn->flow_idx_invalid, 2425 rx_attn->wifi_parser_error, 2426 rx_attn->amsdu_parser_error, 2427 rx_attn->sa_idx_timeout, 2428 rx_attn->da_idx_timeout, 2429 rx_attn->msdu_limit_error, 2430 rx_attn->da_is_valid, 2431 rx_attn->da_is_mcbc, 2432 rx_attn->sa_is_valid, 2433 rx_attn->decrypt_status_code, 2434 rx_attn->rx_bitmap_not_updated, 2435 rx_attn->reserved_2, 2436 rx_attn->msdu_done); 2437 } 2438 2439 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2440 uint8_t dbg_level, 2441 struct hal_soc *hal) 2442 { 2443 2444 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2445 } 2446 /** 2447 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2448 * human readable format. 2449 * @ msdu_end: pointer the msdu_end TLV in pkt. 2450 * @ dbg_level: log level. 2451 * 2452 * Return: void 2453 */ 2454 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2455 struct rx_msdu_end *msdu_end, 2456 uint8_t dbg_level) 2457 { 2458 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2459 } 2460 2461 /** 2462 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2463 * human readable format. 2464 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2465 * @ dbg_level: log level. 2466 * 2467 * Return: void 2468 */ 2469 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2470 uint8_t dbg_level) 2471 { 2472 hal_verbose_debug( 2473 "rx_mpdu_end tlv - " 2474 "rxpcu_mpdu_filter_in_category: %x " 2475 "sw_frame_group_id: %x " 2476 "phy_ppdu_id: %x " 2477 "unsup_ktype_short_frame: %x " 2478 "rx_in_tx_decrypt_byp: %x " 2479 "overflow_err: %x " 2480 "mpdu_length_err: %x " 2481 "tkip_mic_err: %x " 2482 "decrypt_err: %x " 2483 "unencrypted_frame_err: %x " 2484 "pn_fields_contain_valid_info: %x " 2485 "fcs_err: %x " 2486 "msdu_length_err: %x " 2487 "rxdma0_destination_ring: %x " 2488 "rxdma1_destination_ring: %x " 2489 "decrypt_status_code: %x " 2490 "rx_bitmap_not_updated: %x ", 2491 mpdu_end->rxpcu_mpdu_filter_in_category, 2492 mpdu_end->sw_frame_group_id, 2493 mpdu_end->phy_ppdu_id, 2494 mpdu_end->unsup_ktype_short_frame, 2495 mpdu_end->rx_in_tx_decrypt_byp, 2496 mpdu_end->overflow_err, 2497 mpdu_end->mpdu_length_err, 2498 mpdu_end->tkip_mic_err, 2499 mpdu_end->decrypt_err, 2500 mpdu_end->unencrypted_frame_err, 2501 mpdu_end->pn_fields_contain_valid_info, 2502 mpdu_end->fcs_err, 2503 mpdu_end->msdu_length_err, 2504 mpdu_end->rxdma0_destination_ring, 2505 mpdu_end->rxdma1_destination_ring, 2506 mpdu_end->decrypt_status_code, 2507 mpdu_end->rx_bitmap_not_updated); 2508 } 2509 2510 #ifdef NO_RX_PKT_HDR_TLV 2511 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2512 uint8_t dbg_level) 2513 { 2514 } 2515 #else 2516 /** 2517 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2518 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2519 * @ dbg_level: log level. 2520 * 2521 * Return: void 2522 */ 2523 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2524 uint8_t dbg_level) 2525 { 2526 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2527 2528 hal_verbose_debug( 2529 "\n---------------\n" 2530 "rx_pkt_hdr_tlv \n" 2531 "---------------\n" 2532 "phy_ppdu_id %d ", 2533 pkt_hdr_tlv->phy_ppdu_id); 2534 2535 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2536 } 2537 #endif 2538 2539 /** 2540 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2541 * structure 2542 * @hal_ring: pointer to hal_srng structure 2543 * 2544 * Return: ring_id 2545 */ 2546 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 2547 { 2548 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 2549 } 2550 2551 /* Rx MSDU link pointer info */ 2552 struct hal_rx_msdu_link_ptr_info { 2553 struct rx_msdu_link msdu_link; 2554 struct hal_buf_info msdu_link_buf_info; 2555 }; 2556 2557 /** 2558 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2559 * 2560 * @nbuf: Pointer to data buffer field 2561 * Returns: pointer to rx_pkt_tlvs 2562 */ 2563 static inline 2564 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2565 { 2566 return (struct rx_pkt_tlvs *)rx_buf_start; 2567 } 2568 2569 /** 2570 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2571 * 2572 * @pkt_tlvs: Pointer to pkt_tlvs 2573 * Returns: pointer to rx_mpdu_info structure 2574 */ 2575 static inline 2576 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2577 { 2578 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2579 } 2580 2581 #define DOT11_SEQ_FRAG_MASK 0x000f 2582 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2583 2584 /** 2585 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2586 * 2587 * @nbuf: Network buffer 2588 * Returns: rx fragment number 2589 */ 2590 static inline 2591 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 2592 uint8_t *buf) 2593 { 2594 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 2595 } 2596 2597 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2598 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2599 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2600 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2601 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2602 /** 2603 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2604 * 2605 * @nbuf: Network buffer 2606 * Returns: rx more fragment bit 2607 */ 2608 static inline 2609 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2610 { 2611 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2612 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2613 uint16_t frame_ctrl = 0; 2614 2615 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2616 DOT11_FC1_MORE_FRAG_OFFSET; 2617 2618 /* more fragment bit if at offset bit 4 */ 2619 return frame_ctrl; 2620 } 2621 2622 /** 2623 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2624 * 2625 * @nbuf: Network buffer 2626 * Returns: rx more fragment bit 2627 * 2628 */ 2629 static inline 2630 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2631 { 2632 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2633 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2634 uint16_t frame_ctrl = 0; 2635 2636 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2637 2638 return frame_ctrl; 2639 } 2640 2641 /* 2642 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2643 * 2644 * @nbuf: Network buffer 2645 * Returns: flag to indicate whether the nbuf has MC/BC address 2646 */ 2647 static inline 2648 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2649 { 2650 uint8 *buf = qdf_nbuf_data(nbuf); 2651 2652 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2653 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2654 2655 return rx_attn->mcast_bcast; 2656 } 2657 2658 /* 2659 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2660 * @hal_soc_hdl: hal soc handle 2661 * @nbuf: Network buffer 2662 * 2663 * Return: value of sequence control valid field 2664 */ 2665 static inline 2666 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 2667 uint8_t *buf) 2668 { 2669 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2670 2671 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 2672 } 2673 2674 /* 2675 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2676 * @hal_soc_hdl: hal soc handle 2677 * @nbuf: Network buffer 2678 * 2679 * Returns: value of frame control valid field 2680 */ 2681 static inline 2682 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 2683 uint8_t *buf) 2684 { 2685 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2686 2687 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 2688 } 2689 2690 /** 2691 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2692 * @hal_soc_hdl: hal soc handle 2693 * @nbuf: Network buffer 2694 * Returns: value of mpdu 4th address valid field 2695 */ 2696 static inline 2697 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 2698 uint8_t *buf) 2699 { 2700 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2701 2702 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 2703 } 2704 2705 /* 2706 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2707 * 2708 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2709 * Returns: None 2710 */ 2711 static inline 2712 void hal_rx_clear_mpdu_desc_info( 2713 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2714 { 2715 qdf_mem_zero(rx_mpdu_desc_info, 2716 sizeof(*rx_mpdu_desc_info)); 2717 } 2718 2719 /* 2720 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2721 * 2722 * @msdu_link_ptr: HAL view of msdu link ptr 2723 * @size: number of msdu link pointers 2724 * Returns: None 2725 */ 2726 static inline 2727 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2728 int size) 2729 { 2730 qdf_mem_zero(msdu_link_ptr, 2731 (sizeof(*msdu_link_ptr) * size)); 2732 } 2733 2734 /* 2735 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2736 * @msdu_link_ptr: msdu link pointer 2737 * @mpdu_desc_info: mpdu descriptor info 2738 * 2739 * Build a list of msdus using msdu link pointer. If the 2740 * number of msdus are more, chain them together 2741 * 2742 * Returns: Number of processed msdus 2743 */ 2744 static inline 2745 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2746 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2747 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2748 { 2749 int j; 2750 struct rx_msdu_link *msdu_link_ptr = 2751 &msdu_link_ptr_info->msdu_link; 2752 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2753 struct rx_msdu_details *msdu_details = 2754 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2755 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2756 struct rx_msdu_desc_info *msdu_desc_info; 2757 uint8_t fragno, more_frag; 2758 uint8_t *rx_desc_info; 2759 struct hal_rx_msdu_list msdu_list; 2760 2761 for (j = 0; j < num_msdus; j++) { 2762 msdu_desc_info = 2763 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2764 hal_soc); 2765 msdu_list.msdu_info[j].msdu_flags = 2766 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2767 msdu_list.msdu_info[j].msdu_len = 2768 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2769 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2770 &msdu_details[j].buffer_addr_info_details); 2771 } 2772 2773 /* Chain msdu links together */ 2774 if (prev_msdu_link_ptr) { 2775 /* 31-0 bits of the physical address */ 2776 prev_msdu_link_ptr-> 2777 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2778 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2779 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2780 /* 39-32 bits of the physical address */ 2781 prev_msdu_link_ptr-> 2782 next_msdu_link_desc_addr_info.buffer_addr_39_32 2783 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2784 >> 32) & 2785 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2786 prev_msdu_link_ptr-> 2787 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2788 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2789 } 2790 2791 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2792 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2793 /* mark first and last MSDUs */ 2794 rx_desc_info = qdf_nbuf_data(msdu); 2795 fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info); 2796 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2797 2798 /* TODO: create skb->fragslist[] */ 2799 2800 if (more_frag == 0) { 2801 msdu_list.msdu_info[num_msdus].msdu_flags |= 2802 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2803 } else if (fragno == 1) { 2804 msdu_list.msdu_info[num_msdus].msdu_flags |= 2805 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2806 2807 msdu_list.msdu_info[num_msdus].msdu_flags |= 2808 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2809 } 2810 2811 num_msdus++; 2812 2813 /* Number of MSDUs per mpdu descriptor is updated */ 2814 mpdu_desc_info->msdu_count += num_msdus; 2815 } else { 2816 num_msdus = 0; 2817 prev_msdu_link_ptr = msdu_link_ptr; 2818 } 2819 2820 return num_msdus; 2821 } 2822 2823 /* 2824 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2825 * 2826 * @ring_desc: HAL view of ring descriptor 2827 * @mpdu_des_info: saved mpdu desc info 2828 * @msdu_link_ptr: saved msdu link ptr 2829 * 2830 * API used explicitly for rx defrag to update ring desc with 2831 * mpdu desc info and msdu link ptr before reinjecting the 2832 * packet back to REO 2833 * 2834 * Returns: None 2835 */ 2836 static inline 2837 void hal_rx_defrag_update_src_ring_desc( 2838 hal_ring_desc_t ring_desc, 2839 void *saved_mpdu_desc_info, 2840 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 2841 { 2842 struct reo_entrance_ring *reo_ent_ring; 2843 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 2844 struct hal_buf_info buf_info; 2845 2846 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 2847 reo_ring_mpdu_desc_info = &reo_ent_ring-> 2848 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 2849 2850 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 2851 sizeof(*reo_ring_mpdu_desc_info)); 2852 2853 /* 2854 * TODO: Check for additional fields that need configuration in 2855 * reo_ring_mpdu_desc_info 2856 */ 2857 2858 /* Update msdu_link_ptr in the reo entrance ring */ 2859 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 2860 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 2861 buf_info.sw_cookie = 2862 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 2863 } 2864 2865 /* 2866 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 2867 * 2868 * @msdu_link_desc_va: msdu link descriptor handle 2869 * @msdu_link_ptr_info: HAL view of msdu link pointer info 2870 * 2871 * API used to save msdu link information along with physical 2872 * address. The API also copues the sw cookie. 2873 * 2874 * Returns: None 2875 */ 2876 static inline 2877 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 2878 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2879 struct hal_buf_info *hbi) 2880 { 2881 struct rx_msdu_link *msdu_link_ptr = 2882 (struct rx_msdu_link *)msdu_link_desc_va; 2883 2884 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 2885 sizeof(struct rx_msdu_link)); 2886 2887 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 2888 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 2889 } 2890 2891 /* 2892 * hal_rx_get_desc_len(): Returns rx descriptor length 2893 * 2894 * Returns the size of rx_pkt_tlvs which follows the 2895 * data in the nbuf 2896 * 2897 * Returns: Length of rx descriptor 2898 */ 2899 static inline 2900 uint16_t hal_rx_get_desc_len(void) 2901 { 2902 return SIZE_OF_DATA_RX_TLV; 2903 } 2904 2905 /* 2906 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 2907 * reo_entrance_ring descriptor 2908 * 2909 * @reo_ent_desc: reo_entrance_ring descriptor 2910 * Returns: value of rxdma_push_reason 2911 */ 2912 static inline 2913 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 2914 { 2915 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2916 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 2917 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 2918 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 2919 } 2920 2921 /** 2922 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 2923 * reo_entrance_ring descriptor 2924 * @reo_ent_desc: reo_entrance_ring descriptor 2925 * Return: value of rxdma_error_code 2926 */ 2927 static inline 2928 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 2929 { 2930 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2931 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 2932 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 2933 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 2934 } 2935 2936 /** 2937 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 2938 * save it to hal_wbm_err_desc_info structure passed by caller 2939 * @wbm_desc: wbm ring descriptor 2940 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2941 * Return: void 2942 */ 2943 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 2944 struct hal_wbm_err_desc_info *wbm_er_info, 2945 hal_soc_handle_t hal_soc_hdl) 2946 { 2947 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2948 2949 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 2950 } 2951 2952 /** 2953 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 2954 * the reserved bytes of rx_tlv_hdr 2955 * @buf: start of rx_tlv_hdr 2956 * @wbm_er_info: hal_wbm_err_desc_info structure 2957 * Return: void 2958 */ 2959 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 2960 struct hal_wbm_err_desc_info *wbm_er_info) 2961 { 2962 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2963 2964 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 2965 sizeof(struct hal_wbm_err_desc_info)); 2966 } 2967 2968 /** 2969 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 2970 * the reserved bytes of rx_tlv_hdr. 2971 * @buf: start of rx_tlv_hdr 2972 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2973 * Return: void 2974 */ 2975 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 2976 struct hal_wbm_err_desc_info *wbm_er_info) 2977 { 2978 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2979 2980 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 2981 sizeof(struct hal_wbm_err_desc_info)); 2982 } 2983 2984 /** 2985 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 2986 * bit from wbm release ring descriptor 2987 * @wbm_desc: wbm ring descriptor 2988 * Return: uint8_t 2989 */ 2990 static inline 2991 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 2992 void *wbm_desc) 2993 { 2994 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2995 2996 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 2997 } 2998 2999 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 3000 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 3001 RX_MSDU_START_5_NSS_OFFSET)), \ 3002 RX_MSDU_START_5_NSS_MASK, \ 3003 RX_MSDU_START_5_NSS_LSB)) 3004 3005 /** 3006 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 3007 * 3008 * @ hal_soc: HAL version of the SOC pointer 3009 * @ hw_desc_addr: Start address of Rx HW TLVs 3010 * @ rs: Status for monitor mode 3011 * 3012 * Return: void 3013 */ 3014 static inline 3015 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 3016 void *hw_desc_addr, 3017 struct mon_rx_status *rs) 3018 { 3019 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3020 3021 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 3022 } 3023 3024 /* 3025 * hal_rx_get_tlv(): API to get the tlv 3026 * 3027 * @hal_soc: HAL version of the SOC pointer 3028 * @rx_tlv: TLV data extracted from the rx packet 3029 * Return: uint8_t 3030 */ 3031 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 3032 { 3033 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 3034 } 3035 3036 /* 3037 * hal_rx_msdu_start_nss_get(): API to get the NSS 3038 * Interval from rx_msdu_start 3039 * 3040 * @hal_soc: HAL version of the SOC pointer 3041 * @buf: pointer to the start of RX PKT TLV header 3042 * Return: uint32_t(nss) 3043 */ 3044 static inline 3045 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3046 { 3047 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3048 3049 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3050 } 3051 3052 /** 3053 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3054 * human readable format. 3055 * @ msdu_start: pointer the msdu_start TLV in pkt. 3056 * @ dbg_level: log level. 3057 * 3058 * Return: void 3059 */ 3060 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3061 struct rx_msdu_start *msdu_start, 3062 uint8_t dbg_level) 3063 { 3064 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3065 } 3066 3067 /** 3068 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3069 * info details 3070 * 3071 * @ buf - Pointer to buffer containing rx pkt tlvs. 3072 * 3073 * 3074 */ 3075 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 3076 uint8_t *buf) 3077 { 3078 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3079 3080 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3081 } 3082 3083 /* 3084 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3085 * Interval from rx_msdu_start 3086 * 3087 * @buf: pointer to the start of RX PKT TLV header 3088 * Return: uint32_t(reception_type) 3089 */ 3090 static inline 3091 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 3092 uint8_t *buf) 3093 { 3094 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3095 3096 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3097 } 3098 3099 /** 3100 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3101 * RX TLVs 3102 * @ buf: pointer the pkt buffer. 3103 * @ dbg_level: log level. 3104 * 3105 * Return: void 3106 */ 3107 static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 3108 uint8_t *buf, uint8_t dbg_level) 3109 { 3110 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3111 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3112 struct rx_mpdu_start *mpdu_start = 3113 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3114 struct rx_msdu_start *msdu_start = 3115 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3116 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3117 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3118 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3119 3120 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3121 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3122 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3123 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3124 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3125 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3126 } 3127 3128 3129 /** 3130 * hal_reo_status_get_header_generic - Process reo desc info 3131 * @d - Pointer to reo descriptior 3132 * @b - tlv type info 3133 * @h - Pointer to hal_reo_status_header where info to be stored 3134 * @hal- pointer to hal_soc structure 3135 * Return - none. 3136 * 3137 */ 3138 static inline 3139 void hal_reo_status_get_header(uint32_t *d, int b, 3140 void *h, struct hal_soc *hal_soc) 3141 { 3142 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3143 } 3144 3145 /** 3146 * hal_rx_desc_is_first_msdu() - Check if first msdu 3147 * 3148 * @hal_soc_hdl: hal_soc handle 3149 * @hw_desc_addr: hardware descriptor address 3150 * 3151 * Return: 0 - success/ non-zero failure 3152 */ 3153 static inline 3154 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 3155 void *hw_desc_addr) 3156 { 3157 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3158 3159 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 3160 } 3161 3162 static inline 3163 uint32_t 3164 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3165 struct rx_msdu_start *rx_msdu_start; 3166 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3167 3168 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3169 3170 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3171 } 3172 3173 #ifdef NO_RX_PKT_HDR_TLV 3174 static inline 3175 uint8_t * 3176 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3177 uint8_t *rx_pkt_hdr; 3178 struct rx_mon_pkt_tlvs *rx_desc = 3179 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 3180 3181 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3182 3183 return rx_pkt_hdr; 3184 } 3185 #else 3186 static inline 3187 uint8_t * 3188 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3189 uint8_t *rx_pkt_hdr; 3190 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3191 3192 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3193 3194 return rx_pkt_hdr; 3195 } 3196 #endif 3197 3198 static inline 3199 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3200 uint8_t *rx_tlv_hdr) 3201 { 3202 uint8_t decap_format; 3203 3204 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 3205 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3206 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3207 return true; 3208 } 3209 3210 return false; 3211 } 3212 3213 /** 3214 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 3215 * from rx_msdu_end TLV 3216 * @buf: pointer to the start of RX PKT TLV headers 3217 * 3218 * Return: fse metadata value from MSDU END TLV 3219 */ 3220 static inline uint32_t 3221 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 3222 uint8_t *buf) 3223 { 3224 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3225 3226 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 3227 } 3228 3229 /** 3230 * hal_rx_msdu_flow_idx_get: API to get flow index 3231 * from rx_msdu_end TLV 3232 * @buf: pointer to the start of RX PKT TLV headers 3233 * 3234 * Return: flow index value from MSDU END TLV 3235 */ 3236 static inline uint32_t 3237 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 3238 uint8_t *buf) 3239 { 3240 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3241 3242 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 3243 } 3244 3245 /** 3246 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 3247 * from rx_msdu_end TLV 3248 * @buf: pointer to the start of RX PKT TLV headers 3249 * 3250 * Return: flow index timeout value from MSDU END TLV 3251 */ 3252 static inline bool 3253 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 3254 uint8_t *buf) 3255 { 3256 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3257 3258 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 3259 } 3260 3261 /** 3262 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 3263 * from rx_msdu_end TLV 3264 * @buf: pointer to the start of RX PKT TLV headers 3265 * 3266 * Return: flow index invalid value from MSDU END TLV 3267 */ 3268 static inline bool 3269 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 3270 uint8_t *buf) 3271 { 3272 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3273 3274 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 3275 } 3276 3277 /** 3278 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 3279 * @hal_soc_hdl: hal_soc handle 3280 * @rx_tlv_hdr: Rx_tlv_hdr 3281 * @rxdma_dst_ring_desc: Rx HW descriptor 3282 * 3283 * Return: ppdu id 3284 */ 3285 static inline 3286 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 3287 void *rx_tlv_hdr, 3288 void *rxdma_dst_ring_desc) 3289 { 3290 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3291 3292 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 3293 rxdma_dst_ring_desc); 3294 } 3295 3296 /** 3297 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 3298 * @hal_soc_hdl: hal_soc handle 3299 * @buf: rx tlv address 3300 * 3301 * Return: sw peer id 3302 */ 3303 static inline 3304 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 3305 uint8_t *buf) 3306 { 3307 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3308 3309 if ((!hal_soc) || (!hal_soc->ops)) { 3310 hal_err("hal handle is NULL"); 3311 QDF_BUG(0); 3312 return QDF_STATUS_E_INVAL; 3313 } 3314 3315 if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get) 3316 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 3317 3318 return QDF_STATUS_E_INVAL; 3319 } 3320 3321 static inline 3322 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 3323 void *link_desc_addr) 3324 { 3325 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3326 3327 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 3328 } 3329 3330 static inline 3331 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 3332 void *msdu_addr) 3333 { 3334 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3335 3336 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 3337 } 3338 3339 static inline 3340 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3341 void *hw_addr) 3342 { 3343 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3344 3345 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 3346 } 3347 3348 static inline 3349 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3350 void *hw_addr) 3351 { 3352 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3353 3354 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 3355 } 3356 3357 static inline 3358 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 3359 uint8_t *buf) 3360 { 3361 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3362 3363 return hal_soc->ops->hal_rx_get_fc_valid(buf); 3364 } 3365 3366 static inline 3367 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3368 { 3369 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3370 3371 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 3372 } 3373 3374 static inline 3375 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 3376 uint8_t *buf) 3377 { 3378 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3379 3380 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 3381 } 3382 3383 static inline 3384 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 3385 uint8_t *buf) 3386 { 3387 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3388 3389 return hal_soc->ops->hal_rx_get_filter_category(buf); 3390 } 3391 3392 static inline 3393 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 3394 uint8_t *buf) 3395 { 3396 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3397 3398 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 3399 } 3400 3401 /** 3402 * hal_reo_config(): Set reo config parameters 3403 * @soc: hal soc handle 3404 * @reg_val: value to be set 3405 * @reo_params: reo parameters 3406 * 3407 * Return: void 3408 */ 3409 static inline 3410 void hal_reo_config(struct hal_soc *hal_soc, 3411 uint32_t reg_val, 3412 struct hal_reo_params *reo_params) 3413 { 3414 hal_soc->ops->hal_reo_config(hal_soc, 3415 reg_val, 3416 reo_params); 3417 } 3418 3419 /** 3420 * hal_rx_msdu_get_flow_params: API to get flow index, 3421 * flow index invalid and flow index timeout from rx_msdu_end TLV 3422 * @buf: pointer to the start of RX PKT TLV headers 3423 * @flow_invalid: pointer to return value of flow_idx_valid 3424 * @flow_timeout: pointer to return value of flow_idx_timeout 3425 * @flow_index: pointer to return value of flow_idx 3426 * 3427 * Return: none 3428 */ 3429 static inline void 3430 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 3431 uint8_t *buf, 3432 bool *flow_invalid, 3433 bool *flow_timeout, 3434 uint32_t *flow_index) 3435 { 3436 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3437 3438 if ((!hal_soc) || (!hal_soc->ops)) { 3439 hal_err("hal handle is NULL"); 3440 QDF_BUG(0); 3441 return; 3442 } 3443 3444 if (hal_soc->ops->hal_rx_msdu_get_flow_params) 3445 hal_soc->ops-> 3446 hal_rx_msdu_get_flow_params(buf, 3447 flow_invalid, 3448 flow_timeout, 3449 flow_index); 3450 } 3451 3452 static inline 3453 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 3454 uint8_t *buf) 3455 { 3456 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3457 3458 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 3459 } 3460 3461 static inline 3462 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 3463 uint8_t *buf) 3464 { 3465 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3466 3467 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 3468 } 3469 3470 static inline void 3471 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 3472 void *rx_tlv, 3473 void *ppdu_info) 3474 { 3475 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3476 3477 if (hal_soc->ops->hal_rx_get_bb_info) 3478 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 3479 } 3480 3481 static inline void 3482 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 3483 void *rx_tlv, 3484 void *ppdu_info) 3485 { 3486 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3487 3488 if (hal_soc->ops->hal_rx_get_rtt_info) 3489 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 3490 } 3491 3492 /** 3493 * hal_rx_msdu_metadata_get(): API to get the 3494 * fast path information from rx_msdu_end TLV 3495 * 3496 * @ hal_soc_hdl: DP soc handle 3497 * @ buf: pointer to the start of RX PKT TLV headers 3498 * @ msdu_metadata: Structure to hold msdu end information 3499 * Return: none 3500 */ 3501 static inline void 3502 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 3503 struct hal_rx_msdu_metadata *msdu_md) 3504 { 3505 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3506 3507 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 3508 } 3509 3510 /** 3511 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 3512 * from rx_msdu_end TLV 3513 * @buf: pointer to the start of RX PKT TLV headers 3514 * 3515 * Return: cumulative_l4_checksum 3516 */ 3517 static inline uint16_t 3518 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 3519 uint8_t *buf) 3520 { 3521 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3522 3523 if (!hal_soc || !hal_soc->ops) { 3524 hal_err("hal handle is NULL"); 3525 QDF_BUG(0); 3526 return 0; 3527 } 3528 3529 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 3530 return 0; 3531 3532 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 3533 } 3534 3535 /** 3536 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 3537 * from rx_msdu_end TLV 3538 * @buf: pointer to the start of RX PKT TLV headers 3539 * 3540 * Return: cumulative_ip_length 3541 */ 3542 static inline uint16_t 3543 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 3544 uint8_t *buf) 3545 { 3546 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3547 3548 if (!hal_soc || !hal_soc->ops) { 3549 hal_err("hal handle is NULL"); 3550 QDF_BUG(0); 3551 return 0; 3552 } 3553 3554 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 3555 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 3556 3557 return 0; 3558 } 3559 3560 /** 3561 * hal_rx_get_udp_proto: API to get UDP proto field 3562 * from rx_msdu_start TLV 3563 * @buf: pointer to the start of RX PKT TLV headers 3564 * 3565 * Return: UDP proto field value 3566 */ 3567 static inline bool 3568 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3569 { 3570 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3571 3572 if (!hal_soc || !hal_soc->ops) { 3573 hal_err("hal handle is NULL"); 3574 QDF_BUG(0); 3575 return 0; 3576 } 3577 3578 if (hal_soc->ops->hal_rx_get_udp_proto) 3579 return hal_soc->ops->hal_rx_get_udp_proto(buf); 3580 3581 return 0; 3582 } 3583 3584 /** 3585 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 3586 * from rx_msdu_end TLV 3587 * @buf: pointer to the start of RX PKT TLV headers 3588 * 3589 * Return: flow_agg_continuation bit field value 3590 */ 3591 static inline bool 3592 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 3593 uint8_t *buf) 3594 { 3595 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3596 3597 if (!hal_soc || !hal_soc->ops) { 3598 hal_err("hal handle is NULL"); 3599 QDF_BUG(0); 3600 return 0; 3601 } 3602 3603 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 3604 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 3605 3606 return 0; 3607 } 3608 3609 /** 3610 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 3611 * rx_msdu_end TLV 3612 * @buf: pointer to the start of RX PKT TLV headers 3613 * 3614 * Return: flow_agg count value 3615 */ 3616 static inline uint8_t 3617 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 3618 uint8_t *buf) 3619 { 3620 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3621 3622 if (!hal_soc || !hal_soc->ops) { 3623 hal_err("hal handle is NULL"); 3624 QDF_BUG(0); 3625 return 0; 3626 } 3627 3628 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 3629 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 3630 3631 return 0; 3632 } 3633 3634 /** 3635 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 3636 * @buf: pointer to the start of RX PKT TLV headers 3637 * 3638 * Return: fisa flow_agg timeout bit value 3639 */ 3640 static inline bool 3641 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3642 { 3643 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3644 3645 if (!hal_soc || !hal_soc->ops) { 3646 hal_err("hal handle is NULL"); 3647 QDF_BUG(0); 3648 return 0; 3649 } 3650 3651 if (hal_soc->ops->hal_rx_get_fisa_timeout) 3652 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 3653 3654 return 0; 3655 } 3656 3657 /** 3658 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 3659 * tag is valid 3660 * 3661 * @hal_soc_hdl: HAL SOC handle 3662 * @rx_tlv_hdr: start address of rx_pkt_tlvs 3663 * 3664 * Return: true if RX_MPDU_START tlv tag is valid, else false 3665 */ 3666 3667 static inline uint8_t 3668 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 3669 void *rx_tlv_hdr) 3670 { 3671 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3672 3673 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 3674 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 3675 3676 return 0; 3677 } 3678 3679 /** 3680 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 3681 * <struct buffer_addr_info> structure 3682 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 3683 * @buf_info: structure to return the buffer information including 3684 * paddr/cookie 3685 * 3686 * return: None 3687 */ 3688 static inline 3689 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 3690 struct hal_buf_info *buf_info) 3691 { 3692 buf_info->paddr = 3693 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 3694 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 3695 3696 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 3697 } 3698 3699 /** 3700 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 3701 * buffer addr info 3702 * @link_desc_va: pointer to current msdu link Desc 3703 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 3704 * 3705 * return: None 3706 */ 3707 static inline 3708 void hal_rx_get_next_msdu_link_desc_buf_addr_info( 3709 void *link_desc_va, 3710 struct buffer_addr_info *next_addr_info) 3711 { 3712 struct rx_msdu_link *msdu_link = link_desc_va; 3713 3714 if (!msdu_link) { 3715 qdf_mem_zero(next_addr_info, 3716 sizeof(struct buffer_addr_info)); 3717 return; 3718 } 3719 3720 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 3721 } 3722 3723 /** 3724 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 3725 * 3726 * @buf_addr_info: pointer to buf_addr_info structure 3727 * 3728 * return: true: has valid paddr, false: not. 3729 */ 3730 static inline 3731 bool hal_rx_is_buf_addr_info_valid( 3732 struct buffer_addr_info *buf_addr_info) 3733 { 3734 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 3735 false : true; 3736 } 3737 3738 /** 3739 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 3740 * rx_pkt_tlvs structure 3741 * 3742 * @hal_soc_hdl: HAL SOC handle 3743 * return: msdu_end_tlv offset value 3744 */ 3745 static inline 3746 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 3747 { 3748 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3749 3750 if (!hal_soc || !hal_soc->ops) { 3751 hal_err("hal handle is NULL"); 3752 QDF_BUG(0); 3753 return 0; 3754 } 3755 3756 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 3757 } 3758 3759 /** 3760 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 3761 * rx_pkt_tlvs structure 3762 * 3763 * @hal_soc_hdl: HAL SOC handle 3764 * return: msdu_start_tlv offset value 3765 */ 3766 static inline 3767 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 3768 { 3769 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3770 3771 if (!hal_soc || !hal_soc->ops) { 3772 hal_err("hal handle is NULL"); 3773 QDF_BUG(0); 3774 return 0; 3775 } 3776 3777 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 3778 } 3779 3780 /** 3781 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 3782 * rx_pkt_tlvs structure 3783 * 3784 * @hal_soc_hdl: HAL SOC handle 3785 * return: mpdu_start_tlv offset value 3786 */ 3787 static inline 3788 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 3789 { 3790 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3791 3792 if (!hal_soc || !hal_soc->ops) { 3793 hal_err("hal handle is NULL"); 3794 QDF_BUG(0); 3795 return 0; 3796 } 3797 3798 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 3799 } 3800 3801 /** 3802 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 3803 * rx_pkt_tlvs structure 3804 * 3805 * @hal_soc_hdl: HAL SOC handle 3806 * return: mpdu_end_tlv offset value 3807 */ 3808 static inline 3809 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 3810 { 3811 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3812 3813 if (!hal_soc || !hal_soc->ops) { 3814 hal_err("hal handle is NULL"); 3815 QDF_BUG(0); 3816 return 0; 3817 } 3818 3819 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 3820 } 3821 3822 /** 3823 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 3824 * rx_pkt_tlvs structure 3825 * 3826 * @hal_soc_hdl: HAL SOC handle 3827 * return: attn_tlv offset value 3828 */ 3829 static inline 3830 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 3831 { 3832 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3833 3834 if (!hal_soc || !hal_soc->ops) { 3835 hal_err("hal handle is NULL"); 3836 QDF_BUG(0); 3837 return 0; 3838 } 3839 3840 return hal_soc->ops->hal_rx_attn_offset_get(); 3841 } 3842 #endif /* _HAL_RX_H */ 3843