1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 24 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 25 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 26 #define HAL_RX_LSB(block, field) block##_##field##_LSB 27 #define HAL_RX_MASk(block, field) block##_##field##_MASK 28 29 #define HAL_RX_GET(_ptr, block, field) \ 30 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 31 HAL_RX_MASk(block, field)) >> \ 32 HAL_RX_LSB(block, field)) 33 34 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 35 #ifndef RX_DATA_BUFFER_SIZE 36 #define RX_DATA_BUFFER_SIZE 2048 37 #endif 38 39 #ifndef RX_MONITOR_BUFFER_SIZE 40 #define RX_MONITOR_BUFFER_SIZE 2048 41 #endif 42 43 /* MONITOR STATUS BUFFER SIZE = 1536 data bytes, buffer allocation of 2k bytes 44 * including skb shared info and buffer alignment. 45 */ 46 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 47 #define RX_MON_STATUS_BUF_ALIGN 128 48 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 49 RX_MON_STATUS_BUF_ALIGN - QDF_SHINFO_SIZE) 50 51 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 52 #define HAL_RX_NON_QOS_TID 16 53 54 enum { 55 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 56 HAL_HW_RX_DECAP_FORMAT_NWIFI, 57 HAL_HW_RX_DECAP_FORMAT_ETH2, 58 HAL_HW_RX_DECAP_FORMAT_8023, 59 }; 60 61 /** 62 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 63 * 64 * @reo_psh_rsn: REO push reason 65 * @reo_err_code: REO Error code 66 * @rxdma_psh_rsn: RXDMA push reason 67 * @rxdma_err_code: RXDMA Error code 68 * @reserved_1: Reserved bits 69 * @wbm_err_src: WBM error source 70 * @pool_id: pool ID, indicates which rxdma pool 71 * @reserved_2: Reserved bits 72 */ 73 struct hal_wbm_err_desc_info { 74 uint16_t reo_psh_rsn:2, 75 reo_err_code:5, 76 rxdma_psh_rsn:2, 77 rxdma_err_code:5, 78 reserved_1:2; 79 uint8_t wbm_err_src:3, 80 pool_id:2, 81 msdu_continued:1, 82 reserved_2:2; 83 }; 84 85 /** 86 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 87 * @first_buffer: First buffer of MSDU 88 * @last_buffer: Last buffer of MSDU 89 * @is_decap_raw: Is RAW Frame 90 * @reserved_1: Reserved 91 * 92 * MSDU with continuation: 93 * ----------------------------------------------------------- 94 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 95 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 96 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 97 * ----------------------------------------------------------- 98 * 99 * Single buffer MSDU: 100 * ------------------ 101 * | first_buffer:1 | 102 * | last_buffer :1 | 103 * | is_decap_raw:1/0 | 104 * ------------------ 105 */ 106 struct hal_rx_mon_dest_buf_info { 107 uint8_t first_buffer:1, 108 last_buffer:1, 109 is_decap_raw:1, 110 reserved_1:5; 111 }; 112 113 /** 114 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 115 * 116 * @l3_hdr_pad: l3 header padding 117 * @reserved: Reserved bits 118 * @sa_sw_peer_id: sa sw peer id 119 * @sa_idx: sa index 120 * @da_idx: da index 121 */ 122 struct hal_rx_msdu_metadata { 123 uint32_t l3_hdr_pad:16, 124 sa_sw_peer_id:16; 125 uint32_t sa_idx:16, 126 da_idx:16; 127 }; 128 129 /** 130 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 131 * 132 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 133 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 134 */ 135 enum hal_reo_error_status { 136 HAL_REO_ERROR_DETECTED = 0, 137 HAL_REO_ROUTING_INSTRUCTION = 1, 138 }; 139 140 /** 141 * @msdu_flags: [0] first_msdu_in_mpdu 142 * [1] last_msdu_in_mpdu 143 * [2] msdu_continuation - MSDU spread across buffers 144 * [23] sa_is_valid - SA match in peer table 145 * [24] sa_idx_timeout - Timeout while searching for SA match 146 * [25] da_is_valid - Used to identtify intra-bss forwarding 147 * [26] da_is_MCBC 148 * [27] da_idx_timeout - Timeout while searching for DA match 149 * 150 */ 151 struct hal_rx_msdu_desc_info { 152 uint32_t msdu_flags; 153 uint16_t msdu_len; /* 14 bits for length */ 154 }; 155 156 /** 157 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 158 * 159 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 160 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 161 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 162 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 163 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 164 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 165 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 166 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 167 */ 168 enum hal_rx_msdu_desc_flags { 169 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 170 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 171 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 172 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 173 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 174 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 175 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 176 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 177 }; 178 179 /* 180 * @msdu_count: no. of msdus in the MPDU 181 * @mpdu_seq: MPDU sequence number 182 * @mpdu_flags [0] Fragment flag 183 * [1] MPDU_retry_bit 184 * [2] AMPDU flag 185 * [3] raw_ampdu 186 * @peer_meta_data: Upper bits containing peer id, vdev id 187 */ 188 struct hal_rx_mpdu_desc_info { 189 uint16_t msdu_count; 190 uint16_t mpdu_seq; /* 12 bits for length */ 191 uint32_t mpdu_flags; 192 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 193 }; 194 195 /** 196 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 197 * 198 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 199 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 200 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 201 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 202 */ 203 enum hal_rx_mpdu_desc_flags { 204 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 205 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 206 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 207 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 208 }; 209 210 /** 211 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 212 * BUFFER_ADDR_INFO structure 213 * 214 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 215 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 216 * descriptor list 217 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 218 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 219 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 220 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 221 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 222 */ 223 enum hal_rx_ret_buf_manager { 224 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 225 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 226 HAL_RX_BUF_RBM_FW_BM = 2, 227 HAL_RX_BUF_RBM_SW0_BM = 3, 228 HAL_RX_BUF_RBM_SW1_BM = 4, 229 HAL_RX_BUF_RBM_SW2_BM = 5, 230 HAL_RX_BUF_RBM_SW3_BM = 6, 231 }; 232 233 /* 234 * Given the offset of a field in bytes, returns uint8_t * 235 */ 236 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 237 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 238 239 /* 240 * Given the offset of a field in bytes, returns uint32_t * 241 */ 242 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 243 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 244 245 #define _HAL_MS(_word, _mask, _shift) \ 246 (((_word) & (_mask)) >> (_shift)) 247 248 /* 249 * macro to set the LSW of the nbuf data physical address 250 * to the rxdma ring entry 251 */ 252 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 253 ((*(((unsigned int *) buff_addr_info) + \ 254 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 255 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 256 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 257 258 /* 259 * macro to set the LSB of MSW of the nbuf data physical address 260 * to the rxdma ring entry 261 */ 262 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 263 ((*(((unsigned int *) buff_addr_info) + \ 264 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 265 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 266 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 267 268 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 269 270 /* 271 * macro to get the invalid bit for sw cookie 272 */ 273 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 274 ((*(((unsigned int *)buff_addr_info) + \ 275 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 276 HAL_RX_COOKIE_INVALID_MASK) 277 278 /* 279 * macro to set the invalid bit for sw cookie 280 */ 281 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 282 ((*(((unsigned int *)buff_addr_info) + \ 283 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 284 HAL_RX_COOKIE_INVALID_MASK) 285 286 /* 287 * macro to set the cookie into the rxdma ring entry 288 */ 289 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 290 ((*(((unsigned int *) buff_addr_info) + \ 291 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 292 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 293 ((*(((unsigned int *) buff_addr_info) + \ 294 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 295 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 296 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 297 298 /* 299 * macro to set the manager into the rxdma ring entry 300 */ 301 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 302 ((*(((unsigned int *) buff_addr_info) + \ 303 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 304 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 305 ((*(((unsigned int *) buff_addr_info) + \ 306 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 307 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 308 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 309 310 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 311 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 312 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 313 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 314 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 315 316 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 317 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 318 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 319 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 320 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 321 322 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 324 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 325 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 326 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 327 328 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 329 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 330 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 331 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 332 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 333 334 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 335 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 336 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 337 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 338 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 339 340 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 341 342 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 343 ((*(((unsigned int *)buff_addr_info) + \ 344 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 345 HAL_RX_LINK_COOKIE_INVALID_MASK) 346 347 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 348 ((*(((unsigned int *)buff_addr_info) + \ 349 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 350 HAL_RX_LINK_COOKIE_INVALID_MASK) 351 352 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 353 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 354 (((struct reo_destination_ring *) \ 355 reo_desc)->buf_or_link_desc_addr_info))) 356 357 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 358 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 359 (((struct reo_destination_ring *) \ 360 reo_desc)->buf_or_link_desc_addr_info))) 361 362 /* TODO: Convert the following structure fields accesseses to offsets */ 363 364 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 365 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 366 (((struct reo_destination_ring *) \ 367 reo_desc)->buf_or_link_desc_addr_info))) 368 369 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 370 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 371 (((struct reo_destination_ring *) \ 372 reo_desc)->buf_or_link_desc_addr_info))) 373 374 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 375 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 376 (((struct reo_destination_ring *) \ 377 reo_desc)->buf_or_link_desc_addr_info))) 378 379 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 380 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 381 (((struct reo_destination_ring *) \ 382 reo_desc)->buf_or_link_desc_addr_info))) 383 384 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 385 (HAL_RX_BUF_COOKIE_GET(& \ 386 (((struct reo_destination_ring *) \ 387 reo_desc)->buf_or_link_desc_addr_info))) 388 389 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 390 ((mpdu_info_ptr \ 391 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 392 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 393 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 394 395 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 396 ((mpdu_info_ptr \ 397 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 398 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 399 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 400 401 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 402 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 403 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 404 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 405 406 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 407 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 408 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 409 410 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 411 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 412 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 413 414 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 415 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 416 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 417 418 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 419 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 420 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 421 422 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 423 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 424 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 425 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 426 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 427 428 429 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 430 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 431 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 432 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 433 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 434 435 /* 436 * NOTE: None of the following _GET macros need a right 437 * shift by the corresponding _LSB. This is because, they are 438 * finally taken and "OR'ed" into a single word again. 439 */ 440 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 441 ((*(((uint32_t *)msdu_info_ptr) + \ 442 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 443 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 444 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 445 446 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 447 ((*(((uint32_t *)msdu_info_ptr) + \ 448 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 449 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 450 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 451 452 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 453 ((*(((uint32_t *)msdu_info_ptr) + \ 454 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 455 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 456 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 457 458 459 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 460 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 461 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 462 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 463 464 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 465 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 466 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 467 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 468 469 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 470 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 471 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 472 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 473 474 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 475 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 476 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 477 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 478 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 479 480 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 481 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 482 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 483 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 484 485 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 486 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 487 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 488 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 489 490 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 491 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 492 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 493 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 494 495 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 496 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 497 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 498 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 499 500 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 501 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 502 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 503 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 504 505 506 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 507 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 508 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 509 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 510 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 511 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 512 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 513 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 514 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 515 516 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 517 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 518 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 519 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 520 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 521 522 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 523 (*(uint32_t *)(((uint8_t *)_ptr) + \ 524 _wrd ## _ ## _field ## _OFFSET) |= \ 525 ((_val << _wrd ## _ ## _field ## _LSB) & \ 526 _wrd ## _ ## _field ## _MASK)) 527 528 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 529 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 530 _field, _val) 531 532 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 533 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 534 _field, _val) 535 536 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 537 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 538 _field, _val) 539 540 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 541 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 542 { 543 struct reo_destination_ring *reo_dst_ring; 544 uint32_t *mpdu_info; 545 546 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 547 548 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 549 550 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 551 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 552 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 553 mpdu_desc_info->peer_meta_data = 554 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 555 } 556 557 /* 558 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 559 * @ Specifically flags needed are: 560 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 561 * @ msdu_continuation, sa_is_valid, 562 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 563 * @ da_is_MCBC 564 * 565 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 566 * @ descriptor 567 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 568 * @ Return: void 569 */ 570 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 571 struct hal_rx_msdu_desc_info *msdu_desc_info) 572 { 573 struct reo_destination_ring *reo_dst_ring; 574 uint32_t *msdu_info; 575 576 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 577 578 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 579 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 580 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 581 } 582 583 /* 584 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 585 * rxdma ring entry. 586 * @rxdma_entry: descriptor entry 587 * @paddr: physical address of nbuf data pointer. 588 * @cookie: SW cookie used as a index to SW rx desc. 589 * @manager: who owns the nbuf (host, NSS, etc...). 590 * 591 */ 592 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 593 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 594 { 595 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 596 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 597 598 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 599 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 600 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 601 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 602 } 603 604 /* 605 * Structures & Macros to obtain fields from the TLV's in the Rx packet 606 * pre-header. 607 */ 608 609 /* 610 * Every Rx packet starts at an offset from the top of the buffer. 611 * If the host hasn't subscribed to any specific TLV, there is 612 * still space reserved for the following TLV's from the start of 613 * the buffer: 614 * -- RX ATTENTION 615 * -- RX MPDU START 616 * -- RX MSDU START 617 * -- RX MSDU END 618 * -- RX MPDU END 619 * -- RX PACKET HEADER (802.11) 620 * If the host subscribes to any of the TLV's above, that TLV 621 * if populated by the HW 622 */ 623 624 #define NUM_DWORDS_TAG 1 625 626 /* By default the packet header TLV is 128 bytes */ 627 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 628 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 629 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 630 631 #define RX_PKT_OFFSET_WORDS \ 632 ( \ 633 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 634 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 635 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 636 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 637 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 638 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 639 ) 640 641 #define RX_PKT_OFFSET_BYTES \ 642 (RX_PKT_OFFSET_WORDS << 2) 643 644 #define RX_PKT_HDR_TLV_LEN 120 645 646 /* 647 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 648 */ 649 struct rx_attention_tlv { 650 uint32_t tag; 651 struct rx_attention rx_attn; 652 }; 653 654 struct rx_mpdu_start_tlv { 655 uint32_t tag; 656 struct rx_mpdu_start rx_mpdu_start; 657 }; 658 659 struct rx_msdu_start_tlv { 660 uint32_t tag; 661 struct rx_msdu_start rx_msdu_start; 662 }; 663 664 struct rx_msdu_end_tlv { 665 uint32_t tag; 666 struct rx_msdu_end rx_msdu_end; 667 }; 668 669 struct rx_mpdu_end_tlv { 670 uint32_t tag; 671 struct rx_mpdu_end rx_mpdu_end; 672 }; 673 674 struct rx_pkt_hdr_tlv { 675 uint32_t tag; /* 4 B */ 676 uint32_t phy_ppdu_id; /* 4 B */ 677 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 678 }; 679 680 681 #define RXDMA_OPTIMIZATION 682 683 /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status 684 * buffers, monitor destination buffers and monitor descriptor buffers. 685 */ 686 #ifdef RXDMA_OPTIMIZATION 687 /* 688 * The RX_PADDING_BYTES is required so that the TLV's don't 689 * spread across the 128 byte boundary 690 * RXDMA optimization requires: 691 * 1) MSDU_END & ATTENTION TLV's follow in that order 692 * 2) TLV's don't span across 128 byte lines 693 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 694 */ 695 #define RX_PADDING0_BYTES 4 696 #define RX_PADDING1_BYTES 16 697 struct rx_pkt_tlvs { 698 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 699 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 700 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 701 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 702 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 703 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 704 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 705 #ifndef NO_RX_PKT_HDR_TLV 706 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 707 #endif 708 }; 709 #else /* RXDMA_OPTIMIZATION */ 710 struct rx_pkt_tlvs { 711 struct rx_attention_tlv attn_tlv; 712 struct rx_mpdu_start_tlv mpdu_start_tlv; 713 struct rx_msdu_start_tlv msdu_start_tlv; 714 struct rx_msdu_end_tlv msdu_end_tlv; 715 struct rx_mpdu_end_tlv mpdu_end_tlv; 716 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 717 }; 718 #endif /* RXDMA_OPTIMIZATION */ 719 720 /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */ 721 #ifdef RXDMA_OPTIMIZATION 722 struct rx_mon_pkt_tlvs { 723 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 724 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 725 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 726 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 727 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 728 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 729 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 730 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 731 }; 732 #else /* RXDMA_OPTIMIZATION */ 733 struct rx_mon_pkt_tlvs { 734 struct rx_attention_tlv attn_tlv; 735 struct rx_mpdu_start_tlv mpdu_start_tlv; 736 struct rx_msdu_start_tlv msdu_start_tlv; 737 struct rx_msdu_end_tlv msdu_end_tlv; 738 struct rx_mpdu_end_tlv mpdu_end_tlv; 739 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 740 }; 741 #endif 742 743 #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs) 744 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 745 746 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 747 748 #ifdef NO_RX_PKT_HDR_TLV 749 static inline uint8_t 750 *hal_rx_pkt_hdr_get(uint8_t *buf) 751 { 752 return buf + RX_PKT_TLVS_LEN; 753 } 754 #else 755 static inline uint8_t 756 *hal_rx_pkt_hdr_get(uint8_t *buf) 757 { 758 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 759 760 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 761 762 } 763 #endif 764 765 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 766 767 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 768 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 769 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 770 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 771 RX_PKT_TLV_OFFSET(msdu_start_tlv) 772 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 773 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 774 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 775 776 static inline uint8_t 777 *hal_rx_padding0_get(uint8_t *buf) 778 { 779 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 780 781 return pkt_tlvs->rx_padding0; 782 } 783 784 /* 785 * hal_rx_encryption_info_valid(): Returns encryption type. 786 * 787 * @hal_soc_hdl: hal soc handle 788 * @buf: rx_tlv_hdr of the received packet 789 * 790 * Return: encryption type 791 */ 792 static inline uint32_t 793 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 794 { 795 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 796 797 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 798 799 } 800 801 /* 802 * hal_rx_print_pn: Prints the PN of rx packet. 803 * @hal_soc_hdl: hal soc handle 804 * @buf: rx_tlv_hdr of the received packet 805 * 806 * Return: void 807 */ 808 static inline void 809 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 810 { 811 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 812 813 hal_soc->ops->hal_rx_print_pn(buf); 814 } 815 816 /* 817 * Get msdu_done bit from the RX_ATTENTION TLV 818 */ 819 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 820 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 821 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 822 RX_ATTENTION_2_MSDU_DONE_MASK, \ 823 RX_ATTENTION_2_MSDU_DONE_LSB)) 824 825 static inline uint32_t 826 hal_rx_attn_msdu_done_get(uint8_t *buf) 827 { 828 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 829 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 830 uint32_t msdu_done; 831 832 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 833 834 return msdu_done; 835 } 836 837 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 838 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 839 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 840 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 841 RX_ATTENTION_1_FIRST_MPDU_LSB)) 842 843 /* 844 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 845 * @buf: pointer to rx_pkt_tlvs 846 * 847 * reutm: uint32_t(first_msdu) 848 */ 849 static inline uint32_t 850 hal_rx_attn_first_mpdu_get(uint8_t *buf) 851 { 852 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 853 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 854 uint32_t first_mpdu; 855 856 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 857 858 return first_mpdu; 859 } 860 861 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 862 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 863 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 864 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 865 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 866 867 /* 868 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 869 * from rx attention 870 * @buf: pointer to rx_pkt_tlvs 871 * 872 * Return: tcp_udp_cksum_fail 873 */ 874 static inline bool 875 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 876 { 877 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 878 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 879 bool tcp_udp_cksum_fail; 880 881 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 882 883 return tcp_udp_cksum_fail; 884 } 885 886 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 887 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 888 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 889 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 890 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 891 892 /* 893 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 894 * from rx attention 895 * @buf: pointer to rx_pkt_tlvs 896 * 897 * Return: ip_cksum_fail 898 */ 899 static inline bool 900 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 901 { 902 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 903 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 904 bool ip_cksum_fail; 905 906 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 907 908 return ip_cksum_fail; 909 } 910 911 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 912 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 913 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 914 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 915 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 916 917 /* 918 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 919 * from rx attention 920 * @buf: pointer to rx_pkt_tlvs 921 * 922 * Return: phy_ppdu_id 923 */ 924 static inline uint16_t 925 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 926 { 927 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 928 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 929 uint16_t phy_ppdu_id; 930 931 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 932 933 return phy_ppdu_id; 934 } 935 936 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 937 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 938 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 939 RX_ATTENTION_1_CCE_MATCH_MASK, \ 940 RX_ATTENTION_1_CCE_MATCH_LSB)) 941 942 /* 943 * hal_rx_msdu_cce_match_get(): get CCE match bit 944 * from rx attention 945 * @buf: pointer to rx_pkt_tlvs 946 * Return: CCE match value 947 */ 948 static inline bool 949 hal_rx_msdu_cce_match_get(uint8_t *buf) 950 { 951 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 952 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 953 bool cce_match_val; 954 955 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 956 return cce_match_val; 957 } 958 959 /* 960 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 961 */ 962 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 963 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 964 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 965 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 966 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 967 968 static inline uint32_t 969 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 970 { 971 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 972 struct rx_mpdu_start *mpdu_start = 973 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 974 975 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 976 uint32_t peer_meta_data; 977 978 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 979 980 return peer_meta_data; 981 } 982 983 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 984 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 985 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 986 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 987 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 988 /** 989 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 990 * from rx mpdu info 991 * @buf: pointer to rx_pkt_tlvs 992 * 993 * Return: ampdu flag 994 */ 995 static inline bool 996 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 997 { 998 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 999 struct rx_mpdu_start *mpdu_start = 1000 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1001 1002 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1003 bool ampdu_flag; 1004 1005 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 1006 1007 return ampdu_flag; 1008 } 1009 1010 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 1011 ((*(((uint32_t *)_rx_mpdu_info) + \ 1012 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 1013 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 1014 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 1015 1016 /* 1017 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 1018 * 1019 * @ buf: rx_tlv_hdr of the received packet 1020 * @ peer_mdata: peer meta data to be set. 1021 * @ Return: void 1022 */ 1023 static inline void 1024 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 1025 { 1026 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1027 struct rx_mpdu_start *mpdu_start = 1028 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1029 1030 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1031 1032 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 1033 } 1034 1035 /** 1036 * LRO information needed from the TLVs 1037 */ 1038 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 1039 (_HAL_MS( \ 1040 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1041 msdu_end_tlv.rx_msdu_end), \ 1042 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 1043 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 1044 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 1045 1046 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 1047 (_HAL_MS( \ 1048 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1049 msdu_end_tlv.rx_msdu_end), \ 1050 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 1051 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 1052 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 1053 1054 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 1055 (_HAL_MS( \ 1056 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1057 msdu_end_tlv.rx_msdu_end), \ 1058 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 1059 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 1060 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 1061 1062 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 1063 (_HAL_MS( \ 1064 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1065 msdu_end_tlv.rx_msdu_end), \ 1066 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 1067 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 1068 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 1069 1070 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 1071 (_HAL_MS( \ 1072 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1073 msdu_start_tlv.rx_msdu_start), \ 1074 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 1075 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 1076 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 1077 1078 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 1079 (_HAL_MS( \ 1080 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1081 msdu_start_tlv.rx_msdu_start), \ 1082 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 1083 RX_MSDU_START_2_TCP_PROTO_MASK, \ 1084 RX_MSDU_START_2_TCP_PROTO_LSB)) 1085 1086 #define HAL_RX_TLV_GET_UDP_PROTO(buf) \ 1087 (_HAL_MS( \ 1088 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1089 msdu_start_tlv.rx_msdu_start), \ 1090 RX_MSDU_START_2_UDP_PROTO_OFFSET)), \ 1091 RX_MSDU_START_2_UDP_PROTO_MASK, \ 1092 RX_MSDU_START_2_UDP_PROTO_LSB)) 1093 1094 #define HAL_RX_TLV_GET_IPV6(buf) \ 1095 (_HAL_MS( \ 1096 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1097 msdu_start_tlv.rx_msdu_start), \ 1098 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 1099 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 1100 RX_MSDU_START_2_IPV6_PROTO_LSB)) 1101 1102 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 1103 (_HAL_MS( \ 1104 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1105 msdu_start_tlv.rx_msdu_start), \ 1106 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 1107 RX_MSDU_START_1_L3_OFFSET_MASK, \ 1108 RX_MSDU_START_1_L3_OFFSET_LSB)) 1109 1110 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 1111 (_HAL_MS( \ 1112 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1113 msdu_start_tlv.rx_msdu_start), \ 1114 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 1115 RX_MSDU_START_1_L4_OFFSET_MASK, \ 1116 RX_MSDU_START_1_L4_OFFSET_LSB)) 1117 1118 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 1119 (_HAL_MS( \ 1120 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1121 msdu_start_tlv.rx_msdu_start), \ 1122 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1123 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1124 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1125 1126 /** 1127 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 1128 * l3_header padding from rx_msdu_end TLV 1129 * 1130 * @buf: pointer to the start of RX PKT TLV headers 1131 * Return: number of l3 header padding bytes 1132 */ 1133 static inline uint32_t 1134 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 1135 uint8_t *buf) 1136 { 1137 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1138 1139 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 1140 } 1141 1142 /** 1143 * hal_rx_msdu_end_sa_idx_get(): API to get the 1144 * sa_idx from rx_msdu_end TLV 1145 * 1146 * @ buf: pointer to the start of RX PKT TLV headers 1147 * Return: sa_idx (SA AST index) 1148 */ 1149 static inline uint16_t 1150 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 1151 uint8_t *buf) 1152 { 1153 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1154 1155 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 1156 } 1157 1158 /** 1159 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1160 * sa_is_valid bit from rx_msdu_end TLV 1161 * 1162 * @ buf: pointer to the start of RX PKT TLV headers 1163 * Return: sa_is_valid bit 1164 */ 1165 static inline uint8_t 1166 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1167 uint8_t *buf) 1168 { 1169 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1170 1171 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 1172 } 1173 1174 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1176 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1177 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1178 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1179 1180 /** 1181 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1182 * from rx_msdu_start TLV 1183 * 1184 * @ buf: pointer to the start of RX PKT TLV headers 1185 * Return: msdu length 1186 */ 1187 static inline uint32_t 1188 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1189 { 1190 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1191 struct rx_msdu_start *msdu_start = 1192 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1193 uint32_t msdu_len; 1194 1195 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1196 1197 return msdu_len; 1198 } 1199 1200 /** 1201 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1202 * from rx_msdu_start TLV 1203 * 1204 * @buf: pointer to the start of RX PKT TLV headers 1205 * @len: msdu length 1206 * 1207 * Return: none 1208 */ 1209 static inline void 1210 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1211 { 1212 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1213 struct rx_msdu_start *msdu_start = 1214 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1215 void *wrd1; 1216 1217 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1218 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1219 *(uint32_t *)wrd1 |= len; 1220 } 1221 1222 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1223 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1224 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1225 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1226 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1227 1228 /* 1229 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1230 * Interval from rx_msdu_start 1231 * 1232 * @buf: pointer to the start of RX PKT TLV header 1233 * Return: uint32_t(bw) 1234 */ 1235 static inline uint32_t 1236 hal_rx_msdu_start_bw_get(uint8_t *buf) 1237 { 1238 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1239 struct rx_msdu_start *msdu_start = 1240 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1241 uint32_t bw; 1242 1243 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1244 1245 return bw; 1246 } 1247 1248 1249 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1250 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1251 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1252 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1253 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1254 1255 /** 1256 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1257 * from rx_msdu_start TLV 1258 * 1259 * @ buf: pointer to the start of RX PKT TLV headers 1260 * Return: toeplitz hash 1261 */ 1262 static inline uint32_t 1263 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1264 { 1265 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1266 struct rx_msdu_start *msdu_start = 1267 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1268 1269 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1270 } 1271 1272 /** 1273 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 1274 * 1275 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 1276 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 1277 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 1278 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 1279 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 1280 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 1281 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 1282 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 1283 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 1284 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 1285 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 1286 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 1287 */ 1288 enum hal_rx_mpdu_info_sw_frame_group_id_type { 1289 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 1290 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 1291 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 1292 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 1293 HAL_MPDU_SW_FRAME_GROUP_MGMT, 1294 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 1295 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 1296 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 1297 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 1298 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 1299 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 1300 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 1301 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 1302 }; 1303 1304 /** 1305 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 1306 * Retrieve qos control valid bit from the tlv. 1307 * @hal_soc_hdl: hal_soc handle 1308 * @buf: pointer to rx pkt TLV. 1309 * 1310 * Return: qos control value. 1311 */ 1312 static inline uint32_t 1313 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 1314 hal_soc_handle_t hal_soc_hdl, 1315 uint8_t *buf) 1316 { 1317 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1318 1319 if ((!hal_soc) || (!hal_soc->ops)) { 1320 hal_err("hal handle is NULL"); 1321 QDF_BUG(0); 1322 return QDF_STATUS_E_INVAL; 1323 } 1324 1325 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 1326 return hal_soc->ops-> 1327 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 1328 1329 return QDF_STATUS_E_INVAL; 1330 } 1331 1332 /** 1333 * hal_rx_is_unicast: check packet is unicast frame or not. 1334 * @hal_soc_hdl: hal_soc handle 1335 * @buf: pointer to rx pkt TLV. 1336 * 1337 * Return: true on unicast. 1338 */ 1339 static inline bool 1340 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1341 { 1342 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1343 1344 return hal_soc->ops->hal_rx_is_unicast(buf); 1345 } 1346 1347 /** 1348 * hal_rx_tid_get: get tid based on qos control valid. 1349 * @hal_soc_hdl: hal soc handle 1350 * @buf: pointer to rx pkt TLV. 1351 * 1352 * Return: tid 1353 */ 1354 static inline uint32_t 1355 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1356 { 1357 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1358 1359 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 1360 } 1361 1362 /** 1363 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 1364 * @hal_soc_hdl: hal soc handle 1365 * @buf: pointer to rx pkt TLV. 1366 * 1367 * Return: sw peer_id 1368 */ 1369 static inline uint32_t 1370 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1371 uint8_t *buf) 1372 { 1373 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1374 1375 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1376 } 1377 1378 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1379 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1380 RX_MSDU_START_5_SGI_OFFSET)), \ 1381 RX_MSDU_START_5_SGI_MASK, \ 1382 RX_MSDU_START_5_SGI_LSB)) 1383 /** 1384 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1385 * Interval from rx_msdu_start TLV 1386 * 1387 * @buf: pointer to the start of RX PKT TLV headers 1388 * Return: uint32_t(sgi) 1389 */ 1390 static inline uint32_t 1391 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1392 { 1393 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1394 struct rx_msdu_start *msdu_start = 1395 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1396 uint32_t sgi; 1397 1398 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1399 1400 return sgi; 1401 } 1402 1403 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1404 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1405 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1406 RX_MSDU_START_5_RATE_MCS_MASK, \ 1407 RX_MSDU_START_5_RATE_MCS_LSB)) 1408 /** 1409 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1410 * from rx_msdu_start TLV 1411 * 1412 * @buf: pointer to the start of RX PKT TLV headers 1413 * Return: uint32_t(rate_mcs) 1414 */ 1415 static inline uint32_t 1416 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1417 { 1418 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1419 struct rx_msdu_start *msdu_start = 1420 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1421 uint32_t rate_mcs; 1422 1423 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1424 1425 return rate_mcs; 1426 } 1427 1428 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1429 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1430 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1431 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1432 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1433 1434 /* 1435 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1436 * packet from rx_attention 1437 * 1438 * @buf: pointer to the start of RX PKT TLV header 1439 * Return: uint32_t(decryt status) 1440 */ 1441 1442 static inline uint32_t 1443 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1444 { 1445 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1446 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1447 uint32_t is_decrypt = 0; 1448 uint32_t decrypt_status; 1449 1450 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1451 1452 if (!decrypt_status) 1453 is_decrypt = 1; 1454 1455 return is_decrypt; 1456 } 1457 1458 /* 1459 * Get key index from RX_MSDU_END 1460 */ 1461 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1462 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1463 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1464 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1465 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1466 /* 1467 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1468 * from rx_msdu_end 1469 * 1470 * @buf: pointer to the start of RX PKT TLV header 1471 * Return: uint32_t(key id) 1472 */ 1473 1474 static inline uint32_t 1475 hal_rx_msdu_get_keyid(uint8_t *buf) 1476 { 1477 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1478 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1479 uint32_t keyid_octet; 1480 1481 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1482 1483 return keyid_octet & 0x3; 1484 } 1485 1486 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1487 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1488 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1489 RX_MSDU_START_5_USER_RSSI_MASK, \ 1490 RX_MSDU_START_5_USER_RSSI_LSB)) 1491 /* 1492 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1493 * from rx_msdu_start 1494 * 1495 * @buf: pointer to the start of RX PKT TLV header 1496 * Return: uint32_t(rssi) 1497 */ 1498 1499 static inline uint32_t 1500 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1501 { 1502 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1503 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1504 uint32_t rssi; 1505 1506 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1507 1508 return rssi; 1509 1510 } 1511 1512 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1513 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1514 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1515 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1516 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1517 1518 /* 1519 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1520 * from rx_msdu_start 1521 * 1522 * @buf: pointer to the start of RX PKT TLV header 1523 * Return: uint32_t(frequency) 1524 */ 1525 1526 static inline uint32_t 1527 hal_rx_msdu_start_get_freq(uint8_t *buf) 1528 { 1529 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1530 struct rx_msdu_start *msdu_start = 1531 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1532 uint32_t freq; 1533 1534 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1535 1536 return freq; 1537 } 1538 1539 1540 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1541 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1542 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1543 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1544 RX_MSDU_START_5_PKT_TYPE_LSB)) 1545 1546 /* 1547 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1548 * from rx_msdu_start 1549 * 1550 * @buf: pointer to the start of RX PKT TLV header 1551 * Return: uint32_t(pkt type) 1552 */ 1553 1554 static inline uint32_t 1555 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1556 { 1557 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1558 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1559 uint32_t pkt_type; 1560 1561 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1562 1563 return pkt_type; 1564 } 1565 1566 /* 1567 * hal_rx_mpdu_get_tods(): API to get the tods info 1568 * from rx_mpdu_start 1569 * 1570 * @buf: pointer to the start of RX PKT TLV header 1571 * Return: uint32_t(to_ds) 1572 */ 1573 1574 static inline uint32_t 1575 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1576 { 1577 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1578 1579 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1580 } 1581 1582 1583 /* 1584 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1585 * from rx_mpdu_start 1586 * @hal_soc_hdl: hal soc handle 1587 * @buf: pointer to the start of RX PKT TLV header 1588 * 1589 * Return: uint32_t(fr_ds) 1590 */ 1591 static inline uint32_t 1592 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1593 { 1594 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1595 1596 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1597 } 1598 1599 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1600 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1601 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1602 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1603 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1604 1605 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1606 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1607 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1608 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1609 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1610 1611 /* 1612 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1613 * @hal_soc_hdl: hal soc handle 1614 * @buf: pointer to the start of RX PKT TLV headera 1615 * @mac_addr: pointer to mac address 1616 * 1617 * Return: success/failure 1618 */ 1619 static inline 1620 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1621 uint8_t *buf, uint8_t *mac_addr) 1622 { 1623 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1624 1625 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1626 } 1627 1628 /* 1629 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1630 * in the packet 1631 * @hal_soc_hdl: hal soc handle 1632 * @buf: pointer to the start of RX PKT TLV header 1633 * @mac_addr: pointer to mac address 1634 * 1635 * Return: success/failure 1636 */ 1637 static inline 1638 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1639 uint8_t *buf, uint8_t *mac_addr) 1640 { 1641 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1642 1643 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1644 } 1645 1646 /* 1647 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1648 * in the packet 1649 * @hal_soc_hdl: hal soc handle 1650 * @buf: pointer to the start of RX PKT TLV header 1651 * @mac_addr: pointer to mac address 1652 * 1653 * Return: success/failure 1654 */ 1655 static inline 1656 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1657 uint8_t *buf, uint8_t *mac_addr) 1658 { 1659 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1660 1661 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1662 } 1663 1664 /* 1665 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1666 * in the packet 1667 * @hal_soc_hdl: hal_soc handle 1668 * @buf: pointer to the start of RX PKT TLV header 1669 * @mac_addr: pointer to mac address 1670 * Return: success/failure 1671 */ 1672 static inline 1673 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1674 uint8_t *buf, uint8_t *mac_addr) 1675 { 1676 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1677 1678 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1679 } 1680 1681 /** 1682 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1683 * from rx_msdu_end TLV 1684 * 1685 * @ buf: pointer to the start of RX PKT TLV headers 1686 * Return: da index 1687 */ 1688 static inline uint16_t 1689 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1690 { 1691 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1692 1693 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1694 } 1695 1696 /** 1697 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1698 * from rx_msdu_end TLV 1699 * @hal_soc_hdl: hal soc handle 1700 * @ buf: pointer to the start of RX PKT TLV headers 1701 * 1702 * Return: da_is_valid 1703 */ 1704 static inline uint8_t 1705 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1706 uint8_t *buf) 1707 { 1708 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1709 1710 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1711 } 1712 1713 /** 1714 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1715 * from rx_msdu_end TLV 1716 * 1717 * @buf: pointer to the start of RX PKT TLV headers 1718 * 1719 * Return: da_is_mcbc 1720 */ 1721 static inline uint8_t 1722 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1723 { 1724 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1725 1726 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1727 } 1728 1729 /** 1730 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1731 * from rx_msdu_end TLV 1732 * @hal_soc_hdl: hal soc handle 1733 * @buf: pointer to the start of RX PKT TLV headers 1734 * 1735 * Return: first_msdu 1736 */ 1737 static inline uint8_t 1738 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1739 uint8_t *buf) 1740 { 1741 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1742 1743 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1744 } 1745 1746 /** 1747 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1748 * from rx_msdu_end TLV 1749 * @hal_soc_hdl: hal soc handle 1750 * @buf: pointer to the start of RX PKT TLV headers 1751 * 1752 * Return: last_msdu 1753 */ 1754 static inline uint8_t 1755 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1756 uint8_t *buf) 1757 { 1758 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1759 1760 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1761 } 1762 1763 /** 1764 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1765 * from rx_msdu_end TLV 1766 * @buf: pointer to the start of RX PKT TLV headers 1767 * Return: cce_meta_data 1768 */ 1769 static inline uint16_t 1770 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1771 uint8_t *buf) 1772 { 1773 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1774 1775 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1776 } 1777 1778 /******************************************************************************* 1779 * RX ERROR APIS 1780 ******************************************************************************/ 1781 1782 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1783 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1784 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1785 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1786 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1787 1788 /** 1789 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1790 * from rx_mpdu_end TLV 1791 * 1792 * @buf: pointer to the start of RX PKT TLV headers 1793 * Return: uint32_t(decrypt_err) 1794 */ 1795 static inline uint32_t 1796 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1797 { 1798 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1799 struct rx_mpdu_end *mpdu_end = 1800 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1801 uint32_t decrypt_err; 1802 1803 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1804 1805 return decrypt_err; 1806 } 1807 1808 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1809 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1810 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1811 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1812 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1813 1814 /** 1815 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1816 * from rx_mpdu_end TLV 1817 * 1818 * @buf: pointer to the start of RX PKT TLV headers 1819 * Return: uint32_t(mic_err) 1820 */ 1821 static inline uint32_t 1822 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1823 { 1824 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1825 struct rx_mpdu_end *mpdu_end = 1826 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1827 uint32_t mic_err; 1828 1829 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1830 1831 return mic_err; 1832 } 1833 1834 /******************************************************************************* 1835 * RX REO ERROR APIS 1836 ******************************************************************************/ 1837 1838 #define HAL_RX_NUM_MSDU_DESC 6 1839 #define HAL_RX_MAX_SAVED_RING_DESC 16 1840 1841 /* TODO: rework the structure */ 1842 struct hal_rx_msdu_list { 1843 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1844 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1845 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1846 /* physical address of the msdu */ 1847 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1848 }; 1849 1850 struct hal_buf_info { 1851 uint64_t paddr; 1852 uint32_t sw_cookie; 1853 uint8_t rbm; 1854 }; 1855 1856 /** 1857 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1858 * @msdu_link_ptr - msdu link ptr 1859 * @hal - pointer to hal_soc 1860 * Return - Pointer to rx_msdu_details structure 1861 * 1862 */ 1863 static inline 1864 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1865 struct hal_soc *hal_soc) 1866 { 1867 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1868 } 1869 1870 /** 1871 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1872 * @msdu_details_ptr - Pointer to msdu_details_ptr 1873 * @hal - pointer to hal_soc 1874 * Return - Pointer to rx_msdu_desc_info structure. 1875 * 1876 */ 1877 static inline 1878 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1879 struct hal_soc *hal_soc) 1880 { 1881 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1882 } 1883 1884 /* This special cookie value will be used to indicate FW allocated buffers 1885 * received through RXDMA2SW ring for RXDMA WARs 1886 */ 1887 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1888 1889 /** 1890 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1891 * from the MSDU link descriptor 1892 * 1893 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1894 * MSDU link descriptor (struct rx_msdu_link) 1895 * 1896 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1897 * 1898 * @num_msdus: Number of MSDUs in the MPDU 1899 * 1900 * Return: void 1901 */ 1902 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1903 void *msdu_link_desc, 1904 struct hal_rx_msdu_list *msdu_list, 1905 uint16_t *num_msdus) 1906 { 1907 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1908 struct rx_msdu_details *msdu_details; 1909 struct rx_msdu_desc_info *msdu_desc_info; 1910 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1911 int i; 1912 1913 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1914 1915 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1916 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1917 __func__, __LINE__, msdu_link, msdu_details); 1918 1919 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1920 /* num_msdus received in mpdu descriptor may be incorrect 1921 * sometimes due to HW issue. Check msdu buffer address also 1922 */ 1923 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1924 &msdu_details[i].buffer_addr_info_details) == 0)) 1925 break; 1926 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1927 &msdu_details[i].buffer_addr_info_details) == 0) { 1928 /* set the last msdu bit in the prev msdu_desc_info */ 1929 msdu_desc_info = 1930 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1931 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1932 break; 1933 } 1934 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1935 hal_soc); 1936 1937 /* set first MSDU bit or the last MSDU bit */ 1938 if (!i) 1939 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1940 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1941 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1942 1943 msdu_list->msdu_info[i].msdu_flags = 1944 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1945 msdu_list->msdu_info[i].msdu_len = 1946 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1947 msdu_list->sw_cookie[i] = 1948 HAL_RX_BUF_COOKIE_GET( 1949 &msdu_details[i].buffer_addr_info_details); 1950 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1951 &msdu_details[i].buffer_addr_info_details); 1952 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1953 &msdu_details[i].buffer_addr_info_details) | 1954 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1955 &msdu_details[i].buffer_addr_info_details) << 32; 1956 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1957 "[%s][%d] i=%d sw_cookie=%d", 1958 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1959 } 1960 *num_msdus = i; 1961 } 1962 1963 /** 1964 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1965 * destination ring ID from the msdu desc info 1966 * 1967 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1968 * the current descriptor 1969 * 1970 * Return: dst_ind (REO destination ring ID) 1971 */ 1972 static inline uint32_t 1973 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 1974 { 1975 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1976 struct rx_msdu_details *msdu_details; 1977 struct rx_msdu_desc_info *msdu_desc_info; 1978 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1979 uint32_t dst_ind; 1980 1981 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1982 1983 /* The first msdu in the link should exsist */ 1984 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1985 hal_soc); 1986 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1987 return dst_ind; 1988 } 1989 1990 /** 1991 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1992 * cookie from the REO destination ring element 1993 * 1994 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1995 * the current descriptor 1996 * @ buf_info: structure to return the buffer information 1997 * Return: void 1998 */ 1999 static inline 2000 void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc, 2001 struct hal_buf_info *buf_info) 2002 { 2003 struct reo_destination_ring *reo_ring = 2004 (struct reo_destination_ring *)rx_desc; 2005 2006 buf_info->paddr = 2007 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 2008 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 2009 2010 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 2011 } 2012 2013 /** 2014 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 2015 * 2016 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 2017 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 2018 * descriptor 2019 */ 2020 enum hal_rx_reo_buf_type { 2021 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 2022 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 2023 }; 2024 2025 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2026 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 2027 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 2028 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 2029 2030 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 2031 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 2032 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 2033 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 2034 2035 /** 2036 * enum hal_reo_error_code: Error code describing the type of error detected 2037 * 2038 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 2039 * REO_ENTRANCE ring is set to 0 2040 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 2041 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 2042 * having been setup 2043 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 2044 * Retry bit set: duplicate frame 2045 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 2046 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 2047 * received with 2K jump in SN 2048 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 2049 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 2050 * with SN falling within the OOR window 2051 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 2052 * OOR window 2053 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 2054 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 2055 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 2056 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2057 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 2058 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2059 * of the pn_error_detected_flag been set in the REO Queue descriptor 2060 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 2061 * the queue descriptor(address) being blocked as SW/FW seems to be currently 2062 * in the process of making updates to this descriptor 2063 */ 2064 enum hal_reo_error_code { 2065 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 2066 HAL_REO_ERR_QUEUE_DESC_INVALID, 2067 HAL_REO_ERR_AMPDU_IN_NON_BA, 2068 HAL_REO_ERR_NON_BA_DUPLICATE, 2069 HAL_REO_ERR_BA_DUPLICATE, 2070 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 2071 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 2072 HAL_REO_ERR_REGULAR_FRAME_OOR, 2073 HAL_REO_ERR_BAR_FRAME_OOR, 2074 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 2075 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 2076 HAL_REO_ERR_PN_CHECK_FAILED, 2077 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 2078 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 2079 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 2080 HAL_REO_ERR_MAX 2081 }; 2082 2083 /** 2084 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 2085 * 2086 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 2087 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 2088 * overflow 2089 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 2090 * incomplete 2091 * MPDU from the PHY 2092 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 2093 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 2094 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 2095 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 2096 * encrypted but wasn’t 2097 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 2098 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 2099 * the max allowed 2100 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2101 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2102 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2103 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2104 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2105 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2106 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2107 */ 2108 enum hal_rxdma_error_code { 2109 HAL_RXDMA_ERR_OVERFLOW = 0, 2110 HAL_RXDMA_ERR_MPDU_LENGTH, 2111 HAL_RXDMA_ERR_FCS, 2112 HAL_RXDMA_ERR_DECRYPT, 2113 HAL_RXDMA_ERR_TKIP_MIC, 2114 HAL_RXDMA_ERR_UNENCRYPTED, 2115 HAL_RXDMA_ERR_MSDU_LEN, 2116 HAL_RXDMA_ERR_MSDU_LIMIT, 2117 HAL_RXDMA_ERR_WIFI_PARSE, 2118 HAL_RXDMA_ERR_AMSDU_PARSE, 2119 HAL_RXDMA_ERR_SA_TIMEOUT, 2120 HAL_RXDMA_ERR_DA_TIMEOUT, 2121 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2122 HAL_RXDMA_ERR_FLUSH_REQUEST, 2123 HAL_RXDMA_ERR_WAR = 31, 2124 HAL_RXDMA_ERR_MAX 2125 }; 2126 2127 /** 2128 * HW BM action settings in WBM release ring 2129 */ 2130 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2131 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2132 2133 /** 2134 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2135 * release of this buffer or descriptor 2136 * 2137 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2138 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2139 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2140 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2141 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2142 */ 2143 enum hal_rx_wbm_error_source { 2144 HAL_RX_WBM_ERR_SRC_TQM = 0, 2145 HAL_RX_WBM_ERR_SRC_RXDMA, 2146 HAL_RX_WBM_ERR_SRC_REO, 2147 HAL_RX_WBM_ERR_SRC_FW, 2148 HAL_RX_WBM_ERR_SRC_SW, 2149 }; 2150 2151 /** 2152 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2153 * released 2154 * 2155 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2156 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2157 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2158 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2159 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2160 */ 2161 enum hal_rx_wbm_buf_type { 2162 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2163 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2164 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2165 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2166 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2167 }; 2168 2169 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2170 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2171 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2172 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2173 2174 /** 2175 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2176 * PN check failure 2177 * 2178 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2179 * 2180 * Return: true: error caused by PN check, false: other error 2181 */ 2182 static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc) 2183 { 2184 struct reo_destination_ring *reo_desc = 2185 (struct reo_destination_ring *)rx_desc; 2186 2187 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2188 HAL_REO_ERR_PN_CHECK_FAILED) | 2189 (HAL_RX_REO_ERROR_GET(reo_desc) == 2190 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2191 true : false; 2192 } 2193 2194 /** 2195 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2196 * the sequence number 2197 * 2198 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2199 * 2200 * Return: true: error caused by 2K jump, false: other error 2201 */ 2202 static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc) 2203 { 2204 struct reo_destination_ring *reo_desc = 2205 (struct reo_destination_ring *)rx_desc; 2206 2207 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2208 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2209 (HAL_RX_REO_ERROR_GET(reo_desc) == 2210 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2211 true : false; 2212 } 2213 2214 /** 2215 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 2216 * 2217 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2218 * 2219 * Return: true: error caused by OOR, false: other error 2220 */ 2221 static inline bool hal_rx_reo_is_oor_error(void *rx_desc) 2222 { 2223 struct reo_destination_ring *reo_desc = 2224 (struct reo_destination_ring *)rx_desc; 2225 2226 return (HAL_RX_REO_ERROR_GET(reo_desc) == 2227 HAL_REO_ERR_REGULAR_FRAME_OOR) ? true : false; 2228 } 2229 2230 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 2231 /** 2232 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 2233 * @hal_desc: hardware descriptor pointer 2234 * 2235 * This function will print wbm release descriptor 2236 * 2237 * Return: none 2238 */ 2239 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 2240 { 2241 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 2242 uint32_t i; 2243 2244 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2245 "Current Rx wbm release descriptor is"); 2246 2247 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 2248 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2249 "DWORD[i] = 0x%x", wbm_comp[i]); 2250 } 2251 } 2252 2253 /** 2254 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2255 * 2256 * @ hal_soc_hdl : HAL version of the SOC pointer 2257 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2258 * @ buf_addr_info : void pointer to the buffer_addr_info 2259 * @ bm_action : put in IDLE list or release to MSDU_LIST 2260 * 2261 * Return: void 2262 */ 2263 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2264 static inline 2265 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 2266 void *src_srng_desc, 2267 hal_buff_addrinfo_t buf_addr_info, 2268 uint8_t bm_action) 2269 { 2270 struct wbm_release_ring *wbm_rel_srng = 2271 (struct wbm_release_ring *)src_srng_desc; 2272 uint32_t addr_31_0; 2273 uint8_t addr_39_32; 2274 2275 /* Structure copy !!! */ 2276 wbm_rel_srng->released_buff_or_desc_addr_info = 2277 *((struct buffer_addr_info *)buf_addr_info); 2278 2279 addr_31_0 = 2280 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 2281 addr_39_32 = 2282 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 2283 2284 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2285 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2286 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2287 bm_action); 2288 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2289 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2290 2291 /* WBM error is indicated when any of the link descriptors given to 2292 * WBM has a NULL address, and one those paths is the link descriptors 2293 * released from host after processing RXDMA errors, 2294 * or from Rx defrag path, and we want to add an assert here to ensure 2295 * host is not releasing descriptors with NULL address. 2296 */ 2297 2298 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 2299 hal_dump_wbm_rel_desc(src_srng_desc); 2300 qdf_assert_always(0); 2301 } 2302 } 2303 2304 /* 2305 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2306 * REO entrance ring 2307 * 2308 * @ soc: HAL version of the SOC pointer 2309 * @ pa: Physical address of the MSDU Link Descriptor 2310 * @ cookie: SW cookie to get to the virtual address 2311 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2312 * to the error enabled REO queue 2313 * 2314 * Return: void 2315 */ 2316 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2317 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2318 { 2319 /* TODO */ 2320 } 2321 2322 /** 2323 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2324 * BUFFER_ADDR_INFO, give the RX descriptor 2325 * (Assumption -- BUFFER_ADDR_INFO is the 2326 * first field in the descriptor structure) 2327 */ 2328 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 2329 ((hal_link_desc_t)(ring_desc)) 2330 2331 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2332 2333 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2334 2335 /** 2336 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2337 * from the BUFFER_ADDR_INFO structure 2338 * given a REO destination ring descriptor. 2339 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2340 * 2341 * Return: uint8_t (value of the return_buffer_manager) 2342 */ 2343 static inline 2344 uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc) 2345 { 2346 /* 2347 * The following macro takes buf_addr_info as argument, 2348 * but since buf_addr_info is the first field in ring_desc 2349 * Hence the following call is OK 2350 */ 2351 return HAL_RX_BUF_RBM_GET(ring_desc); 2352 } 2353 2354 2355 /******************************************************************************* 2356 * RX WBM ERROR APIS 2357 ******************************************************************************/ 2358 2359 2360 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2361 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2362 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2363 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2364 2365 /** 2366 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2367 * the frame to this release ring 2368 * 2369 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2370 * frame to this queue 2371 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2372 * received routing instructions. No error within REO was detected 2373 */ 2374 enum hal_rx_wbm_reo_push_reason { 2375 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2376 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2377 }; 2378 2379 2380 /** 2381 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2382 * this release ring 2383 * 2384 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2385 * this frame to this queue 2386 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2387 * per received routing instructions. No error within RXDMA was detected 2388 */ 2389 enum hal_rx_wbm_rxdma_push_reason { 2390 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2391 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2392 }; 2393 2394 2395 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2396 (((*(((uint32_t *) wbm_desc) + \ 2397 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2398 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2399 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2400 2401 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2402 (((*(((uint32_t *) wbm_desc) + \ 2403 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2404 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2405 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2406 2407 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2408 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2409 wbm_desc)->released_buff_or_desc_addr_info) 2410 2411 /** 2412 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2413 * humman readable format. 2414 * @ rx_attn: pointer the rx_attention TLV in pkt. 2415 * @ dbg_level: log level. 2416 * 2417 * Return: void 2418 */ 2419 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2420 uint8_t dbg_level) 2421 { 2422 hal_verbose_debug( 2423 "rx_attention tlv (1/2) - " 2424 "rxpcu_mpdu_filter_in_category: %x " 2425 "sw_frame_group_id: %x " 2426 "reserved_0: %x " 2427 "phy_ppdu_id: %x " 2428 "first_mpdu : %x " 2429 "reserved_1a: %x " 2430 "mcast_bcast: %x " 2431 "ast_index_not_found: %x " 2432 "ast_index_timeout: %x " 2433 "power_mgmt: %x " 2434 "non_qos: %x " 2435 "null_data: %x " 2436 "mgmt_type: %x " 2437 "ctrl_type: %x " 2438 "more_data: %x " 2439 "eosp: %x " 2440 "a_msdu_error: %x " 2441 "fragment_flag: %x " 2442 "order: %x " 2443 "cce_match: %x " 2444 "overflow_err: %x " 2445 "msdu_length_err: %x " 2446 "tcp_udp_chksum_fail: %x " 2447 "ip_chksum_fail: %x " 2448 "sa_idx_invalid: %x " 2449 "da_idx_invalid: %x " 2450 "reserved_1b: %x " 2451 "rx_in_tx_decrypt_byp: %x ", 2452 rx_attn->rxpcu_mpdu_filter_in_category, 2453 rx_attn->sw_frame_group_id, 2454 rx_attn->reserved_0, 2455 rx_attn->phy_ppdu_id, 2456 rx_attn->first_mpdu, 2457 rx_attn->reserved_1a, 2458 rx_attn->mcast_bcast, 2459 rx_attn->ast_index_not_found, 2460 rx_attn->ast_index_timeout, 2461 rx_attn->power_mgmt, 2462 rx_attn->non_qos, 2463 rx_attn->null_data, 2464 rx_attn->mgmt_type, 2465 rx_attn->ctrl_type, 2466 rx_attn->more_data, 2467 rx_attn->eosp, 2468 rx_attn->a_msdu_error, 2469 rx_attn->fragment_flag, 2470 rx_attn->order, 2471 rx_attn->cce_match, 2472 rx_attn->overflow_err, 2473 rx_attn->msdu_length_err, 2474 rx_attn->tcp_udp_chksum_fail, 2475 rx_attn->ip_chksum_fail, 2476 rx_attn->sa_idx_invalid, 2477 rx_attn->da_idx_invalid, 2478 rx_attn->reserved_1b, 2479 rx_attn->rx_in_tx_decrypt_byp); 2480 2481 hal_verbose_debug( 2482 "rx_attention tlv (2/2) - " 2483 "encrypt_required: %x " 2484 "directed: %x " 2485 "buffer_fragment: %x " 2486 "mpdu_length_err: %x " 2487 "tkip_mic_err: %x " 2488 "decrypt_err: %x " 2489 "unencrypted_frame_err: %x " 2490 "fcs_err: %x " 2491 "flow_idx_timeout: %x " 2492 "flow_idx_invalid: %x " 2493 "wifi_parser_error: %x " 2494 "amsdu_parser_error: %x " 2495 "sa_idx_timeout: %x " 2496 "da_idx_timeout: %x " 2497 "msdu_limit_error: %x " 2498 "da_is_valid: %x " 2499 "da_is_mcbc: %x " 2500 "sa_is_valid: %x " 2501 "decrypt_status_code: %x " 2502 "rx_bitmap_not_updated: %x " 2503 "reserved_2: %x " 2504 "msdu_done: %x ", 2505 rx_attn->encrypt_required, 2506 rx_attn->directed, 2507 rx_attn->buffer_fragment, 2508 rx_attn->mpdu_length_err, 2509 rx_attn->tkip_mic_err, 2510 rx_attn->decrypt_err, 2511 rx_attn->unencrypted_frame_err, 2512 rx_attn->fcs_err, 2513 rx_attn->flow_idx_timeout, 2514 rx_attn->flow_idx_invalid, 2515 rx_attn->wifi_parser_error, 2516 rx_attn->amsdu_parser_error, 2517 rx_attn->sa_idx_timeout, 2518 rx_attn->da_idx_timeout, 2519 rx_attn->msdu_limit_error, 2520 rx_attn->da_is_valid, 2521 rx_attn->da_is_mcbc, 2522 rx_attn->sa_is_valid, 2523 rx_attn->decrypt_status_code, 2524 rx_attn->rx_bitmap_not_updated, 2525 rx_attn->reserved_2, 2526 rx_attn->msdu_done); 2527 } 2528 2529 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2530 uint8_t dbg_level, 2531 struct hal_soc *hal) 2532 { 2533 2534 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2535 } 2536 /** 2537 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2538 * human readable format. 2539 * @ msdu_end: pointer the msdu_end TLV in pkt. 2540 * @ dbg_level: log level. 2541 * 2542 * Return: void 2543 */ 2544 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2545 struct rx_msdu_end *msdu_end, 2546 uint8_t dbg_level) 2547 { 2548 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2549 } 2550 2551 /** 2552 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2553 * human readable format. 2554 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2555 * @ dbg_level: log level. 2556 * 2557 * Return: void 2558 */ 2559 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2560 uint8_t dbg_level) 2561 { 2562 hal_verbose_debug( 2563 "rx_mpdu_end tlv - " 2564 "rxpcu_mpdu_filter_in_category: %x " 2565 "sw_frame_group_id: %x " 2566 "phy_ppdu_id: %x " 2567 "unsup_ktype_short_frame: %x " 2568 "rx_in_tx_decrypt_byp: %x " 2569 "overflow_err: %x " 2570 "mpdu_length_err: %x " 2571 "tkip_mic_err: %x " 2572 "decrypt_err: %x " 2573 "unencrypted_frame_err: %x " 2574 "pn_fields_contain_valid_info: %x " 2575 "fcs_err: %x " 2576 "msdu_length_err: %x " 2577 "rxdma0_destination_ring: %x " 2578 "rxdma1_destination_ring: %x " 2579 "decrypt_status_code: %x " 2580 "rx_bitmap_not_updated: %x ", 2581 mpdu_end->rxpcu_mpdu_filter_in_category, 2582 mpdu_end->sw_frame_group_id, 2583 mpdu_end->phy_ppdu_id, 2584 mpdu_end->unsup_ktype_short_frame, 2585 mpdu_end->rx_in_tx_decrypt_byp, 2586 mpdu_end->overflow_err, 2587 mpdu_end->mpdu_length_err, 2588 mpdu_end->tkip_mic_err, 2589 mpdu_end->decrypt_err, 2590 mpdu_end->unencrypted_frame_err, 2591 mpdu_end->pn_fields_contain_valid_info, 2592 mpdu_end->fcs_err, 2593 mpdu_end->msdu_length_err, 2594 mpdu_end->rxdma0_destination_ring, 2595 mpdu_end->rxdma1_destination_ring, 2596 mpdu_end->decrypt_status_code, 2597 mpdu_end->rx_bitmap_not_updated); 2598 } 2599 2600 #ifdef NO_RX_PKT_HDR_TLV 2601 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2602 uint8_t dbg_level) 2603 { 2604 } 2605 #else 2606 /** 2607 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2608 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2609 * @ dbg_level: log level. 2610 * 2611 * Return: void 2612 */ 2613 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2614 uint8_t dbg_level) 2615 { 2616 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2617 2618 hal_verbose_debug( 2619 "\n---------------\n" 2620 "rx_pkt_hdr_tlv \n" 2621 "---------------\n" 2622 "phy_ppdu_id %d ", 2623 pkt_hdr_tlv->phy_ppdu_id); 2624 2625 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2626 } 2627 #endif 2628 2629 /** 2630 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2631 * structure 2632 * @hal_ring: pointer to hal_srng structure 2633 * 2634 * Return: ring_id 2635 */ 2636 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 2637 { 2638 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 2639 } 2640 2641 /* Rx MSDU link pointer info */ 2642 struct hal_rx_msdu_link_ptr_info { 2643 struct rx_msdu_link msdu_link; 2644 struct hal_buf_info msdu_link_buf_info; 2645 }; 2646 2647 /** 2648 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2649 * 2650 * @nbuf: Pointer to data buffer field 2651 * Returns: pointer to rx_pkt_tlvs 2652 */ 2653 static inline 2654 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2655 { 2656 return (struct rx_pkt_tlvs *)rx_buf_start; 2657 } 2658 2659 /** 2660 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2661 * 2662 * @pkt_tlvs: Pointer to pkt_tlvs 2663 * Returns: pointer to rx_mpdu_info structure 2664 */ 2665 static inline 2666 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2667 { 2668 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2669 } 2670 2671 #define DOT11_SEQ_FRAG_MASK 0x000f 2672 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2673 2674 /** 2675 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2676 * 2677 * @nbuf: Network buffer 2678 * Returns: rx fragment number 2679 */ 2680 static inline 2681 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 2682 uint8_t *buf) 2683 { 2684 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 2685 } 2686 2687 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2688 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2689 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2690 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2691 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2692 /** 2693 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2694 * 2695 * @nbuf: Network buffer 2696 * Returns: rx more fragment bit 2697 */ 2698 static inline 2699 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2700 { 2701 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2702 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2703 uint16_t frame_ctrl = 0; 2704 2705 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2706 DOT11_FC1_MORE_FRAG_OFFSET; 2707 2708 /* more fragment bit if at offset bit 4 */ 2709 return frame_ctrl; 2710 } 2711 2712 /** 2713 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2714 * 2715 * @nbuf: Network buffer 2716 * Returns: rx more fragment bit 2717 * 2718 */ 2719 static inline 2720 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2721 { 2722 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2723 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2724 uint16_t frame_ctrl = 0; 2725 2726 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2727 2728 return frame_ctrl; 2729 } 2730 2731 /* 2732 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2733 * 2734 * @nbuf: Network buffer 2735 * Returns: flag to indicate whether the nbuf has MC/BC address 2736 */ 2737 static inline 2738 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2739 { 2740 uint8 *buf = qdf_nbuf_data(nbuf); 2741 2742 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2743 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2744 2745 return rx_attn->mcast_bcast; 2746 } 2747 2748 /* 2749 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2750 * @hal_soc_hdl: hal soc handle 2751 * @nbuf: Network buffer 2752 * 2753 * Return: value of sequence control valid field 2754 */ 2755 static inline 2756 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 2757 uint8_t *buf) 2758 { 2759 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2760 2761 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 2762 } 2763 2764 /* 2765 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2766 * @hal_soc_hdl: hal soc handle 2767 * @nbuf: Network buffer 2768 * 2769 * Returns: value of frame control valid field 2770 */ 2771 static inline 2772 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 2773 uint8_t *buf) 2774 { 2775 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2776 2777 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 2778 } 2779 2780 /** 2781 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2782 * @hal_soc_hdl: hal soc handle 2783 * @nbuf: Network buffer 2784 * Returns: value of mpdu 4th address valid field 2785 */ 2786 static inline 2787 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 2788 uint8_t *buf) 2789 { 2790 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2791 2792 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 2793 } 2794 2795 /* 2796 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2797 * 2798 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2799 * Returns: None 2800 */ 2801 static inline 2802 void hal_rx_clear_mpdu_desc_info( 2803 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2804 { 2805 qdf_mem_zero(rx_mpdu_desc_info, 2806 sizeof(*rx_mpdu_desc_info)); 2807 } 2808 2809 /* 2810 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2811 * 2812 * @msdu_link_ptr: HAL view of msdu link ptr 2813 * @size: number of msdu link pointers 2814 * Returns: None 2815 */ 2816 static inline 2817 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2818 int size) 2819 { 2820 qdf_mem_zero(msdu_link_ptr, 2821 (sizeof(*msdu_link_ptr) * size)); 2822 } 2823 2824 /* 2825 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2826 * @msdu_link_ptr: msdu link pointer 2827 * @mpdu_desc_info: mpdu descriptor info 2828 * 2829 * Build a list of msdus using msdu link pointer. If the 2830 * number of msdus are more, chain them together 2831 * 2832 * Returns: Number of processed msdus 2833 */ 2834 static inline 2835 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2836 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2837 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2838 { 2839 int j; 2840 struct rx_msdu_link *msdu_link_ptr = 2841 &msdu_link_ptr_info->msdu_link; 2842 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2843 struct rx_msdu_details *msdu_details = 2844 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2845 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2846 struct rx_msdu_desc_info *msdu_desc_info; 2847 uint8_t fragno, more_frag; 2848 uint8_t *rx_desc_info; 2849 struct hal_rx_msdu_list msdu_list; 2850 2851 for (j = 0; j < num_msdus; j++) { 2852 msdu_desc_info = 2853 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2854 hal_soc); 2855 msdu_list.msdu_info[j].msdu_flags = 2856 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2857 msdu_list.msdu_info[j].msdu_len = 2858 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2859 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2860 &msdu_details[j].buffer_addr_info_details); 2861 } 2862 2863 /* Chain msdu links together */ 2864 if (prev_msdu_link_ptr) { 2865 /* 31-0 bits of the physical address */ 2866 prev_msdu_link_ptr-> 2867 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2868 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2869 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2870 /* 39-32 bits of the physical address */ 2871 prev_msdu_link_ptr-> 2872 next_msdu_link_desc_addr_info.buffer_addr_39_32 2873 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2874 >> 32) & 2875 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2876 prev_msdu_link_ptr-> 2877 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2878 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2879 } 2880 2881 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2882 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2883 /* mark first and last MSDUs */ 2884 rx_desc_info = qdf_nbuf_data(msdu); 2885 fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info); 2886 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2887 2888 /* TODO: create skb->fragslist[] */ 2889 2890 if (more_frag == 0) { 2891 msdu_list.msdu_info[num_msdus].msdu_flags |= 2892 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2893 } else if (fragno == 1) { 2894 msdu_list.msdu_info[num_msdus].msdu_flags |= 2895 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2896 2897 msdu_list.msdu_info[num_msdus].msdu_flags |= 2898 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2899 } 2900 2901 num_msdus++; 2902 2903 /* Number of MSDUs per mpdu descriptor is updated */ 2904 mpdu_desc_info->msdu_count += num_msdus; 2905 } else { 2906 num_msdus = 0; 2907 prev_msdu_link_ptr = msdu_link_ptr; 2908 } 2909 2910 return num_msdus; 2911 } 2912 2913 /* 2914 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2915 * 2916 * @ring_desc: HAL view of ring descriptor 2917 * @mpdu_des_info: saved mpdu desc info 2918 * @msdu_link_ptr: saved msdu link ptr 2919 * 2920 * API used explicitly for rx defrag to update ring desc with 2921 * mpdu desc info and msdu link ptr before reinjecting the 2922 * packet back to REO 2923 * 2924 * Returns: None 2925 */ 2926 static inline 2927 void hal_rx_defrag_update_src_ring_desc( 2928 hal_ring_desc_t ring_desc, 2929 void *saved_mpdu_desc_info, 2930 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 2931 { 2932 struct reo_entrance_ring *reo_ent_ring; 2933 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 2934 struct hal_buf_info buf_info; 2935 2936 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 2937 reo_ring_mpdu_desc_info = &reo_ent_ring-> 2938 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 2939 2940 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 2941 sizeof(*reo_ring_mpdu_desc_info)); 2942 2943 /* 2944 * TODO: Check for additional fields that need configuration in 2945 * reo_ring_mpdu_desc_info 2946 */ 2947 2948 /* Update msdu_link_ptr in the reo entrance ring */ 2949 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 2950 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 2951 buf_info.sw_cookie = 2952 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 2953 } 2954 2955 /* 2956 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 2957 * 2958 * @msdu_link_desc_va: msdu link descriptor handle 2959 * @msdu_link_ptr_info: HAL view of msdu link pointer info 2960 * 2961 * API used to save msdu link information along with physical 2962 * address. The API also copues the sw cookie. 2963 * 2964 * Returns: None 2965 */ 2966 static inline 2967 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 2968 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2969 struct hal_buf_info *hbi) 2970 { 2971 struct rx_msdu_link *msdu_link_ptr = 2972 (struct rx_msdu_link *)msdu_link_desc_va; 2973 2974 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 2975 sizeof(struct rx_msdu_link)); 2976 2977 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 2978 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 2979 } 2980 2981 /* 2982 * hal_rx_get_desc_len(): Returns rx descriptor length 2983 * 2984 * Returns the size of rx_pkt_tlvs which follows the 2985 * data in the nbuf 2986 * 2987 * Returns: Length of rx descriptor 2988 */ 2989 static inline 2990 uint16_t hal_rx_get_desc_len(void) 2991 { 2992 return SIZE_OF_DATA_RX_TLV; 2993 } 2994 2995 /* 2996 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 2997 * reo_entrance_ring descriptor 2998 * 2999 * @reo_ent_desc: reo_entrance_ring descriptor 3000 * Returns: value of rxdma_push_reason 3001 */ 3002 static inline 3003 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 3004 { 3005 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3006 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 3007 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 3008 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 3009 } 3010 3011 /** 3012 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 3013 * reo_entrance_ring descriptor 3014 * @reo_ent_desc: reo_entrance_ring descriptor 3015 * Return: value of rxdma_error_code 3016 */ 3017 static inline 3018 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 3019 { 3020 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3021 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 3022 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 3023 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 3024 } 3025 3026 /** 3027 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 3028 * save it to hal_wbm_err_desc_info structure passed by caller 3029 * @wbm_desc: wbm ring descriptor 3030 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3031 * Return: void 3032 */ 3033 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 3034 struct hal_wbm_err_desc_info *wbm_er_info, 3035 hal_soc_handle_t hal_soc_hdl) 3036 { 3037 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3038 3039 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 3040 } 3041 3042 /** 3043 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 3044 * the reserved bytes of rx_tlv_hdr 3045 * @buf: start of rx_tlv_hdr 3046 * @wbm_er_info: hal_wbm_err_desc_info structure 3047 * Return: void 3048 */ 3049 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 3050 struct hal_wbm_err_desc_info *wbm_er_info) 3051 { 3052 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3053 3054 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 3055 sizeof(struct hal_wbm_err_desc_info)); 3056 } 3057 3058 /** 3059 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 3060 * the reserved bytes of rx_tlv_hdr. 3061 * @buf: start of rx_tlv_hdr 3062 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3063 * Return: void 3064 */ 3065 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 3066 struct hal_wbm_err_desc_info *wbm_er_info) 3067 { 3068 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3069 3070 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 3071 sizeof(struct hal_wbm_err_desc_info)); 3072 } 3073 3074 /** 3075 * hal_rx_mon_dest_set_buffer_info_to_tlv(): Save the mon dest frame info 3076 * into the reserved bytes of rx_tlv_hdr. 3077 * @buf: start of rx_tlv_hdr 3078 * @buf_info: hal_rx_mon_dest_buf_info structure 3079 * 3080 * Return: void 3081 */ 3082 static inline 3083 void hal_rx_mon_dest_set_buffer_info_to_tlv(uint8_t *buf, 3084 struct hal_rx_mon_dest_buf_info *buf_info) 3085 { 3086 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3087 3088 qdf_mem_copy(pkt_tlvs->rx_padding0, buf_info, 3089 sizeof(struct hal_rx_mon_dest_buf_info)); 3090 } 3091 3092 /** 3093 * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info 3094 * from the reserved bytes of rx_tlv_hdr. 3095 * @buf: start of rx_tlv_hdr 3096 * @buf_info: hal_rx_mon_dest_buf_info structure 3097 * 3098 * Return: void 3099 */ 3100 static inline 3101 void hal_rx_mon_dest_get_buffer_info_from_tlv(uint8_t *buf, 3102 struct hal_rx_mon_dest_buf_info *buf_info) 3103 { 3104 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3105 3106 qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0, 3107 sizeof(struct hal_rx_mon_dest_buf_info)); 3108 } 3109 3110 /** 3111 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 3112 * bit from wbm release ring descriptor 3113 * @wbm_desc: wbm ring descriptor 3114 * Return: uint8_t 3115 */ 3116 static inline 3117 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 3118 void *wbm_desc) 3119 { 3120 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3121 3122 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 3123 } 3124 3125 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 3126 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 3127 RX_MSDU_START_5_NSS_OFFSET)), \ 3128 RX_MSDU_START_5_NSS_MASK, \ 3129 RX_MSDU_START_5_NSS_LSB)) 3130 3131 /** 3132 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 3133 * 3134 * @ hal_soc: HAL version of the SOC pointer 3135 * @ hw_desc_addr: Start address of Rx HW TLVs 3136 * @ rs: Status for monitor mode 3137 * 3138 * Return: void 3139 */ 3140 static inline 3141 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 3142 void *hw_desc_addr, 3143 struct mon_rx_status *rs) 3144 { 3145 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3146 3147 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 3148 } 3149 3150 /* 3151 * hal_rx_get_tlv(): API to get the tlv 3152 * 3153 * @hal_soc: HAL version of the SOC pointer 3154 * @rx_tlv: TLV data extracted from the rx packet 3155 * Return: uint8_t 3156 */ 3157 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 3158 { 3159 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 3160 } 3161 3162 /* 3163 * hal_rx_msdu_start_nss_get(): API to get the NSS 3164 * Interval from rx_msdu_start 3165 * 3166 * @hal_soc: HAL version of the SOC pointer 3167 * @buf: pointer to the start of RX PKT TLV header 3168 * Return: uint32_t(nss) 3169 */ 3170 static inline 3171 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3172 { 3173 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3174 3175 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3176 } 3177 3178 /** 3179 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3180 * human readable format. 3181 * @ msdu_start: pointer the msdu_start TLV in pkt. 3182 * @ dbg_level: log level. 3183 * 3184 * Return: void 3185 */ 3186 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3187 struct rx_msdu_start *msdu_start, 3188 uint8_t dbg_level) 3189 { 3190 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3191 } 3192 3193 /** 3194 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3195 * info details 3196 * 3197 * @ buf - Pointer to buffer containing rx pkt tlvs. 3198 * 3199 * 3200 */ 3201 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 3202 uint8_t *buf) 3203 { 3204 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3205 3206 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3207 } 3208 3209 /* 3210 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3211 * Interval from rx_msdu_start 3212 * 3213 * @buf: pointer to the start of RX PKT TLV header 3214 * Return: uint32_t(reception_type) 3215 */ 3216 static inline 3217 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 3218 uint8_t *buf) 3219 { 3220 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3221 3222 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3223 } 3224 3225 /** 3226 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3227 * RX TLVs 3228 * @ buf: pointer the pkt buffer. 3229 * @ dbg_level: log level. 3230 * 3231 * Return: void 3232 */ 3233 static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 3234 uint8_t *buf, uint8_t dbg_level) 3235 { 3236 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3237 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3238 struct rx_mpdu_start *mpdu_start = 3239 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3240 struct rx_msdu_start *msdu_start = 3241 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3242 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3243 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3244 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3245 3246 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3247 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3248 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3249 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3250 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3251 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3252 } 3253 3254 3255 /** 3256 * hal_reo_status_get_header_generic - Process reo desc info 3257 * @d - Pointer to reo descriptior 3258 * @b - tlv type info 3259 * @h - Pointer to hal_reo_status_header where info to be stored 3260 * @hal- pointer to hal_soc structure 3261 * Return - none. 3262 * 3263 */ 3264 static inline 3265 void hal_reo_status_get_header(uint32_t *d, int b, 3266 void *h, struct hal_soc *hal_soc) 3267 { 3268 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3269 } 3270 3271 /** 3272 * hal_rx_desc_is_first_msdu() - Check if first msdu 3273 * 3274 * @hal_soc_hdl: hal_soc handle 3275 * @hw_desc_addr: hardware descriptor address 3276 * 3277 * Return: 0 - success/ non-zero failure 3278 */ 3279 static inline 3280 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 3281 void *hw_desc_addr) 3282 { 3283 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3284 3285 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 3286 } 3287 3288 static inline 3289 uint32_t 3290 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3291 struct rx_msdu_start *rx_msdu_start; 3292 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3293 3294 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3295 3296 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3297 } 3298 3299 #ifdef NO_RX_PKT_HDR_TLV 3300 static inline 3301 uint8_t * 3302 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3303 uint8_t *rx_pkt_hdr; 3304 struct rx_mon_pkt_tlvs *rx_desc = 3305 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 3306 3307 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3308 3309 return rx_pkt_hdr; 3310 } 3311 #else 3312 static inline 3313 uint8_t * 3314 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3315 uint8_t *rx_pkt_hdr; 3316 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3317 3318 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3319 3320 return rx_pkt_hdr; 3321 } 3322 #endif 3323 3324 static inline 3325 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3326 uint8_t *rx_tlv_hdr) 3327 { 3328 uint8_t decap_format; 3329 3330 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 3331 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3332 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3333 return true; 3334 } 3335 3336 return false; 3337 } 3338 3339 /** 3340 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 3341 * from rx_msdu_end TLV 3342 * @buf: pointer to the start of RX PKT TLV headers 3343 * 3344 * Return: fse metadata value from MSDU END TLV 3345 */ 3346 static inline uint32_t 3347 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 3348 uint8_t *buf) 3349 { 3350 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3351 3352 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 3353 } 3354 3355 /** 3356 * hal_rx_msdu_flow_idx_get: API to get flow index 3357 * from rx_msdu_end TLV 3358 * @buf: pointer to the start of RX PKT TLV headers 3359 * 3360 * Return: flow index value from MSDU END TLV 3361 */ 3362 static inline uint32_t 3363 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 3364 uint8_t *buf) 3365 { 3366 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3367 3368 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 3369 } 3370 3371 /** 3372 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 3373 * from rx_msdu_end TLV 3374 * @buf: pointer to the start of RX PKT TLV headers 3375 * 3376 * Return: flow index timeout value from MSDU END TLV 3377 */ 3378 static inline bool 3379 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 3380 uint8_t *buf) 3381 { 3382 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3383 3384 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 3385 } 3386 3387 /** 3388 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 3389 * from rx_msdu_end TLV 3390 * @buf: pointer to the start of RX PKT TLV headers 3391 * 3392 * Return: flow index invalid value from MSDU END TLV 3393 */ 3394 static inline bool 3395 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 3396 uint8_t *buf) 3397 { 3398 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3399 3400 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 3401 } 3402 3403 /** 3404 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 3405 * @hal_soc_hdl: hal_soc handle 3406 * @rx_tlv_hdr: Rx_tlv_hdr 3407 * @rxdma_dst_ring_desc: Rx HW descriptor 3408 * 3409 * Return: ppdu id 3410 */ 3411 static inline 3412 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 3413 void *rx_tlv_hdr, 3414 void *rxdma_dst_ring_desc) 3415 { 3416 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3417 3418 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 3419 rxdma_dst_ring_desc); 3420 } 3421 3422 /** 3423 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 3424 * @hal_soc_hdl: hal_soc handle 3425 * @buf: rx tlv address 3426 * 3427 * Return: sw peer id 3428 */ 3429 static inline 3430 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 3431 uint8_t *buf) 3432 { 3433 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3434 3435 if ((!hal_soc) || (!hal_soc->ops)) { 3436 hal_err("hal handle is NULL"); 3437 QDF_BUG(0); 3438 return QDF_STATUS_E_INVAL; 3439 } 3440 3441 if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get) 3442 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 3443 3444 return QDF_STATUS_E_INVAL; 3445 } 3446 3447 static inline 3448 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 3449 void *link_desc_addr) 3450 { 3451 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3452 3453 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 3454 } 3455 3456 static inline 3457 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 3458 void *msdu_addr) 3459 { 3460 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3461 3462 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 3463 } 3464 3465 static inline 3466 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3467 void *hw_addr) 3468 { 3469 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3470 3471 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 3472 } 3473 3474 static inline 3475 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3476 void *hw_addr) 3477 { 3478 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3479 3480 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 3481 } 3482 3483 static inline 3484 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 3485 uint8_t *buf) 3486 { 3487 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3488 3489 return hal_soc->ops->hal_rx_get_fc_valid(buf); 3490 } 3491 3492 static inline 3493 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3494 { 3495 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3496 3497 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 3498 } 3499 3500 static inline 3501 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 3502 uint8_t *buf) 3503 { 3504 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3505 3506 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 3507 } 3508 3509 static inline 3510 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 3511 uint8_t *buf) 3512 { 3513 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3514 3515 return hal_soc->ops->hal_rx_get_filter_category(buf); 3516 } 3517 3518 static inline 3519 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 3520 uint8_t *buf) 3521 { 3522 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3523 3524 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 3525 } 3526 3527 /** 3528 * hal_reo_config(): Set reo config parameters 3529 * @soc: hal soc handle 3530 * @reg_val: value to be set 3531 * @reo_params: reo parameters 3532 * 3533 * Return: void 3534 */ 3535 static inline 3536 void hal_reo_config(struct hal_soc *hal_soc, 3537 uint32_t reg_val, 3538 struct hal_reo_params *reo_params) 3539 { 3540 hal_soc->ops->hal_reo_config(hal_soc, 3541 reg_val, 3542 reo_params); 3543 } 3544 3545 /** 3546 * hal_rx_msdu_get_flow_params: API to get flow index, 3547 * flow index invalid and flow index timeout from rx_msdu_end TLV 3548 * @buf: pointer to the start of RX PKT TLV headers 3549 * @flow_invalid: pointer to return value of flow_idx_valid 3550 * @flow_timeout: pointer to return value of flow_idx_timeout 3551 * @flow_index: pointer to return value of flow_idx 3552 * 3553 * Return: none 3554 */ 3555 static inline void 3556 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 3557 uint8_t *buf, 3558 bool *flow_invalid, 3559 bool *flow_timeout, 3560 uint32_t *flow_index) 3561 { 3562 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3563 3564 if ((!hal_soc) || (!hal_soc->ops)) { 3565 hal_err("hal handle is NULL"); 3566 QDF_BUG(0); 3567 return; 3568 } 3569 3570 if (hal_soc->ops->hal_rx_msdu_get_flow_params) 3571 hal_soc->ops-> 3572 hal_rx_msdu_get_flow_params(buf, 3573 flow_invalid, 3574 flow_timeout, 3575 flow_index); 3576 } 3577 3578 static inline 3579 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 3580 uint8_t *buf) 3581 { 3582 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3583 3584 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 3585 } 3586 3587 static inline 3588 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 3589 uint8_t *buf) 3590 { 3591 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3592 3593 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 3594 } 3595 3596 static inline void 3597 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 3598 void *rx_tlv, 3599 void *ppdu_info) 3600 { 3601 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3602 3603 if (hal_soc->ops->hal_rx_get_bb_info) 3604 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 3605 } 3606 3607 static inline void 3608 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 3609 void *rx_tlv, 3610 void *ppdu_info) 3611 { 3612 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3613 3614 if (hal_soc->ops->hal_rx_get_rtt_info) 3615 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 3616 } 3617 3618 /** 3619 * hal_rx_msdu_metadata_get(): API to get the 3620 * fast path information from rx_msdu_end TLV 3621 * 3622 * @ hal_soc_hdl: DP soc handle 3623 * @ buf: pointer to the start of RX PKT TLV headers 3624 * @ msdu_metadata: Structure to hold msdu end information 3625 * Return: none 3626 */ 3627 static inline void 3628 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 3629 struct hal_rx_msdu_metadata *msdu_md) 3630 { 3631 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3632 3633 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 3634 } 3635 3636 /** 3637 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 3638 * from rx_msdu_end TLV 3639 * @buf: pointer to the start of RX PKT TLV headers 3640 * 3641 * Return: cumulative_l4_checksum 3642 */ 3643 static inline uint16_t 3644 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 3645 uint8_t *buf) 3646 { 3647 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3648 3649 if (!hal_soc || !hal_soc->ops) { 3650 hal_err("hal handle is NULL"); 3651 QDF_BUG(0); 3652 return 0; 3653 } 3654 3655 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 3656 return 0; 3657 3658 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 3659 } 3660 3661 /** 3662 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 3663 * from rx_msdu_end TLV 3664 * @buf: pointer to the start of RX PKT TLV headers 3665 * 3666 * Return: cumulative_ip_length 3667 */ 3668 static inline uint16_t 3669 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 3670 uint8_t *buf) 3671 { 3672 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3673 3674 if (!hal_soc || !hal_soc->ops) { 3675 hal_err("hal handle is NULL"); 3676 QDF_BUG(0); 3677 return 0; 3678 } 3679 3680 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 3681 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 3682 3683 return 0; 3684 } 3685 3686 /** 3687 * hal_rx_get_udp_proto: API to get UDP proto field 3688 * from rx_msdu_start TLV 3689 * @buf: pointer to the start of RX PKT TLV headers 3690 * 3691 * Return: UDP proto field value 3692 */ 3693 static inline bool 3694 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3695 { 3696 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3697 3698 if (!hal_soc || !hal_soc->ops) { 3699 hal_err("hal handle is NULL"); 3700 QDF_BUG(0); 3701 return 0; 3702 } 3703 3704 if (hal_soc->ops->hal_rx_get_udp_proto) 3705 return hal_soc->ops->hal_rx_get_udp_proto(buf); 3706 3707 return 0; 3708 } 3709 3710 /** 3711 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 3712 * from rx_msdu_end TLV 3713 * @buf: pointer to the start of RX PKT TLV headers 3714 * 3715 * Return: flow_agg_continuation bit field value 3716 */ 3717 static inline bool 3718 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 3719 uint8_t *buf) 3720 { 3721 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3722 3723 if (!hal_soc || !hal_soc->ops) { 3724 hal_err("hal handle is NULL"); 3725 QDF_BUG(0); 3726 return 0; 3727 } 3728 3729 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 3730 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 3731 3732 return 0; 3733 } 3734 3735 /** 3736 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 3737 * rx_msdu_end TLV 3738 * @buf: pointer to the start of RX PKT TLV headers 3739 * 3740 * Return: flow_agg count value 3741 */ 3742 static inline uint8_t 3743 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 3744 uint8_t *buf) 3745 { 3746 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3747 3748 if (!hal_soc || !hal_soc->ops) { 3749 hal_err("hal handle is NULL"); 3750 QDF_BUG(0); 3751 return 0; 3752 } 3753 3754 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 3755 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 3756 3757 return 0; 3758 } 3759 3760 /** 3761 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 3762 * @buf: pointer to the start of RX PKT TLV headers 3763 * 3764 * Return: fisa flow_agg timeout bit value 3765 */ 3766 static inline bool 3767 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3768 { 3769 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3770 3771 if (!hal_soc || !hal_soc->ops) { 3772 hal_err("hal handle is NULL"); 3773 QDF_BUG(0); 3774 return 0; 3775 } 3776 3777 if (hal_soc->ops->hal_rx_get_fisa_timeout) 3778 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 3779 3780 return 0; 3781 } 3782 3783 /** 3784 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 3785 * tag is valid 3786 * 3787 * @hal_soc_hdl: HAL SOC handle 3788 * @rx_tlv_hdr: start address of rx_pkt_tlvs 3789 * 3790 * Return: true if RX_MPDU_START tlv tag is valid, else false 3791 */ 3792 3793 static inline uint8_t 3794 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 3795 void *rx_tlv_hdr) 3796 { 3797 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3798 3799 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 3800 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 3801 3802 return 0; 3803 } 3804 3805 /** 3806 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 3807 * <struct buffer_addr_info> structure 3808 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 3809 * @buf_info: structure to return the buffer information including 3810 * paddr/cookie 3811 * 3812 * return: None 3813 */ 3814 static inline 3815 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 3816 struct hal_buf_info *buf_info) 3817 { 3818 buf_info->paddr = 3819 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 3820 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 3821 3822 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 3823 } 3824 3825 /** 3826 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 3827 * buffer addr info 3828 * @link_desc_va: pointer to current msdu link Desc 3829 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 3830 * 3831 * return: None 3832 */ 3833 static inline 3834 void hal_rx_get_next_msdu_link_desc_buf_addr_info( 3835 void *link_desc_va, 3836 struct buffer_addr_info *next_addr_info) 3837 { 3838 struct rx_msdu_link *msdu_link = link_desc_va; 3839 3840 if (!msdu_link) { 3841 qdf_mem_zero(next_addr_info, 3842 sizeof(struct buffer_addr_info)); 3843 return; 3844 } 3845 3846 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 3847 } 3848 3849 /** 3850 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 3851 * 3852 * @buf_addr_info: pointer to buf_addr_info structure 3853 * 3854 * return: true: has valid paddr, false: not. 3855 */ 3856 static inline 3857 bool hal_rx_is_buf_addr_info_valid( 3858 struct buffer_addr_info *buf_addr_info) 3859 { 3860 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 3861 false : true; 3862 } 3863 3864 /** 3865 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 3866 * rx_pkt_tlvs structure 3867 * 3868 * @hal_soc_hdl: HAL SOC handle 3869 * return: msdu_end_tlv offset value 3870 */ 3871 static inline 3872 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 3873 { 3874 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3875 3876 if (!hal_soc || !hal_soc->ops) { 3877 hal_err("hal handle is NULL"); 3878 QDF_BUG(0); 3879 return 0; 3880 } 3881 3882 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 3883 } 3884 3885 /** 3886 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 3887 * rx_pkt_tlvs structure 3888 * 3889 * @hal_soc_hdl: HAL SOC handle 3890 * return: msdu_start_tlv offset value 3891 */ 3892 static inline 3893 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 3894 { 3895 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3896 3897 if (!hal_soc || !hal_soc->ops) { 3898 hal_err("hal handle is NULL"); 3899 QDF_BUG(0); 3900 return 0; 3901 } 3902 3903 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 3904 } 3905 3906 /** 3907 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 3908 * rx_pkt_tlvs structure 3909 * 3910 * @hal_soc_hdl: HAL SOC handle 3911 * return: mpdu_start_tlv offset value 3912 */ 3913 static inline 3914 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 3915 { 3916 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3917 3918 if (!hal_soc || !hal_soc->ops) { 3919 hal_err("hal handle is NULL"); 3920 QDF_BUG(0); 3921 return 0; 3922 } 3923 3924 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 3925 } 3926 3927 /** 3928 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 3929 * rx_pkt_tlvs structure 3930 * 3931 * @hal_soc_hdl: HAL SOC handle 3932 * return: mpdu_end_tlv offset value 3933 */ 3934 static inline 3935 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 3936 { 3937 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3938 3939 if (!hal_soc || !hal_soc->ops) { 3940 hal_err("hal handle is NULL"); 3941 QDF_BUG(0); 3942 return 0; 3943 } 3944 3945 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 3946 } 3947 3948 /** 3949 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 3950 * rx_pkt_tlvs structure 3951 * 3952 * @hal_soc_hdl: HAL SOC handle 3953 * return: attn_tlv offset value 3954 */ 3955 static inline 3956 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 3957 { 3958 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3959 3960 if (!hal_soc || !hal_soc->ops) { 3961 hal_err("hal handle is NULL"); 3962 QDF_BUG(0); 3963 return 0; 3964 } 3965 3966 return hal_soc->ops->hal_rx_attn_offset_get(); 3967 } 3968 #endif /* _HAL_RX_H */ 3969