1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_RX_H_ 21 #define _HAL_RX_H_ 22 23 #include <hal_api.h> 24 #include "hal_rx_hw_defines.h" 25 #include "hal_hw_headers.h" 26 27 /************************************* 28 * Ring desc offset/shift/masks 29 *************************************/ 30 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 31 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 32 #define HAL_RX_LSB(block, field) block##_##field##_LSB 33 #define HAL_RX_MASK(block, field) block##_##field##_MASK 34 #define HAL_RX_TLV_L3_TYPE_INVALID 0xFFFF 35 36 #define HAL_RX_GET(_ptr, block, field) \ 37 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 38 HAL_RX_MASK(block, field)) >> \ 39 HAL_RX_LSB(block, field)) 40 41 #define HAL_RX_GET_64(_ptr, block, field) \ 42 (((*((volatile uint64_t *)(_ptr) + \ 43 (HAL_RX_OFFSET(block, field) >> 3))) & \ 44 HAL_RX_MASK(block, field)) >> \ 45 HAL_RX_LSB(block, field)) 46 47 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 48 (*(uint32_t *)(((uint8_t *)_ptr) + \ 49 _wrd ## _ ## _field ## _OFFSET) |= \ 50 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 51 _wrd ## _ ## _field ## _MASK)) 52 53 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 54 #ifndef RX_DATA_BUFFER_SIZE 55 #define RX_DATA_BUFFER_SIZE 2048 56 #endif 57 58 #ifndef RX_MONITOR_BUFFER_SIZE 59 #define RX_MONITOR_BUFFER_SIZE 2048 60 #endif 61 62 #define RXDMA_OPTIMIZATION 63 64 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 65 * including buffer reservation, buffer alignment and skb shared info size. 66 */ 67 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 68 #define RX_MON_STATUS_BUF_ALIGN 128 69 #define RX_MON_STATUS_BUF_RESERVATION 128 70 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 71 (RX_MON_STATUS_BUF_RESERVATION + \ 72 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 73 74 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 75 76 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 77 #define HAL_RX_NON_QOS_TID 16 78 79 enum { 80 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 81 HAL_HW_RX_DECAP_FORMAT_NWIFI, 82 HAL_HW_RX_DECAP_FORMAT_ETH2, 83 HAL_HW_RX_DECAP_FORMAT_8023, 84 }; 85 86 /** 87 * struct hal_wbm_err_desc_info - structure to hold wbm error codes and reasons 88 * 89 * @reo_psh_rsn: REO push reason 90 * @reo_err_code: REO Error code 91 * @rxdma_psh_rsn: RXDMA push reason 92 * @rxdma_err_code: RXDMA Error code 93 * @reserved_1: Reserved bits 94 * @wbm_err_src: WBM error source 95 * @pool_id: pool ID, indicates which rxdma pool 96 * @msdu_continued: Is the MSDU continued 97 * @reserved_2: Reserved bits 98 */ 99 struct hal_wbm_err_desc_info { 100 uint16_t reo_psh_rsn:2, 101 reo_err_code:5, 102 rxdma_psh_rsn:2, 103 rxdma_err_code:5, 104 reserved_1:2; 105 uint8_t wbm_err_src:3, 106 pool_id:2, 107 msdu_continued:1, 108 reserved_2:2; 109 }; 110 111 /** 112 * struct hal_rx_mon_dest_buf_info - Structure to hold rx mon dest buffer info 113 * @first_buffer: First buffer of MSDU 114 * @last_buffer: Last buffer of MSDU 115 * @is_decap_raw: Is RAW Frame 116 * @mpdu_len_err: Is there an MPDU length error 117 * @l2_hdr_pad: Amount of layer 2 header padding 118 * @reserved_1: Reserved 119 * 120 * MSDU with continuation: 121 * ----------------------------------------------------------- 122 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 123 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 124 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 125 * ----------------------------------------------------------- 126 * 127 * Single buffer MSDU: 128 * ------------------ 129 * | first_buffer:1 | 130 * | last_buffer :1 | 131 * | is_decap_raw:1/0 | 132 * ------------------ 133 */ 134 struct hal_rx_mon_dest_buf_info { 135 uint8_t first_buffer:1, 136 last_buffer:1, 137 is_decap_raw:1, 138 mpdu_len_err:1, 139 l2_hdr_pad:2, 140 reserved_1:2; 141 }; 142 143 /** 144 * struct hal_rx_msdu_metadata - Structure to hold rx fast path information. 145 * 146 * @l3_hdr_pad: l3 header padding 147 * @reserved: Reserved bits 148 * @sa_sw_peer_id: sa sw peer id 149 * @sa_idx: sa index 150 * @da_idx: da index 151 */ 152 struct hal_rx_msdu_metadata { 153 uint32_t l3_hdr_pad:16, 154 sa_sw_peer_id:16; 155 uint32_t sa_idx:16, 156 da_idx:16; 157 }; 158 159 struct hal_proto_params { 160 uint8_t tcp_proto; 161 uint8_t udp_proto; 162 uint8_t ipv6_proto; 163 }; 164 165 /** 166 * enum hal_reo_error_status - Enum which encapsulates "reo_push_reason" 167 * 168 * @HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 169 * @HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 170 */ 171 enum hal_reo_error_status { 172 HAL_REO_ERROR_DETECTED = 0, 173 HAL_REO_ROUTING_INSTRUCTION = 1, 174 }; 175 176 /** 177 * struct hal_rx_msdu_desc_info - RX MSDU Descriptor 178 * @msdu_flags: [0] first_msdu_in_mpdu 179 * [1] last_msdu_in_mpdu 180 * [2] msdu_continuation - MSDU spread across buffers 181 * [23] sa_is_valid - SA match in peer table 182 * [24] sa_idx_timeout - Timeout while searching for SA match 183 * [25] da_is_valid - Used to identtify intra-bss forwarding 184 * [26] da_is_MCBC 185 * [27] da_idx_timeout - Timeout while searching for DA match 186 * @msdu_len: length of the MSDU (14 bits of length) 187 * 188 */ 189 struct hal_rx_msdu_desc_info { 190 uint32_t msdu_flags; 191 uint16_t msdu_len; 192 }; 193 194 /** 195 * enum hal_rx_msdu_desc_flags - Enum for flags in MSDU_DESC_INFO 196 * 197 * @HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 198 * @HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 199 * @HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 200 * @HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 201 * @HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 202 * @HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 203 * @HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 204 * @HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 205 * @HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 206 */ 207 enum hal_rx_msdu_desc_flags { 208 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 209 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 210 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 211 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 212 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 213 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 214 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 215 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 216 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 217 }; 218 219 /** 220 * struct hal_rx_mpdu_desc_info - RX MPDU descriptor 221 * @msdu_count: no. of msdus in the MPDU 222 * @mpdu_seq: MPDU sequence number 223 * @mpdu_flags: [0] Fragment flag 224 * [1] MPDU_retry_bit 225 * [2] AMPDU flag 226 * [3] raw_ampdu 227 * @peer_meta_data: Upper bits containing peer id, vdev id 228 * @bar_frame: indicates if received frame is a bar frame 229 * @tid: tid value of received MPDU 230 * @reserved: spare bits 231 */ 232 struct hal_rx_mpdu_desc_info { 233 uint16_t msdu_count; 234 uint16_t mpdu_seq; /* 12 bits for length */ 235 uint32_t mpdu_flags; 236 uint32_t peer_meta_data; /* sw programmed meta-data:MAC Id & peer Id */ 237 uint16_t bar_frame; 238 uint8_t tid:4, 239 reserved:4; 240 }; 241 242 /** 243 * enum hal_rx_mpdu_desc_flags - Enum for flags in MPDU_DESC_INFO 244 * 245 * @HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 246 * @HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 247 * @HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 248 * @HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 249 * @HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field 250 */ 251 enum hal_rx_mpdu_desc_flags { 252 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 253 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 254 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 255 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30), 256 HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31) 257 }; 258 259 /* Return Buffer manager ID */ 260 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 261 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 262 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 263 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 264 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 265 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 266 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 267 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 268 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 269 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 270 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 271 272 #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id) 273 274 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 275 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 276 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 277 278 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 279 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 280 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 281 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 282 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 283 284 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 285 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 286 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 287 288 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 289 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 290 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 291 292 /* 293 * macro to set the LSW of the nbuf data physical address 294 * to the rxdma ring entry 295 */ 296 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 297 ((*(((unsigned int *) buff_addr_info) + \ 298 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 299 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 300 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 301 302 /* 303 * macro to set the LSB of MSW of the nbuf data physical address 304 * to the rxdma ring entry 305 */ 306 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 307 ((*(((unsigned int *) buff_addr_info) + \ 308 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 309 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 310 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 311 312 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 313 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 314 315 /* 316 * macro to get the invalid bit for sw cookie 317 */ 318 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 319 ((*(((unsigned int *)buff_addr_info) + \ 320 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 321 HAL_RX_COOKIE_INVALID_MASK) 322 323 /* 324 * macro to set the invalid bit for sw cookie 325 */ 326 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 327 ((*(((unsigned int *)buff_addr_info) + \ 328 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 329 HAL_RX_COOKIE_INVALID_MASK) 330 331 /* 332 * macro to reset the invalid bit for sw cookie 333 */ 334 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 335 ((*(((unsigned int *)buff_addr_info) + \ 336 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 337 ~HAL_RX_COOKIE_INVALID_MASK) 338 339 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 340 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 341 (((struct reo_destination_ring *) \ 342 reo_desc)->buf_or_link_desc_addr_info))) 343 344 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 345 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 346 (((struct reo_destination_ring *) \ 347 reo_desc)->buf_or_link_desc_addr_info))) 348 349 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 350 351 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 352 ((*(((unsigned int *)buff_addr_info) + \ 353 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 354 HAL_RX_LINK_COOKIE_INVALID_MASK) 355 356 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 357 ((*(((unsigned int *)buff_addr_info) + \ 358 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 359 HAL_RX_LINK_COOKIE_INVALID_MASK) 360 361 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 362 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 363 (((struct reo_destination_ring *) \ 364 reo_desc)->buf_or_link_desc_addr_info))) 365 366 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 367 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 368 (((struct reo_destination_ring *) \ 369 reo_desc)->buf_or_link_desc_addr_info))) 370 #endif 371 372 /* TODO: Convert the following structure fields accesseses to offsets */ 373 374 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 375 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 376 (((struct reo_destination_ring *) \ 377 reo_desc)->buf_or_link_desc_addr_info))) 378 379 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 380 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 381 (((struct reo_destination_ring *) \ 382 reo_desc)->buf_or_link_desc_addr_info))) 383 384 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 385 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 386 (((struct reo_destination_ring *) \ 387 reo_desc)->buf_or_link_desc_addr_info))) 388 389 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 390 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 391 _field, _val) 392 393 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 394 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 395 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 396 397 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 398 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 399 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 400 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 401 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 402 403 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 404 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 405 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 406 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 407 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 408 409 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 410 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 411 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 412 413 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 414 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 415 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 416 417 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 418 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 419 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 420 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 421 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 422 423 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 424 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 425 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 426 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 427 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 428 429 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 430 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 431 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 432 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 433 434 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 435 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 436 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 437 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 438 439 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 440 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 441 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 442 443 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 444 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 445 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 446 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 447 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 448 449 static inline uint32_t 450 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 451 rx_msdu_desc_info_t msdu_desc_info_hdl) 452 { 453 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 454 455 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 456 } 457 458 /* 459 * Structures & Macros to obtain fields from the TLV's in the Rx packet 460 * pre-header. 461 */ 462 463 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 464 void *hw_desc_addr) 465 { 466 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 467 468 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 469 } 470 471 /** 472 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 473 * @hal_soc_hdl: hal soc handle 474 * @desc_addr: ring descriptor 475 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 476 * 477 * Return: None 478 */ 479 static inline void 480 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 481 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 482 { 483 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 484 485 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 486 mpdu_desc_info); 487 } 488 489 #define HAL_RX_NUM_MSDU_DESC 6 490 #define HAL_RX_MAX_SAVED_RING_DESC 16 491 492 /* TODO: rework the structure */ 493 struct hal_rx_msdu_list { 494 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 495 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 496 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 497 /* physical address of the msdu */ 498 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 499 }; 500 501 struct hal_buf_info { 502 uint64_t paddr; 503 uint32_t sw_cookie; 504 uint8_t rbm; 505 }; 506 507 /* This special cookie value will be used to indicate FW allocated buffers 508 * received through RXDMA2SW ring for RXDMA WARs 509 */ 510 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 511 512 /** 513 * enum hal_rx_reo_buf_type - Indicates that type of buffer or descriptor 514 * 515 * @HAL_RX_REO_MSDU_BUF_ADDR_TYPE: Reo buffer address points to the MSDU buffer 516 * @HAL_RX_REO_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 517 * descriptor 518 */ 519 enum hal_rx_reo_buf_type { 520 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 521 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 522 }; 523 524 /** 525 * enum hal_reo_error_code - Error code describing the type of error detected 526 * 527 * @HAL_REO_ERR_QUEUE_DESC_ADDR_0: Reo queue descriptor provided in the 528 * REO_ENTRANCE ring is set to 0 529 * @HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 530 * @HAL_REO_ERR_AMPDU_IN_NON_BA: AMPDU frame received without BA session 531 * having been setup 532 * @HAL_REO_ERR_NON_BA_DUPLICATE: Non-BA session, SN equal to SSN, 533 * Retry bit set: duplicate frame 534 * @HAL_REO_ERR_BA_DUPLICATE: BA session, duplicate frame 535 * @HAL_REO_ERR_REGULAR_FRAME_2K_JUMP: A normal (management/data frame) 536 * received with 2K jump in SN 537 * @HAL_REO_ERR_BAR_FRAME_2K_JUMP: A bar received with 2K jump in SSN 538 * @HAL_REO_ERR_REGULAR_FRAME_OOR: A normal (management/data frame) received 539 * with SN falling within the OOR window 540 * @HAL_REO_ERR_BAR_FRAME_OOR: A bar received with SSN falling within the 541 * OOR window 542 * @HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION: A bar received without a BA session 543 * @HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN: A bar received with SSN equal to SN 544 * @HAL_REO_ERR_PN_CHECK_FAILED: PN Check Failed packet 545 * @HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET: Frame is forwarded as a result 546 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 547 * @HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET: Frame is forwarded as a result 548 * of the pn_error_detected_flag been set in the REO Queue descriptor 549 * @HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET: Frame is forwarded as a result of 550 * the queue descriptor(address) being blocked as SW/FW seems to be currently 551 * in the process of making updates to this descriptor 552 * @HAL_REO_ERR_MAX: count of number of enumerators 553 */ 554 enum hal_reo_error_code { 555 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 556 HAL_REO_ERR_QUEUE_DESC_INVALID, 557 HAL_REO_ERR_AMPDU_IN_NON_BA, 558 HAL_REO_ERR_NON_BA_DUPLICATE, 559 HAL_REO_ERR_BA_DUPLICATE, 560 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 561 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 562 HAL_REO_ERR_REGULAR_FRAME_OOR, 563 HAL_REO_ERR_BAR_FRAME_OOR, 564 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 565 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 566 HAL_REO_ERR_PN_CHECK_FAILED, 567 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 568 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 569 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 570 HAL_REO_ERR_MAX 571 }; 572 573 /** 574 * enum hal_rxdma_error_code - Code describing the type of RxDMA error detected 575 * 576 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 577 * @HAL_RXDMA_ERR_MPDU_LENGTH: MPDU frame is not complete due to receiving 578 * incomplete MPDU from the PHY 579 * @HAL_RXDMA_ERR_FCS: FCS check on the MPDU frame failed 580 * @HAL_RXDMA_ERR_DECRYPT: Decryption error 581 * @HAL_RXDMA_ERR_TKIP_MIC: TKIP MIC error 582 * @HAL_RXDMA_ERR_UNENCRYPTED: Received a frame that was expected to be 583 * encrypted but wasn’t 584 * @HAL_RXDMA_ERR_MSDU_LEN: MSDU related length error 585 * @HAL_RXDMA_ERR_MSDU_LIMIT: Number of MSDUs in the MPDUs exceeded 586 * the max allowed 587 * @HAL_RXDMA_ERR_WIFI_PARSE: wifi parsing error 588 * @HAL_RXDMA_ERR_AMSDU_PARSE: Amsdu parsing error 589 * @HAL_RXDMA_ERR_SA_TIMEOUT: Source Address search timeout 590 * @HAL_RXDMA_ERR_DA_TIMEOUT: Destination Address search timeout 591 * @HAL_RXDMA_ERR_FLOW_TIMEOUT: Flow Search Timeout 592 * @HAL_RXDMA_ERR_FLUSH_REQUEST: RxDMA FIFO Flush request 593 * @HAL_RXDMA_AMSDU_FRAGMENT: Rx PCU reported A-MSDU 594 * present as well as a fragmented MPDU 595 * @HAL_RXDMA_MULTICAST_ECHO: RX OLE reported a multicast echo 596 * @HAL_RXDMA_AMSDU_ADDR_MISMATCH: RX OLE reported AMSDU address mismatch 597 * @HAL_RXDMA_UNAUTHORIZED_WDS: RX PCU reported unauthorized wds 598 * @HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS: RX PCU reported group cast AMSDU or WDS 599 * @HAL_RXDMA_ERR_WAR: RxDMA WAR dummy errors 600 * @HAL_RXDMA_ERR_MAX: count of number of enumerators 601 */ 602 enum hal_rxdma_error_code { 603 HAL_RXDMA_ERR_OVERFLOW = 0, 604 HAL_RXDMA_ERR_MPDU_LENGTH, 605 HAL_RXDMA_ERR_FCS, 606 HAL_RXDMA_ERR_DECRYPT, 607 HAL_RXDMA_ERR_TKIP_MIC, 608 HAL_RXDMA_ERR_UNENCRYPTED, 609 HAL_RXDMA_ERR_MSDU_LEN, 610 HAL_RXDMA_ERR_MSDU_LIMIT, 611 HAL_RXDMA_ERR_WIFI_PARSE, 612 HAL_RXDMA_ERR_AMSDU_PARSE, 613 HAL_RXDMA_ERR_SA_TIMEOUT, 614 HAL_RXDMA_ERR_DA_TIMEOUT, 615 HAL_RXDMA_ERR_FLOW_TIMEOUT, 616 HAL_RXDMA_ERR_FLUSH_REQUEST, 617 HAL_RXDMA_AMSDU_FRAGMENT, 618 HAL_RXDMA_MULTICAST_ECHO, 619 HAL_RXDMA_AMSDU_ADDR_MISMATCH, 620 HAL_RXDMA_UNAUTHORIZED_WDS, 621 HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS, 622 HAL_RXDMA_ERR_WAR = 31, 623 HAL_RXDMA_ERR_MAX 624 }; 625 626 /* 627 * HW BM action settings in WBM release ring 628 */ 629 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 630 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 631 632 /** 633 * enum hal_rx_wbm_error_source - Indicates which module initiated the 634 * release of this buffer or descriptor 635 * 636 * @HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 637 * @HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 638 * @HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 639 * @HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 640 * @HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 641 */ 642 enum hal_rx_wbm_error_source { 643 HAL_RX_WBM_ERR_SRC_TQM = 0, 644 HAL_RX_WBM_ERR_SRC_RXDMA, 645 HAL_RX_WBM_ERR_SRC_REO, 646 HAL_RX_WBM_ERR_SRC_FW, 647 HAL_RX_WBM_ERR_SRC_SW, 648 }; 649 650 /** 651 * enum hal_rx_wbm_buf_type - Indicates that type of buffer or descriptor 652 * released 653 * 654 * @HAL_RX_WBM_BUF_TYPE_REL_BUF: 655 * @HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC: 656 * @HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC: 657 * @HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC: 658 * @HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC: 659 */ 660 enum hal_rx_wbm_buf_type { 661 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 662 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 663 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 664 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 665 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 666 }; 667 668 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 669 670 /** 671 * hal_rx_msdu_is_wlan_mcast() - Check if the buffer is for multicast address 672 * @hal_soc_hdl: hal soc handle 673 * @nbuf: Network buffer 674 * 675 * Return: flag to indicate whether the nbuf has MC/BC address 676 */ 677 static inline uint32_t 678 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 679 qdf_nbuf_t nbuf) 680 { 681 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 682 683 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 684 } 685 686 /** 687 * hal_rx_priv_info_set_in_tlv() - Save the private info to 688 * the reserved bytes of rx_tlv_hdr 689 * @hal_soc_hdl: hal soc handle 690 * @buf: start of rx_tlv_hdr 691 * @priv_data: private info to store 692 * @len: length of @priv_data 693 * 694 * Return: void 695 */ 696 static inline void 697 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 698 uint8_t *buf, uint8_t *priv_data, 699 uint32_t len) 700 { 701 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 702 703 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 704 priv_data, 705 len); 706 } 707 708 /** 709 * hal_rx_reo_ent_rxdma_push_reason_get() - Retrieves RXDMA push reason from 710 * reo_entrance_ring descriptor 711 * 712 * @reo_ent_desc: reo_entrance_ring descriptor 713 * 714 * Return: value of rxdma_push_reason 715 */ 716 static inline 717 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 718 { 719 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 720 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 721 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 722 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 723 } 724 725 /** 726 * hal_rx_reo_ent_rxdma_error_code_get() - Retrieves RXDMA error code from 727 * reo_entrance_ring descriptor 728 * @reo_ent_desc: reo_entrance_ring descriptor 729 * 730 * Return: value of rxdma_error_code 731 */ 732 static inline 733 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 734 { 735 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 736 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 737 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 738 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 739 } 740 741 /** 742 * hal_rx_priv_info_get_from_tlv() - retrieve the private data from 743 * the reserved bytes of rx_tlv_hdr. 744 * @hal_soc_hdl: hal soc handle 745 * @buf: start of rx_tlv_hdr 746 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 747 * @len: length of the buffer 748 * 749 * Return: void 750 */ 751 static inline void 752 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 753 uint8_t *buf, uint8_t *wbm_er_info, 754 uint32_t len) 755 { 756 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 757 758 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 759 wbm_er_info, 760 len); 761 } 762 763 static inline void 764 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 765 uint16_t *rx_mon_pkt_tlv_size) 766 { 767 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 768 769 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 770 rx_mon_pkt_tlv_size); 771 } 772 773 /** 774 * hal_rx_encryption_info_valid() - Returns encryption type. 775 * @hal_soc_hdl: hal soc handle 776 * @buf: rx_tlv_hdr of the received packet 777 * 778 * Return: encryption type 779 */ 780 static inline uint32_t 781 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 782 { 783 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 784 785 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 786 } 787 788 /** 789 * hal_rx_print_pn() - Prints the PN of rx packet. 790 * @hal_soc_hdl: hal soc handle 791 * @buf: rx_tlv_hdr of the received packet 792 * 793 * Return: void 794 */ 795 static inline void 796 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 797 { 798 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 799 800 hal_soc->ops->hal_rx_print_pn(buf); 801 } 802 803 /** 804 * hal_rx_msdu_end_l3_hdr_padding_get() - API to get the 805 * l3_header padding from rx_msdu_end TLV 806 * @hal_soc_hdl: hal_soc handle 807 * @buf: pointer to the start of RX PKT TLV headers 808 * 809 * Return: number of l3 header padding bytes 810 */ 811 static inline uint32_t 812 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 813 uint8_t *buf) 814 { 815 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 816 817 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 818 } 819 820 /** 821 * hal_rx_msdu_end_sa_idx_get() - API to get the sa_idx from rx_msdu_end TLV 822 * @hal_soc_hdl: hal_soc handle 823 * @buf: pointer to the start of RX PKT TLV headers 824 * 825 * Return: sa_idx (SA AST index) 826 */ 827 static inline uint16_t 828 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 829 uint8_t *buf) 830 { 831 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 832 833 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 834 } 835 836 /** 837 * hal_rx_msdu_end_sa_is_valid_get() - API to get the 838 * sa_is_valid bit from rx_msdu_end TLV 839 * @hal_soc_hdl: hal_soc handle 840 * @buf: pointer to the start of RX PKT TLV headers 841 * 842 * Return: sa_is_valid bit 843 */ 844 static inline uint8_t 845 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 846 uint8_t *buf) 847 { 848 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 849 850 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 851 } 852 853 /** 854 * hal_rx_tlv_msdu_len_set() - API to set the MSDU length from rx_msdu_start TLV 855 * @hal_soc_hdl: hal_soc handle 856 * @buf: pointer to the start of RX PKT TLV headers 857 * @len: msdu length 858 * 859 * Return: none 860 */ 861 static inline void 862 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 863 uint32_t len) 864 { 865 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 866 867 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 868 } 869 870 /** 871 * enum hal_rx_mpdu_info_sw_frame_group_id_type - Enum for group id in MPDU_INFO 872 * 873 * @HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 874 * @HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 875 * @HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 876 * @HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 877 * @HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 878 * @HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 879 * @HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON: beacon frame 880 * @HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 881 * @HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 882 * @HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 883 * @HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 884 * @HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 885 * @HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 886 */ 887 enum hal_rx_mpdu_info_sw_frame_group_id_type { 888 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 889 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 890 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 891 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 892 HAL_MPDU_SW_FRAME_GROUP_MGMT, 893 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 894 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 895 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 896 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 897 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 898 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 899 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 900 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 901 }; 902 903 /** 904 * hal_rx_mpdu_start_mpdu_qos_control_valid_get() - 905 * Retrieve qos control valid bit from the tlv. 906 * @hal_soc_hdl: hal_soc handle 907 * @buf: pointer to rx pkt TLV. 908 * 909 * Return: qos control value. 910 */ 911 static inline uint32_t 912 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 913 hal_soc_handle_t hal_soc_hdl, 914 uint8_t *buf) 915 { 916 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 917 918 if ((!hal_soc) || (!hal_soc->ops)) { 919 hal_err("hal handle is NULL"); 920 QDF_BUG(0); 921 return QDF_STATUS_E_INVAL; 922 } 923 924 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 925 return hal_soc->ops-> 926 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 927 928 return QDF_STATUS_E_INVAL; 929 } 930 931 /** 932 * hal_rx_is_unicast() - check packet is unicast frame or not. 933 * @hal_soc_hdl: hal_soc handle 934 * @buf: pointer to rx pkt TLV. 935 * 936 * Return: true on unicast. 937 */ 938 static inline bool 939 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 940 { 941 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 942 943 return hal_soc->ops->hal_rx_is_unicast(buf); 944 } 945 946 /** 947 * hal_rx_tid_get() - get tid based on qos control valid. 948 * @hal_soc_hdl: hal soc handle 949 * @buf: pointer to rx pkt TLV. 950 * 951 * Return: tid 952 */ 953 static inline uint32_t 954 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 955 { 956 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 957 958 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 959 } 960 961 /** 962 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 963 * @hal_soc_hdl: hal soc handle 964 * @buf: pointer to rx pkt TLV. 965 * 966 * Return: sw peer_id 967 */ 968 static inline uint32_t 969 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 970 uint8_t *buf) 971 { 972 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 973 974 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 975 } 976 977 /** 978 * hal_rx_tlv_peer_meta_data_get() - Retrieve PEER_META_DATA 979 * @hal_soc_hdl: hal soc handle 980 * @buf: pointer to rx pkt TLV. 981 * 982 * Return: peer meta data 983 */ 984 static inline uint32_t 985 hal_rx_tlv_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl, 986 uint8_t *buf) 987 { 988 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 989 990 return hal_soc->ops->hal_rx_tlv_peer_meta_data_get(buf); 991 } 992 993 /** 994 * hal_rx_mpdu_get_to_ds() - API to get the tods info from rx_mpdu_start 995 * @hal_soc_hdl: hal_soc handle 996 * @buf: pointer to the start of RX PKT TLV header 997 * 998 * Return: uint32_t(to_ds) 999 */ 1000 1001 static inline uint32_t 1002 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1003 { 1004 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1005 1006 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1007 } 1008 1009 1010 /** 1011 * hal_rx_mpdu_get_fr_ds() - API to get the from ds info 1012 * from rx_mpdu_start 1013 * @hal_soc_hdl: hal soc handle 1014 * @buf: pointer to the start of RX PKT TLV header 1015 * 1016 * Return: uint32_t(fr_ds) 1017 */ 1018 static inline uint32_t 1019 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1020 { 1021 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1022 1023 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1024 } 1025 1026 /** 1027 * hal_rx_mpdu_get_addr1() - API to check get address1 of the mpdu 1028 * @hal_soc_hdl: hal soc handle 1029 * @buf: pointer to the start of RX PKT TLV headera 1030 * @mac_addr: pointer to mac address 1031 * 1032 * Return: success/failure 1033 */ 1034 static inline 1035 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1036 uint8_t *buf, uint8_t *mac_addr) 1037 { 1038 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1039 1040 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1041 } 1042 1043 /** 1044 * hal_rx_mpdu_get_addr2() - API to check get address2 of the mpdu 1045 * in the packet 1046 * @hal_soc_hdl: hal soc handle 1047 * @buf: pointer to the start of RX PKT TLV header 1048 * @mac_addr: pointer to mac address 1049 * 1050 * Return: success/failure 1051 */ 1052 static inline 1053 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1054 uint8_t *buf, uint8_t *mac_addr) 1055 { 1056 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1057 1058 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1059 } 1060 1061 /** 1062 * hal_rx_mpdu_get_addr3() - API to get address3 of the mpdu 1063 * in the packet 1064 * @hal_soc_hdl: hal soc handle 1065 * @buf: pointer to the start of RX PKT TLV header 1066 * @mac_addr: pointer to mac address 1067 * 1068 * Return: success/failure 1069 */ 1070 static inline 1071 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1072 uint8_t *buf, uint8_t *mac_addr) 1073 { 1074 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1075 1076 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1077 } 1078 1079 /** 1080 * hal_rx_mpdu_get_addr4() - API to get address4 of the mpdu 1081 * in the packet 1082 * @hal_soc_hdl: hal_soc handle 1083 * @buf: pointer to the start of RX PKT TLV header 1084 * @mac_addr: pointer to mac address 1085 * Return: success/failure 1086 */ 1087 static inline 1088 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1089 uint8_t *buf, uint8_t *mac_addr) 1090 { 1091 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1092 1093 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1094 } 1095 1096 /** 1097 * hal_rx_msdu_end_da_idx_get() - API to get da_idx from rx_msdu_end TLV 1098 * @hal_soc_hdl: hal_soc handle 1099 * @buf: pointer to the start of RX PKT TLV headers 1100 * 1101 * Return: da index 1102 */ 1103 static inline uint16_t 1104 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1105 { 1106 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1107 1108 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1109 } 1110 1111 /** 1112 * hal_rx_msdu_end_da_is_valid_get() - API to check if da is valid 1113 * from rx_msdu_end TLV 1114 * @hal_soc_hdl: hal soc handle 1115 * @buf: pointer to the start of RX PKT TLV headers 1116 * 1117 * Return: da_is_valid 1118 */ 1119 static inline uint8_t 1120 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1121 uint8_t *buf) 1122 { 1123 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1124 1125 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1126 } 1127 1128 /** 1129 * hal_rx_msdu_end_da_is_mcbc_get() - API to check if pkt is MCBC 1130 * from rx_msdu_end TLV 1131 * @hal_soc_hdl: HAL SOC handle 1132 * @buf: pointer to the start of RX PKT TLV headers 1133 * 1134 * Return: da_is_mcbc 1135 */ 1136 static inline uint8_t 1137 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1138 { 1139 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1140 1141 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1142 } 1143 1144 /** 1145 * hal_rx_msdu_end_is_tkip_mic_err() - API to check if pkt has mic error 1146 * from rx_msdu_end TLV 1147 * @hal_soc_hdl: HAL SOC handle 1148 * @buf: pointer to the start of RX PKT TLV headers 1149 * 1150 * Return: tkip_mic_err 1151 */ 1152 static inline uint8_t 1153 hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl, 1154 uint8_t *buf) 1155 { 1156 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1157 1158 if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err) 1159 return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf); 1160 else 1161 return 0; 1162 } 1163 1164 /** 1165 * hal_rx_msdu_end_first_msdu_get() - API to get first msdu status 1166 * from rx_msdu_end TLV 1167 * @hal_soc_hdl: hal soc handle 1168 * @buf: pointer to the start of RX PKT TLV headers 1169 * 1170 * Return: first_msdu 1171 */ 1172 static inline uint8_t 1173 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1174 uint8_t *buf) 1175 { 1176 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1177 1178 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1179 } 1180 1181 /** 1182 * hal_rx_msdu_end_last_msdu_get() - API to get last msdu status 1183 * from rx_msdu_end TLV 1184 * @hal_soc_hdl: hal soc handle 1185 * @buf: pointer to the start of RX PKT TLV headers 1186 * 1187 * Return: last_msdu 1188 */ 1189 static inline uint8_t 1190 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1191 uint8_t *buf) 1192 { 1193 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1194 1195 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1196 } 1197 1198 /** 1199 * hal_rx_msdu_cce_match_get() - API to get CCE match from rx_msdu_end TLV 1200 * @hal_soc_hdl: HAL SOC handle 1201 * @buf: pointer to the start of RX PKT TLV headers 1202 * 1203 * Return: cce_meta_data 1204 */ 1205 static inline bool 1206 hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl, 1207 uint8_t *buf) 1208 { 1209 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1210 1211 return hal_soc->ops->hal_rx_msdu_cce_match_get(buf); 1212 } 1213 1214 /** 1215 * hal_rx_msdu_cce_metadata_get() - API to get CCE metadata 1216 * from rx_msdu_end TLV 1217 * @hal_soc_hdl: HAL SOC handle 1218 * @buf: pointer to the start of RX PKT TLV headers 1219 * 1220 * Return: cce_meta_data 1221 */ 1222 static inline uint16_t 1223 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1224 uint8_t *buf) 1225 { 1226 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1227 1228 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1229 } 1230 1231 /******************************************************************************* 1232 * RX REO ERROR APIS 1233 ******************************************************************************/ 1234 1235 /** 1236 * hal_rx_link_desc_msdu0_ptr() - Get pointer to rx_msdu details 1237 * @msdu_link_ptr: msdu link ptr 1238 * @hal_soc: pointer to hal_soc 1239 * 1240 * Return: Pointer to rx_msdu_details structure 1241 * 1242 */ 1243 static inline 1244 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1245 struct hal_soc *hal_soc) 1246 { 1247 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1248 } 1249 1250 /** 1251 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1252 * @msdu_details_ptr: Pointer to msdu_details_ptr 1253 * @hal_soc: pointer to hal_soc 1254 * 1255 * Return: Pointer to rx_msdu_desc_info structure. 1256 * 1257 */ 1258 static inline 1259 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1260 struct hal_soc *hal_soc) 1261 { 1262 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1263 } 1264 1265 /** 1266 * hal_rx_reo_buf_paddr_get() - Gets the physical address and 1267 * cookie from the REO destination ring element 1268 * @hal_soc_hdl: HAL SOC handle 1269 * @rx_desc: the current descriptor 1270 * @buf_info: structure to return the buffer information 1271 * 1272 * Return: void 1273 */ 1274 static inline 1275 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1276 hal_ring_desc_t rx_desc, 1277 struct hal_buf_info *buf_info) 1278 { 1279 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1280 1281 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1282 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1283 rx_desc, 1284 buf_info); 1285 1286 } 1287 1288 /** 1289 * hal_rx_wbm_rel_buf_paddr_get() - Gets the physical address and 1290 * cookie from the WBM release ring element 1291 * @hal_soc_hdl: HAL SOC handle 1292 * @rx_desc: the current descriptor 1293 * @buf_info: structure to return the buffer information 1294 * 1295 * Return: void 1296 */ 1297 static inline 1298 void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1299 hal_ring_desc_t rx_desc, 1300 struct hal_buf_info *buf_info) 1301 { 1302 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1303 1304 if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get) 1305 return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc, 1306 buf_info); 1307 } 1308 1309 /** 1310 * hal_rx_buf_cookie_rbm_get() - Gets the physical address and cookie 1311 * from the REO entrance ring element 1312 * @hal_soc_hdl: hal soc handle 1313 * @buf_addr_info: pointer to buf_addr_info structure 1314 * @buf_info: structure to return the buffer information 1315 * 1316 * Return: void 1317 */ 1318 static inline 1319 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1320 uint32_t *buf_addr_info, 1321 struct hal_buf_info *buf_info) 1322 { 1323 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1324 1325 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1326 buf_addr_info, 1327 buf_info); 1328 } 1329 1330 /** 1331 * hal_rx_msdu_list_get() - API to get the MSDU information 1332 * from the MSDU link descriptor 1333 * @hal_soc_hdl: hal soc handle 1334 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1335 * MSDU link descriptor (struct rx_msdu_link) 1336 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1337 * @num_msdus: Number of MSDUs in the MPDU 1338 * 1339 * Return: void 1340 */ 1341 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1342 void *msdu_link_desc, 1343 struct hal_rx_msdu_list *msdu_list, 1344 uint16_t *num_msdus) 1345 { 1346 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1347 struct rx_msdu_details *msdu_details; 1348 struct rx_msdu_desc_info *msdu_desc_info; 1349 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1350 int i; 1351 struct hal_buf_info buf_info; 1352 1353 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1354 1355 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1356 __func__, __LINE__, msdu_link, msdu_details); 1357 1358 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1359 /* num_msdus received in mpdu descriptor may be incorrect 1360 * sometimes due to HW issue. Check msdu buffer address also 1361 */ 1362 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1363 &msdu_details[i].buffer_addr_info_details) == 0)) 1364 break; 1365 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1366 &msdu_details[i].buffer_addr_info_details) == 0) { 1367 /* set the last msdu bit in the prev msdu_desc_info */ 1368 msdu_desc_info = 1369 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1370 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1371 break; 1372 } 1373 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1374 hal_soc); 1375 1376 /* set first MSDU bit or the last MSDU bit */ 1377 if (!i) 1378 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1379 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1380 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1381 1382 msdu_list->msdu_info[i].msdu_flags = 1383 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1384 msdu_list->msdu_info[i].msdu_len = 1385 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1386 1387 /* addr field in buf_info will not be valid */ 1388 hal_rx_buf_cookie_rbm_get( 1389 hal_soc_hdl, 1390 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1391 &buf_info); 1392 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1393 msdu_list->rbm[i] = buf_info.rbm; 1394 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1395 &msdu_details[i].buffer_addr_info_details) | 1396 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1397 &msdu_details[i].buffer_addr_info_details) << 32; 1398 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1399 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1400 } 1401 *num_msdus = i; 1402 } 1403 1404 /** 1405 * hal_rx_reo_is_pn_error() - Indicate if this error was caused by a 1406 * PN check failure 1407 * @error_code: error code obtained from ring descriptor. 1408 * 1409 * Return: true: error caused by PN check, false: other error 1410 */ 1411 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1412 { 1413 1414 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1415 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1416 true : false; 1417 } 1418 1419 /** 1420 * hal_rx_reo_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1421 * the sequence number 1422 * @error_code: error code obtained from ring descriptor. 1423 * 1424 * Return: true: error caused by 2K jump, false: other error 1425 */ 1426 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1427 { 1428 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1429 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1430 true : false; 1431 } 1432 1433 /** 1434 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1435 * @error_code: error code obtained from ring descriptor. 1436 * 1437 * Return: true: error caused by OOR, false: other error 1438 */ 1439 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1440 { 1441 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1442 true : false; 1443 } 1444 1445 /** 1446 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1447 * @error_code: error code obtained from ring descriptor. 1448 * 1449 * Return: true, if the error code is 2k-jump or OOR 1450 * false, for other error codes. 1451 */ 1452 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1453 { 1454 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1455 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1456 true : false; 1457 } 1458 1459 /** 1460 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1461 * @src_srng_desc: hardware descriptor pointer 1462 * 1463 * This function will print wbm release descriptor 1464 * 1465 * Return: none 1466 */ 1467 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1468 { 1469 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1470 uint32_t i; 1471 1472 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1473 "Current Rx wbm release descriptor is"); 1474 1475 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1476 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1477 "DWORD[i] = 0x%x", wbm_comp[i]); 1478 } 1479 } 1480 1481 /** 1482 * hal_rx_msdu_link_desc_set() - Retrieves MSDU Link Descriptor to WBM 1483 * 1484 * @hal_soc_hdl: HAL version of the SOC pointer 1485 * @src_srng_desc: void pointer to the WBM Release Ring descriptor 1486 * @buf_addr_info: void pointer to the buffer_addr_info 1487 * @bm_action: put in IDLE list or release to MSDU_LIST 1488 * 1489 * Return: void 1490 */ 1491 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1492 static inline 1493 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1494 void *src_srng_desc, 1495 hal_buff_addrinfo_t buf_addr_info, 1496 uint8_t bm_action) 1497 { 1498 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1499 1500 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1501 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1502 src_srng_desc, 1503 buf_addr_info, 1504 bm_action); 1505 } 1506 1507 /** 1508 * HAL_RX_BUF_ADDR_INFO_GET() - Returns the address of the 1509 * BUFFER_ADDR_INFO, give the RX descriptor 1510 * (Assumption -- BUFFER_ADDR_INFO is the 1511 * first field in the descriptor structure) 1512 * @ring_desc: RX descriptor 1513 * 1514 * Return: pointer to buffer addr info 1515 */ 1516 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1517 ((hal_link_desc_t)(ring_desc)) 1518 1519 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1520 1521 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1522 1523 /******************************************************************************* 1524 * RX WBM ERROR APIS 1525 ******************************************************************************/ 1526 1527 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1528 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1529 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1530 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1531 /** 1532 * enum hal_rx_wbm_reo_push_reason - Indicates why REO pushed 1533 * the frame to this release ring 1534 * 1535 * @HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1536 * frame to this queue 1537 * @HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1538 * received routing instructions. No error within REO was detected 1539 */ 1540 enum hal_rx_wbm_reo_push_reason { 1541 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1542 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1543 }; 1544 1545 1546 /** 1547 * enum hal_rx_wbm_rxdma_push_reason - Indicates why REO pushed the frame to 1548 * this release ring 1549 * 1550 * @HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1551 * this frame to this queue 1552 * @HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1553 * per received routing instructions. No error within RXDMA was detected 1554 * @HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH: 1555 */ 1556 enum hal_rx_wbm_rxdma_push_reason { 1557 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1558 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1559 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1560 }; 1561 1562 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 1563 uint8_t dbg_level, 1564 struct hal_soc *hal) 1565 { 1566 1567 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 1568 } 1569 1570 /** 1571 * hal_rx_dump_msdu_end_tlv() - dump RX msdu_end TLV in structured 1572 * human readable format. 1573 * @hal_soc: HAL soc 1574 * @msdu_end: pointer the msdu_end TLV in pkt. 1575 * @dbg_level: log level. 1576 * 1577 * Return: void 1578 */ 1579 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1580 struct rx_msdu_end *msdu_end, 1581 uint8_t dbg_level) 1582 { 1583 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 1584 } 1585 1586 /** 1587 * hal_srng_ring_id_get() - API to retrieve ring id from hal ring 1588 * structure 1589 * @hal_ring_hdl: handle to hal_srng structure 1590 * 1591 * Return: ring_id 1592 */ 1593 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1594 { 1595 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1596 } 1597 1598 #define DOT11_SEQ_FRAG_MASK 0x000f 1599 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1600 1601 /** 1602 * hal_rx_get_rx_fragment_number() - Function to retrieve rx fragment number 1603 * @hal_soc: HAL soc 1604 * @buf: Network buffer 1605 * 1606 * Return: rx fragment number 1607 */ 1608 static inline 1609 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1610 uint8_t *buf) 1611 { 1612 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1613 } 1614 1615 /** 1616 * hal_rx_get_mpdu_sequence_control_valid() - Get mpdu sequence control valid 1617 * @hal_soc_hdl: hal soc handle 1618 * @buf: Network buffer 1619 * 1620 * Return: value of sequence control valid field 1621 */ 1622 static inline 1623 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1624 uint8_t *buf) 1625 { 1626 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1627 1628 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1629 } 1630 1631 /** 1632 * hal_rx_get_mpdu_frame_control_valid() - Retrieves mpdu frame control valid 1633 * @hal_soc_hdl: hal soc handle 1634 * @buf: Network buffer 1635 * 1636 * Return: value of frame control valid field 1637 */ 1638 static inline 1639 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1640 uint8_t *buf) 1641 { 1642 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1643 1644 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1645 } 1646 1647 /** 1648 * hal_rx_get_mpdu_mac_ad4_valid() - Retrieves if mpdu 4th addr is valid 1649 * @hal_soc_hdl: hal soc handle 1650 * @buf: Network buffer 1651 * 1652 * Return: value of mpdu 4th address valid field 1653 */ 1654 static inline 1655 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1656 uint8_t *buf) 1657 { 1658 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1659 1660 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1661 } 1662 1663 /** 1664 * hal_rx_clear_mpdu_desc_info() - Clears mpdu_desc_info 1665 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1666 * 1667 * Return: None 1668 */ 1669 static inline void 1670 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1671 { 1672 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1673 } 1674 1675 /** 1676 * hal_rx_wbm_err_info_get() - Retrieves WBM error code and reason and 1677 * save it to hal_wbm_err_desc_info structure passed by caller 1678 * @wbm_desc: wbm ring descriptor 1679 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1680 * @hal_soc_hdl: HAL SOC handle 1681 * 1682 * Return: void 1683 */ 1684 static inline 1685 void hal_rx_wbm_err_info_get(void *wbm_desc, 1686 struct hal_wbm_err_desc_info *wbm_er_info, 1687 hal_soc_handle_t hal_soc_hdl) 1688 { 1689 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1690 1691 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1692 } 1693 1694 /** 1695 * hal_rx_wbm_err_msdu_continuation_get() - Get wbm msdu continuation 1696 * bit from wbm release ring descriptor 1697 * @hal_soc_hdl: HAL SOC handle 1698 * @wbm_desc: wbm ring descriptor 1699 * 1700 * Return: uint8_t 1701 */ 1702 static inline 1703 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1704 void *wbm_desc) 1705 { 1706 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1707 1708 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1709 } 1710 1711 /** 1712 * hal_rx_mon_hw_desc_get_mpdu_status() - Retrieve MPDU status 1713 * @hal_soc_hdl: HAL SOC handle 1714 * @hw_desc_addr: Start address of Rx HW TLVs 1715 * @rs: Status for monitor mode 1716 * 1717 * Return: void 1718 */ 1719 static inline 1720 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1721 void *hw_desc_addr, 1722 struct mon_rx_status *rs) 1723 { 1724 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1725 1726 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1727 } 1728 1729 /** 1730 * hal_rx_get_tlv() - API to get the tlv 1731 * 1732 * @hal_soc: HAL version of the SOC pointer 1733 * @rx_tlv: TLV data extracted from the rx packet 1734 * 1735 * Return: uint8_t 1736 */ 1737 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1738 { 1739 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1740 } 1741 1742 /** 1743 * hal_rx_msdu_start_nss_get() - API to get the NSS 1744 * Interval from rx_msdu_start 1745 * @hal_soc_hdl: HAL SOC handle 1746 * @buf: pointer to the start of RX PKT TLV header 1747 * 1748 * Return: uint32_t(nss) 1749 */ 1750 static inline 1751 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1752 { 1753 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1754 1755 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1756 } 1757 1758 /** 1759 * hal_rx_dump_msdu_start_tlv() - dump RX msdu_start TLV in structured 1760 * human readable format. 1761 * @hal_soc: HAL SOC 1762 * @msdu_start: pointer the msdu_start TLV in pkt. 1763 * @dbg_level: log level. 1764 * 1765 * Return: void 1766 */ 1767 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1768 struct rx_msdu_start *msdu_start, 1769 uint8_t dbg_level) 1770 { 1771 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 1772 } 1773 1774 /** 1775 * hal_rx_mpdu_start_tid_get() - Return tid info from the rx mpdu start 1776 * info details 1777 * @hal_soc_hdl: HAL SOC handle 1778 * @buf: Pointer to buffer containing rx pkt tlvs. 1779 * 1780 * 1781 */ 1782 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1783 uint8_t *buf) 1784 { 1785 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1786 1787 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1788 } 1789 1790 /** 1791 * hal_rx_msdu_start_reception_type_get() - API to get the reception type 1792 * Interval from rx_msdu_start 1793 * @hal_soc_hdl: hal_soc handle 1794 * @buf: pointer to the start of RX PKT TLV header 1795 * 1796 * Return: uint32_t(reception_type) 1797 */ 1798 static inline 1799 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1800 uint8_t *buf) 1801 { 1802 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1803 1804 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1805 } 1806 1807 /** 1808 * hal_reo_status_get_header() - Process reo desc info 1809 * @ring_desc: Pointer to reo descriptor 1810 * @b: tlv type info 1811 * @h: Pointer to hal_reo_status_header where info to be stored 1812 * @hal_soc: pointer to hal_soc structure 1813 * 1814 * Return: none. 1815 * 1816 */ 1817 static inline 1818 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1819 void *h, struct hal_soc *hal_soc) 1820 { 1821 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1822 } 1823 1824 /** 1825 * hal_rx_desc_is_first_msdu() - Check if first msdu 1826 * 1827 * @hal_soc_hdl: hal_soc handle 1828 * @hw_desc_addr: hardware descriptor address 1829 * 1830 * Return: 0 - success/ non-zero failure 1831 */ 1832 static inline 1833 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1834 void *hw_desc_addr) 1835 { 1836 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1837 1838 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1839 } 1840 1841 /** 1842 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1843 * the rx tlv fields. 1844 * @hal_soc_hdl: HAL SoC handle 1845 * @buf: rx tlv start address [To be validated by caller] 1846 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1847 * 1848 * Return: None 1849 */ 1850 static inline void 1851 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1852 uint8_t *buf, 1853 void *mpdu_desc_info_hdl) 1854 { 1855 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1856 1857 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1858 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1859 mpdu_desc_info_hdl); 1860 } 1861 1862 static inline uint32_t 1863 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1864 { 1865 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1866 1867 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1868 } 1869 1870 static inline 1871 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1872 uint8_t *rx_tlv_hdr) 1873 { 1874 uint8_t decap_format; 1875 1876 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1877 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1878 rx_tlv_hdr); 1879 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1880 return true; 1881 } 1882 1883 return false; 1884 } 1885 1886 /** 1887 * hal_rx_msdu_fse_metadata_get() - API to get FSE metadata 1888 * from rx_msdu_end TLV 1889 * @hal_soc_hdl: HAL SOC handle 1890 * @buf: pointer to the start of RX PKT TLV headers 1891 * 1892 * Return: fse metadata value from MSDU END TLV 1893 */ 1894 static inline uint32_t 1895 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1896 uint8_t *buf) 1897 { 1898 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1899 1900 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1901 } 1902 1903 /** 1904 * hal_rx_buffer_addr_info_get_paddr() - get paddr/sw_cookie from 1905 * <struct buffer_addr_info> structure 1906 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1907 * @buf_info: structure to return the buffer information including 1908 * paddr/cookie 1909 * 1910 * Return: None 1911 */ 1912 static inline 1913 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 1914 struct hal_buf_info *buf_info) 1915 { 1916 buf_info->paddr = 1917 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 1918 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 1919 } 1920 1921 /** 1922 * hal_rx_msdu_flow_idx_get() - API to get flow index from rx_msdu_end TLV 1923 * @hal_soc_hdl: HAL SOC handle 1924 * @buf: pointer to the start of RX PKT TLV headers 1925 * 1926 * Return: flow index value from MSDU END TLV 1927 */ 1928 static inline uint32_t 1929 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 1930 uint8_t *buf) 1931 { 1932 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1933 1934 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 1935 } 1936 1937 /** 1938 * hal_rx_msdu_get_reo_destination_indication() - API to get reo 1939 * destination index from rx_msdu_end TLV 1940 * @hal_soc_hdl: HAL SOC handle 1941 * @buf: pointer to the start of RX PKT TLV headers 1942 * @reo_destination_indication: pointer to return value of 1943 * reo_destination_indication 1944 * 1945 * Return: reo_destination_indication value from MSDU END TLV 1946 */ 1947 static inline void 1948 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 1949 uint8_t *buf, 1950 uint32_t *reo_destination_indication) 1951 { 1952 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1953 1954 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 1955 reo_destination_indication); 1956 } 1957 1958 /** 1959 * hal_rx_msdu_flow_idx_timeout() - API to get flow index timeout 1960 * from rx_msdu_end TLV 1961 * @hal_soc_hdl: HAL SOC handle 1962 * @buf: pointer to the start of RX PKT TLV headers 1963 * 1964 * Return: flow index timeout value from MSDU END TLV 1965 */ 1966 static inline bool 1967 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 1968 uint8_t *buf) 1969 { 1970 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1971 1972 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 1973 } 1974 1975 /** 1976 * hal_rx_msdu_flow_idx_invalid() - API to get flow index invalid 1977 * from rx_msdu_end TLV 1978 * @hal_soc_hdl: HAL SOC handle 1979 * @buf: pointer to the start of RX PKT TLV headers 1980 * 1981 * Return: flow index invalid value from MSDU END TLV 1982 */ 1983 static inline bool 1984 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 1985 uint8_t *buf) 1986 { 1987 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1988 1989 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 1990 } 1991 1992 /** 1993 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 1994 * @hal_soc_hdl: hal_soc handle 1995 * @rx_tlv_hdr: Rx_tlv_hdr 1996 * @rxdma_dst_ring_desc: Rx HW descriptor 1997 * 1998 * Return: ppdu id 1999 */ 2000 static inline 2001 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 2002 void *rx_tlv_hdr, 2003 void *rxdma_dst_ring_desc) 2004 { 2005 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2006 2007 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 2008 rxdma_dst_ring_desc); 2009 } 2010 2011 /** 2012 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 2013 * @hal_soc_hdl: hal_soc handle 2014 * @buf: rx tlv address 2015 * 2016 * Return: sw peer id 2017 */ 2018 static inline 2019 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 2020 uint8_t *buf) 2021 { 2022 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2023 2024 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 2025 } 2026 2027 static inline 2028 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 2029 void *link_desc_addr) 2030 { 2031 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2032 2033 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 2034 } 2035 2036 static inline 2037 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 2038 void *msdu_addr) 2039 { 2040 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2041 2042 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 2043 } 2044 2045 static inline 2046 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2047 void *hw_addr) 2048 { 2049 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2050 2051 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 2052 } 2053 2054 static inline 2055 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2056 void *hw_addr) 2057 { 2058 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2059 2060 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 2061 } 2062 2063 static inline 2064 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 2065 uint8_t *buf) 2066 { 2067 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2068 2069 return hal_soc->ops->hal_rx_get_fc_valid(buf); 2070 } 2071 2072 static inline 2073 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2074 { 2075 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2076 2077 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 2078 } 2079 2080 static inline 2081 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 2082 uint8_t *buf) 2083 { 2084 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2085 2086 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 2087 } 2088 2089 static inline 2090 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 2091 uint8_t *buf) 2092 { 2093 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2094 2095 return hal_soc->ops->hal_rx_get_filter_category(buf); 2096 } 2097 2098 static inline 2099 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 2100 uint8_t *buf) 2101 { 2102 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2103 2104 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 2105 } 2106 2107 /** 2108 * hal_reo_config() - Set reo config parameters 2109 * @hal_soc: hal soc handle 2110 * @reg_val: value to be set 2111 * @reo_params: reo parameters 2112 * 2113 * Return: void 2114 */ 2115 static inline 2116 void hal_reo_config(struct hal_soc *hal_soc, 2117 uint32_t reg_val, 2118 struct hal_reo_params *reo_params) 2119 { 2120 hal_soc->ops->hal_reo_config(hal_soc, 2121 reg_val, 2122 reo_params); 2123 } 2124 2125 /** 2126 * hal_rx_msdu_get_flow_params() - API to get flow index, 2127 * flow index invalid and flow index timeout from rx_msdu_end TLV 2128 * @hal_soc_hdl: HAL SOC handle 2129 * @buf: pointer to the start of RX PKT TLV headers 2130 * @flow_invalid: pointer to return value of flow_idx_valid 2131 * @flow_timeout: pointer to return value of flow_idx_timeout 2132 * @flow_index: pointer to return value of flow_idx 2133 * 2134 * Return: none 2135 */ 2136 static inline void 2137 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2138 uint8_t *buf, 2139 bool *flow_invalid, 2140 bool *flow_timeout, 2141 uint32_t *flow_index) 2142 { 2143 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2144 2145 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2146 flow_invalid, 2147 flow_timeout, 2148 flow_index); 2149 } 2150 2151 static inline 2152 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2153 uint8_t *buf) 2154 { 2155 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2156 2157 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2158 } 2159 2160 static inline 2161 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2162 uint8_t *buf) 2163 { 2164 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2165 2166 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2167 } 2168 2169 static inline void 2170 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2171 void *rx_tlv, 2172 void *ppdu_info) 2173 { 2174 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2175 2176 if (hal_soc->ops->hal_rx_get_bb_info) 2177 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2178 } 2179 2180 static inline void 2181 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2182 void *rx_tlv, 2183 void *ppdu_info) 2184 { 2185 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2186 2187 if (hal_soc->ops->hal_rx_get_rtt_info) 2188 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2189 } 2190 2191 /** 2192 * hal_rx_msdu_metadata_get() - API to get the 2193 * fast path information from rx_msdu_end TLV 2194 * 2195 * @hal_soc_hdl: DP soc handle 2196 * @buf: pointer to the start of RX PKT TLV headers 2197 * @msdu_md: Structure to hold msdu end information 2198 * Return: none 2199 */ 2200 static inline void 2201 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2202 struct hal_rx_msdu_metadata *msdu_md) 2203 { 2204 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2205 2206 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2207 } 2208 2209 /** 2210 * hal_rx_get_fisa_cumulative_l4_checksum() - API to get cumulative_l4_checksum 2211 * from rx_msdu_end TLV 2212 * @hal_soc_hdl: HAL SOC handle 2213 * @buf: pointer to the start of RX PKT TLV headers 2214 * 2215 * Return: cumulative_l4_checksum 2216 */ 2217 static inline uint16_t 2218 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2219 uint8_t *buf) 2220 { 2221 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2222 2223 if (!hal_soc || !hal_soc->ops) { 2224 hal_err("hal handle is NULL"); 2225 QDF_BUG(0); 2226 return 0; 2227 } 2228 2229 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2230 return 0; 2231 2232 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2233 } 2234 2235 /** 2236 * hal_rx_get_fisa_cumulative_ip_length() - API to get cumulative_ip_length 2237 * from rx_msdu_end TLV 2238 * @hal_soc_hdl: HAL SOC handle 2239 * @buf: pointer to the start of RX PKT TLV headers 2240 * 2241 * Return: cumulative_ip_length 2242 */ 2243 static inline uint16_t 2244 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2245 uint8_t *buf) 2246 { 2247 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2248 2249 if (!hal_soc || !hal_soc->ops) { 2250 hal_err("hal handle is NULL"); 2251 QDF_BUG(0); 2252 return 0; 2253 } 2254 2255 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2256 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2257 2258 return 0; 2259 } 2260 2261 /** 2262 * hal_rx_get_udp_proto() - API to get UDP proto field 2263 * from rx_msdu_start TLV 2264 * @hal_soc_hdl: HAL SOC handle 2265 * @buf: pointer to the start of RX PKT TLV headers 2266 * 2267 * Return: UDP proto field value 2268 */ 2269 static inline bool 2270 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2271 { 2272 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2273 2274 if (!hal_soc || !hal_soc->ops) { 2275 hal_err("hal handle is NULL"); 2276 QDF_BUG(0); 2277 return 0; 2278 } 2279 2280 if (hal_soc->ops->hal_rx_get_udp_proto) 2281 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2282 2283 return 0; 2284 } 2285 2286 /** 2287 * hal_rx_get_fisa_flow_agg_continuation() - API to get fisa 2288 * flow_agg_continuation from rx_msdu_end TLV 2289 * @hal_soc_hdl: HAL SOC handle 2290 * @buf: pointer to the start of RX PKT TLV headers 2291 * 2292 * Return: flow_agg_continuation bit field value 2293 */ 2294 static inline bool 2295 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2296 uint8_t *buf) 2297 { 2298 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2299 2300 if (!hal_soc || !hal_soc->ops) { 2301 hal_err("hal handle is NULL"); 2302 QDF_BUG(0); 2303 return 0; 2304 } 2305 2306 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2307 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2308 2309 return 0; 2310 } 2311 2312 /** 2313 * hal_rx_get_fisa_flow_agg_count() - API to get fisa flow_agg count from 2314 * rx_msdu_end TLV 2315 * @hal_soc_hdl: HAL SOC handle 2316 * @buf: pointer to the start of RX PKT TLV headers 2317 * 2318 * Return: flow_agg count value 2319 */ 2320 static inline uint8_t 2321 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2322 uint8_t *buf) 2323 { 2324 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2325 2326 if (!hal_soc || !hal_soc->ops) { 2327 hal_err("hal handle is NULL"); 2328 QDF_BUG(0); 2329 return 0; 2330 } 2331 2332 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2333 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2334 2335 return 0; 2336 } 2337 2338 /** 2339 * hal_rx_get_fisa_timeout() - API to get fisa time out from rx_msdu_end TLV 2340 * @hal_soc_hdl: HAL SOC handle 2341 * @buf: pointer to the start of RX PKT TLV headers 2342 * 2343 * Return: fisa flow_agg timeout bit value 2344 */ 2345 static inline bool 2346 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2347 { 2348 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2349 2350 if (!hal_soc || !hal_soc->ops) { 2351 hal_err("hal handle is NULL"); 2352 QDF_BUG(0); 2353 return 0; 2354 } 2355 2356 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2357 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2358 2359 return 0; 2360 } 2361 2362 /** 2363 * hal_rx_mpdu_start_tlv_tag_valid() - API to check if RX_MPDU_START tlv 2364 * tag is valid 2365 * 2366 * @hal_soc_hdl: HAL SOC handle 2367 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2368 * 2369 * Return: true if RX_MPDU_START tlv tag is valid, else false 2370 */ 2371 2372 static inline uint8_t 2373 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2374 void *rx_tlv_hdr) 2375 { 2376 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2377 2378 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2379 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2380 2381 return 0; 2382 } 2383 2384 /** 2385 * hal_rx_get_next_msdu_link_desc_buf_addr_info() - get next msdu link desc 2386 * buffer addr info 2387 * @link_desc_va: pointer to current msdu link Desc 2388 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2389 * 2390 * return: None 2391 */ 2392 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2393 void *link_desc_va, 2394 struct buffer_addr_info *next_addr_info) 2395 { 2396 struct rx_msdu_link *msdu_link = link_desc_va; 2397 2398 if (!msdu_link) { 2399 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2400 return; 2401 } 2402 2403 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2404 } 2405 2406 /** 2407 * hal_rx_clear_next_msdu_link_desc_buf_addr_info() - clear next msdu link desc 2408 * buffer addr info 2409 * @link_desc_va: pointer to current msdu link Desc 2410 * 2411 * return: None 2412 */ 2413 static inline 2414 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2415 { 2416 struct rx_msdu_link *msdu_link = link_desc_va; 2417 2418 if (msdu_link) 2419 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2420 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2421 } 2422 2423 /** 2424 * hal_rx_is_buf_addr_info_valid() - check is the buf_addr_info valid 2425 * 2426 * @buf_addr_info: pointer to buf_addr_info structure 2427 * 2428 * return: true: has valid paddr, false: not. 2429 */ 2430 static inline 2431 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2432 { 2433 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2434 false : true; 2435 } 2436 2437 /** 2438 * hal_rx_msdu_end_offset_get() - Get the MSDU end offset from 2439 * rx_pkt_tlvs structure 2440 * 2441 * @hal_soc_hdl: HAL SOC handle 2442 * return: msdu_end_tlv offset value 2443 */ 2444 static inline 2445 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2446 { 2447 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2448 2449 if (!hal_soc || !hal_soc->ops) { 2450 hal_err("hal handle is NULL"); 2451 QDF_BUG(0); 2452 return 0; 2453 } 2454 2455 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2456 } 2457 2458 /** 2459 * hal_rx_msdu_start_offset_get() - Get the MSDU start offset from 2460 * rx_pkt_tlvs structure 2461 * 2462 * @hal_soc_hdl: HAL SOC handle 2463 * return: msdu_start_tlv offset value 2464 */ 2465 static inline 2466 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2467 { 2468 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2469 2470 if (!hal_soc || !hal_soc->ops) { 2471 hal_err("hal handle is NULL"); 2472 QDF_BUG(0); 2473 return 0; 2474 } 2475 2476 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2477 } 2478 2479 /** 2480 * hal_rx_mpdu_start_offset_get() - Get the MPDU start offset from 2481 * rx_pkt_tlvs structure 2482 * 2483 * @hal_soc_hdl: HAL SOC handle 2484 * return: mpdu_start_tlv offset value 2485 */ 2486 static inline 2487 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2488 { 2489 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2490 2491 if (!hal_soc || !hal_soc->ops) { 2492 hal_err("hal handle is NULL"); 2493 QDF_BUG(0); 2494 return 0; 2495 } 2496 2497 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2498 } 2499 2500 static inline 2501 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2502 { 2503 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2504 2505 if (!hal_soc || !hal_soc->ops) { 2506 hal_err("hal handle is NULL"); 2507 QDF_BUG(0); 2508 return 0; 2509 } 2510 2511 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2512 } 2513 2514 /** 2515 * hal_rx_mpdu_end_offset_get() - Get the MPDU end offset from 2516 * rx_pkt_tlvs structure 2517 * 2518 * @hal_soc_hdl: HAL SOC handle 2519 * return: mpdu_end_tlv offset value 2520 */ 2521 static inline 2522 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2523 { 2524 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2525 2526 if (!hal_soc || !hal_soc->ops) { 2527 hal_err("hal handle is NULL"); 2528 QDF_BUG(0); 2529 return 0; 2530 } 2531 2532 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2533 } 2534 2535 #ifdef CONFIG_WORD_BASED_TLV 2536 /** 2537 * hal_rx_mpdu_start_wmask_get() - Get the MPDU start word mask 2538 * 2539 * @hal_soc_hdl: HAL SOC handle 2540 * return: mpdu_start_tlv word mask value 2541 */ 2542 static inline 2543 uint32_t hal_rx_mpdu_start_wmask_get(hal_soc_handle_t hal_soc_hdl) 2544 { 2545 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2546 2547 if (!hal_soc || !hal_soc->ops) { 2548 hal_err("hal handle is NULL"); 2549 QDF_BUG(0); 2550 return 0; 2551 } 2552 2553 return hal_soc->ops->hal_rx_mpdu_start_wmask_get(); 2554 } 2555 2556 /** 2557 * hal_rx_msdu_end_wmask_get() - Get the MSDU END word mask 2558 * 2559 * @hal_soc_hdl: HAL SOC handle 2560 * return: msdu_end_tlv word mask value 2561 */ 2562 static inline 2563 uint32_t hal_rx_msdu_end_wmask_get(hal_soc_handle_t hal_soc_hdl) 2564 { 2565 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2566 2567 if (!hal_soc || !hal_soc->ops) { 2568 hal_err("hal handle is NULL"); 2569 QDF_BUG(0); 2570 return 0; 2571 } 2572 2573 return hal_soc->ops->hal_rx_msdu_end_wmask_get(); 2574 } 2575 #endif 2576 2577 /** 2578 * hal_rx_attn_offset_get() - Get the ATTENTION offset from 2579 * rx_pkt_tlvs structure 2580 * 2581 * @hal_soc_hdl: HAL SOC handle 2582 * return: attn_tlv offset value 2583 */ 2584 static inline 2585 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2586 { 2587 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2588 2589 if (!hal_soc || !hal_soc->ops) { 2590 hal_err("hal handle is NULL"); 2591 QDF_BUG(0); 2592 return 0; 2593 } 2594 2595 return hal_soc->ops->hal_rx_attn_offset_get(); 2596 } 2597 2598 /** 2599 * hal_rx_msdu_ext_desc_info_get_ptr() - Get msdu extension desc info ptr 2600 * @msdu_details_ptr: Pointer to msdu_details_ptr 2601 * @hal_soc: pointer to hal_soc 2602 * 2603 * Return: Pointer to rx_msdu_desc_info structure. 2604 * 2605 */ 2606 static inline 2607 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2608 struct hal_soc *hal_soc) 2609 { 2610 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2611 msdu_details_ptr); 2612 } 2613 2614 static inline void 2615 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2616 uint8_t *buf, uint8_t dbg_level) 2617 { 2618 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2619 2620 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2621 } 2622 2623 //TODO - Change the names to not include tlv names 2624 static inline uint16_t 2625 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2626 { 2627 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2628 2629 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2630 } 2631 2632 static inline uint32_t 2633 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2634 { 2635 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2636 2637 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2638 } 2639 2640 static inline uint32_t 2641 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2642 { 2643 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2644 2645 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2646 } 2647 2648 static inline uint16_t 2649 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2650 { 2651 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2652 2653 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2654 } 2655 2656 static inline int 2657 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2658 uint8_t *rx_pkt_tlv, 2659 struct hal_offload_info *offload_info) 2660 { 2661 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2662 2663 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2664 offload_info); 2665 2666 } 2667 2668 static inline int 2669 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2670 void *proto_params) 2671 { 2672 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2673 2674 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2675 } 2676 2677 static inline int 2678 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2679 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2680 { 2681 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2682 2683 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2684 l3_hdr_offset, 2685 l4_hdr_offset); 2686 } 2687 2688 static inline uint32_t 2689 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2690 { 2691 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2692 2693 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2694 } 2695 2696 /** 2697 * hal_rx_tlv_get_pkt_type() - API to get the pkt type 2698 * from rx_msdu_start 2699 * @hal_soc_hdl: hal_soc handle 2700 * @buf: pointer to the start of RX PKT TLV header 2701 * Return: uint32_t(pkt type) 2702 */ 2703 2704 static inline uint32_t 2705 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2706 { 2707 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2708 2709 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2710 } 2711 2712 static inline void 2713 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2714 uint8_t *buf, uint64_t *pn_num) 2715 { 2716 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2717 2718 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2719 } 2720 2721 static inline uint8_t * 2722 hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc) 2723 { 2724 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2725 2726 if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr) 2727 return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc); 2728 2729 return NULL; 2730 } 2731 2732 static inline uint64_t 2733 hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc, 2734 uint8_t *buf) 2735 { 2736 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2737 2738 if (hal_soc->ops->hal_rx_get_qdesc_addr) 2739 return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf); 2740 2741 return 0; 2742 } 2743 2744 static inline void 2745 hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl, 2746 uint8_t *desc, uint32_t dst_ind) 2747 { 2748 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2749 2750 if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind) 2751 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind); 2752 } 2753 2754 static inline uint32_t 2755 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2756 { 2757 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2758 2759 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2760 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2761 2762 return 0; 2763 } 2764 2765 static inline uint8_t * 2766 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2767 { 2768 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2769 2770 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2771 } 2772 2773 static inline uint8_t 2774 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2775 { 2776 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2777 2778 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2779 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2780 2781 return 0; 2782 } 2783 2784 static inline uint32_t 2785 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2786 { 2787 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2788 2789 if (hal_soc->ops->hal_rx_tlv_get_freq) 2790 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2791 2792 return 0; 2793 } 2794 2795 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2796 void *desc, 2797 void *mpdu_desc_info, 2798 uint32_t val) 2799 { 2800 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2801 2802 if (hal_soc->ops->hal_mpdu_desc_info_set) 2803 return hal_soc->ops->hal_mpdu_desc_info_set( 2804 hal_soc_hdl, desc, mpdu_desc_info, val); 2805 } 2806 2807 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2808 void *msdu_desc_info, 2809 uint32_t val, uint32_t nbuf_len) 2810 { 2811 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2812 2813 if (hal_soc->ops->hal_msdu_desc_info_set) 2814 return hal_soc->ops->hal_msdu_desc_info_set( 2815 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2816 } 2817 2818 static inline uint32_t 2819 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2820 { 2821 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2822 2823 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2824 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2825 hal_soc_hdl, msdu_link_desc); 2826 2827 return 0; 2828 } 2829 2830 static inline uint32_t 2831 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2832 { 2833 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2834 2835 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2836 } 2837 2838 static inline uint32_t 2839 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2840 { 2841 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2842 2843 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2844 } 2845 2846 static inline uint32_t 2847 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2848 { 2849 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2850 2851 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2852 } 2853 2854 static inline uint32_t 2855 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2856 { 2857 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2858 2859 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2860 } 2861 2862 static inline uint32_t 2863 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2864 { 2865 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2866 2867 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2868 } 2869 2870 static inline uint32_t 2871 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2872 hal_ring_desc_t ring_desc) 2873 { 2874 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2875 2876 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2877 } 2878 2879 /** 2880 * hal_rx_ret_buf_manager_get() - Returns the "return_buffer_manager" 2881 * from the BUFFER_ADDR_INFO structure 2882 * given a REO destination ring descriptor. 2883 * @hal_soc_hdl: hal soc handle 2884 * @ring_desc: RX(REO/WBM release) destination ring descriptor 2885 * 2886 * Return: uint8_t (value of the return_buffer_manager) 2887 */ 2888 static inline uint8_t 2889 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2890 hal_ring_desc_t ring_desc) 2891 { 2892 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2893 2894 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2895 } 2896 2897 /** 2898 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2899 * rxdma ring entry. 2900 * @hal_soc_hdl: hal soc handle 2901 * @rxdma_entry: descriptor entry 2902 * @paddr: physical address of nbuf data pointer. 2903 * @cookie: SW cookie used as a index to SW rx desc. 2904 * @manager: who owns the nbuf (host, NSS, etc...). 2905 * 2906 */ 2907 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 2908 void *rxdma_entry, 2909 qdf_dma_addr_t paddr, 2910 uint32_t cookie, 2911 uint8_t manager) 2912 { 2913 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2914 2915 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 2916 paddr, 2917 cookie, 2918 manager); 2919 } 2920 2921 static inline uint32_t 2922 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2923 { 2924 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2925 2926 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 2927 } 2928 2929 static inline void 2930 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 2931 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 2932 { 2933 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2934 2935 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 2936 ip_csum_err, 2937 tcp_udp_csum_err); 2938 } 2939 2940 static inline void 2941 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 2942 uint8_t *rx_tlv_hdr, 2943 struct hal_rx_pkt_capture_flags *flags) 2944 { 2945 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2946 2947 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 2948 flags); 2949 } 2950 2951 static inline uint8_t 2952 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2953 { 2954 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2955 2956 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 2957 } 2958 2959 static inline uint8_t 2960 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2961 { 2962 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2963 2964 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 2965 } 2966 2967 /** 2968 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 2969 * @hal_soc_hdl: HAL SoC handle 2970 * @ring_desc: REO ring descriptor 2971 * @prev_pn: Buffer to populate the previous PN 2972 * 2973 * Return: None 2974 */ 2975 static inline void 2976 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 2977 uint64_t *prev_pn) 2978 { 2979 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2980 2981 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 2982 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 2983 } 2984 2985 /** 2986 * hal_rx_mpdu_info_ampdu_flag_get() - get ampdu flag bit from rx mpdu info 2987 * @hal_soc_hdl: hal soc handle 2988 * @buf: pointer to rx_pkt_tlvs 2989 * 2990 * No input validdataion, since this function is supposed to be 2991 * called from fastpath. 2992 * 2993 * Return: ampdu flag 2994 */ 2995 static inline bool 2996 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2997 { 2998 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2999 3000 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 3001 } 3002 3003 #ifdef REO_SHARED_QREF_TABLE_EN 3004 /** 3005 * hal_reo_shared_qaddr_write() - Write REo tid queue addr 3006 * LUT shared by SW and HW at the index given by peer id 3007 * and tid. 3008 * 3009 * @hal_soc_hdl: hal soc handle 3010 * @peer_id: peer_id 3011 * @tid: tid queue number 3012 * @hw_qdesc_paddr: reo queue addr 3013 */ 3014 static inline void 3015 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 3016 uint16_t peer_id, 3017 int tid, 3018 qdf_dma_addr_t hw_qdesc_paddr) 3019 { 3020 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3021 3022 if (hal_soc->ops->hal_reo_shared_qaddr_write) 3023 return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl, 3024 peer_id, tid, hw_qdesc_paddr); 3025 } 3026 3027 /** 3028 * hal_reo_shared_qaddr_init() - Initialize reo qref LUT 3029 * @hal_soc_hdl: Hal soc handle 3030 * @qref_reset: reset qref LUT 3031 * 3032 * Write MLO and Non MLO table start addr to HW reg 3033 * 3034 * Return: void 3035 */ 3036 static inline void 3037 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) 3038 { 3039 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3040 3041 if (hal_soc->ops->hal_reo_shared_qaddr_init) 3042 return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl, 3043 qref_reset); 3044 } 3045 3046 /** 3047 * hal_reo_shared_qaddr_cache_clear() - Set and unset 'clear_qdesc_array' 3048 * bit in reo reg for shared qref feature. This is done for every MLO 3049 * connection to clear HW reo internal storage for clearing stale entry 3050 * of prev peer having same peer id 3051 * 3052 * @hal_soc_hdl: Hal soc handle 3053 * 3054 * Write MLO and Non MLO table start addr to HW reg 3055 * 3056 * Return: void 3057 */ 3058 static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) 3059 { 3060 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3061 3062 if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear) 3063 return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl); 3064 } 3065 3066 #else 3067 static inline void 3068 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 3069 uint16_t peer_id, 3070 int tid, 3071 qdf_dma_addr_t hw_qdesc_paddr) {} 3072 static inline void 3073 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {} 3074 3075 static inline void 3076 hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {} 3077 3078 #endif /* REO_SHARED_QREF_TABLE_EN */ 3079 3080 static inline uint8_t 3081 hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl) 3082 { 3083 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3084 3085 return hal->reo_qref.reo_qref_table_en; 3086 } 3087 3088 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3089 static inline uint8_t 3090 hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3091 { 3092 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3093 3094 return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf); 3095 } 3096 #endif 3097 3098 static inline uint32_t 3099 hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3100 { 3101 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3102 3103 return hal_soc->ops->hal_rx_tlv_l3_type_get ? 3104 hal_soc->ops->hal_rx_tlv_l3_type_get(buf) : 3105 HAL_RX_TLV_L3_TYPE_INVALID; 3106 } 3107 3108 /** 3109 * hal_get_tsf_time() - Get tsf time 3110 * @hal_soc_hdl: HAL soc handle 3111 * @tsf_id: 3112 * @mac_id: mac_id 3113 * @tsf: pointer to update tsf value 3114 * @tsf_sync_soc_time: pointer to update tsf sync time 3115 * 3116 * Return: None. 3117 */ 3118 static inline void 3119 hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 3120 uint32_t mac_id, uint64_t *tsf, 3121 uint64_t *tsf_sync_soc_time) 3122 { 3123 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3124 3125 if (hal_soc->ops->hal_get_tsf_time) 3126 hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id, 3127 tsf, tsf_sync_soc_time); 3128 } 3129 #endif /* _HAL_RX_H */ 3130