1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_internal.h> 23 24 /** 25 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 26 * 27 * @reo_psh_rsn: REO push reason 28 * @reo_err_code: REO Error code 29 * @rxdma_psh_rsn: RXDMA push reason 30 * @rxdma_err_code: RXDMA Error code 31 * @reserved_1: Reserved bits 32 * @wbm_err_src: WBM error source 33 * @pool_id: pool ID, indicates which rxdma pool 34 * @reserved_2: Reserved bits 35 */ 36 struct hal_wbm_err_desc_info { 37 uint16_t reo_psh_rsn:2, 38 reo_err_code:5, 39 rxdma_psh_rsn:2, 40 rxdma_err_code:5, 41 reserved_1:2; 42 uint8_t wbm_err_src:3, 43 pool_id:2, 44 reserved_2:3; 45 }; 46 47 /** 48 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 49 * 50 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 51 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 52 */ 53 enum hal_reo_error_status { 54 HAL_REO_ERROR_DETECTED = 0, 55 HAL_REO_ROUTING_INSTRUCTION = 1, 56 }; 57 58 /** 59 * @msdu_flags: [0] first_msdu_in_mpdu 60 * [1] last_msdu_in_mpdu 61 * [2] msdu_continuation - MSDU spread across buffers 62 * [23] sa_is_valid - SA match in peer table 63 * [24] sa_idx_timeout - Timeout while searching for SA match 64 * [25] da_is_valid - Used to identtify intra-bss forwarding 65 * [26] da_is_MCBC 66 * [27] da_idx_timeout - Timeout while searching for DA match 67 * 68 */ 69 struct hal_rx_msdu_desc_info { 70 uint32_t msdu_flags; 71 uint16_t msdu_len; /* 14 bits for length */ 72 }; 73 74 /** 75 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 76 * 77 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 78 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 79 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 80 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 81 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 82 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 83 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 84 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 85 */ 86 enum hal_rx_msdu_desc_flags { 87 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 88 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 89 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 90 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 91 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 92 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 93 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 94 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 95 }; 96 97 /* 98 * @msdu_count: no. of msdus in the MPDU 99 * @mpdu_seq: MPDU sequence number 100 * @mpdu_flags [0] Fragment flag 101 * [1] MPDU_retry_bit 102 * [2] AMPDU flag 103 * [3] raw_ampdu 104 * @peer_meta_data: Upper bits containing peer id, vdev id 105 */ 106 struct hal_rx_mpdu_desc_info { 107 uint16_t msdu_count; 108 uint16_t mpdu_seq; /* 12 bits for length */ 109 uint32_t mpdu_flags; 110 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 111 }; 112 113 /** 114 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 115 * 116 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 117 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 118 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 119 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 120 */ 121 enum hal_rx_mpdu_desc_flags { 122 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 123 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 124 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 125 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 126 }; 127 128 /** 129 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 130 * BUFFER_ADDR_INFO structure 131 * 132 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 133 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 134 * descriptor list 135 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 136 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 137 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 138 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 139 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 140 */ 141 enum hal_rx_ret_buf_manager { 142 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 143 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 144 HAL_RX_BUF_RBM_FW_BM = 2, 145 HAL_RX_BUF_RBM_SW0_BM = 3, 146 HAL_RX_BUF_RBM_SW1_BM = 4, 147 HAL_RX_BUF_RBM_SW2_BM = 5, 148 HAL_RX_BUF_RBM_SW3_BM = 6, 149 }; 150 151 /* 152 * Given the offset of a field in bytes, returns uint8_t * 153 */ 154 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 155 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 156 157 /* 158 * Given the offset of a field in bytes, returns uint32_t * 159 */ 160 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 161 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 162 163 #define _HAL_MS(_word, _mask, _shift) \ 164 (((_word) & (_mask)) >> (_shift)) 165 166 /* 167 * macro to set the LSW of the nbuf data physical address 168 * to the rxdma ring entry 169 */ 170 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 171 ((*(((unsigned int *) buff_addr_info) + \ 172 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 173 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 174 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 175 176 /* 177 * macro to set the LSB of MSW of the nbuf data physical address 178 * to the rxdma ring entry 179 */ 180 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 181 ((*(((unsigned int *) buff_addr_info) + \ 182 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 183 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 184 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 185 186 /* 187 * macro to set the cookie into the rxdma ring entry 188 */ 189 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 190 ((*(((unsigned int *) buff_addr_info) + \ 191 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 192 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 193 ((*(((unsigned int *) buff_addr_info) + \ 194 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 195 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 196 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 197 198 /* 199 * macro to set the LSW of the nbuf data physical address 200 * to the WBM ring entry 201 */ 202 #define HAL_WBM_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 203 ((*(((unsigned int *) buff_addr_info) + \ 204 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 205 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 206 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 207 208 /* 209 * macro to set the LSB of MSW of the nbuf data physical address 210 * to the WBM ring entry 211 */ 212 #define HAL_WBM_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 213 ((*(((unsigned int *) buff_addr_info) + \ 214 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 215 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 216 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 217 218 /* 219 * macro to set the manager into the rxdma ring entry 220 */ 221 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 222 ((*(((unsigned int *) buff_addr_info) + \ 223 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 224 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 225 ((*(((unsigned int *) buff_addr_info) + \ 226 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 227 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 228 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 229 230 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 232 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 233 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 234 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 235 236 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 237 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 238 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 239 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 240 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 241 242 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 243 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 244 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 245 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 246 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 247 248 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 249 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 250 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 251 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 252 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 253 254 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 255 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 256 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 257 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 258 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 259 260 /* TODO: Convert the following structure fields accesseses to offsets */ 261 262 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 263 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 264 (((struct reo_destination_ring *) \ 265 reo_desc)->buf_or_link_desc_addr_info))) 266 267 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 268 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 269 (((struct reo_destination_ring *) \ 270 reo_desc)->buf_or_link_desc_addr_info))) 271 272 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 273 (HAL_RX_BUF_COOKIE_GET(& \ 274 (((struct reo_destination_ring *) \ 275 reo_desc)->buf_or_link_desc_addr_info))) 276 277 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 278 ((mpdu_info_ptr \ 279 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 280 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 281 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 282 283 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 284 ((mpdu_info_ptr \ 285 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 286 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 287 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 288 289 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 290 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 291 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 292 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 293 294 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 295 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 296 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 297 298 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 299 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 300 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 301 302 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 303 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 304 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 305 306 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 307 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 308 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 309 310 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 311 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 312 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 313 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 314 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 315 316 317 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 318 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 319 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 320 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 321 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 322 323 /* 324 * NOTE: None of the following _GET macros need a right 325 * shift by the corresponding _LSB. This is because, they are 326 * finally taken and "OR'ed" into a single word again. 327 */ 328 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 329 ((*(((uint32_t *)msdu_info_ptr) + \ 330 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 331 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 332 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 333 334 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 335 ((*(((uint32_t *)msdu_info_ptr) + \ 336 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 337 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 338 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 339 340 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 341 ((*(((uint32_t *)msdu_info_ptr) + \ 342 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 343 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 344 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 345 346 347 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 348 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 349 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 350 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 351 352 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 353 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 354 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 355 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 356 357 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 358 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 359 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 360 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 361 362 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 363 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 364 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 365 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 366 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 367 368 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 369 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 370 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 371 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 372 373 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 374 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 375 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 376 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 377 378 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 379 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 380 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 381 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 382 383 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 384 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 385 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 386 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 387 388 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 389 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 390 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 391 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 392 393 394 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 395 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 396 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 397 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 398 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 399 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 400 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 401 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 402 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 403 404 405 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 406 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 407 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 408 RX_MPDU_INFO_4_PN_31_0_MASK, \ 409 RX_MPDU_INFO_4_PN_31_0_LSB)) 410 411 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 412 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 413 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 414 RX_MPDU_INFO_5_PN_63_32_MASK, \ 415 RX_MPDU_INFO_5_PN_63_32_LSB)) 416 417 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 418 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 419 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 420 RX_MPDU_INFO_6_PN_95_64_MASK, \ 421 RX_MPDU_INFO_6_PN_95_64_LSB)) 422 423 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 424 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 425 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 426 RX_MPDU_INFO_7_PN_127_96_MASK, \ 427 RX_MPDU_INFO_7_PN_127_96_LSB)) 428 429 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 430 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 431 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 432 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 433 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 434 435 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 436 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 437 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 438 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 439 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 440 441 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 442 (*(uint32_t *)(((uint8_t *)_ptr) + \ 443 _wrd ## _ ## _field ## _OFFSET) |= \ 444 ((_val << _wrd ## _ ## _field ## _LSB) & \ 445 _wrd ## _ ## _field ## _MASK)) 446 447 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 448 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 449 _field, _val) 450 451 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 452 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 453 _field, _val) 454 455 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 456 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 457 _field, _val) 458 459 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 460 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 461 { 462 struct reo_destination_ring *reo_dst_ring; 463 uint32_t mpdu_info[NUM_OF_DWORDS_RX_MPDU_DESC_INFO]; 464 465 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 466 467 qdf_mem_copy(&mpdu_info, 468 (const void *)&reo_dst_ring->rx_mpdu_desc_info_details, 469 sizeof(struct rx_mpdu_desc_info)); 470 471 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 472 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 473 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 474 mpdu_desc_info->peer_meta_data = 475 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 476 } 477 478 /* 479 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 480 * @ Specifically flags needed are: 481 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 482 * @ msdu_continuation, sa_is_valid, 483 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 484 * @ da_is_MCBC 485 * 486 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 487 * @ descriptor 488 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 489 * @ Return: void 490 */ 491 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 492 struct hal_rx_msdu_desc_info *msdu_desc_info) 493 { 494 struct reo_destination_ring *reo_dst_ring; 495 uint32_t msdu_info[NUM_OF_DWORDS_RX_MSDU_DESC_INFO]; 496 497 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 498 499 qdf_mem_copy(&msdu_info, 500 (const void *)&reo_dst_ring->rx_msdu_desc_info_details, 501 sizeof(struct rx_msdu_desc_info)); 502 503 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 504 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 505 } 506 507 /* 508 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 509 * rxdma ring entry. 510 * @rxdma_entry: descriptor entry 511 * @paddr: physical address of nbuf data pointer. 512 * @cookie: SW cookie used as a index to SW rx desc. 513 * @manager: who owns the nbuf (host, NSS, etc...). 514 * 515 */ 516 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 517 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 518 { 519 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 520 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 521 522 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 523 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 524 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 525 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 526 } 527 528 /* 529 * Structures & Macros to obtain fields from the TLV's in the Rx packet 530 * pre-header. 531 */ 532 533 /* 534 * Every Rx packet starts at an offset from the top of the buffer. 535 * If the host hasn't subscribed to any specific TLV, there is 536 * still space reserved for the following TLV's from the start of 537 * the buffer: 538 * -- RX ATTENTION 539 * -- RX MPDU START 540 * -- RX MSDU START 541 * -- RX MSDU END 542 * -- RX MPDU END 543 * -- RX PACKET HEADER (802.11) 544 * If the host subscribes to any of the TLV's above, that TLV 545 * if populated by the HW 546 */ 547 548 #define NUM_DWORDS_TAG 1 549 550 /* By default the packet header TLV is 128 bytes */ 551 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 552 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 553 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 554 555 #define RX_PKT_OFFSET_WORDS \ 556 ( \ 557 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 558 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 559 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 560 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 561 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 562 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 563 ) 564 565 #define RX_PKT_OFFSET_BYTES \ 566 (RX_PKT_OFFSET_WORDS << 2) 567 568 #define RX_PKT_HDR_TLV_LEN 120 569 570 /* 571 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 572 */ 573 struct rx_attention_tlv { 574 uint32_t tag; 575 struct rx_attention rx_attn; 576 }; 577 578 struct rx_mpdu_start_tlv { 579 uint32_t tag; 580 struct rx_mpdu_start rx_mpdu_start; 581 }; 582 583 struct rx_msdu_start_tlv { 584 uint32_t tag; 585 struct rx_msdu_start rx_msdu_start; 586 }; 587 588 struct rx_msdu_end_tlv { 589 uint32_t tag; 590 struct rx_msdu_end rx_msdu_end; 591 }; 592 593 struct rx_mpdu_end_tlv { 594 uint32_t tag; 595 struct rx_mpdu_end rx_mpdu_end; 596 }; 597 598 struct rx_pkt_hdr_tlv { 599 uint32_t tag; /* 4 B */ 600 uint32_t phy_ppdu_id; /* 4 B */ 601 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 602 }; 603 604 605 #define RXDMA_OPTIMIZATION 606 607 #ifdef RXDMA_OPTIMIZATION 608 /* 609 * The RX_PADDING_BYTES is required so that the TLV's don't 610 * spread across the 128 byte boundary 611 * RXDMA optimization requires: 612 * 1) MSDU_END & ATTENTION TLV's follow in that order 613 * 2) TLV's don't span across 128 byte lines 614 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 615 */ 616 #if defined(WCSS_VERSION) && \ 617 ((defined(CONFIG_WIN) && (WCSS_VERSION >= 96)) || \ 618 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 619 #define RX_PADDING0_BYTES 4 620 #endif 621 #define RX_PADDING1_BYTES 16 622 struct rx_pkt_tlvs { 623 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 624 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 625 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 626 #if defined(WCSS_VERSION) && \ 627 ((defined(CONFIG_WIN) && (WCSS_VERSION >= 96)) || \ 628 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 629 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 630 #endif 631 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 632 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 633 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 634 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 635 }; 636 #else /* RXDMA_OPTIMIZATION */ 637 struct rx_pkt_tlvs { 638 struct rx_attention_tlv attn_tlv; 639 struct rx_mpdu_start_tlv mpdu_start_tlv; 640 struct rx_msdu_start_tlv msdu_start_tlv; 641 struct rx_msdu_end_tlv msdu_end_tlv; 642 struct rx_mpdu_end_tlv mpdu_end_tlv; 643 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 644 }; 645 #endif /* RXDMA_OPTIMIZATION */ 646 647 #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs)) 648 649 static inline uint8_t 650 *hal_rx_pkt_hdr_get(uint8_t *buf) 651 { 652 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 653 654 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 655 656 } 657 658 static inline uint8_t 659 *hal_rx_padding0_get(uint8_t *buf) 660 { 661 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 662 663 return pkt_tlvs->rx_padding0; 664 } 665 666 /* 667 * @ hal_rx_encryption_info_valid: Returns encryption type. 668 * 669 * @ buf: rx_tlv_hdr of the received packet 670 * @ Return: encryption type 671 */ 672 static inline uint32_t 673 hal_rx_encryption_info_valid(uint8_t *buf) 674 { 675 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 676 struct rx_mpdu_start *mpdu_start = 677 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 678 struct rx_mpdu_info *mpdu_info = &(mpdu_start->rx_mpdu_info_details); 679 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 680 681 return encryption_info; 682 } 683 684 /* 685 * @ hal_rx_print_pn: Prints the PN of rx packet. 686 * 687 * @ buf: rx_tlv_hdr of the received packet 688 * @ Return: void 689 */ 690 static inline void 691 hal_rx_print_pn(uint8_t *buf) 692 { 693 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 694 struct rx_mpdu_start *mpdu_start = 695 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 696 struct rx_mpdu_info *mpdu_info = &(mpdu_start->rx_mpdu_info_details); 697 698 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 699 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 700 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 701 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 702 703 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 704 "PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 705 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 706 } 707 708 /* 709 * Get msdu_done bit from the RX_ATTENTION TLV 710 */ 711 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 712 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 713 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 714 RX_ATTENTION_2_MSDU_DONE_MASK, \ 715 RX_ATTENTION_2_MSDU_DONE_LSB)) 716 717 static inline uint32_t 718 hal_rx_attn_msdu_done_get(uint8_t *buf) 719 { 720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 721 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 722 uint32_t msdu_done; 723 724 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 725 726 return msdu_done; 727 } 728 729 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 730 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 731 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 732 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 733 RX_ATTENTION_1_FIRST_MPDU_LSB)) 734 735 /* 736 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 737 * @buf: pointer to rx_pkt_tlvs 738 * 739 * reutm: uint32_t(first_msdu) 740 */ 741 static inline uint32_t 742 hal_rx_attn_first_mpdu_get(uint8_t *buf) 743 { 744 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 745 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 746 uint32_t first_mpdu; 747 748 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 749 750 return first_mpdu; 751 } 752 753 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 754 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 755 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 756 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 757 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 758 759 /* 760 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 761 * from rx attention 762 * @buf: pointer to rx_pkt_tlvs 763 * 764 * Return: tcp_udp_cksum_fail 765 */ 766 static inline bool 767 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 768 { 769 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 770 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 771 bool tcp_udp_cksum_fail; 772 773 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 774 775 return tcp_udp_cksum_fail; 776 } 777 778 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 779 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 780 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 781 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 782 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 783 784 /* 785 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 786 * from rx attention 787 * @buf: pointer to rx_pkt_tlvs 788 * 789 * Return: ip_cksum_fail 790 */ 791 static inline bool 792 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 793 { 794 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 795 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 796 bool ip_cksum_fail; 797 798 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 799 800 return ip_cksum_fail; 801 } 802 803 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 804 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 805 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 806 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 807 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 808 809 /* 810 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 811 * from rx attention 812 * @buf: pointer to rx_pkt_tlvs 813 * 814 * Return: phy_ppdu_id 815 */ 816 static inline uint16_t 817 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 818 { 819 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 820 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 821 uint16_t phy_ppdu_id; 822 823 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 824 825 return phy_ppdu_id; 826 } 827 828 /* 829 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 830 */ 831 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 832 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 833 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 834 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 835 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 836 837 static inline uint32_t 838 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 839 { 840 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 841 struct rx_mpdu_start *mpdu_start = 842 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 843 844 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 845 uint32_t peer_meta_data; 846 847 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 848 849 return peer_meta_data; 850 } 851 852 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 853 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 854 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 855 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 856 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 857 /** 858 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 859 * from rx mpdu info 860 * @buf: pointer to rx_pkt_tlvs 861 * 862 * Return: ampdu flag 863 */ 864 static inline bool 865 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 866 { 867 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 868 struct rx_mpdu_start *mpdu_start = 869 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 870 871 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 872 bool ampdu_flag; 873 874 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 875 876 return ampdu_flag; 877 } 878 879 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 880 ((*(((uint32_t *)_rx_mpdu_info) + \ 881 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 882 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 883 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 884 885 /* 886 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 887 * 888 * @ buf: rx_tlv_hdr of the received packet 889 * @ peer_mdata: peer meta data to be set. 890 * @ Return: void 891 */ 892 static inline void 893 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 894 { 895 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 896 struct rx_mpdu_start *mpdu_start = 897 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 898 899 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 900 901 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 902 } 903 904 #if defined(WCSS_VERSION) && \ 905 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 906 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 907 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 908 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 909 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 910 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 911 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 912 #else 913 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 914 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 915 RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET)), \ 916 RX_MSDU_END_9_L3_HEADER_PADDING_MASK, \ 917 RX_MSDU_END_9_L3_HEADER_PADDING_LSB)) 918 #endif 919 920 /** 921 * LRO information needed from the TLVs 922 */ 923 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 924 (_HAL_MS( \ 925 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 926 msdu_end_tlv.rx_msdu_end), \ 927 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 928 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 929 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 930 931 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 932 (_HAL_MS( \ 933 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 934 msdu_end_tlv.rx_msdu_end), \ 935 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 936 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 937 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 938 939 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 940 (_HAL_MS( \ 941 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 942 msdu_end_tlv.rx_msdu_end), \ 943 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 944 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 945 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 946 947 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 948 (_HAL_MS( \ 949 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 950 msdu_end_tlv.rx_msdu_end), \ 951 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 952 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 953 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 954 955 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 956 (_HAL_MS( \ 957 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 958 msdu_end_tlv.rx_msdu_end), \ 959 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 960 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 961 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 962 963 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 964 (_HAL_MS( \ 965 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 966 msdu_start_tlv.rx_msdu_start), \ 967 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 968 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 969 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 970 971 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 972 (_HAL_MS( \ 973 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 974 msdu_start_tlv.rx_msdu_start), \ 975 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 976 RX_MSDU_START_2_TCP_PROTO_MASK, \ 977 RX_MSDU_START_2_TCP_PROTO_LSB)) 978 979 #define HAL_RX_TLV_GET_IPV6(buf) \ 980 (_HAL_MS( \ 981 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 982 msdu_start_tlv.rx_msdu_start), \ 983 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 984 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 985 RX_MSDU_START_2_IPV6_PROTO_LSB)) 986 987 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 988 (_HAL_MS( \ 989 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 990 msdu_start_tlv.rx_msdu_start), \ 991 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 992 RX_MSDU_START_1_L3_OFFSET_MASK, \ 993 RX_MSDU_START_1_L3_OFFSET_LSB)) 994 995 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 996 (_HAL_MS( \ 997 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 998 msdu_start_tlv.rx_msdu_start), \ 999 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 1000 RX_MSDU_START_1_L4_OFFSET_MASK, \ 1001 RX_MSDU_START_1_L4_OFFSET_LSB)) 1002 1003 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 1004 (_HAL_MS( \ 1005 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 1006 msdu_start_tlv.rx_msdu_start), \ 1007 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1008 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1009 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1010 1011 /** 1012 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 1013 * l3_header padding from rx_msdu_end TLV 1014 * 1015 * @ buf: pointer to the start of RX PKT TLV headers 1016 * Return: number of l3 header padding bytes 1017 */ 1018 static inline uint32_t 1019 hal_rx_msdu_end_l3_hdr_padding_get(uint8_t *buf) 1020 { 1021 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1022 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1023 uint32_t l3_header_padding; 1024 1025 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1026 1027 return l3_header_padding; 1028 } 1029 1030 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 1031 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1032 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 1033 RX_MSDU_END_13_SA_IDX_MASK, \ 1034 RX_MSDU_END_13_SA_IDX_LSB)) 1035 1036 /** 1037 * hal_rx_msdu_end_sa_idx_get(): API to get the 1038 * sa_idx from rx_msdu_end TLV 1039 * 1040 * @ buf: pointer to the start of RX PKT TLV headers 1041 * Return: sa_idx (SA AST index) 1042 */ 1043 static inline uint16_t 1044 hal_rx_msdu_end_sa_idx_get(uint8_t *buf) 1045 { 1046 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1047 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1048 uint16_t sa_idx; 1049 1050 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1051 1052 return sa_idx; 1053 } 1054 1055 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 1056 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1057 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 1058 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 1059 RX_MSDU_END_5_SA_IS_VALID_LSB)) 1060 1061 /** 1062 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1063 * sa_is_valid bit from rx_msdu_end TLV 1064 * 1065 * @ buf: pointer to the start of RX PKT TLV headers 1066 * Return: sa_is_valid bit 1067 */ 1068 static inline uint8_t 1069 hal_rx_msdu_end_sa_is_valid_get(uint8_t *buf) 1070 { 1071 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1072 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1073 uint8_t sa_is_valid; 1074 1075 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 1076 1077 return sa_is_valid; 1078 } 1079 1080 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 1081 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1082 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 1083 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 1084 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 1085 1086 /** 1087 * hal_rx_msdu_end_sa_sw_peer_id_get(): API to get the 1088 * sa_sw_peer_id from rx_msdu_end TLV 1089 * 1090 * @ buf: pointer to the start of RX PKT TLV headers 1091 * Return: sa_sw_peer_id index 1092 */ 1093 static inline uint32_t 1094 hal_rx_msdu_end_sa_sw_peer_id_get(uint8_t *buf) 1095 { 1096 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1097 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1098 uint32_t sa_sw_peer_id; 1099 1100 sa_sw_peer_id = HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1101 1102 return sa_sw_peer_id; 1103 } 1104 1105 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1106 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1107 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1108 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1109 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1110 1111 /** 1112 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1113 * from rx_msdu_start TLV 1114 * 1115 * @ buf: pointer to the start of RX PKT TLV headers 1116 * Return: msdu length 1117 */ 1118 static inline uint32_t 1119 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1120 { 1121 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1122 struct rx_msdu_start *msdu_start = 1123 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1124 uint32_t msdu_len; 1125 1126 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1127 1128 return msdu_len; 1129 } 1130 1131 /** 1132 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1133 * from rx_msdu_start TLV 1134 * 1135 * @buf: pointer to the start of RX PKT TLV headers 1136 * @len: msdu length 1137 * 1138 * Return: none 1139 */ 1140 static inline void 1141 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1142 { 1143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1144 struct rx_msdu_start *msdu_start = 1145 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1146 void *wrd1; 1147 1148 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1149 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1150 *(uint32_t *)wrd1 |= len; 1151 } 1152 1153 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1154 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1155 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1156 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1157 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1158 1159 /* 1160 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1161 * Interval from rx_msdu_start 1162 * 1163 * @buf: pointer to the start of RX PKT TLV header 1164 * Return: uint32_t(bw) 1165 */ 1166 static inline uint32_t 1167 hal_rx_msdu_start_bw_get(uint8_t *buf) 1168 { 1169 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1170 struct rx_msdu_start *msdu_start = 1171 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1172 uint32_t bw; 1173 1174 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1175 1176 return bw; 1177 } 1178 1179 1180 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1182 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1183 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1184 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1185 1186 /** 1187 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1188 * from rx_msdu_start TLV 1189 * 1190 * @ buf: pointer to the start of RX PKT TLV headers 1191 * Return: toeplitz hash 1192 */ 1193 static inline uint32_t 1194 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1195 { 1196 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1197 struct rx_msdu_start *msdu_start = 1198 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1199 1200 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1201 } 1202 1203 /* 1204 * Get qos_control_valid from RX_MPDU_START 1205 */ 1206 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 1207 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 1208 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 1209 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 1210 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 1211 1212 static inline uint32_t 1213 hal_rx_mpdu_start_mpdu_qos_control_valid_get(uint8_t *buf) 1214 { 1215 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1216 struct rx_mpdu_start *mpdu_start = 1217 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1218 uint32_t qos_control_valid; 1219 1220 qos_control_valid = HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1221 &(mpdu_start->rx_mpdu_info_details)); 1222 1223 return qos_control_valid; 1224 } 1225 1226 1227 /* 1228 * Get SW peer id from RX_MPDU_START 1229 */ 1230 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 1231 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 1232 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 1233 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 1234 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 1235 1236 static inline uint32_t 1237 hal_rx_mpdu_start_sw_peer_id_get(uint8_t *buf) 1238 { 1239 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1240 struct rx_mpdu_start *mpdu_start = 1241 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1242 uint32_t sw_peer_id; 1243 1244 sw_peer_id = HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 1245 &(mpdu_start->rx_mpdu_info_details)); 1246 1247 return sw_peer_id; 1248 } 1249 1250 #if defined(WCSS_VERSION) && \ 1251 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1252 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1253 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1254 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1255 RX_MSDU_START_5_SGI_OFFSET)), \ 1256 RX_MSDU_START_5_SGI_MASK, \ 1257 RX_MSDU_START_5_SGI_LSB)) 1258 #else 1259 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1260 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1261 RX_MSDU_START_6_SGI_OFFSET)), \ 1262 RX_MSDU_START_6_SGI_MASK, \ 1263 RX_MSDU_START_6_SGI_LSB)) 1264 #endif 1265 /** 1266 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1267 * Interval from rx_msdu_start TLV 1268 * 1269 * @buf: pointer to the start of RX PKT TLV headers 1270 * Return: uint32_t(sgi) 1271 */ 1272 static inline uint32_t 1273 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1274 { 1275 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1276 struct rx_msdu_start *msdu_start = 1277 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1278 uint32_t sgi; 1279 1280 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1281 1282 return sgi; 1283 } 1284 1285 #if defined(WCSS_VERSION) && \ 1286 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1287 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1288 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1289 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1290 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1291 RX_MSDU_START_5_RATE_MCS_MASK, \ 1292 RX_MSDU_START_5_RATE_MCS_LSB)) 1293 #else 1294 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1295 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1296 RX_MSDU_START_6_RATE_MCS_OFFSET)), \ 1297 RX_MSDU_START_6_RATE_MCS_MASK, \ 1298 RX_MSDU_START_6_RATE_MCS_LSB)) 1299 #endif 1300 /** 1301 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1302 * from rx_msdu_start TLV 1303 * 1304 * @buf: pointer to the start of RX PKT TLV headers 1305 * Return: uint32_t(rate_mcs) 1306 */ 1307 static inline uint32_t 1308 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1309 { 1310 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1311 struct rx_msdu_start *msdu_start = 1312 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1313 uint32_t rate_mcs; 1314 1315 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1316 1317 return rate_mcs; 1318 } 1319 1320 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1321 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1322 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1323 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1324 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1325 1326 /* 1327 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1328 * packet from rx_attention 1329 * 1330 * @buf: pointer to the start of RX PKT TLV header 1331 * Return: uint32_t(decryt status) 1332 */ 1333 1334 static inline uint32_t 1335 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1336 { 1337 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1338 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1339 uint32_t is_decrypt = 0; 1340 uint32_t decrypt_status; 1341 1342 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1343 1344 if (!decrypt_status) 1345 is_decrypt = 1; 1346 1347 return is_decrypt; 1348 } 1349 1350 /* 1351 * Get key index from RX_MSDU_END 1352 */ 1353 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1354 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1355 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1356 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1357 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1358 /* 1359 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1360 * from rx_msdu_end 1361 * 1362 * @buf: pointer to the start of RX PKT TLV header 1363 * Return: uint32_t(key id) 1364 */ 1365 1366 static inline uint32_t 1367 hal_rx_msdu_get_keyid(uint8_t *buf) 1368 { 1369 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1370 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1371 uint32_t keyid_octet; 1372 1373 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1374 1375 return keyid_octet & 0x3; 1376 } 1377 1378 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1379 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1380 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1381 RX_MSDU_START_5_USER_RSSI_MASK, \ 1382 RX_MSDU_START_5_USER_RSSI_LSB)) 1383 /* 1384 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1385 * from rx_msdu_start 1386 * 1387 * @buf: pointer to the start of RX PKT TLV header 1388 * Return: uint32_t(rssi) 1389 */ 1390 1391 static inline uint32_t 1392 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1393 { 1394 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1395 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1396 uint32_t rssi; 1397 1398 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1399 1400 return rssi; 1401 1402 } 1403 1404 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1405 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1406 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1407 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1408 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1409 1410 /* 1411 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1412 * from rx_msdu_start 1413 * 1414 * @buf: pointer to the start of RX PKT TLV header 1415 * Return: uint32_t(frequency) 1416 */ 1417 1418 static inline uint32_t 1419 hal_rx_msdu_start_get_freq(uint8_t *buf) 1420 { 1421 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1422 struct rx_msdu_start *msdu_start = 1423 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1424 uint32_t freq; 1425 1426 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1427 1428 return freq; 1429 } 1430 1431 1432 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1433 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1434 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1435 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1436 RX_MSDU_START_5_PKT_TYPE_LSB)) 1437 1438 /* 1439 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1440 * from rx_msdu_start 1441 * 1442 * @buf: pointer to the start of RX PKT TLV header 1443 * Return: uint32_t(pkt type) 1444 */ 1445 1446 static inline uint32_t 1447 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1448 { 1449 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1450 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1451 uint32_t pkt_type; 1452 1453 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1454 1455 return pkt_type; 1456 } 1457 1458 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 1459 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1460 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 1461 RX_MPDU_INFO_2_TO_DS_MASK, \ 1462 RX_MPDU_INFO_2_TO_DS_LSB)) 1463 1464 /* 1465 * hal_rx_mpdu_get_tods(): API to get the tods info 1466 * from rx_mpdu_start 1467 * 1468 * @buf: pointer to the start of RX PKT TLV header 1469 * Return: uint32_t(to_ds) 1470 */ 1471 1472 static inline uint32_t 1473 hal_rx_mpdu_get_to_ds(uint8_t *buf) 1474 { 1475 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1476 struct rx_mpdu_start *mpdu_start = 1477 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1478 1479 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1480 uint32_t to_ds; 1481 1482 to_ds = HAL_RX_MPDU_GET_TODS(mpdu_info); 1483 1484 return to_ds; 1485 } 1486 1487 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 1488 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1489 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 1490 RX_MPDU_INFO_2_FR_DS_MASK, \ 1491 RX_MPDU_INFO_2_FR_DS_LSB)) 1492 1493 /* 1494 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1495 * from rx_mpdu_start 1496 * 1497 * @buf: pointer to the start of RX PKT TLV header 1498 * Return: uint32_t(fr_ds) 1499 */ 1500 1501 static inline uint32_t 1502 hal_rx_mpdu_get_fr_ds(uint8_t *buf) 1503 { 1504 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1505 struct rx_mpdu_start *mpdu_start = 1506 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1507 1508 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1509 uint32_t fr_ds; 1510 1511 fr_ds = HAL_RX_MPDU_GET_FROMDS(mpdu_info); 1512 1513 return fr_ds; 1514 } 1515 1516 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 1517 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1518 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 1519 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 1520 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 1521 1522 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 1523 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1524 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 1525 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 1526 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 1527 1528 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 1529 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1530 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 1531 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 1532 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 1533 1534 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 1535 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1536 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 1537 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 1538 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 1539 1540 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 1541 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1542 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 1543 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 1544 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 1545 1546 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 1547 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1548 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 1549 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 1550 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 1551 1552 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 1553 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1554 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 1555 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 1556 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 1557 1558 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 1559 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1560 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 1561 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 1562 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 1563 1564 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 1565 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1566 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 1567 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 1568 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 1569 1570 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 1571 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1572 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 1573 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 1574 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 1575 1576 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1577 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1578 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1579 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1580 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1581 1582 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1583 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1584 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1585 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1586 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1587 1588 /* 1589 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1590 * 1591 * @buf: pointer to the start of RX PKT TLV headera 1592 * @mac_addr: pointer to mac address 1593 * Return: success/failure 1594 */ 1595 static inline 1596 QDF_STATUS hal_rx_mpdu_get_addr1(uint8_t *buf, uint8_t *mac_addr) 1597 { 1598 struct __attribute__((__packed__)) hal_addr1 { 1599 uint32_t ad1_31_0; 1600 uint16_t ad1_47_32; 1601 }; 1602 1603 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1604 struct rx_mpdu_start *mpdu_start = 1605 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1606 1607 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1608 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 1609 uint32_t mac_addr_ad1_valid; 1610 1611 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 1612 1613 if (mac_addr_ad1_valid) { 1614 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 1615 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 1616 return QDF_STATUS_SUCCESS; 1617 } 1618 1619 return QDF_STATUS_E_FAILURE; 1620 } 1621 1622 /* 1623 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1624 * in the packet 1625 * 1626 * @buf: pointer to the start of RX PKT TLV header 1627 * @mac_addr: pointer to mac address 1628 * Return: success/failure 1629 */ 1630 static inline 1631 QDF_STATUS hal_rx_mpdu_get_addr2(uint8_t *buf, uint8_t *mac_addr) 1632 { 1633 struct __attribute__((__packed__)) hal_addr2 { 1634 uint16_t ad2_15_0; 1635 uint32_t ad2_47_16; 1636 }; 1637 1638 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1639 struct rx_mpdu_start *mpdu_start = 1640 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1641 1642 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1643 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 1644 uint32_t mac_addr_ad2_valid; 1645 1646 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 1647 1648 if (mac_addr_ad2_valid) { 1649 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 1650 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 1651 return QDF_STATUS_SUCCESS; 1652 } 1653 1654 return QDF_STATUS_E_FAILURE; 1655 } 1656 1657 /* 1658 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1659 * in the packet 1660 * 1661 * @buf: pointer to the start of RX PKT TLV header 1662 * @mac_addr: pointer to mac address 1663 * Return: success/failure 1664 */ 1665 static inline 1666 QDF_STATUS hal_rx_mpdu_get_addr3(uint8_t *buf, uint8_t *mac_addr) 1667 { 1668 struct __attribute__((__packed__)) hal_addr3 { 1669 uint32_t ad3_31_0; 1670 uint16_t ad3_47_32; 1671 }; 1672 1673 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1674 struct rx_mpdu_start *mpdu_start = 1675 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1676 1677 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1678 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1679 uint32_t mac_addr_ad3_valid; 1680 1681 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1682 1683 if (mac_addr_ad3_valid) { 1684 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1685 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1686 return QDF_STATUS_SUCCESS; 1687 } 1688 1689 return QDF_STATUS_E_FAILURE; 1690 } 1691 1692 /* 1693 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1694 * in the packet 1695 * 1696 * @buf: pointer to the start of RX PKT TLV header 1697 * @mac_addr: pointer to mac address 1698 * Return: success/failure 1699 */ 1700 static inline 1701 QDF_STATUS hal_rx_mpdu_get_addr4(uint8_t *buf, uint8_t *mac_addr) 1702 { 1703 struct __attribute__((__packed__)) hal_addr4 { 1704 uint32_t ad4_31_0; 1705 uint16_t ad4_47_32; 1706 }; 1707 1708 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1709 struct rx_mpdu_start *mpdu_start = 1710 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1711 1712 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1713 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1714 uint32_t mac_addr_ad4_valid; 1715 1716 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1717 1718 if (mac_addr_ad4_valid) { 1719 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1720 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1721 return QDF_STATUS_SUCCESS; 1722 } 1723 1724 return QDF_STATUS_E_FAILURE; 1725 } 1726 1727 /** 1728 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1729 * from rx_msdu_end TLV 1730 * 1731 * @ buf: pointer to the start of RX PKT TLV headers 1732 * Return: da index 1733 */ 1734 static inline uint16_t 1735 hal_rx_msdu_end_da_idx_get(struct hal_soc *hal_soc, uint8_t *buf) 1736 { 1737 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1738 } 1739 1740 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 1741 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1742 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 1743 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 1744 RX_MSDU_END_5_DA_IS_VALID_LSB)) 1745 1746 /** 1747 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1748 * from rx_msdu_end TLV 1749 * 1750 * @ buf: pointer to the start of RX PKT TLV headers 1751 * Return: da_is_valid 1752 */ 1753 static inline uint8_t 1754 hal_rx_msdu_end_da_is_valid_get(uint8_t *buf) 1755 { 1756 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1757 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1758 uint8_t da_is_valid; 1759 1760 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 1761 1762 return da_is_valid; 1763 } 1764 1765 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 1766 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1767 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 1768 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 1769 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 1770 1771 /** 1772 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1773 * from rx_msdu_end TLV 1774 * 1775 * @ buf: pointer to the start of RX PKT TLV headers 1776 * Return: da_is_mcbc 1777 */ 1778 static inline uint8_t 1779 hal_rx_msdu_end_da_is_mcbc_get(uint8_t *buf) 1780 { 1781 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1782 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1783 uint8_t da_is_mcbc; 1784 1785 da_is_mcbc = HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 1786 1787 return da_is_mcbc; 1788 } 1789 1790 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 1791 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1792 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 1793 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 1794 RX_MSDU_END_5_FIRST_MSDU_LSB)) 1795 1796 /** 1797 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1798 * from rx_msdu_end TLV 1799 * 1800 * @ buf: pointer to the start of RX PKT TLV headers 1801 * Return: first_msdu 1802 */ 1803 static inline uint8_t 1804 hal_rx_msdu_end_first_msdu_get(uint8_t *buf) 1805 { 1806 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1807 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1808 uint8_t first_msdu; 1809 1810 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 1811 1812 return first_msdu; 1813 } 1814 1815 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 1816 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1817 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 1818 RX_MSDU_END_5_LAST_MSDU_MASK, \ 1819 RX_MSDU_END_5_LAST_MSDU_LSB)) 1820 1821 /** 1822 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1823 * from rx_msdu_end TLV 1824 * 1825 * @ buf: pointer to the start of RX PKT TLV headers 1826 * Return: last_msdu 1827 */ 1828 static inline uint8_t 1829 hal_rx_msdu_end_last_msdu_get(uint8_t *buf) 1830 { 1831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1832 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1833 uint8_t last_msdu; 1834 1835 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 1836 1837 return last_msdu; 1838 } 1839 /******************************************************************************* 1840 * RX ERROR APIS 1841 ******************************************************************************/ 1842 1843 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1844 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1845 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1846 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1847 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1848 1849 /** 1850 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1851 * from rx_mpdu_end TLV 1852 * 1853 * @buf: pointer to the start of RX PKT TLV headers 1854 * Return: uint32_t(decrypt_err) 1855 */ 1856 static inline uint32_t 1857 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1858 { 1859 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1860 struct rx_mpdu_end *mpdu_end = 1861 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1862 uint32_t decrypt_err; 1863 1864 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1865 1866 return decrypt_err; 1867 } 1868 1869 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1870 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1871 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1872 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1873 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1874 1875 /** 1876 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1877 * from rx_mpdu_end TLV 1878 * 1879 * @buf: pointer to the start of RX PKT TLV headers 1880 * Return: uint32_t(mic_err) 1881 */ 1882 static inline uint32_t 1883 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1884 { 1885 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1886 struct rx_mpdu_end *mpdu_end = 1887 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1888 uint32_t mic_err; 1889 1890 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1891 1892 return mic_err; 1893 } 1894 1895 /******************************************************************************* 1896 * RX REO ERROR APIS 1897 ******************************************************************************/ 1898 1899 #define HAL_RX_NUM_MSDU_DESC 6 1900 #define HAL_RX_MAX_SAVED_RING_DESC 16 1901 1902 /* TODO: rework the structure */ 1903 struct hal_rx_msdu_list { 1904 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1905 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1906 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1907 }; 1908 1909 struct hal_buf_info { 1910 uint64_t paddr; 1911 uint32_t sw_cookie; 1912 }; 1913 1914 /** 1915 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1916 * @msdu_link_ptr - msdu link ptr 1917 * @hal - pointer to hal_soc 1918 * Return - Pointer to rx_msdu_details structure 1919 * 1920 */ 1921 static inline void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, void *hal) 1922 { 1923 struct hal_soc *hal_soc = (struct hal_soc *)hal; 1924 1925 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1926 } 1927 1928 /** 1929 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1930 * @msdu_details_ptr - Pointer to msdu_details_ptr 1931 * @hal - pointer to hal_soc 1932 * Return - Pointer to rx_msdu_desc_info structure. 1933 * 1934 */ 1935 static inline void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, void *hal) 1936 { 1937 struct hal_soc *hal_soc = (struct hal_soc *)hal; 1938 1939 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1940 } 1941 1942 /* This special cookie value will be used to indicate FW allocated buffers 1943 * received through RXDMA2SW ring for RXDMA WARs 1944 */ 1945 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1946 1947 /** 1948 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1949 * from the MSDU link descriptor 1950 * 1951 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1952 * MSDU link descriptor (struct rx_msdu_link) 1953 * 1954 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1955 * 1956 * @num_msdus: Number of MSDUs in the MPDU 1957 * 1958 * Return: void 1959 */ 1960 static inline void hal_rx_msdu_list_get(struct hal_soc *hal_soc, 1961 void *msdu_link_desc, 1962 struct hal_rx_msdu_list *msdu_list, 1963 uint16_t *num_msdus) 1964 { 1965 struct rx_msdu_details *msdu_details; 1966 struct rx_msdu_desc_info *msdu_desc_info; 1967 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1968 int i; 1969 1970 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1971 1972 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1973 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1974 __func__, __LINE__, msdu_link, msdu_details); 1975 1976 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1977 /* num_msdus received in mpdu descriptor may be incorrect 1978 * sometimes due to HW issue. Check msdu buffer address also 1979 */ 1980 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1981 &msdu_details[i].buffer_addr_info_details) == 0) { 1982 /* set the last msdu bit in the prev msdu_desc_info */ 1983 msdu_desc_info = 1984 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1985 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1986 break; 1987 } 1988 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1989 hal_soc); 1990 1991 /* set first MSDU bit or the last MSDU bit */ 1992 if (!i) 1993 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1994 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1995 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1996 1997 msdu_list->msdu_info[i].msdu_flags = 1998 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1999 msdu_list->msdu_info[i].msdu_len = 2000 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2001 msdu_list->sw_cookie[i] = 2002 HAL_RX_BUF_COOKIE_GET( 2003 &msdu_details[i].buffer_addr_info_details); 2004 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 2005 &msdu_details[i].buffer_addr_info_details); 2006 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 2007 "[%s][%d] i=%d sw_cookie=%d", 2008 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 2009 } 2010 *num_msdus = i; 2011 } 2012 2013 /** 2014 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 2015 * destination ring ID from the msdu desc info 2016 * 2017 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 2018 * the current descriptor 2019 * 2020 * Return: dst_ind (REO destination ring ID) 2021 */ 2022 static inline uint32_t 2023 hal_rx_msdu_reo_dst_ind_get(struct hal_soc *hal_soc, void *msdu_link_desc) 2024 { 2025 struct rx_msdu_details *msdu_details; 2026 struct rx_msdu_desc_info *msdu_desc_info; 2027 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 2028 uint32_t dst_ind; 2029 2030 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 2031 2032 /* The first msdu in the link should exsist */ 2033 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 2034 hal_soc); 2035 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 2036 return dst_ind; 2037 } 2038 2039 /** 2040 * hal_rx_reo_buf_paddr_get: Gets the physical address and 2041 * cookie from the REO destination ring element 2042 * 2043 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 2044 * the current descriptor 2045 * @ buf_info: structure to return the buffer information 2046 * Return: void 2047 */ 2048 static inline void hal_rx_reo_buf_paddr_get(void *rx_desc, 2049 struct hal_buf_info *buf_info) 2050 { 2051 struct reo_destination_ring *reo_ring = 2052 (struct reo_destination_ring *)rx_desc; 2053 2054 buf_info->paddr = 2055 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 2056 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 2057 2058 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 2059 } 2060 2061 /** 2062 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 2063 * 2064 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 2065 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 2066 * descriptor 2067 */ 2068 enum hal_rx_reo_buf_type { 2069 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 2070 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 2071 }; 2072 2073 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2074 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 2075 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 2076 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 2077 2078 /** 2079 * enum hal_reo_error_code: Error code describing the type of error detected 2080 * 2081 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 2082 * REO_ENTRANCE ring is set to 0 2083 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 2084 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 2085 * having been setup 2086 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 2087 * Retry bit set: duplicate frame 2088 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 2089 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 2090 * received with 2K jump in SN 2091 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 2092 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 2093 * with SN falling within the OOR window 2094 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 2095 * OOR window 2096 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 2097 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 2098 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 2099 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2100 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 2101 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2102 * of the pn_error_detected_flag been set in the REO Queue descriptor 2103 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 2104 * the queue descriptor(address) being blocked as SW/FW seems to be currently 2105 * in the process of making updates to this descriptor 2106 */ 2107 enum hal_reo_error_code { 2108 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 2109 HAL_REO_ERR_QUEUE_DESC_INVALID, 2110 HAL_REO_ERR_AMPDU_IN_NON_BA, 2111 HAL_REO_ERR_NON_BA_DUPLICATE, 2112 HAL_REO_ERR_BA_DUPLICATE, 2113 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 2114 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 2115 HAL_REO_ERR_REGULAR_FRAME_OOR, 2116 HAL_REO_ERR_BAR_FRAME_OOR, 2117 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 2118 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 2119 HAL_REO_ERR_PN_CHECK_FAILED, 2120 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 2121 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 2122 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 2123 HAL_REO_ERR_MAX 2124 }; 2125 2126 /** 2127 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 2128 * 2129 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 2130 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 2131 * overflow 2132 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 2133 * incomplete 2134 * MPDU from the PHY 2135 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 2136 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 2137 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 2138 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 2139 * encrypted but wasn’t 2140 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 2141 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 2142 * the max allowed 2143 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2144 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2145 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2146 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2147 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2148 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2149 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2150 */ 2151 enum hal_rxdma_error_code { 2152 HAL_RXDMA_ERR_OVERFLOW = 0, 2153 HAL_RXDMA_ERR_MPDU_LENGTH, 2154 HAL_RXDMA_ERR_FCS, 2155 HAL_RXDMA_ERR_DECRYPT, 2156 HAL_RXDMA_ERR_TKIP_MIC, 2157 HAL_RXDMA_ERR_UNENCRYPTED, 2158 HAL_RXDMA_ERR_MSDU_LEN, 2159 HAL_RXDMA_ERR_MSDU_LIMIT, 2160 HAL_RXDMA_ERR_WIFI_PARSE, 2161 HAL_RXDMA_ERR_AMSDU_PARSE, 2162 HAL_RXDMA_ERR_SA_TIMEOUT, 2163 HAL_RXDMA_ERR_DA_TIMEOUT, 2164 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2165 HAL_RXDMA_ERR_FLUSH_REQUEST, 2166 HAL_RXDMA_ERR_WAR = 31, 2167 HAL_RXDMA_ERR_MAX 2168 }; 2169 2170 /** 2171 * HW BM action settings in WBM release ring 2172 */ 2173 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2174 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2175 2176 /** 2177 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2178 * release of this buffer or descriptor 2179 * 2180 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2181 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2182 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2183 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2184 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2185 */ 2186 enum hal_rx_wbm_error_source { 2187 HAL_RX_WBM_ERR_SRC_TQM = 0, 2188 HAL_RX_WBM_ERR_SRC_RXDMA, 2189 HAL_RX_WBM_ERR_SRC_REO, 2190 HAL_RX_WBM_ERR_SRC_FW, 2191 HAL_RX_WBM_ERR_SRC_SW, 2192 }; 2193 2194 /** 2195 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2196 * released 2197 * 2198 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2199 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2200 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2201 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2202 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2203 */ 2204 enum hal_rx_wbm_buf_type { 2205 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2206 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2207 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2208 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2209 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2210 }; 2211 2212 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2213 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2214 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2215 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2216 2217 /** 2218 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2219 * PN check failure 2220 * 2221 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2222 * 2223 * Return: true: error caused by PN check, false: other error 2224 */ 2225 static inline bool hal_rx_reo_is_pn_error(void *rx_desc) 2226 { 2227 struct reo_destination_ring *reo_desc = 2228 (struct reo_destination_ring *)rx_desc; 2229 2230 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2231 HAL_REO_ERR_PN_CHECK_FAILED) | 2232 (HAL_RX_REO_ERROR_GET(reo_desc) == 2233 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2234 true : false; 2235 } 2236 2237 /** 2238 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2239 * the sequence number 2240 * 2241 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2242 * 2243 * Return: true: error caused by 2K jump, false: other error 2244 */ 2245 static inline bool hal_rx_reo_is_2k_jump(void *rx_desc) 2246 { 2247 struct reo_destination_ring *reo_desc = 2248 (struct reo_destination_ring *)rx_desc; 2249 2250 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2251 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2252 (HAL_RX_REO_ERROR_GET(reo_desc) == 2253 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2254 true : false; 2255 } 2256 2257 /** 2258 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2259 * 2260 * @ soc : HAL version of the SOC pointer 2261 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2262 * @ buf_addr_info : void pointer to the buffer_addr_info 2263 * @ bm_action : put in IDLE list or release to MSDU_LIST 2264 * 2265 * Return: void 2266 */ 2267 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2268 static inline void hal_rx_msdu_link_desc_set(struct hal_soc *soc, 2269 void *src_srng_desc, void *buf_addr_info, 2270 uint8_t bm_action) 2271 { 2272 struct wbm_release_ring *wbm_rel_srng = 2273 (struct wbm_release_ring *)src_srng_desc; 2274 2275 /* Structure copy !!! */ 2276 wbm_rel_srng->released_buff_or_desc_addr_info = 2277 *((struct buffer_addr_info *)buf_addr_info); 2278 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2279 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2280 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2281 bm_action); 2282 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2283 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2284 } 2285 2286 /* 2287 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2288 * REO entrance ring 2289 * 2290 * @ soc: HAL version of the SOC pointer 2291 * @ pa: Physical address of the MSDU Link Descriptor 2292 * @ cookie: SW cookie to get to the virtual address 2293 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2294 * to the error enabled REO queue 2295 * 2296 * Return: void 2297 */ 2298 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2299 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2300 { 2301 /* TODO */ 2302 } 2303 2304 /** 2305 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2306 * BUFFER_ADDR_INFO, give the RX descriptor 2307 * (Assumption -- BUFFER_ADDR_INFO is the 2308 * first field in the descriptor structure) 2309 */ 2310 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) ((void *)(ring_desc)) 2311 2312 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2313 2314 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2315 2316 /** 2317 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2318 * from the BUFFER_ADDR_INFO structure 2319 * given a REO destination ring descriptor. 2320 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2321 * 2322 * Return: uint8_t (value of the return_buffer_manager) 2323 */ 2324 static inline 2325 uint8_t hal_rx_ret_buf_manager_get(void *ring_desc) 2326 { 2327 /* 2328 * The following macro takes buf_addr_info as argument, 2329 * but since buf_addr_info is the first field in ring_desc 2330 * Hence the following call is OK 2331 */ 2332 return HAL_RX_BUF_RBM_GET(ring_desc); 2333 } 2334 2335 2336 /******************************************************************************* 2337 * RX WBM ERROR APIS 2338 ******************************************************************************/ 2339 2340 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2341 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 2342 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 2343 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 2344 2345 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2346 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2347 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2348 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2349 2350 /** 2351 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2352 * the frame to this release ring 2353 * 2354 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2355 * frame to this queue 2356 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2357 * received routing instructions. No error within REO was detected 2358 */ 2359 enum hal_rx_wbm_reo_push_reason { 2360 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2361 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2362 }; 2363 2364 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2365 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 2366 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 2367 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 2368 2369 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2370 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 2371 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 2372 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 2373 2374 /** 2375 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2376 * this release ring 2377 * 2378 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2379 * this frame to this queue 2380 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2381 * per received routing instructions. No error within RXDMA was detected 2382 */ 2383 enum hal_rx_wbm_rxdma_push_reason { 2384 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2385 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2386 }; 2387 2388 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 2389 (((*(((uint32_t *) wbm_desc) + \ 2390 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 2391 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 2392 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 2393 2394 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 2395 (((*(((uint32_t *) wbm_desc) + \ 2396 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 2397 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 2398 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 2399 2400 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2401 (((*(((uint32_t *) wbm_desc) + \ 2402 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2403 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2404 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2405 2406 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2407 (((*(((uint32_t *) wbm_desc) + \ 2408 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2409 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2410 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2411 2412 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2413 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2414 wbm_desc)->released_buff_or_desc_addr_info) 2415 2416 /** 2417 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2418 * humman readable format. 2419 * @ rx_attn: pointer the rx_attention TLV in pkt. 2420 * @ dbg_level: log level. 2421 * 2422 * Return: void 2423 */ 2424 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2425 uint8_t dbg_level) 2426 { 2427 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2428 "rx_attention tlv=" 2429 "rxpcu_mpdu_filter_in_category: %d " 2430 "sw_frame_group_id: %d " 2431 "reserved_0: %d " 2432 "phy_ppdu_id: %d " 2433 "first_mpdu : %d " 2434 "reserved_1a: %d " 2435 "mcast_bcast: %d " 2436 "ast_index_not_found: %d " 2437 "ast_index_timeout: %d " 2438 "power_mgmt: %d " 2439 "non_qos: %d " 2440 "null_data: %d " 2441 "mgmt_type: %d " 2442 "ctrl_type: %d " 2443 "more_data: %d " 2444 "eosp: %d " 2445 "a_msdu_error: %d " 2446 "fragment_flag: %d " 2447 "order: %d " 2448 "cce_match: %d " 2449 "overflow_err: %d " 2450 "msdu_length_err: %d " 2451 "tcp_udp_chksum_fail: %d " 2452 "ip_chksum_fail: %d " 2453 "sa_idx_invalid: %d " 2454 "da_idx_invalid: %d " 2455 "reserved_1b: %d " 2456 "rx_in_tx_decrypt_byp: %d " 2457 "encrypt_required: %d " 2458 "directed: %d " 2459 "buffer_fragment: %d " 2460 "mpdu_length_err: %d " 2461 "tkip_mic_err: %d " 2462 "decrypt_err: %d " 2463 "unencrypted_frame_err: %d " 2464 "fcs_err: %d " 2465 "flow_idx_timeout: %d " 2466 "flow_idx_invalid: %d " 2467 "wifi_parser_error: %d " 2468 "amsdu_parser_error: %d " 2469 "sa_idx_timeout: %d " 2470 "da_idx_timeout: %d " 2471 "msdu_limit_error: %d " 2472 "da_is_valid: %d " 2473 "da_is_mcbc: %d " 2474 "sa_is_valid: %d " 2475 "decrypt_status_code: %d " 2476 "rx_bitmap_not_updated: %d " 2477 "reserved_2: %d " 2478 "msdu_done: %d ", 2479 rx_attn->rxpcu_mpdu_filter_in_category, 2480 rx_attn->sw_frame_group_id, 2481 rx_attn->reserved_0, 2482 rx_attn->phy_ppdu_id, 2483 rx_attn->first_mpdu, 2484 rx_attn->reserved_1a, 2485 rx_attn->mcast_bcast, 2486 rx_attn->ast_index_not_found, 2487 rx_attn->ast_index_timeout, 2488 rx_attn->power_mgmt, 2489 rx_attn->non_qos, 2490 rx_attn->null_data, 2491 rx_attn->mgmt_type, 2492 rx_attn->ctrl_type, 2493 rx_attn->more_data, 2494 rx_attn->eosp, 2495 rx_attn->a_msdu_error, 2496 rx_attn->fragment_flag, 2497 rx_attn->order, 2498 rx_attn->cce_match, 2499 rx_attn->overflow_err, 2500 rx_attn->msdu_length_err, 2501 rx_attn->tcp_udp_chksum_fail, 2502 rx_attn->ip_chksum_fail, 2503 rx_attn->sa_idx_invalid, 2504 rx_attn->da_idx_invalid, 2505 rx_attn->reserved_1b, 2506 rx_attn->rx_in_tx_decrypt_byp, 2507 rx_attn->encrypt_required, 2508 rx_attn->directed, 2509 rx_attn->buffer_fragment, 2510 rx_attn->mpdu_length_err, 2511 rx_attn->tkip_mic_err, 2512 rx_attn->decrypt_err, 2513 rx_attn->unencrypted_frame_err, 2514 rx_attn->fcs_err, 2515 rx_attn->flow_idx_timeout, 2516 rx_attn->flow_idx_invalid, 2517 rx_attn->wifi_parser_error, 2518 rx_attn->amsdu_parser_error, 2519 rx_attn->sa_idx_timeout, 2520 rx_attn->da_idx_timeout, 2521 rx_attn->msdu_limit_error, 2522 rx_attn->da_is_valid, 2523 rx_attn->da_is_mcbc, 2524 rx_attn->sa_is_valid, 2525 rx_attn->decrypt_status_code, 2526 rx_attn->rx_bitmap_not_updated, 2527 rx_attn->reserved_2, 2528 rx_attn->msdu_done); 2529 2530 2531 } 2532 2533 /** 2534 * hal_rx_dump_mpdu_start_tlv: dump RX mpdu_start TLV in structured 2535 * human readable format. 2536 * @ mpdu_start: pointer the rx_attention TLV in pkt. 2537 * @ dbg_level: log level. 2538 * 2539 * Return: void 2540 */ 2541 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2542 uint8_t dbg_level) 2543 { 2544 struct rx_mpdu_info *mpdu_info = 2545 (struct rx_mpdu_info *) &mpdu_start->rx_mpdu_info_details; 2546 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2547 "rx_mpdu_start tlv - " 2548 "rxpcu_mpdu_filter_in_category: %d " 2549 "sw_frame_group_id: %d " 2550 "ndp_frame: %d " 2551 "phy_err: %d " 2552 "phy_err_during_mpdu_header: %d " 2553 "protocol_version_err: %d " 2554 "ast_based_lookup_valid: %d " 2555 "phy_ppdu_id: %d " 2556 "ast_index: %d " 2557 "sw_peer_id: %d " 2558 "mpdu_frame_control_valid: %d " 2559 "mpdu_duration_valid: %d " 2560 "mac_addr_ad1_valid: %d " 2561 "mac_addr_ad2_valid: %d " 2562 "mac_addr_ad3_valid: %d " 2563 "mac_addr_ad4_valid: %d " 2564 "mpdu_sequence_control_valid: %d " 2565 "mpdu_qos_control_valid: %d " 2566 "mpdu_ht_control_valid: %d " 2567 "frame_encryption_info_valid: %d " 2568 "fr_ds: %d " 2569 "to_ds: %d " 2570 "encrypted: %d " 2571 "mpdu_retry: %d " 2572 "mpdu_sequence_number: %d " 2573 "epd_en: %d " 2574 "all_frames_shall_be_encrypted: %d " 2575 "encrypt_type: %d " 2576 "mesh_sta: %d " 2577 "bssid_hit: %d " 2578 "bssid_number: %d " 2579 "tid: %d " 2580 "pn_31_0: %d " 2581 "pn_63_32: %d " 2582 "pn_95_64: %d " 2583 "pn_127_96: %d " 2584 "peer_meta_data: %d " 2585 "rxpt_classify_info.reo_destination_indication: %d " 2586 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %d " 2587 "rx_reo_queue_desc_addr_31_0: %d " 2588 "rx_reo_queue_desc_addr_39_32: %d " 2589 "receive_queue_number: %d " 2590 "pre_delim_err_warning: %d " 2591 "first_delim_err: %d " 2592 "key_id_octet: %d " 2593 "new_peer_entry: %d " 2594 "decrypt_needed: %d " 2595 "decap_type: %d " 2596 "rx_insert_vlan_c_tag_padding: %d " 2597 "rx_insert_vlan_s_tag_padding: %d " 2598 "strip_vlan_c_tag_decap: %d " 2599 "strip_vlan_s_tag_decap: %d " 2600 "pre_delim_count: %d " 2601 "ampdu_flag: %d " 2602 "bar_frame: %d " 2603 "mpdu_length: %d " 2604 "first_mpdu: %d " 2605 "mcast_bcast: %d " 2606 "ast_index_not_found: %d " 2607 "ast_index_timeout: %d " 2608 "power_mgmt: %d " 2609 "non_qos: %d " 2610 "null_data: %d " 2611 "mgmt_type: %d " 2612 "ctrl_type: %d " 2613 "more_data: %d " 2614 "eosp: %d " 2615 "fragment_flag: %d " 2616 "order: %d " 2617 "u_apsd_trigger: %d " 2618 "encrypt_required: %d " 2619 "directed: %d " 2620 "mpdu_frame_control_field: %d " 2621 "mpdu_duration_field: %d " 2622 "mac_addr_ad1_31_0: %d " 2623 "mac_addr_ad1_47_32: %d " 2624 "mac_addr_ad2_15_0: %d " 2625 "mac_addr_ad2_47_16: %d " 2626 "mac_addr_ad3_31_0: %d " 2627 "mac_addr_ad3_47_32: %d " 2628 "mpdu_sequence_control_field: %d " 2629 "mac_addr_ad4_31_0: %d " 2630 "mac_addr_ad4_47_32: %d " 2631 "mpdu_qos_control_field: %d " 2632 "mpdu_ht_control_field: %d ", 2633 mpdu_info->rxpcu_mpdu_filter_in_category, 2634 mpdu_info->sw_frame_group_id, 2635 mpdu_info->ndp_frame, 2636 mpdu_info->phy_err, 2637 mpdu_info->phy_err_during_mpdu_header, 2638 mpdu_info->protocol_version_err, 2639 mpdu_info->ast_based_lookup_valid, 2640 mpdu_info->phy_ppdu_id, 2641 mpdu_info->ast_index, 2642 mpdu_info->sw_peer_id, 2643 mpdu_info->mpdu_frame_control_valid, 2644 mpdu_info->mpdu_duration_valid, 2645 mpdu_info->mac_addr_ad1_valid, 2646 mpdu_info->mac_addr_ad2_valid, 2647 mpdu_info->mac_addr_ad3_valid, 2648 mpdu_info->mac_addr_ad4_valid, 2649 mpdu_info->mpdu_sequence_control_valid, 2650 mpdu_info->mpdu_qos_control_valid, 2651 mpdu_info->mpdu_ht_control_valid, 2652 mpdu_info->frame_encryption_info_valid, 2653 mpdu_info->fr_ds, 2654 mpdu_info->to_ds, 2655 mpdu_info->encrypted, 2656 mpdu_info->mpdu_retry, 2657 mpdu_info->mpdu_sequence_number, 2658 mpdu_info->epd_en, 2659 mpdu_info->all_frames_shall_be_encrypted, 2660 mpdu_info->encrypt_type, 2661 mpdu_info->mesh_sta, 2662 mpdu_info->bssid_hit, 2663 mpdu_info->bssid_number, 2664 mpdu_info->tid, 2665 mpdu_info->pn_31_0, 2666 mpdu_info->pn_63_32, 2667 mpdu_info->pn_95_64, 2668 mpdu_info->pn_127_96, 2669 mpdu_info->peer_meta_data, 2670 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 2671 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 2672 mpdu_info->rx_reo_queue_desc_addr_31_0, 2673 mpdu_info->rx_reo_queue_desc_addr_39_32, 2674 mpdu_info->receive_queue_number, 2675 mpdu_info->pre_delim_err_warning, 2676 mpdu_info->first_delim_err, 2677 mpdu_info->key_id_octet, 2678 mpdu_info->new_peer_entry, 2679 mpdu_info->decrypt_needed, 2680 mpdu_info->decap_type, 2681 mpdu_info->rx_insert_vlan_c_tag_padding, 2682 mpdu_info->rx_insert_vlan_s_tag_padding, 2683 mpdu_info->strip_vlan_c_tag_decap, 2684 mpdu_info->strip_vlan_s_tag_decap, 2685 mpdu_info->pre_delim_count, 2686 mpdu_info->ampdu_flag, 2687 mpdu_info->bar_frame, 2688 mpdu_info->mpdu_length, 2689 mpdu_info->first_mpdu, 2690 mpdu_info->mcast_bcast, 2691 mpdu_info->ast_index_not_found, 2692 mpdu_info->ast_index_timeout, 2693 mpdu_info->power_mgmt, 2694 mpdu_info->non_qos, 2695 mpdu_info->null_data, 2696 mpdu_info->mgmt_type, 2697 mpdu_info->ctrl_type, 2698 mpdu_info->more_data, 2699 mpdu_info->eosp, 2700 mpdu_info->fragment_flag, 2701 mpdu_info->order, 2702 mpdu_info->u_apsd_trigger, 2703 mpdu_info->encrypt_required, 2704 mpdu_info->directed, 2705 mpdu_info->mpdu_frame_control_field, 2706 mpdu_info->mpdu_duration_field, 2707 mpdu_info->mac_addr_ad1_31_0, 2708 mpdu_info->mac_addr_ad1_47_32, 2709 mpdu_info->mac_addr_ad2_15_0, 2710 mpdu_info->mac_addr_ad2_47_16, 2711 mpdu_info->mac_addr_ad3_31_0, 2712 mpdu_info->mac_addr_ad3_47_32, 2713 mpdu_info->mpdu_sequence_control_field, 2714 mpdu_info->mac_addr_ad4_31_0, 2715 mpdu_info->mac_addr_ad4_47_32, 2716 mpdu_info->mpdu_qos_control_field, 2717 mpdu_info->mpdu_ht_control_field); 2718 } 2719 2720 /** 2721 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2722 * human readable format. 2723 * @ msdu_end: pointer the msdu_end TLV in pkt. 2724 * @ dbg_level: log level. 2725 * 2726 * Return: void 2727 */ 2728 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2729 struct rx_msdu_end *msdu_end, 2730 uint8_t dbg_level) 2731 { 2732 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2733 } 2734 2735 /** 2736 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2737 * human readable format. 2738 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2739 * @ dbg_level: log level. 2740 * 2741 * Return: void 2742 */ 2743 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2744 uint8_t dbg_level) 2745 { 2746 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2747 "rx_mpdu_end tlv - " 2748 "rxpcu_mpdu_filter_in_category: %d " 2749 "sw_frame_group_id: %d " 2750 "phy_ppdu_id: %d " 2751 "unsup_ktype_short_frame: %d " 2752 "rx_in_tx_decrypt_byp: %d " 2753 "overflow_err: %d " 2754 "mpdu_length_err: %d " 2755 "tkip_mic_err: %d " 2756 "decrypt_err: %d " 2757 "unencrypted_frame_err: %d " 2758 "pn_fields_contain_valid_info: %d " 2759 "fcs_err: %d " 2760 "msdu_length_err: %d " 2761 "rxdma0_destination_ring: %d " 2762 "rxdma1_destination_ring: %d " 2763 "decrypt_status_code: %d " 2764 "rx_bitmap_not_updated: %d ", 2765 mpdu_end->rxpcu_mpdu_filter_in_category, 2766 mpdu_end->sw_frame_group_id, 2767 mpdu_end->phy_ppdu_id, 2768 mpdu_end->unsup_ktype_short_frame, 2769 mpdu_end->rx_in_tx_decrypt_byp, 2770 mpdu_end->overflow_err, 2771 mpdu_end->mpdu_length_err, 2772 mpdu_end->tkip_mic_err, 2773 mpdu_end->decrypt_err, 2774 mpdu_end->unencrypted_frame_err, 2775 mpdu_end->pn_fields_contain_valid_info, 2776 mpdu_end->fcs_err, 2777 mpdu_end->msdu_length_err, 2778 mpdu_end->rxdma0_destination_ring, 2779 mpdu_end->rxdma1_destination_ring, 2780 mpdu_end->decrypt_status_code, 2781 mpdu_end->rx_bitmap_not_updated); 2782 } 2783 2784 /** 2785 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2786 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2787 * @ dbg_level: log level. 2788 * 2789 * Return: void 2790 */ 2791 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_hdr_tlv *pkt_hdr_tlv, 2792 uint8_t dbg_level) 2793 { 2794 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2795 "\n---------------\n" 2796 "rx_pkt_hdr_tlv \n" 2797 "---------------\n" 2798 "phy_ppdu_id %d ", 2799 pkt_hdr_tlv->phy_ppdu_id); 2800 2801 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, dbg_level, 2802 pkt_hdr_tlv->rx_pkt_hdr, 128); 2803 } 2804 2805 /** 2806 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2807 * structure 2808 * @hal_ring: pointer to hal_srng structure 2809 * 2810 * Return: ring_id 2811 */ 2812 static inline uint8_t hal_srng_ring_id_get(void *hal_ring) 2813 { 2814 return ((struct hal_srng *)hal_ring)->ring_id; 2815 } 2816 2817 /* Rx MSDU link pointer info */ 2818 struct hal_rx_msdu_link_ptr_info { 2819 struct rx_msdu_link msdu_link; 2820 struct hal_buf_info msdu_link_buf_info; 2821 }; 2822 2823 /** 2824 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2825 * 2826 * @nbuf: Pointer to data buffer field 2827 * Returns: pointer to rx_pkt_tlvs 2828 */ 2829 static inline 2830 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2831 { 2832 return (struct rx_pkt_tlvs *)rx_buf_start; 2833 } 2834 2835 /** 2836 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2837 * 2838 * @pkt_tlvs: Pointer to pkt_tlvs 2839 * Returns: pointer to rx_mpdu_info structure 2840 */ 2841 static inline 2842 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2843 { 2844 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2845 } 2846 2847 /** 2848 * hal_rx_get_rx_sequence(): Function to retrieve rx sequence number 2849 * 2850 * @nbuf: Network buffer 2851 * Returns: rx sequence number 2852 */ 2853 #define DOT11_SEQ_FRAG_MASK 0x000f 2854 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2855 2856 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 2857 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2858 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 2859 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 2860 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 2861 static inline 2862 uint16_t hal_rx_get_rx_sequence(uint8_t *buf) 2863 { 2864 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2865 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2866 uint16_t seq_number = 0; 2867 2868 seq_number = 2869 HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) >> 4; 2870 2871 /* Skip first 4-bits for fragment number */ 2872 return seq_number; 2873 } 2874 2875 /** 2876 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2877 * 2878 * @nbuf: Network buffer 2879 * Returns: rx fragment number 2880 */ 2881 static inline 2882 uint8_t hal_rx_get_rx_fragment_number(uint8_t *buf) 2883 { 2884 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2885 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2886 uint8_t frag_number = 0; 2887 2888 frag_number = HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 2889 DOT11_SEQ_FRAG_MASK; 2890 2891 /* Return first 4 bits as fragment number */ 2892 return frag_number; 2893 } 2894 2895 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2896 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2897 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2898 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2899 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2900 /** 2901 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2902 * 2903 * @nbuf: Network buffer 2904 * Returns: rx more fragment bit 2905 */ 2906 static inline 2907 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2908 { 2909 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2910 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2911 uint16_t frame_ctrl = 0; 2912 2913 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2914 DOT11_FC1_MORE_FRAG_OFFSET; 2915 2916 /* more fragment bit if at offset bit 4 */ 2917 return frame_ctrl; 2918 } 2919 2920 /** 2921 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2922 * 2923 * @nbuf: Network buffer 2924 * Returns: rx more fragment bit 2925 * 2926 */ 2927 static inline 2928 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2929 { 2930 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2931 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2932 uint16_t frame_ctrl = 0; 2933 2934 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2935 2936 return frame_ctrl; 2937 } 2938 2939 /* 2940 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2941 * 2942 * @nbuf: Network buffer 2943 * Returns: flag to indicate whether the nbuf has MC/BC address 2944 */ 2945 static inline 2946 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2947 { 2948 uint8 *buf = qdf_nbuf_data(nbuf); 2949 2950 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2951 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2952 2953 return rx_attn->mcast_bcast; 2954 } 2955 2956 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 2957 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2958 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 2959 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 2960 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 2961 /* 2962 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2963 * 2964 * @nbuf: Network buffer 2965 * Returns: value of sequence control valid field 2966 */ 2967 static inline 2968 uint8_t hal_rx_get_mpdu_sequence_control_valid(uint8_t *buf) 2969 { 2970 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2971 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2972 uint8_t seq_ctrl_valid = 0; 2973 2974 seq_ctrl_valid = 2975 HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 2976 2977 return seq_ctrl_valid; 2978 } 2979 2980 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 2981 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2982 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 2983 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 2984 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 2985 /* 2986 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2987 * 2988 * @nbuf: Network buffer 2989 * Returns: value of frame control valid field 2990 */ 2991 static inline 2992 uint8_t hal_rx_get_mpdu_frame_control_valid(uint8_t *buf) 2993 { 2994 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2995 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2996 uint8_t frm_ctrl_valid = 0; 2997 2998 frm_ctrl_valid = 2999 HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 3000 3001 return frm_ctrl_valid; 3002 } 3003 3004 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 3005 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 3006 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 3007 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 3008 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 3009 /* 3010 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 3011 * 3012 * @nbuf: Network buffer 3013 * Returns: value of mpdu 4th address valid field 3014 */ 3015 static inline 3016 bool hal_rx_get_mpdu_mac_ad4_valid(uint8_t *buf) 3017 { 3018 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 3019 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 3020 bool ad4_valid = 0; 3021 3022 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 3023 3024 return ad4_valid; 3025 } 3026 3027 /* 3028 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 3029 * 3030 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 3031 * Returns: None 3032 */ 3033 static inline 3034 void hal_rx_clear_mpdu_desc_info( 3035 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 3036 { 3037 qdf_mem_zero(rx_mpdu_desc_info, 3038 sizeof(*rx_mpdu_desc_info)); 3039 } 3040 3041 /* 3042 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 3043 * 3044 * @msdu_link_ptr: HAL view of msdu link ptr 3045 * @size: number of msdu link pointers 3046 * Returns: None 3047 */ 3048 static inline 3049 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 3050 int size) 3051 { 3052 qdf_mem_zero(msdu_link_ptr, 3053 (sizeof(*msdu_link_ptr) * size)); 3054 } 3055 3056 /* 3057 * hal_rx_chain_msdu_links() - Chains msdu link pointers 3058 * @msdu_link_ptr: msdu link pointer 3059 * @mpdu_desc_info: mpdu descriptor info 3060 * 3061 * Build a list of msdus using msdu link pointer. If the 3062 * number of msdus are more, chain them together 3063 * 3064 * Returns: Number of processed msdus 3065 */ 3066 static inline 3067 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 3068 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 3069 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 3070 { 3071 int j; 3072 struct rx_msdu_link *msdu_link_ptr = 3073 &msdu_link_ptr_info->msdu_link; 3074 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 3075 struct rx_msdu_details *msdu_details = 3076 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 3077 uint8_t num_msdus = mpdu_desc_info->msdu_count; 3078 struct rx_msdu_desc_info *msdu_desc_info; 3079 uint8_t fragno, more_frag; 3080 uint8_t *rx_desc_info; 3081 struct hal_rx_msdu_list msdu_list; 3082 3083 for (j = 0; j < num_msdus; j++) { 3084 msdu_desc_info = 3085 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 3086 hal_soc); 3087 msdu_list.msdu_info[j].msdu_flags = 3088 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 3089 msdu_list.msdu_info[j].msdu_len = 3090 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 3091 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 3092 &msdu_details[j].buffer_addr_info_details); 3093 } 3094 3095 /* Chain msdu links together */ 3096 if (prev_msdu_link_ptr) { 3097 /* 31-0 bits of the physical address */ 3098 prev_msdu_link_ptr-> 3099 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 3100 msdu_link_ptr_info->msdu_link_buf_info.paddr & 3101 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 3102 /* 39-32 bits of the physical address */ 3103 prev_msdu_link_ptr-> 3104 next_msdu_link_desc_addr_info.buffer_addr_39_32 3105 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 3106 >> 32) && 3107 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 3108 prev_msdu_link_ptr-> 3109 next_msdu_link_desc_addr_info.sw_buffer_cookie = 3110 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 3111 } 3112 3113 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 3114 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 3115 /* mark first and last MSDUs */ 3116 rx_desc_info = qdf_nbuf_data(msdu); 3117 fragno = hal_rx_get_rx_fragment_number(rx_desc_info); 3118 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 3119 3120 /* TODO: create skb->fragslist[] */ 3121 3122 if (more_frag == 0) { 3123 msdu_list.msdu_info[num_msdus].msdu_flags |= 3124 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 3125 } else if (fragno == 1) { 3126 msdu_list.msdu_info[num_msdus].msdu_flags |= 3127 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 3128 3129 msdu_list.msdu_info[num_msdus].msdu_flags |= 3130 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 3131 } 3132 3133 num_msdus++; 3134 3135 /* Number of MSDUs per mpdu descriptor is updated */ 3136 mpdu_desc_info->msdu_count += num_msdus; 3137 } else { 3138 num_msdus = 0; 3139 prev_msdu_link_ptr = msdu_link_ptr; 3140 } 3141 3142 return num_msdus; 3143 } 3144 3145 /* 3146 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 3147 * 3148 * @ring_desc: HAL view of ring descriptor 3149 * @mpdu_des_info: saved mpdu desc info 3150 * @msdu_link_ptr: saved msdu link ptr 3151 * 3152 * API used explicitly for rx defrag to update ring desc with 3153 * mpdu desc info and msdu link ptr before reinjecting the 3154 * packet back to REO 3155 * 3156 * Returns: None 3157 */ 3158 static inline 3159 void hal_rx_defrag_update_src_ring_desc(void *ring_desc, 3160 void *saved_mpdu_desc_info, 3161 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 3162 { 3163 struct reo_entrance_ring *reo_ent_ring; 3164 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 3165 struct hal_buf_info buf_info; 3166 3167 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 3168 reo_ring_mpdu_desc_info = &reo_ent_ring-> 3169 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 3170 3171 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 3172 sizeof(*reo_ring_mpdu_desc_info)); 3173 3174 /* 3175 * TODO: Check for additional fields that need configuration in 3176 * reo_ring_mpdu_desc_info 3177 */ 3178 3179 /* Update msdu_link_ptr in the reo entrance ring */ 3180 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 3181 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 3182 buf_info.sw_cookie = 3183 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 3184 } 3185 3186 /* 3187 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 3188 * 3189 * @msdu_link_desc_va: msdu link descriptor handle 3190 * @msdu_link_ptr_info: HAL view of msdu link pointer info 3191 * 3192 * API used to save msdu link information along with physical 3193 * address. The API also copues the sw cookie. 3194 * 3195 * Returns: None 3196 */ 3197 static inline 3198 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 3199 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 3200 struct hal_buf_info *hbi) 3201 { 3202 struct rx_msdu_link *msdu_link_ptr = 3203 (struct rx_msdu_link *)msdu_link_desc_va; 3204 3205 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 3206 sizeof(struct rx_msdu_link)); 3207 3208 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 3209 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 3210 } 3211 3212 /* 3213 * hal_rx_get_desc_len(): Returns rx descriptor length 3214 * 3215 * Returns the size of rx_pkt_tlvs which follows the 3216 * data in the nbuf 3217 * 3218 * Returns: Length of rx descriptor 3219 */ 3220 static inline 3221 uint16_t hal_rx_get_desc_len(void) 3222 { 3223 return sizeof(struct rx_pkt_tlvs); 3224 } 3225 3226 /* 3227 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 3228 * reo_entrance_ring descriptor 3229 * 3230 * @reo_ent_desc: reo_entrance_ring descriptor 3231 * Returns: value of rxdma_push_reason 3232 */ 3233 static inline 3234 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(void *reo_ent_desc) 3235 { 3236 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3237 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 3238 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 3239 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 3240 } 3241 3242 /** 3243 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 3244 * reo_entrance_ring descriptor 3245 * @reo_ent_desc: reo_entrance_ring descriptor 3246 * Return: value of rxdma_error_code 3247 */ 3248 static inline 3249 uint8_t hal_rx_reo_ent_rxdma_error_code_get(void *reo_ent_desc) 3250 { 3251 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3252 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 3253 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 3254 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 3255 } 3256 3257 /** 3258 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 3259 * save it to hal_wbm_err_desc_info structure passed by caller 3260 * @wbm_desc: wbm ring descriptor 3261 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3262 * Return: void 3263 */ 3264 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 3265 struct hal_wbm_err_desc_info *wbm_er_info) 3266 { 3267 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 3268 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 3269 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 3270 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 3271 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 3272 } 3273 3274 /** 3275 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 3276 * the reserved bytes of rx_tlv_hdr 3277 * @buf: start of rx_tlv_hdr 3278 * @wbm_er_info: hal_wbm_err_desc_info structure 3279 * Return: void 3280 */ 3281 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 3282 struct hal_wbm_err_desc_info *wbm_er_info) 3283 { 3284 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3285 3286 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 3287 sizeof(struct hal_wbm_err_desc_info)); 3288 } 3289 3290 /** 3291 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 3292 * the reserved bytes of rx_tlv_hdr. 3293 * @buf: start of rx_tlv_hdr 3294 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3295 * Return: void 3296 */ 3297 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 3298 struct hal_wbm_err_desc_info *wbm_er_info) 3299 { 3300 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3301 3302 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 3303 sizeof(struct hal_wbm_err_desc_info)); 3304 } 3305 3306 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 3307 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 3308 RX_MSDU_START_5_NSS_OFFSET)), \ 3309 RX_MSDU_START_5_NSS_MASK, \ 3310 RX_MSDU_START_5_NSS_LSB)) 3311 3312 /** 3313 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 3314 * 3315 * @ hal_soc: HAL version of the SOC pointer 3316 * @ hw_desc_addr: Start address of Rx HW TLVs 3317 * @ rs: Status for monitor mode 3318 * 3319 * Return: void 3320 */ 3321 static inline void hal_rx_mon_hw_desc_get_mpdu_status(struct hal_soc *hal_soc, 3322 void *hw_desc_addr, 3323 struct mon_rx_status *rs) 3324 { 3325 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 3326 } 3327 3328 /* 3329 * hal_rx_get_tlv(): API to get the tlv 3330 * 3331 * @hal_soc: HAL version of the SOC pointer 3332 * @rx_tlv: TLV data extracted from the rx packet 3333 * Return: uint8_t 3334 */ 3335 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 3336 { 3337 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 3338 } 3339 3340 /* 3341 * hal_rx_msdu_start_nss_get(): API to get the NSS 3342 * Interval from rx_msdu_start 3343 * 3344 * @hal_soc: HAL version of the SOC pointer 3345 * @buf: pointer to the start of RX PKT TLV header 3346 * Return: uint32_t(nss) 3347 */ 3348 static inline uint32_t hal_rx_msdu_start_nss_get(struct hal_soc *hal_soc, 3349 uint8_t *buf) 3350 { 3351 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3352 } 3353 3354 /** 3355 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3356 * human readable format. 3357 * @ msdu_start: pointer the msdu_start TLV in pkt. 3358 * @ dbg_level: log level. 3359 * 3360 * Return: void 3361 */ 3362 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3363 struct rx_msdu_start *msdu_start, 3364 uint8_t dbg_level) 3365 { 3366 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3367 } 3368 3369 /** 3370 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3371 * info details 3372 * 3373 * @ buf - Pointer to buffer containing rx pkt tlvs. 3374 * 3375 * 3376 */ 3377 static inline uint32_t hal_rx_mpdu_start_tid_get(struct hal_soc *hal_soc, 3378 uint8_t *buf) 3379 { 3380 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3381 } 3382 3383 /* 3384 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3385 * Interval from rx_msdu_start 3386 * 3387 * @buf: pointer to the start of RX PKT TLV header 3388 * Return: uint32_t(reception_type) 3389 */ 3390 static inline 3391 uint32_t hal_rx_msdu_start_reception_type_get(struct hal_soc *hal_soc, 3392 uint8_t *buf) 3393 { 3394 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3395 } 3396 3397 /** 3398 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3399 * RX TLVs 3400 * @ buf: pointer the pkt buffer. 3401 * @ dbg_level: log level. 3402 * 3403 * Return: void 3404 */ 3405 static inline void hal_rx_dump_pkt_tlvs(struct hal_soc *hal_soc, 3406 uint8_t *buf, uint8_t dbg_level) 3407 { 3408 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3409 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3410 struct rx_mpdu_start *mpdu_start = 3411 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3412 struct rx_msdu_start *msdu_start = 3413 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3414 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3415 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3416 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 3417 3418 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3419 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 3420 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3421 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3422 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3423 hal_rx_dump_pkt_hdr_tlv(pkt_hdr_tlv, dbg_level); 3424 } 3425 3426 3427 /** 3428 * hal_reo_status_get_header_generic - Process reo desc info 3429 * @d - Pointer to reo descriptior 3430 * @b - tlv type info 3431 * @h - Pointer to hal_reo_status_header where info to be stored 3432 * @hal- pointer to hal_soc structure 3433 * Return - none. 3434 * 3435 */ 3436 static inline void hal_reo_status_get_header(uint32_t *d, int b, 3437 void *h, void *hal) 3438 { 3439 struct hal_soc *hal_soc = (struct hal_soc *)hal; 3440 3441 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3442 } 3443 3444 #endif /* _HAL_RX_H */ 3445