1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 #include "hal_rx_hw_defines.h" 24 #include "hal_hw_headers.h" 25 26 /************************************* 27 * Ring desc offset/shift/masks 28 *************************************/ 29 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 30 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 31 #define HAL_RX_LSB(block, field) block##_##field##_LSB 32 #define HAL_RX_MASK(block, field) block##_##field##_MASK 33 34 #define HAL_RX_GET(_ptr, block, field) \ 35 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 36 HAL_RX_MASK(block, field)) >> \ 37 HAL_RX_LSB(block, field)) 38 39 #define HAL_RX_GET_64(_ptr, block, field) \ 40 (((*((volatile uint64_t *)(_ptr) + \ 41 (HAL_RX_OFFSET(block, field) >> 3))) & \ 42 HAL_RX_MASK(block, field)) >> \ 43 HAL_RX_LSB(block, field)) 44 45 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 46 (*(uint32_t *)(((uint8_t *)_ptr) + \ 47 _wrd ## _ ## _field ## _OFFSET) |= \ 48 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 49 _wrd ## _ ## _field ## _MASK)) 50 51 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 52 #ifndef RX_DATA_BUFFER_SIZE 53 #define RX_DATA_BUFFER_SIZE 2048 54 #endif 55 56 #ifndef RX_MONITOR_BUFFER_SIZE 57 #define RX_MONITOR_BUFFER_SIZE 2048 58 #endif 59 60 #define RXDMA_OPTIMIZATION 61 62 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 63 * including buffer reservation, buffer alignment and skb shared info size. 64 */ 65 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 66 #define RX_MON_STATUS_BUF_ALIGN 128 67 #define RX_MON_STATUS_BUF_RESERVATION 128 68 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 69 (RX_MON_STATUS_BUF_RESERVATION + \ 70 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 71 72 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 73 74 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 75 #define HAL_RX_NON_QOS_TID 16 76 77 enum { 78 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 79 HAL_HW_RX_DECAP_FORMAT_NWIFI, 80 HAL_HW_RX_DECAP_FORMAT_ETH2, 81 HAL_HW_RX_DECAP_FORMAT_8023, 82 }; 83 84 /** 85 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 86 * 87 * @reo_psh_rsn: REO push reason 88 * @reo_err_code: REO Error code 89 * @rxdma_psh_rsn: RXDMA push reason 90 * @rxdma_err_code: RXDMA Error code 91 * @reserved_1: Reserved bits 92 * @wbm_err_src: WBM error source 93 * @pool_id: pool ID, indicates which rxdma pool 94 * @reserved_2: Reserved bits 95 */ 96 struct hal_wbm_err_desc_info { 97 uint16_t reo_psh_rsn:2, 98 reo_err_code:5, 99 rxdma_psh_rsn:2, 100 rxdma_err_code:5, 101 reserved_1:2; 102 uint8_t wbm_err_src:3, 103 pool_id:2, 104 msdu_continued:1, 105 reserved_2:2; 106 }; 107 108 /** 109 * hal_rx_mon_dest_buf_info: Structure to hold rx mon dest buffer info 110 * @first_buffer: First buffer of MSDU 111 * @last_buffer: Last buffer of MSDU 112 * @is_decap_raw: Is RAW Frame 113 * @reserved_1: Reserved 114 * 115 * MSDU with continuation: 116 * ----------------------------------------------------------- 117 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 118 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 119 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 120 * ----------------------------------------------------------- 121 * 122 * Single buffer MSDU: 123 * ------------------ 124 * | first_buffer:1 | 125 * | last_buffer :1 | 126 * | is_decap_raw:1/0 | 127 * ------------------ 128 */ 129 struct hal_rx_mon_dest_buf_info { 130 uint8_t first_buffer:1, 131 last_buffer:1, 132 is_decap_raw:1, 133 reserved_1:5; 134 }; 135 136 /** 137 * struct hal_rx_msdu_metadata:Structure to hold rx fast path information. 138 * 139 * @l3_hdr_pad: l3 header padding 140 * @reserved: Reserved bits 141 * @sa_sw_peer_id: sa sw peer id 142 * @sa_idx: sa index 143 * @da_idx: da index 144 */ 145 struct hal_rx_msdu_metadata { 146 uint32_t l3_hdr_pad:16, 147 sa_sw_peer_id:16; 148 uint32_t sa_idx:16, 149 da_idx:16; 150 }; 151 152 struct hal_proto_params { 153 uint8_t tcp_proto; 154 uint8_t udp_proto; 155 uint8_t ipv6_proto; 156 }; 157 158 /** 159 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 160 * 161 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 162 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 163 */ 164 enum hal_reo_error_status { 165 HAL_REO_ERROR_DETECTED = 0, 166 HAL_REO_ROUTING_INSTRUCTION = 1, 167 }; 168 169 /** 170 * @msdu_flags: [0] first_msdu_in_mpdu 171 * [1] last_msdu_in_mpdu 172 * [2] msdu_continuation - MSDU spread across buffers 173 * [23] sa_is_valid - SA match in peer table 174 * [24] sa_idx_timeout - Timeout while searching for SA match 175 * [25] da_is_valid - Used to identtify intra-bss forwarding 176 * [26] da_is_MCBC 177 * [27] da_idx_timeout - Timeout while searching for DA match 178 * 179 */ 180 struct hal_rx_msdu_desc_info { 181 uint32_t msdu_flags; 182 uint16_t msdu_len; /* 14 bits for length */ 183 }; 184 185 /** 186 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 187 * 188 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 189 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 190 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 191 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 192 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 193 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 194 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 195 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 196 * @ HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 197 */ 198 enum hal_rx_msdu_desc_flags { 199 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 200 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 201 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 202 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 203 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 204 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 205 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 206 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 207 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 208 }; 209 210 /* 211 * @msdu_count: no. of msdus in the MPDU 212 * @mpdu_seq: MPDU sequence number 213 * @mpdu_flags [0] Fragment flag 214 * [1] MPDU_retry_bit 215 * [2] AMPDU flag 216 * [3] raw_ampdu 217 * @peer_meta_data: Upper bits containing peer id, vdev id 218 * @bar_frame: indicates if received frame is a bar frame 219 */ 220 struct hal_rx_mpdu_desc_info { 221 uint16_t msdu_count; 222 uint16_t mpdu_seq; /* 12 bits for length */ 223 uint32_t mpdu_flags; 224 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 225 uint16_t bar_frame; 226 }; 227 228 /** 229 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 230 * 231 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 232 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 233 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 234 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 235 */ 236 enum hal_rx_mpdu_desc_flags { 237 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 238 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 239 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 240 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 241 }; 242 243 /* Return Buffer manager ID */ 244 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 245 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 246 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 247 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 248 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 249 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 250 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 251 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 252 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 253 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 254 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 255 256 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 257 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 258 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 259 260 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 261 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 262 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 263 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 264 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 265 266 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 267 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 268 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 269 270 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 271 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 272 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 273 274 /* 275 * macro to set the LSW of the nbuf data physical address 276 * to the rxdma ring entry 277 */ 278 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 279 ((*(((unsigned int *) buff_addr_info) + \ 280 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 281 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 282 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 283 284 /* 285 * macro to set the LSB of MSW of the nbuf data physical address 286 * to the rxdma ring entry 287 */ 288 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 289 ((*(((unsigned int *) buff_addr_info) + \ 290 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 291 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 292 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 293 294 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 295 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 296 297 /* 298 * macro to get the invalid bit for sw cookie 299 */ 300 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 301 ((*(((unsigned int *)buff_addr_info) + \ 302 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 303 HAL_RX_COOKIE_INVALID_MASK) 304 305 /* 306 * macro to set the invalid bit for sw cookie 307 */ 308 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 309 ((*(((unsigned int *)buff_addr_info) + \ 310 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 311 HAL_RX_COOKIE_INVALID_MASK) 312 313 /* 314 * macro to reset the invalid bit for sw cookie 315 */ 316 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 317 ((*(((unsigned int *)buff_addr_info) + \ 318 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 319 ~HAL_RX_COOKIE_INVALID_MASK) 320 321 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 322 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 323 (((struct reo_destination_ring *) \ 324 reo_desc)->buf_or_link_desc_addr_info))) 325 326 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 327 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 328 (((struct reo_destination_ring *) \ 329 reo_desc)->buf_or_link_desc_addr_info))) 330 331 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 332 333 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 334 ((*(((unsigned int *)buff_addr_info) + \ 335 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 336 HAL_RX_LINK_COOKIE_INVALID_MASK) 337 338 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 339 ((*(((unsigned int *)buff_addr_info) + \ 340 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 341 HAL_RX_LINK_COOKIE_INVALID_MASK) 342 343 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 344 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 345 (((struct reo_destination_ring *) \ 346 reo_desc)->buf_or_link_desc_addr_info))) 347 348 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 349 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 350 (((struct reo_destination_ring *) \ 351 reo_desc)->buf_or_link_desc_addr_info))) 352 #endif 353 354 /* TODO: Convert the following structure fields accesseses to offsets */ 355 356 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 357 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 358 (((struct reo_destination_ring *) \ 359 reo_desc)->buf_or_link_desc_addr_info))) 360 361 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 362 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 363 (((struct reo_destination_ring *) \ 364 reo_desc)->buf_or_link_desc_addr_info))) 365 366 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 367 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 368 (((struct reo_destination_ring *) \ 369 reo_desc)->buf_or_link_desc_addr_info))) 370 371 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 372 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 373 _field, _val) 374 375 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 376 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 377 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 378 379 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 380 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 381 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 382 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 383 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 384 385 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 386 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 387 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 388 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 389 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 390 391 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 392 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 393 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 394 395 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 396 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 397 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 398 399 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 400 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 401 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 402 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 403 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 404 405 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 406 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 407 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 408 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 409 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 410 411 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 412 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 413 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 414 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 415 416 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 417 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 418 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 419 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 420 421 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 422 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 423 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 424 425 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 426 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 427 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 428 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 429 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 430 431 static inline uint32_t 432 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 433 rx_msdu_desc_info_t msdu_desc_info_hdl) 434 { 435 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 436 437 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 438 } 439 440 /* 441 * Structures & Macros to obtain fields from the TLV's in the Rx packet 442 * pre-header. 443 */ 444 445 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 446 void *hw_desc_addr) 447 { 448 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 449 450 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 451 } 452 453 /** 454 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 455 * @hal_soc_hdl: hal soc handle 456 * @desc_addr: ring descriptor 457 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 458 * 459 * Return: None 460 */ 461 static inline void 462 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 463 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 464 { 465 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 466 467 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 468 mpdu_desc_info); 469 } 470 471 #define HAL_RX_NUM_MSDU_DESC 6 472 #define HAL_RX_MAX_SAVED_RING_DESC 16 473 474 /* TODO: rework the structure */ 475 struct hal_rx_msdu_list { 476 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 477 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 478 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 479 /* physical address of the msdu */ 480 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 481 }; 482 483 struct hal_buf_info { 484 uint64_t paddr; 485 uint32_t sw_cookie; 486 uint8_t rbm; 487 }; 488 489 /* This special cookie value will be used to indicate FW allocated buffers 490 * received through RXDMA2SW ring for RXDMA WARs 491 */ 492 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 493 494 /** 495 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 496 * 497 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 498 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 499 * descriptor 500 */ 501 enum hal_rx_reo_buf_type { 502 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 503 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 504 }; 505 506 /** 507 * enum hal_reo_error_code: Error code describing the type of error detected 508 * 509 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 510 * REO_ENTRANCE ring is set to 0 511 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 512 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 513 * having been setup 514 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 515 * Retry bit set: duplicate frame 516 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 517 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 518 * received with 2K jump in SN 519 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 520 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 521 * with SN falling within the OOR window 522 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 523 * OOR window 524 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 525 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 526 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 527 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 528 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 529 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 530 * of the pn_error_detected_flag been set in the REO Queue descriptor 531 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 532 * the queue descriptor(address) being blocked as SW/FW seems to be currently 533 * in the process of making updates to this descriptor 534 */ 535 enum hal_reo_error_code { 536 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 537 HAL_REO_ERR_QUEUE_DESC_INVALID, 538 HAL_REO_ERR_AMPDU_IN_NON_BA, 539 HAL_REO_ERR_NON_BA_DUPLICATE, 540 HAL_REO_ERR_BA_DUPLICATE, 541 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 542 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 543 HAL_REO_ERR_REGULAR_FRAME_OOR, 544 HAL_REO_ERR_BAR_FRAME_OOR, 545 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 546 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 547 HAL_REO_ERR_PN_CHECK_FAILED, 548 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 549 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 550 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 551 HAL_REO_ERR_MAX 552 }; 553 554 /** 555 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 556 * 557 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 558 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 559 * overflow 560 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 561 * incomplete 562 * MPDU from the PHY 563 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 564 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 565 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 566 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 567 * encrypted but wasn’t 568 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 569 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 570 * the max allowed 571 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 572 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 573 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 574 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 575 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 576 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 577 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 578 */ 579 enum hal_rxdma_error_code { 580 HAL_RXDMA_ERR_OVERFLOW = 0, 581 HAL_RXDMA_ERR_MPDU_LENGTH, 582 HAL_RXDMA_ERR_FCS, 583 HAL_RXDMA_ERR_DECRYPT, 584 HAL_RXDMA_ERR_TKIP_MIC, 585 HAL_RXDMA_ERR_UNENCRYPTED, 586 HAL_RXDMA_ERR_MSDU_LEN, 587 HAL_RXDMA_ERR_MSDU_LIMIT, 588 HAL_RXDMA_ERR_WIFI_PARSE, 589 HAL_RXDMA_ERR_AMSDU_PARSE, 590 HAL_RXDMA_ERR_SA_TIMEOUT, 591 HAL_RXDMA_ERR_DA_TIMEOUT, 592 HAL_RXDMA_ERR_FLOW_TIMEOUT, 593 HAL_RXDMA_ERR_FLUSH_REQUEST, 594 HAL_RXDMA_ERR_WAR = 31, 595 HAL_RXDMA_ERR_MAX 596 }; 597 598 /** 599 * HW BM action settings in WBM release ring 600 */ 601 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 602 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 603 604 /** 605 * enum hal_rx_wbm_error_source: Indicates which module initiated the 606 * release of this buffer or descriptor 607 * 608 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 609 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 610 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 611 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 612 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 613 */ 614 enum hal_rx_wbm_error_source { 615 HAL_RX_WBM_ERR_SRC_TQM = 0, 616 HAL_RX_WBM_ERR_SRC_RXDMA, 617 HAL_RX_WBM_ERR_SRC_REO, 618 HAL_RX_WBM_ERR_SRC_FW, 619 HAL_RX_WBM_ERR_SRC_SW, 620 }; 621 622 /** 623 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 624 * released 625 * 626 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 627 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 628 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 629 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 630 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 631 */ 632 enum hal_rx_wbm_buf_type { 633 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 634 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 635 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 636 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 637 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 638 }; 639 640 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 641 642 //#include "hal_rx_be.h" 643 644 /* 645 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 646 * 647 * @nbuf: Network buffer 648 * Returns: flag to indicate whether the nbuf has MC/BC address 649 */ 650 static inline uint32_t 651 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 652 qdf_nbuf_t nbuf) 653 { 654 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 655 656 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 657 } 658 659 /** 660 * hal_rx_priv_info_set_in_tlv(): Save the private info to 661 * the reserved bytes of rx_tlv_hdr 662 * @buf: start of rx_tlv_hdr 663 * @wbm_er_info: hal_wbm_err_desc_info structure 664 * Return: void 665 */ 666 static inline void 667 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 668 uint8_t *buf, uint8_t *priv_data, 669 uint32_t len) 670 { 671 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 672 673 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 674 priv_data, 675 len); 676 } 677 678 /* 679 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 680 * reo_entrance_ring descriptor 681 * 682 * @reo_ent_desc: reo_entrance_ring descriptor 683 * Returns: value of rxdma_push_reason 684 */ 685 static inline 686 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 687 { 688 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 689 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 690 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 691 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 692 } 693 694 /** 695 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 696 * reo_entrance_ring descriptor 697 * @reo_ent_desc: reo_entrance_ring descriptor 698 * Return: value of rxdma_error_code 699 */ 700 static inline 701 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 702 { 703 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 704 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 705 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 706 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 707 } 708 709 /** 710 * hal_rx_priv_info_get_from_tlv(): retrieve the private data from 711 * the reserved bytes of rx_tlv_hdr. 712 * @buf: start of rx_tlv_hdr 713 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 714 * Return: void 715 */ 716 static inline void 717 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 718 uint8_t *buf, uint8_t *wbm_er_info, 719 uint32_t len) 720 { 721 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 722 723 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 724 wbm_er_info, 725 len); 726 } 727 728 static inline void 729 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 730 uint16_t *rx_mon_pkt_tlv_size) 731 { 732 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 733 734 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 735 rx_mon_pkt_tlv_size); 736 } 737 738 /* 739 * hal_rx_encryption_info_valid(): Returns encryption type. 740 * 741 * @hal_soc_hdl: hal soc handle 742 * @buf: rx_tlv_hdr of the received packet 743 * 744 * Return: encryption type 745 */ 746 static inline uint32_t 747 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 748 { 749 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 750 751 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 752 } 753 754 /* 755 * hal_rx_print_pn: Prints the PN of rx packet. 756 * @hal_soc_hdl: hal soc handle 757 * @buf: rx_tlv_hdr of the received packet 758 * 759 * Return: void 760 */ 761 static inline void 762 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 763 { 764 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 765 766 hal_soc->ops->hal_rx_print_pn(buf); 767 } 768 769 /** 770 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 771 * l3_header padding from rx_msdu_end TLV 772 * 773 * @buf: pointer to the start of RX PKT TLV headers 774 * Return: number of l3 header padding bytes 775 */ 776 static inline uint32_t 777 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 778 uint8_t *buf) 779 { 780 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 781 782 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 783 } 784 785 /** 786 * hal_rx_msdu_end_sa_idx_get(): API to get the 787 * sa_idx from rx_msdu_end TLV 788 * 789 * @ buf: pointer to the start of RX PKT TLV headers 790 * Return: sa_idx (SA AST index) 791 */ 792 static inline uint16_t 793 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 794 uint8_t *buf) 795 { 796 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 797 798 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 799 } 800 801 /** 802 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 803 * sa_is_valid bit from rx_msdu_end TLV 804 * 805 * @ buf: pointer to the start of RX PKT TLV headers 806 * Return: sa_is_valid bit 807 */ 808 static inline uint8_t 809 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 810 uint8_t *buf) 811 { 812 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 813 814 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 815 } 816 817 /** 818 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 819 * from rx_msdu_start TLV 820 * 821 * @buf: pointer to the start of RX PKT TLV headers 822 * @len: msdu length 823 * 824 * Return: none 825 */ 826 static inline void 827 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 828 uint32_t len) 829 { 830 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 831 832 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 833 } 834 835 /** 836 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 837 * 838 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 839 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 840 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 841 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 842 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 843 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 844 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 845 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 846 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 847 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 848 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 849 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 850 */ 851 enum hal_rx_mpdu_info_sw_frame_group_id_type { 852 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 853 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 854 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 855 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 856 HAL_MPDU_SW_FRAME_GROUP_MGMT, 857 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 858 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 859 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 860 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 861 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 862 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 863 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 864 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 865 }; 866 867 /** 868 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 869 * Retrieve qos control valid bit from the tlv. 870 * @hal_soc_hdl: hal_soc handle 871 * @buf: pointer to rx pkt TLV. 872 * 873 * Return: qos control value. 874 */ 875 static inline uint32_t 876 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 877 hal_soc_handle_t hal_soc_hdl, 878 uint8_t *buf) 879 { 880 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 881 882 if ((!hal_soc) || (!hal_soc->ops)) { 883 hal_err("hal handle is NULL"); 884 QDF_BUG(0); 885 return QDF_STATUS_E_INVAL; 886 } 887 888 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 889 return hal_soc->ops-> 890 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 891 892 return QDF_STATUS_E_INVAL; 893 } 894 895 /** 896 * hal_rx_is_unicast: check packet is unicast frame or not. 897 * @hal_soc_hdl: hal_soc handle 898 * @buf: pointer to rx pkt TLV. 899 * 900 * Return: true on unicast. 901 */ 902 static inline bool 903 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 904 { 905 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 906 907 return hal_soc->ops->hal_rx_is_unicast(buf); 908 } 909 910 /** 911 * hal_rx_tid_get: get tid based on qos control valid. 912 * @hal_soc_hdl: hal soc handle 913 * @buf: pointer to rx pkt TLV. 914 * 915 * Return: tid 916 */ 917 static inline uint32_t 918 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 919 { 920 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 921 922 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 923 } 924 925 /** 926 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 927 * @hal_soc_hdl: hal soc handle 928 * @buf: pointer to rx pkt TLV. 929 * 930 * Return: sw peer_id 931 */ 932 static inline uint32_t 933 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 934 uint8_t *buf) 935 { 936 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 937 938 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 939 } 940 941 /* 942 * hal_rx_mpdu_get_tods(): API to get the tods info 943 * from rx_mpdu_start 944 * 945 * @buf: pointer to the start of RX PKT TLV header 946 * Return: uint32_t(to_ds) 947 */ 948 949 static inline uint32_t 950 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 951 { 952 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 953 954 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 955 } 956 957 958 /* 959 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 960 * from rx_mpdu_start 961 * @hal_soc_hdl: hal soc handle 962 * @buf: pointer to the start of RX PKT TLV header 963 * 964 * Return: uint32_t(fr_ds) 965 */ 966 static inline uint32_t 967 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 968 { 969 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 970 971 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 972 } 973 974 /* 975 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 976 * @hal_soc_hdl: hal soc handle 977 * @buf: pointer to the start of RX PKT TLV headera 978 * @mac_addr: pointer to mac address 979 * 980 * Return: success/failure 981 */ 982 static inline 983 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 984 uint8_t *buf, uint8_t *mac_addr) 985 { 986 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 987 988 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 989 } 990 991 /* 992 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 993 * in the packet 994 * @hal_soc_hdl: hal soc handle 995 * @buf: pointer to the start of RX PKT TLV header 996 * @mac_addr: pointer to mac address 997 * 998 * Return: success/failure 999 */ 1000 static inline 1001 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1002 uint8_t *buf, uint8_t *mac_addr) 1003 { 1004 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1005 1006 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1007 } 1008 1009 /* 1010 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1011 * in the packet 1012 * @hal_soc_hdl: hal soc handle 1013 * @buf: pointer to the start of RX PKT TLV header 1014 * @mac_addr: pointer to mac address 1015 * 1016 * Return: success/failure 1017 */ 1018 static inline 1019 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1020 uint8_t *buf, uint8_t *mac_addr) 1021 { 1022 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1023 1024 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1025 } 1026 1027 /* 1028 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1029 * in the packet 1030 * @hal_soc_hdl: hal_soc handle 1031 * @buf: pointer to the start of RX PKT TLV header 1032 * @mac_addr: pointer to mac address 1033 * Return: success/failure 1034 */ 1035 static inline 1036 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1037 uint8_t *buf, uint8_t *mac_addr) 1038 { 1039 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1040 1041 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1042 } 1043 1044 /** 1045 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1046 * from rx_msdu_end TLV 1047 * 1048 * @ buf: pointer to the start of RX PKT TLV headers 1049 * Return: da index 1050 */ 1051 static inline uint16_t 1052 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1053 { 1054 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1055 1056 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1057 } 1058 1059 /** 1060 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1061 * from rx_msdu_end TLV 1062 * @hal_soc_hdl: hal soc handle 1063 * @ buf: pointer to the start of RX PKT TLV headers 1064 * 1065 * Return: da_is_valid 1066 */ 1067 static inline uint8_t 1068 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1069 uint8_t *buf) 1070 { 1071 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1072 1073 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1074 } 1075 1076 /** 1077 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1078 * from rx_msdu_end TLV 1079 * 1080 * @buf: pointer to the start of RX PKT TLV headers 1081 * 1082 * Return: da_is_mcbc 1083 */ 1084 static inline uint8_t 1085 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1086 { 1087 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1088 1089 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1090 } 1091 1092 /** 1093 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1094 * from rx_msdu_end TLV 1095 * @hal_soc_hdl: hal soc handle 1096 * @buf: pointer to the start of RX PKT TLV headers 1097 * 1098 * Return: first_msdu 1099 */ 1100 static inline uint8_t 1101 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1102 uint8_t *buf) 1103 { 1104 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1105 1106 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1107 } 1108 1109 /** 1110 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1111 * from rx_msdu_end TLV 1112 * @hal_soc_hdl: hal soc handle 1113 * @buf: pointer to the start of RX PKT TLV headers 1114 * 1115 * Return: last_msdu 1116 */ 1117 static inline uint8_t 1118 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1119 uint8_t *buf) 1120 { 1121 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1122 1123 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1124 } 1125 1126 /** 1127 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1128 * from rx_msdu_end TLV 1129 * @buf: pointer to the start of RX PKT TLV headers 1130 * Return: cce_meta_data 1131 */ 1132 static inline uint16_t 1133 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1134 uint8_t *buf) 1135 { 1136 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1137 1138 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1139 } 1140 1141 /******************************************************************************* 1142 * RX REO ERROR APIS 1143 ******************************************************************************/ 1144 1145 /** 1146 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1147 * @msdu_link_ptr - msdu link ptr 1148 * @hal - pointer to hal_soc 1149 * Return - Pointer to rx_msdu_details structure 1150 * 1151 */ 1152 static inline 1153 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1154 struct hal_soc *hal_soc) 1155 { 1156 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1157 } 1158 1159 /** 1160 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1161 * @msdu_details_ptr - Pointer to msdu_details_ptr 1162 * @hal - pointer to hal_soc 1163 * Return - Pointer to rx_msdu_desc_info structure. 1164 * 1165 */ 1166 static inline 1167 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1168 struct hal_soc *hal_soc) 1169 { 1170 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1171 } 1172 1173 /** 1174 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1175 * cookie from the REO destination ring element 1176 * 1177 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1178 * the current descriptor 1179 * @ buf_info: structure to return the buffer information 1180 * Return: void 1181 */ 1182 static inline 1183 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1184 hal_ring_desc_t rx_desc, 1185 struct hal_buf_info *buf_info) 1186 { 1187 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1188 1189 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1190 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1191 rx_desc, 1192 buf_info); 1193 1194 } 1195 1196 /** 1197 * hal_rx_buf_cookie_rbm_get: Gets the physical address and 1198 * cookie from the REO entrance ring element 1199 * 1200 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1201 * the current descriptor 1202 * @ buf_info: structure to return the buffer information 1203 * @ msdu_cnt: pointer to msdu count in MPDU 1204 * Return: void 1205 */ 1206 static inline 1207 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1208 uint32_t *buf_addr_info, 1209 struct hal_buf_info *buf_info) 1210 { 1211 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1212 1213 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1214 buf_addr_info, 1215 buf_info); 1216 } 1217 1218 /** 1219 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1220 * from the MSDU link descriptor 1221 * 1222 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1223 * MSDU link descriptor (struct rx_msdu_link) 1224 * 1225 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1226 * 1227 * @num_msdus: Number of MSDUs in the MPDU 1228 * 1229 * Return: void 1230 */ 1231 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1232 void *msdu_link_desc, 1233 struct hal_rx_msdu_list *msdu_list, 1234 uint16_t *num_msdus) 1235 { 1236 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1237 struct rx_msdu_details *msdu_details; 1238 struct rx_msdu_desc_info *msdu_desc_info; 1239 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1240 int i; 1241 struct hal_buf_info buf_info; 1242 1243 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1244 1245 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1246 __func__, __LINE__, msdu_link, msdu_details); 1247 1248 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1249 /* num_msdus received in mpdu descriptor may be incorrect 1250 * sometimes due to HW issue. Check msdu buffer address also 1251 */ 1252 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1253 &msdu_details[i].buffer_addr_info_details) == 0)) 1254 break; 1255 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1256 &msdu_details[i].buffer_addr_info_details) == 0) { 1257 /* set the last msdu bit in the prev msdu_desc_info */ 1258 msdu_desc_info = 1259 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1260 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1261 break; 1262 } 1263 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1264 hal_soc); 1265 1266 /* set first MSDU bit or the last MSDU bit */ 1267 if (!i) 1268 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1269 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1270 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1271 1272 msdu_list->msdu_info[i].msdu_flags = 1273 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1274 msdu_list->msdu_info[i].msdu_len = 1275 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1276 1277 /* addr field in buf_info will not be valid */ 1278 hal_rx_buf_cookie_rbm_get( 1279 hal_soc_hdl, 1280 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1281 &buf_info); 1282 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1283 msdu_list->rbm[i] = buf_info.rbm; 1284 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1285 &msdu_details[i].buffer_addr_info_details) | 1286 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1287 &msdu_details[i].buffer_addr_info_details) << 32; 1288 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1289 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1290 } 1291 *num_msdus = i; 1292 } 1293 1294 /** 1295 * hal_rx_is_pn_error() - Indicate if this error was caused by a 1296 * PN check failure 1297 * 1298 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 1299 * 1300 * Return: true: error caused by PN check, false: other error 1301 */ 1302 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1303 { 1304 1305 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1306 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1307 true : false; 1308 } 1309 1310 /** 1311 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1312 * the sequence number 1313 * 1314 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1315 * 1316 * Return: true: error caused by 2K jump, false: other error 1317 */ 1318 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1319 { 1320 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1321 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1322 true : false; 1323 } 1324 1325 /** 1326 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1327 * 1328 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 1329 * 1330 * Return: true: error caused by OOR, false: other error 1331 */ 1332 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1333 { 1334 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1335 true : false; 1336 } 1337 1338 /** 1339 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1340 * @error_code: error code obtained from ring descriptor. 1341 * 1342 * Return: true, if the error code is 2k-jump or OOR 1343 * false, for other error codes. 1344 */ 1345 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1346 { 1347 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1348 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1349 true : false; 1350 } 1351 1352 /** 1353 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1354 * @hal_desc: hardware descriptor pointer 1355 * 1356 * This function will print wbm release descriptor 1357 * 1358 * Return: none 1359 */ 1360 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1361 { 1362 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1363 uint32_t i; 1364 1365 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1366 "Current Rx wbm release descriptor is"); 1367 1368 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1369 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1370 "DWORD[i] = 0x%x", wbm_comp[i]); 1371 } 1372 } 1373 1374 /** 1375 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 1376 * 1377 * @ hal_soc_hdl : HAL version of the SOC pointer 1378 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 1379 * @ buf_addr_info : void pointer to the buffer_addr_info 1380 * @ bm_action : put in IDLE list or release to MSDU_LIST 1381 * 1382 * Return: void 1383 */ 1384 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1385 static inline 1386 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1387 void *src_srng_desc, 1388 hal_buff_addrinfo_t buf_addr_info, 1389 uint8_t bm_action) 1390 { 1391 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1392 1393 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1394 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1395 src_srng_desc, 1396 buf_addr_info, 1397 bm_action); 1398 } 1399 1400 /** 1401 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 1402 * BUFFER_ADDR_INFO, give the RX descriptor 1403 * (Assumption -- BUFFER_ADDR_INFO is the 1404 * first field in the descriptor structure) 1405 */ 1406 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1407 ((hal_link_desc_t)(ring_desc)) 1408 1409 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1410 1411 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1412 1413 /******************************************************************************* 1414 * RX WBM ERROR APIS 1415 ******************************************************************************/ 1416 1417 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1418 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1419 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1420 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1421 /** 1422 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 1423 * the frame to this release ring 1424 * 1425 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1426 * frame to this queue 1427 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1428 * received routing instructions. No error within REO was detected 1429 */ 1430 enum hal_rx_wbm_reo_push_reason { 1431 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1432 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1433 }; 1434 1435 1436 /** 1437 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 1438 * this release ring 1439 * 1440 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1441 * this frame to this queue 1442 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1443 * per received routing instructions. No error within RXDMA was detected 1444 */ 1445 enum hal_rx_wbm_rxdma_push_reason { 1446 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1447 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1448 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1449 }; 1450 1451 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 1452 uint8_t dbg_level, 1453 struct hal_soc *hal) 1454 { 1455 1456 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 1457 } 1458 1459 /** 1460 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 1461 * human readable format. 1462 * @ msdu_end: pointer the msdu_end TLV in pkt. 1463 * @ dbg_level: log level. 1464 * 1465 * Return: void 1466 */ 1467 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1468 struct rx_msdu_end *msdu_end, 1469 uint8_t dbg_level) 1470 { 1471 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 1472 } 1473 1474 /** 1475 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 1476 * structure 1477 * @hal_ring: pointer to hal_srng structure 1478 * 1479 * Return: ring_id 1480 */ 1481 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1482 { 1483 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1484 } 1485 1486 #define DOT11_SEQ_FRAG_MASK 0x000f 1487 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1488 1489 /** 1490 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 1491 * 1492 * @nbuf: Network buffer 1493 * Returns: rx fragment number 1494 */ 1495 static inline 1496 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1497 uint8_t *buf) 1498 { 1499 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1500 } 1501 1502 /* 1503 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 1504 * @hal_soc_hdl: hal soc handle 1505 * @nbuf: Network buffer 1506 * 1507 * Return: value of sequence control valid field 1508 */ 1509 static inline 1510 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1511 uint8_t *buf) 1512 { 1513 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1514 1515 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1516 } 1517 1518 /* 1519 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 1520 * @hal_soc_hdl: hal soc handle 1521 * @nbuf: Network buffer 1522 * 1523 * Returns: value of frame control valid field 1524 */ 1525 static inline 1526 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1527 uint8_t *buf) 1528 { 1529 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1530 1531 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1532 } 1533 1534 /** 1535 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 1536 * @hal_soc_hdl: hal soc handle 1537 * @nbuf: Network buffer 1538 * Returns: value of mpdu 4th address valid field 1539 */ 1540 static inline 1541 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1542 uint8_t *buf) 1543 { 1544 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1545 1546 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1547 } 1548 1549 /* 1550 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 1551 * 1552 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1553 * Returns: None 1554 */ 1555 static inline void 1556 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1557 { 1558 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1559 } 1560 1561 /** 1562 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 1563 * save it to hal_wbm_err_desc_info structure passed by caller 1564 * @wbm_desc: wbm ring descriptor 1565 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1566 * Return: void 1567 */ 1568 static inline 1569 void hal_rx_wbm_err_info_get(void *wbm_desc, 1570 struct hal_wbm_err_desc_info *wbm_er_info, 1571 hal_soc_handle_t hal_soc_hdl) 1572 { 1573 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1574 1575 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1576 } 1577 1578 /** 1579 * hal_rx_wbm_err_msdu_continuation_get(): Get wbm msdu continuation 1580 * bit from wbm release ring descriptor 1581 * @wbm_desc: wbm ring descriptor 1582 * Return: uint8_t 1583 */ 1584 static inline 1585 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1586 void *wbm_desc) 1587 { 1588 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1589 1590 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1591 } 1592 1593 /** 1594 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 1595 * 1596 * @ hal_soc: HAL version of the SOC pointer 1597 * @ hw_desc_addr: Start address of Rx HW TLVs 1598 * @ rs: Status for monitor mode 1599 * 1600 * Return: void 1601 */ 1602 static inline 1603 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1604 void *hw_desc_addr, 1605 struct mon_rx_status *rs) 1606 { 1607 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1608 1609 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1610 } 1611 1612 /* 1613 * hal_rx_get_tlv(): API to get the tlv 1614 * 1615 * @hal_soc: HAL version of the SOC pointer 1616 * @rx_tlv: TLV data extracted from the rx packet 1617 * Return: uint8_t 1618 */ 1619 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1620 { 1621 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1622 } 1623 1624 /* 1625 * hal_rx_msdu_start_nss_get(): API to get the NSS 1626 * Interval from rx_msdu_start 1627 * 1628 * @hal_soc: HAL version of the SOC pointer 1629 * @buf: pointer to the start of RX PKT TLV header 1630 * Return: uint32_t(nss) 1631 */ 1632 static inline 1633 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1634 { 1635 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1636 1637 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1638 } 1639 1640 /** 1641 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 1642 * human readable format. 1643 * @ msdu_start: pointer the msdu_start TLV in pkt. 1644 * @ dbg_level: log level. 1645 * 1646 * Return: void 1647 */ 1648 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1649 struct rx_msdu_start *msdu_start, 1650 uint8_t dbg_level) 1651 { 1652 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 1653 } 1654 1655 /** 1656 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 1657 * info details 1658 * 1659 * @ buf - Pointer to buffer containing rx pkt tlvs. 1660 * 1661 * 1662 */ 1663 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1664 uint8_t *buf) 1665 { 1666 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1667 1668 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1669 } 1670 1671 /* 1672 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 1673 * Interval from rx_msdu_start 1674 * 1675 * @buf: pointer to the start of RX PKT TLV header 1676 * Return: uint32_t(reception_type) 1677 */ 1678 static inline 1679 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1680 uint8_t *buf) 1681 { 1682 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1683 1684 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1685 } 1686 1687 /** 1688 * hal_reo_status_get_header_generic - Process reo desc info 1689 * @d - Pointer to reo descriptior 1690 * @b - tlv type info 1691 * @h - Pointer to hal_reo_status_header where info to be stored 1692 * @hal- pointer to hal_soc structure 1693 * Return - none. 1694 * 1695 */ 1696 static inline 1697 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1698 void *h, struct hal_soc *hal_soc) 1699 { 1700 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1701 } 1702 1703 /** 1704 * hal_rx_desc_is_first_msdu() - Check if first msdu 1705 * 1706 * @hal_soc_hdl: hal_soc handle 1707 * @hw_desc_addr: hardware descriptor address 1708 * 1709 * Return: 0 - success/ non-zero failure 1710 */ 1711 static inline 1712 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1713 void *hw_desc_addr) 1714 { 1715 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1716 1717 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1718 } 1719 1720 /** 1721 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1722 * the rx tlv fields. 1723 * @hal_soc_hdl: HAL SoC handle 1724 * @buf: rx tlv start address [To be validated by caller] 1725 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1726 * 1727 * Return: None 1728 */ 1729 static inline void 1730 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1731 uint8_t *buf, 1732 void *mpdu_desc_info_hdl) 1733 { 1734 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1735 1736 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1737 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1738 mpdu_desc_info_hdl); 1739 } 1740 1741 static inline uint32_t 1742 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1743 { 1744 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1745 1746 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1747 } 1748 1749 static inline 1750 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1751 uint8_t *rx_tlv_hdr) 1752 { 1753 uint8_t decap_format; 1754 1755 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1756 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1757 rx_tlv_hdr); 1758 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1759 return true; 1760 } 1761 1762 return false; 1763 } 1764 1765 /** 1766 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 1767 * from rx_msdu_end TLV 1768 * @buf: pointer to the start of RX PKT TLV headers 1769 * 1770 * Return: fse metadata value from MSDU END TLV 1771 */ 1772 static inline uint32_t 1773 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1774 uint8_t *buf) 1775 { 1776 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1777 1778 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1779 } 1780 1781 /** 1782 * hal_rx_buffer_addr_info_get_paddr(): get paddr/sw_cookie from 1783 * <struct buffer_addr_info> structure 1784 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1785 * @buf_info: structure to return the buffer information including 1786 * paddr/cookie 1787 * 1788 * return: None 1789 */ 1790 static inline 1791 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 1792 struct hal_buf_info *buf_info) 1793 { 1794 buf_info->paddr = 1795 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 1796 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 1797 } 1798 1799 /** 1800 * hal_rx_msdu_flow_idx_get: API to get flow index 1801 * from rx_msdu_end TLV 1802 * @buf: pointer to the start of RX PKT TLV headers 1803 * 1804 * Return: flow index value from MSDU END TLV 1805 */ 1806 static inline uint32_t 1807 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 1808 uint8_t *buf) 1809 { 1810 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1811 1812 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 1813 } 1814 1815 /** 1816 * hal_rx_msdu_get_reo_destination_indication: API to get reo 1817 * destination index from rx_msdu_end TLV 1818 * @buf: pointer to the start of RX PKT TLV headers 1819 * @reo_destination_indication: pointer to return value of 1820 * reo_destination_indication 1821 * 1822 * Return: reo_destination_indication value from MSDU END TLV 1823 */ 1824 static inline void 1825 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 1826 uint8_t *buf, 1827 uint32_t *reo_destination_indication) 1828 { 1829 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1830 1831 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 1832 reo_destination_indication); 1833 } 1834 1835 /** 1836 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 1837 * from rx_msdu_end TLV 1838 * @buf: pointer to the start of RX PKT TLV headers 1839 * 1840 * Return: flow index timeout value from MSDU END TLV 1841 */ 1842 static inline bool 1843 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 1844 uint8_t *buf) 1845 { 1846 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1847 1848 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 1849 } 1850 1851 /** 1852 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 1853 * from rx_msdu_end TLV 1854 * @buf: pointer to the start of RX PKT TLV headers 1855 * 1856 * Return: flow index invalid value from MSDU END TLV 1857 */ 1858 static inline bool 1859 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 1860 uint8_t *buf) 1861 { 1862 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1863 1864 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 1865 } 1866 1867 /** 1868 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 1869 * @hal_soc_hdl: hal_soc handle 1870 * @rx_tlv_hdr: Rx_tlv_hdr 1871 * @rxdma_dst_ring_desc: Rx HW descriptor 1872 * 1873 * Return: ppdu id 1874 */ 1875 static inline 1876 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 1877 void *rx_tlv_hdr, 1878 void *rxdma_dst_ring_desc) 1879 { 1880 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1881 1882 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 1883 rxdma_dst_ring_desc); 1884 } 1885 1886 /** 1887 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 1888 * @hal_soc_hdl: hal_soc handle 1889 * @buf: rx tlv address 1890 * 1891 * Return: sw peer id 1892 */ 1893 static inline 1894 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1895 uint8_t *buf) 1896 { 1897 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1898 1899 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 1900 } 1901 1902 static inline 1903 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 1904 void *link_desc_addr) 1905 { 1906 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1907 1908 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 1909 } 1910 1911 static inline 1912 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 1913 void *msdu_addr) 1914 { 1915 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1916 1917 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 1918 } 1919 1920 static inline 1921 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1922 void *hw_addr) 1923 { 1924 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1925 1926 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 1927 } 1928 1929 static inline 1930 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1931 void *hw_addr) 1932 { 1933 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1934 1935 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 1936 } 1937 1938 static inline 1939 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 1940 uint8_t *buf) 1941 { 1942 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1943 1944 return hal_soc->ops->hal_rx_get_fc_valid(buf); 1945 } 1946 1947 static inline 1948 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1949 { 1950 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1951 1952 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 1953 } 1954 1955 static inline 1956 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 1957 uint8_t *buf) 1958 { 1959 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1960 1961 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 1962 } 1963 1964 static inline 1965 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 1966 uint8_t *buf) 1967 { 1968 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1969 1970 return hal_soc->ops->hal_rx_get_filter_category(buf); 1971 } 1972 1973 static inline 1974 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 1975 uint8_t *buf) 1976 { 1977 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1978 1979 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 1980 } 1981 1982 /** 1983 * hal_reo_config(): Set reo config parameters 1984 * @soc: hal soc handle 1985 * @reg_val: value to be set 1986 * @reo_params: reo parameters 1987 * 1988 * Return: void 1989 */ 1990 static inline 1991 void hal_reo_config(struct hal_soc *hal_soc, 1992 uint32_t reg_val, 1993 struct hal_reo_params *reo_params) 1994 { 1995 hal_soc->ops->hal_reo_config(hal_soc, 1996 reg_val, 1997 reo_params); 1998 } 1999 2000 /** 2001 * hal_rx_msdu_get_flow_params: API to get flow index, 2002 * flow index invalid and flow index timeout from rx_msdu_end TLV 2003 * @buf: pointer to the start of RX PKT TLV headers 2004 * @flow_invalid: pointer to return value of flow_idx_valid 2005 * @flow_timeout: pointer to return value of flow_idx_timeout 2006 * @flow_index: pointer to return value of flow_idx 2007 * 2008 * Return: none 2009 */ 2010 static inline void 2011 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2012 uint8_t *buf, 2013 bool *flow_invalid, 2014 bool *flow_timeout, 2015 uint32_t *flow_index) 2016 { 2017 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2018 2019 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2020 flow_invalid, 2021 flow_timeout, 2022 flow_index); 2023 } 2024 2025 static inline 2026 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2027 uint8_t *buf) 2028 { 2029 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2030 2031 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2032 } 2033 2034 static inline 2035 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2036 uint8_t *buf) 2037 { 2038 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2039 2040 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2041 } 2042 2043 static inline void 2044 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2045 void *rx_tlv, 2046 void *ppdu_info) 2047 { 2048 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2049 2050 if (hal_soc->ops->hal_rx_get_bb_info) 2051 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2052 } 2053 2054 static inline void 2055 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2056 void *rx_tlv, 2057 void *ppdu_info) 2058 { 2059 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2060 2061 if (hal_soc->ops->hal_rx_get_rtt_info) 2062 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2063 } 2064 2065 /** 2066 * hal_rx_msdu_metadata_get(): API to get the 2067 * fast path information from rx_msdu_end TLV 2068 * 2069 * @ hal_soc_hdl: DP soc handle 2070 * @ buf: pointer to the start of RX PKT TLV headers 2071 * @ msdu_metadata: Structure to hold msdu end information 2072 * Return: none 2073 */ 2074 static inline void 2075 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2076 struct hal_rx_msdu_metadata *msdu_md) 2077 { 2078 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2079 2080 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2081 } 2082 2083 /** 2084 * hal_rx_get_fisa_cumulative_l4_checksum: API to get cumulative_l4_checksum 2085 * from rx_msdu_end TLV 2086 * @buf: pointer to the start of RX PKT TLV headers 2087 * 2088 * Return: cumulative_l4_checksum 2089 */ 2090 static inline uint16_t 2091 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2092 uint8_t *buf) 2093 { 2094 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2095 2096 if (!hal_soc || !hal_soc->ops) { 2097 hal_err("hal handle is NULL"); 2098 QDF_BUG(0); 2099 return 0; 2100 } 2101 2102 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2103 return 0; 2104 2105 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2106 } 2107 2108 /** 2109 * hal_rx_get_fisa_cumulative_ip_length: API to get cumulative_ip_length 2110 * from rx_msdu_end TLV 2111 * @buf: pointer to the start of RX PKT TLV headers 2112 * 2113 * Return: cumulative_ip_length 2114 */ 2115 static inline uint16_t 2116 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2117 uint8_t *buf) 2118 { 2119 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2120 2121 if (!hal_soc || !hal_soc->ops) { 2122 hal_err("hal handle is NULL"); 2123 QDF_BUG(0); 2124 return 0; 2125 } 2126 2127 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2128 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2129 2130 return 0; 2131 } 2132 2133 /** 2134 * hal_rx_get_udp_proto: API to get UDP proto field 2135 * from rx_msdu_start TLV 2136 * @buf: pointer to the start of RX PKT TLV headers 2137 * 2138 * Return: UDP proto field value 2139 */ 2140 static inline bool 2141 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2142 { 2143 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2144 2145 if (!hal_soc || !hal_soc->ops) { 2146 hal_err("hal handle is NULL"); 2147 QDF_BUG(0); 2148 return 0; 2149 } 2150 2151 if (hal_soc->ops->hal_rx_get_udp_proto) 2152 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2153 2154 return 0; 2155 } 2156 2157 /** 2158 * hal_rx_get_fisa_flow_agg_continuation: API to get fisa flow_agg_continuation 2159 * from rx_msdu_end TLV 2160 * @buf: pointer to the start of RX PKT TLV headers 2161 * 2162 * Return: flow_agg_continuation bit field value 2163 */ 2164 static inline bool 2165 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2166 uint8_t *buf) 2167 { 2168 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2169 2170 if (!hal_soc || !hal_soc->ops) { 2171 hal_err("hal handle is NULL"); 2172 QDF_BUG(0); 2173 return 0; 2174 } 2175 2176 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2177 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2178 2179 return 0; 2180 } 2181 2182 /** 2183 * hal_rx_get_fisa_flow_agg_count: API to get fisa flow_agg count from 2184 * rx_msdu_end TLV 2185 * @buf: pointer to the start of RX PKT TLV headers 2186 * 2187 * Return: flow_agg count value 2188 */ 2189 static inline uint8_t 2190 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2191 uint8_t *buf) 2192 { 2193 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2194 2195 if (!hal_soc || !hal_soc->ops) { 2196 hal_err("hal handle is NULL"); 2197 QDF_BUG(0); 2198 return 0; 2199 } 2200 2201 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2202 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2203 2204 return 0; 2205 } 2206 2207 /** 2208 * hal_rx_get_fisa_timeout: API to get fisa time out from rx_msdu_end TLV 2209 * @buf: pointer to the start of RX PKT TLV headers 2210 * 2211 * Return: fisa flow_agg timeout bit value 2212 */ 2213 static inline bool 2214 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2215 { 2216 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2217 2218 if (!hal_soc || !hal_soc->ops) { 2219 hal_err("hal handle is NULL"); 2220 QDF_BUG(0); 2221 return 0; 2222 } 2223 2224 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2225 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2226 2227 return 0; 2228 } 2229 2230 /** 2231 * hal_rx_mpdu_start_tlv_tag_valid - API to check if RX_MPDU_START tlv 2232 * tag is valid 2233 * 2234 * @hal_soc_hdl: HAL SOC handle 2235 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2236 * 2237 * Return: true if RX_MPDU_START tlv tag is valid, else false 2238 */ 2239 2240 static inline uint8_t 2241 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2242 void *rx_tlv_hdr) 2243 { 2244 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2245 2246 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2247 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2248 2249 return 0; 2250 } 2251 2252 /** 2253 * hal_rx_get_next_msdu_link_desc_buf_addr_info(): get next msdu link desc 2254 * buffer addr info 2255 * @link_desc_va: pointer to current msdu link Desc 2256 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2257 * 2258 * return: None 2259 */ 2260 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2261 void *link_desc_va, 2262 struct buffer_addr_info *next_addr_info) 2263 { 2264 struct rx_msdu_link *msdu_link = link_desc_va; 2265 2266 if (!msdu_link) { 2267 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2268 return; 2269 } 2270 2271 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2272 } 2273 2274 /** 2275 * hal_rx_clear_next_msdu_link_desc_buf_addr_info(): clear next msdu link desc 2276 * buffer addr info 2277 * @link_desc_va: pointer to current msdu link Desc 2278 * 2279 * return: None 2280 */ 2281 static inline 2282 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2283 { 2284 struct rx_msdu_link *msdu_link = link_desc_va; 2285 2286 if (msdu_link) 2287 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2288 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2289 } 2290 2291 /** 2292 * hal_rx_is_buf_addr_info_valid(): check is the buf_addr_info valid 2293 * 2294 * @buf_addr_info: pointer to buf_addr_info structure 2295 * 2296 * return: true: has valid paddr, false: not. 2297 */ 2298 static inline 2299 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2300 { 2301 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2302 false : true; 2303 } 2304 2305 /** 2306 * hal_rx_msdu_end_offset_get(): Get the MSDU end offset from 2307 * rx_pkt_tlvs structure 2308 * 2309 * @hal_soc_hdl: HAL SOC handle 2310 * return: msdu_end_tlv offset value 2311 */ 2312 static inline 2313 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2314 { 2315 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2316 2317 if (!hal_soc || !hal_soc->ops) { 2318 hal_err("hal handle is NULL"); 2319 QDF_BUG(0); 2320 return 0; 2321 } 2322 2323 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2324 } 2325 2326 /** 2327 * hal_rx_msdu_start_offset_get(): Get the MSDU start offset from 2328 * rx_pkt_tlvs structure 2329 * 2330 * @hal_soc_hdl: HAL SOC handle 2331 * return: msdu_start_tlv offset value 2332 */ 2333 static inline 2334 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2335 { 2336 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2337 2338 if (!hal_soc || !hal_soc->ops) { 2339 hal_err("hal handle is NULL"); 2340 QDF_BUG(0); 2341 return 0; 2342 } 2343 2344 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2345 } 2346 2347 /** 2348 * hal_rx_mpdu_start_offset_get(): Get the MPDU start offset from 2349 * rx_pkt_tlvs structure 2350 * 2351 * @hal_soc_hdl: HAL SOC handle 2352 * return: mpdu_start_tlv offset value 2353 */ 2354 static inline 2355 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2356 { 2357 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2358 2359 if (!hal_soc || !hal_soc->ops) { 2360 hal_err("hal handle is NULL"); 2361 QDF_BUG(0); 2362 return 0; 2363 } 2364 2365 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2366 } 2367 2368 static inline 2369 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2370 { 2371 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2372 2373 if (!hal_soc || !hal_soc->ops) { 2374 hal_err("hal handle is NULL"); 2375 QDF_BUG(0); 2376 return 0; 2377 } 2378 2379 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2380 } 2381 2382 /** 2383 * hal_rx_mpdu_end_offset_get(): Get the MPDU end offset from 2384 * rx_pkt_tlvs structure 2385 * 2386 * @hal_soc_hdl: HAL SOC handle 2387 * return: mpdu_end_tlv offset value 2388 */ 2389 static inline 2390 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2391 { 2392 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2393 2394 if (!hal_soc || !hal_soc->ops) { 2395 hal_err("hal handle is NULL"); 2396 QDF_BUG(0); 2397 return 0; 2398 } 2399 2400 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2401 } 2402 2403 /** 2404 * hal_rx_attn_offset_get(): Get the ATTENTION offset from 2405 * rx_pkt_tlvs structure 2406 * 2407 * @hal_soc_hdl: HAL SOC handle 2408 * return: attn_tlv offset value 2409 */ 2410 static inline 2411 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2412 { 2413 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2414 2415 if (!hal_soc || !hal_soc->ops) { 2416 hal_err("hal handle is NULL"); 2417 QDF_BUG(0); 2418 return 0; 2419 } 2420 2421 return hal_soc->ops->hal_rx_attn_offset_get(); 2422 } 2423 2424 /** 2425 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 2426 * @msdu_details_ptr - Pointer to msdu_details_ptr 2427 * @hal - pointer to hal_soc 2428 * Return - Pointer to rx_msdu_desc_info structure. 2429 * 2430 */ 2431 static inline 2432 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2433 struct hal_soc *hal_soc) 2434 { 2435 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2436 msdu_details_ptr); 2437 } 2438 2439 static inline void 2440 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2441 uint8_t *buf, uint8_t dbg_level) 2442 { 2443 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2444 2445 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2446 } 2447 2448 //TODO - Change the names to not include tlv names 2449 static inline uint16_t 2450 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2451 { 2452 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2453 2454 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2455 } 2456 2457 static inline uint32_t 2458 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2459 { 2460 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2461 2462 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2463 } 2464 2465 static inline uint32_t 2466 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2467 { 2468 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2469 2470 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2471 } 2472 2473 static inline uint16_t 2474 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2475 { 2476 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2477 2478 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2479 } 2480 2481 static inline int 2482 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2483 uint8_t *rx_pkt_tlv, 2484 struct hal_offload_info *offload_info) 2485 { 2486 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2487 2488 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2489 offload_info); 2490 2491 } 2492 2493 static inline int 2494 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2495 void *proto_params) 2496 { 2497 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2498 2499 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2500 } 2501 2502 static inline int 2503 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2504 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2505 { 2506 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2507 2508 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2509 l3_hdr_offset, 2510 l4_hdr_offset); 2511 } 2512 2513 static inline uint32_t 2514 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2515 { 2516 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2517 2518 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2519 } 2520 2521 /* 2522 * hal_rx_tlv_get_pkt_type(): API to get the pkt type 2523 * from rx_msdu_start 2524 * 2525 * @buf: pointer to the start of RX PKT TLV header 2526 * Return: uint32_t(pkt type) 2527 */ 2528 2529 static inline uint32_t 2530 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2531 { 2532 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2533 2534 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2535 } 2536 2537 static inline void 2538 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2539 uint8_t *buf, uint64_t *pn_num) 2540 { 2541 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2542 2543 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2544 } 2545 2546 static inline uint32_t 2547 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2548 { 2549 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2550 2551 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2552 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2553 2554 return 0; 2555 } 2556 2557 static inline uint8_t * 2558 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2559 { 2560 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2561 2562 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2563 } 2564 2565 static inline uint8_t 2566 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2567 { 2568 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2569 2570 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2571 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2572 2573 return 0; 2574 } 2575 2576 static inline uint32_t 2577 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2578 { 2579 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2580 2581 if (hal_soc->ops->hal_rx_tlv_get_freq) 2582 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2583 2584 return 0; 2585 } 2586 2587 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2588 void *mpdu_desc_info, uint32_t val) 2589 { 2590 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2591 2592 if (hal_soc->ops->hal_mpdu_desc_info_set) 2593 return hal_soc->ops->hal_mpdu_desc_info_set( 2594 hal_soc_hdl, mpdu_desc_info, val); 2595 } 2596 2597 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2598 void *msdu_desc_info, 2599 uint32_t val, uint32_t nbuf_len) 2600 { 2601 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2602 2603 if (hal_soc->ops->hal_msdu_desc_info_set) 2604 return hal_soc->ops->hal_msdu_desc_info_set( 2605 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2606 } 2607 2608 static inline uint32_t 2609 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2610 { 2611 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2612 2613 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2614 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2615 hal_soc_hdl, msdu_link_desc); 2616 2617 return 0; 2618 } 2619 2620 static inline uint32_t 2621 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2622 { 2623 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2624 2625 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2626 } 2627 2628 static inline uint32_t 2629 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2630 { 2631 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2632 2633 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2634 } 2635 2636 static inline uint32_t 2637 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2638 { 2639 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2640 2641 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2642 } 2643 2644 static inline uint32_t 2645 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2646 { 2647 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2648 2649 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2650 } 2651 2652 static inline uint32_t 2653 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2654 { 2655 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2656 2657 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2658 } 2659 2660 static inline uint32_t 2661 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2662 hal_ring_desc_t ring_desc) 2663 { 2664 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2665 2666 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2667 } 2668 2669 /** 2670 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2671 * from the BUFFER_ADDR_INFO structure 2672 * given a REO destination ring descriptor. 2673 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2674 * 2675 * Return: uint8_t (value of the return_buffer_manager) 2676 */ 2677 static inline uint8_t 2678 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2679 hal_ring_desc_t ring_desc) 2680 { 2681 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2682 2683 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2684 } 2685 2686 /* 2687 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2688 * rxdma ring entry. 2689 * @rxdma_entry: descriptor entry 2690 * @paddr: physical address of nbuf data pointer. 2691 * @cookie: SW cookie used as a index to SW rx desc. 2692 * @manager: who owns the nbuf (host, NSS, etc...). 2693 * 2694 */ 2695 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 2696 void *rxdma_entry, 2697 qdf_dma_addr_t paddr, 2698 uint32_t cookie, 2699 uint8_t manager) 2700 { 2701 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2702 2703 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 2704 paddr, 2705 cookie, 2706 manager); 2707 } 2708 2709 static inline uint32_t 2710 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2711 { 2712 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2713 2714 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 2715 } 2716 2717 static inline void 2718 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 2719 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 2720 { 2721 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2722 2723 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 2724 ip_csum_err, 2725 tcp_udp_csum_err); 2726 } 2727 2728 static inline void 2729 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 2730 uint8_t *rx_tlv_hdr, 2731 struct hal_rx_pkt_capture_flags *flags) 2732 { 2733 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2734 2735 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 2736 flags); 2737 } 2738 2739 static inline uint8_t 2740 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2741 { 2742 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2743 2744 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 2745 } 2746 2747 static inline uint8_t 2748 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 2749 { 2750 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2751 2752 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 2753 } 2754 2755 /** 2756 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 2757 * @hal_soc_hdl: HAL SoC handle 2758 * @ring_desc: REO ring descriptor 2759 * @prev_pn: Buffer to populate the previos PN 2760 * 2761 * Return: None 2762 */ 2763 static inline void 2764 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 2765 uint64_t *prev_pn) 2766 { 2767 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2768 2769 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 2770 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 2771 } 2772 2773 /** 2774 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 2775 * from rx mpdu info 2776 * @buf: pointer to rx_pkt_tlvs 2777 * 2778 * No input validdataion, since this function is supposed to be 2779 * called from fastpath. 2780 * 2781 * Return: ampdu flag 2782 */ 2783 static inline bool 2784 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2785 { 2786 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2787 2788 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 2789 } 2790 2791 #endif /* _HAL_RX_H */ 2792