1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_RX_H_ 21 #define _HAL_RX_H_ 22 23 #include <hal_api.h> 24 #include "hal_rx_hw_defines.h" 25 #include "hal_hw_headers.h" 26 27 /************************************* 28 * Ring desc offset/shift/masks 29 *************************************/ 30 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 31 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 32 #define HAL_RX_LSB(block, field) block##_##field##_LSB 33 #define HAL_RX_MASK(block, field) block##_##field##_MASK 34 #define HAL_RX_TLV_L3_TYPE_INVALID 0xFFFF 35 36 #define HAL_RX_GET(_ptr, block, field) \ 37 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 38 HAL_RX_MASK(block, field)) >> \ 39 HAL_RX_LSB(block, field)) 40 41 #define HAL_RX_GET_64(_ptr, block, field) \ 42 (((*((volatile uint64_t *)(_ptr) + \ 43 (HAL_RX_OFFSET(block, field) >> 3))) & \ 44 HAL_RX_MASK(block, field)) >> \ 45 HAL_RX_LSB(block, field)) 46 47 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 48 (*(uint32_t *)(((uint8_t *)_ptr) + \ 49 _wrd ## _ ## _field ## _OFFSET) |= \ 50 (((_val) << _wrd ## _ ## _field ## _LSB) & \ 51 _wrd ## _ ## _field ## _MASK)) 52 53 /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 54 #ifndef RX_DATA_BUFFER_SIZE 55 #define RX_DATA_BUFFER_SIZE 2048 56 #endif 57 58 #ifndef RX_MONITOR_BUFFER_SIZE 59 #define RX_MONITOR_BUFFER_SIZE 2048 60 #endif 61 62 #define RXDMA_OPTIMIZATION 63 64 /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes 65 * including buffer reservation, buffer alignment and skb shared info size. 66 */ 67 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 68 #define RX_MON_STATUS_BUF_ALIGN 128 69 #define RX_MON_STATUS_BUF_RESERVATION 128 70 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 71 (RX_MON_STATUS_BUF_RESERVATION + \ 72 RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE)) 73 74 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 75 76 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 77 #define HAL_RX_NON_QOS_TID 16 78 79 enum { 80 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 81 HAL_HW_RX_DECAP_FORMAT_NWIFI, 82 HAL_HW_RX_DECAP_FORMAT_ETH2, 83 HAL_HW_RX_DECAP_FORMAT_8023, 84 }; 85 86 /** 87 * struct hal_wbm_err_desc_info - structure to hold wbm error codes and reasons 88 * 89 * The fields of this structure is aligned to HAL Rx WBM2SW Ring desc, 90 * inorder to efficiently copy the data from desc to struct. 91 * Do not change the sequence of the fields. 92 * 93 * @wbm_err_src: Module which initiated the buffer release 94 * @bm_action: BM action 95 * @buffer_or_desc_type: Type of Buffer or Desc released 96 * @return_buffer_manager: Buffer address Info for debug 97 * @pool_id: pool ID, indicates which rxdma pool 98 * @cache_id: cache Id 99 * @cookie_conversion_status: cookie conversion status 100 * @rxdma_psh_rsn: RXDMA push reason 101 * @rxdma_err_code: RXDMA Error code 102 * @reo_psh_rsn: REO push reason 103 * @reo_err_code: REO Error code 104 * @wbm_internal_error: WBM Internal error 105 */ 106 struct hal_wbm_err_desc_info { 107 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 108 uint32_t wbm_err_src : 3, 109 bm_action : 3, 110 buffer_or_desc_type : 3, 111 return_buffer_manager : 4, 112 pool_id : 2, 113 cache_id : 1, 114 cookie_conversion_status : 1, 115 rxdma_psh_rsn : 2, 116 rxdma_err_code : 5, 117 reo_psh_rsn : 2, 118 reo_err_code : 5, 119 wbm_internal_error : 1; 120 #else 121 uint32_t wbm_internal_error : 1, 122 reo_err_code : 5, 123 reo_psh_rsn : 2, 124 rxdma_err_code : 5, 125 rxdma_psh_rsn : 2, 126 cookie_conversion_status : 1, 127 cache_id : 1, 128 pool_id : 2, 129 return_buffer_manager : 4, 130 buffer_or_desc_type : 3, 131 bm_action : 3, 132 wbm_err_src : 3; 133 #endif 134 }; 135 136 /** 137 * union hal_wbm_err_info_u - Union to hold wbm error information 138 * @info_bit: hal_wbm_err_desc_info: structure to hold wbm error info bit fields 139 * @info: variable to hold wbm error info 140 * 141 */ 142 union hal_wbm_err_info_u { 143 struct hal_wbm_err_desc_info info_bit; 144 uint32_t info; 145 }; 146 147 /** 148 * struct hal_rx_mon_dest_buf_info - Structure to hold rx mon dest buffer info 149 * @first_buffer: First buffer of MSDU 150 * @last_buffer: Last buffer of MSDU 151 * @is_decap_raw: Is RAW Frame 152 * @mpdu_len_err: Is there an MPDU length error 153 * @l2_hdr_pad: Amount of layer 2 header padding 154 * @reserved_1: Reserved 155 * 156 * MSDU with continuation: 157 * ----------------------------------------------------------- 158 * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 | 159 * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 | 160 * | is_decap_raw:1/0 | Same as earlier | Same as earlier| 161 * ----------------------------------------------------------- 162 * 163 * Single buffer MSDU: 164 * ------------------ 165 * | first_buffer:1 | 166 * | last_buffer :1 | 167 * | is_decap_raw:1/0 | 168 * ------------------ 169 */ 170 struct hal_rx_mon_dest_buf_info { 171 uint8_t first_buffer:1, 172 last_buffer:1, 173 is_decap_raw:1, 174 mpdu_len_err:1, 175 l2_hdr_pad:2, 176 reserved_1:2; 177 }; 178 179 /** 180 * struct hal_rx_msdu_metadata - Structure to hold rx fast path information. 181 * 182 * @l3_hdr_pad: l3 header padding 183 * @reserved: Reserved bits 184 * @sa_sw_peer_id: sa sw peer id 185 * @sa_idx: sa index 186 * @da_idx: da index 187 */ 188 struct hal_rx_msdu_metadata { 189 uint32_t l3_hdr_pad:16, 190 sa_sw_peer_id:16; 191 uint32_t sa_idx:16, 192 da_idx:16; 193 }; 194 195 struct hal_proto_params { 196 uint8_t tcp_proto; 197 uint8_t udp_proto; 198 uint8_t ipv6_proto; 199 }; 200 201 /** 202 * enum hal_reo_error_status - Enum which encapsulates "reo_push_reason" 203 * 204 * @HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 205 * @HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 206 */ 207 enum hal_reo_error_status { 208 HAL_REO_ERROR_DETECTED = 0, 209 HAL_REO_ROUTING_INSTRUCTION = 1, 210 }; 211 212 /** 213 * struct hal_rx_msdu_desc_info - RX MSDU Descriptor 214 * @msdu_flags: [0] first_msdu_in_mpdu 215 * [1] last_msdu_in_mpdu 216 * [2] msdu_continuation - MSDU spread across buffers 217 * [23] sa_is_valid - SA match in peer table 218 * [24] sa_idx_timeout - Timeout while searching for SA match 219 * [25] da_is_valid - Used to identtify intra-bss forwarding 220 * [26] da_is_MCBC 221 * [27] da_idx_timeout - Timeout while searching for DA match 222 * @msdu_len: length of the MSDU (14 bits of length) 223 * 224 */ 225 struct hal_rx_msdu_desc_info { 226 uint32_t msdu_flags; 227 uint16_t msdu_len; 228 }; 229 230 /** 231 * enum hal_rx_msdu_desc_flags - Enum for flags in MSDU_DESC_INFO 232 * 233 * @HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 234 * @HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 235 * @HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 236 * @HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 237 * @HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 238 * @HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 239 * @HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 240 * @HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 241 * @HAL_MSDU_F_INTRA_BSS: This is an intrabss packet 242 */ 243 enum hal_rx_msdu_desc_flags { 244 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 245 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 246 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 247 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 248 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 249 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 250 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 251 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27), 252 HAL_MSDU_F_INTRA_BSS = (0x1 << 28), 253 }; 254 255 /** 256 * struct hal_rx_mpdu_desc_info - RX MPDU descriptor 257 * @msdu_count: no. of msdus in the MPDU 258 * @mpdu_seq: MPDU sequence number 259 * @mpdu_flags: [0] Fragment flag 260 * [1] MPDU_retry_bit 261 * [2] AMPDU flag 262 * [3] raw_ampdu 263 * @peer_meta_data: Upper bits containing peer id, vdev id 264 * @bar_frame: indicates if received frame is a bar frame 265 * @tid: tid value of received MPDU 266 * @reserved: spare bits 267 */ 268 struct hal_rx_mpdu_desc_info { 269 uint16_t msdu_count; 270 uint16_t mpdu_seq; /* 12 bits for length */ 271 uint32_t mpdu_flags; 272 uint32_t peer_meta_data; /* sw programmed meta-data:MAC Id & peer Id */ 273 uint16_t bar_frame; 274 uint8_t tid:4, 275 reserved:4; 276 }; 277 278 /** 279 * enum hal_rx_mpdu_desc_flags - Enum for flags in MPDU_DESC_INFO 280 * 281 * @HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 282 * @HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 283 * @HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 284 * @HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 285 * @HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field 286 */ 287 enum hal_rx_mpdu_desc_flags { 288 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 289 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 290 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 291 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30), 292 HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31) 293 }; 294 295 /* Return Buffer manager ID */ 296 #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0 297 #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1 298 #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2 299 #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3 300 #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id) 301 #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1) 302 #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2) 303 #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3) 304 #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4) 305 #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5) 306 #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6) 307 308 #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id) 309 310 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8 311 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0 312 #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff 313 314 #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \ 315 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 316 HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \ 317 HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \ 318 HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB)) 319 320 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 321 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 322 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 323 324 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4 325 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 326 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 327 328 /* 329 * macro to set the LSW of the nbuf data physical address 330 * to the rxdma ring entry 331 */ 332 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 333 ((*(((unsigned int *) buff_addr_info) + \ 334 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 335 (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \ 336 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK) 337 338 /* 339 * macro to set the LSB of MSW of the nbuf data physical address 340 * to the rxdma ring entry 341 */ 342 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 343 ((*(((unsigned int *) buff_addr_info) + \ 344 (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 345 (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \ 346 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) 347 348 #ifdef DP_RX_DESC_COOKIE_INVALIDATE 349 #define HAL_RX_COOKIE_INVALID_MASK 0x80000000 350 351 /* 352 * macro to get the invalid bit for sw cookie 353 */ 354 #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \ 355 ((*(((unsigned int *)buff_addr_info) + \ 356 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 357 HAL_RX_COOKIE_INVALID_MASK) 358 359 /* 360 * macro to set the invalid bit for sw cookie 361 */ 362 #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \ 363 ((*(((unsigned int *)buff_addr_info) + \ 364 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 365 HAL_RX_COOKIE_INVALID_MASK) 366 367 /* 368 * macro to reset the invalid bit for sw cookie 369 */ 370 #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \ 371 ((*(((unsigned int *)buff_addr_info) + \ 372 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 373 ~HAL_RX_COOKIE_INVALID_MASK) 374 375 #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \ 376 (HAL_RX_BUF_COOKIE_INVALID_GET(& \ 377 (((struct reo_destination_ring *) \ 378 reo_desc)->buf_or_link_desc_addr_info))) 379 380 #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \ 381 (HAL_RX_BUF_COOKIE_INVALID_SET(& \ 382 (((struct reo_destination_ring *) \ 383 reo_desc)->buf_or_link_desc_addr_info))) 384 385 #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000 386 387 #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \ 388 ((*(((unsigned int *)buff_addr_info) + \ 389 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \ 390 HAL_RX_LINK_COOKIE_INVALID_MASK) 391 392 #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \ 393 ((*(((unsigned int *)buff_addr_info) + \ 394 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 395 HAL_RX_LINK_COOKIE_INVALID_MASK) 396 397 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \ 398 (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \ 399 (((struct reo_destination_ring *) \ 400 reo_desc)->buf_or_link_desc_addr_info))) 401 402 #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \ 403 (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \ 404 (((struct reo_destination_ring *) \ 405 reo_desc)->buf_or_link_desc_addr_info))) 406 #endif 407 408 /* TODO: Convert the following structure fields accesseses to offsets */ 409 410 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 411 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 412 (((struct reo_destination_ring *) \ 413 reo_desc)->buf_or_link_desc_addr_info))) 414 415 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 416 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 417 (((struct reo_destination_ring *) \ 418 reo_desc)->buf_or_link_desc_addr_info))) 419 420 #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \ 421 (HAL_RX_BUF_COOKIE_INVALID_RESET(& \ 422 (((struct reo_destination_ring *) \ 423 reo_desc)->buf_or_link_desc_addr_info))) 424 425 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 426 HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \ 427 _field, _val) 428 429 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0 430 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 431 #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 432 433 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 434 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 435 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 436 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 437 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 438 439 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 440 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 441 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 442 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 443 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 444 445 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 446 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 447 #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 448 449 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0 450 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 451 #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 452 453 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 454 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 455 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 456 (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 457 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 458 459 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 460 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 461 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \ 462 (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 463 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 464 465 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 466 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 467 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 468 HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK) 469 470 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 471 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 472 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 473 HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK) 474 475 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0 476 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 477 #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 478 479 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 480 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 481 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \ 482 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \ 483 HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB)) 484 485 static inline uint32_t 486 hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl, 487 rx_msdu_desc_info_t msdu_desc_info_hdl) 488 { 489 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 490 491 return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl); 492 } 493 494 /* 495 * Structures & Macros to obtain fields from the TLV's in the Rx packet 496 * pre-header. 497 */ 498 499 static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl, 500 void *hw_desc_addr) 501 { 502 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 503 504 return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr); 505 } 506 507 /** 508 * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params 509 * @hal_soc_hdl: hal soc handle 510 * @desc_addr: ring descriptor 511 * @mpdu_desc_info: Buffer to fill the mpdu desc info params 512 * 513 * Return: None 514 */ 515 static inline void 516 hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr, 517 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 518 { 519 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 520 521 return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr, 522 mpdu_desc_info); 523 } 524 525 #define HAL_RX_NUM_MSDU_DESC 6 526 #define HAL_RX_MAX_SAVED_RING_DESC 16 527 528 /* TODO: rework the structure */ 529 struct hal_rx_msdu_list { 530 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 531 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 532 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 533 /* physical address of the msdu */ 534 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 535 }; 536 537 struct hal_buf_info { 538 uint64_t paddr; 539 uint32_t sw_cookie; 540 uint8_t rbm; 541 }; 542 543 /* This special cookie value will be used to indicate FW allocated buffers 544 * received through RXDMA2SW ring for RXDMA WARs 545 */ 546 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 547 548 /** 549 * enum hal_rx_reo_buf_type - Indicates that type of buffer or descriptor 550 * 551 * @HAL_RX_REO_MSDU_BUF_ADDR_TYPE: Reo buffer address points to the MSDU buffer 552 * @HAL_RX_REO_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 553 * descriptor 554 */ 555 enum hal_rx_reo_buf_type { 556 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 557 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 558 }; 559 560 /** 561 * enum hal_reo_error_code - Error code describing the type of error detected 562 * 563 * @HAL_REO_ERR_QUEUE_DESC_ADDR_0: Reo queue descriptor provided in the 564 * REO_ENTRANCE ring is set to 0 565 * @HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 566 * @HAL_REO_ERR_AMPDU_IN_NON_BA: AMPDU frame received without BA session 567 * having been setup 568 * @HAL_REO_ERR_NON_BA_DUPLICATE: Non-BA session, SN equal to SSN, 569 * Retry bit set: duplicate frame 570 * @HAL_REO_ERR_BA_DUPLICATE: BA session, duplicate frame 571 * @HAL_REO_ERR_REGULAR_FRAME_2K_JUMP: A normal (management/data frame) 572 * received with 2K jump in SN 573 * @HAL_REO_ERR_BAR_FRAME_2K_JUMP: A bar received with 2K jump in SSN 574 * @HAL_REO_ERR_REGULAR_FRAME_OOR: A normal (management/data frame) received 575 * with SN falling within the OOR window 576 * @HAL_REO_ERR_BAR_FRAME_OOR: A bar received with SSN falling within the 577 * OOR window 578 * @HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION: A bar received without a BA session 579 * @HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN: A bar received with SSN equal to SN 580 * @HAL_REO_ERR_PN_CHECK_FAILED: PN Check Failed packet 581 * @HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET: Frame is forwarded as a result 582 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 583 * @HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET: Frame is forwarded as a result 584 * of the pn_error_detected_flag been set in the REO Queue descriptor 585 * @HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET: Frame is forwarded as a result of 586 * the queue descriptor(address) being blocked as SW/FW seems to be currently 587 * in the process of making updates to this descriptor 588 * @HAL_REO_ERR_MAX: count of number of enumerators 589 */ 590 enum hal_reo_error_code { 591 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 592 HAL_REO_ERR_QUEUE_DESC_INVALID, 593 HAL_REO_ERR_AMPDU_IN_NON_BA, 594 HAL_REO_ERR_NON_BA_DUPLICATE, 595 HAL_REO_ERR_BA_DUPLICATE, 596 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 597 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 598 HAL_REO_ERR_REGULAR_FRAME_OOR, 599 HAL_REO_ERR_BAR_FRAME_OOR, 600 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 601 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 602 HAL_REO_ERR_PN_CHECK_FAILED, 603 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 604 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 605 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 606 HAL_REO_ERR_MAX 607 }; 608 609 /** 610 * enum hal_rxdma_error_code - Code describing the type of RxDMA error detected 611 * 612 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 613 * @HAL_RXDMA_ERR_MPDU_LENGTH: MPDU frame is not complete due to receiving 614 * incomplete MPDU from the PHY 615 * @HAL_RXDMA_ERR_FCS: FCS check on the MPDU frame failed 616 * @HAL_RXDMA_ERR_DECRYPT: Decryption error 617 * @HAL_RXDMA_ERR_TKIP_MIC: TKIP MIC error 618 * @HAL_RXDMA_ERR_UNENCRYPTED: Received a frame that was expected to be 619 * encrypted but wasn’t 620 * @HAL_RXDMA_ERR_MSDU_LEN: MSDU related length error 621 * @HAL_RXDMA_ERR_MSDU_LIMIT: Number of MSDUs in the MPDUs exceeded 622 * the max allowed 623 * @HAL_RXDMA_ERR_WIFI_PARSE: wifi parsing error 624 * @HAL_RXDMA_ERR_AMSDU_PARSE: Amsdu parsing error 625 * @HAL_RXDMA_ERR_SA_TIMEOUT: Source Address search timeout 626 * @HAL_RXDMA_ERR_DA_TIMEOUT: Destination Address search timeout 627 * @HAL_RXDMA_ERR_FLOW_TIMEOUT: Flow Search Timeout 628 * @HAL_RXDMA_ERR_FLUSH_REQUEST: RxDMA FIFO Flush request 629 * @HAL_RXDMA_AMSDU_FRAGMENT: Rx PCU reported A-MSDU 630 * present as well as a fragmented MPDU 631 * @HAL_RXDMA_MULTICAST_ECHO: RX OLE reported a multicast echo 632 * @HAL_RXDMA_AMSDU_ADDR_MISMATCH: RX OLE reported AMSDU address mismatch 633 * @HAL_RXDMA_UNAUTHORIZED_WDS: RX PCU reported unauthorized wds 634 * @HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS: RX PCU reported group cast AMSDU or WDS 635 * @HAL_RXDMA_ERR_WAR: RxDMA WAR dummy errors 636 * @HAL_RXDMA_ERR_MAX: count of number of enumerators 637 */ 638 enum hal_rxdma_error_code { 639 HAL_RXDMA_ERR_OVERFLOW = 0, 640 HAL_RXDMA_ERR_MPDU_LENGTH, 641 HAL_RXDMA_ERR_FCS, 642 HAL_RXDMA_ERR_DECRYPT, 643 HAL_RXDMA_ERR_TKIP_MIC, 644 HAL_RXDMA_ERR_UNENCRYPTED, 645 HAL_RXDMA_ERR_MSDU_LEN, 646 HAL_RXDMA_ERR_MSDU_LIMIT, 647 HAL_RXDMA_ERR_WIFI_PARSE, 648 HAL_RXDMA_ERR_AMSDU_PARSE, 649 HAL_RXDMA_ERR_SA_TIMEOUT, 650 HAL_RXDMA_ERR_DA_TIMEOUT, 651 HAL_RXDMA_ERR_FLOW_TIMEOUT, 652 HAL_RXDMA_ERR_FLUSH_REQUEST, 653 HAL_RXDMA_AMSDU_FRAGMENT, 654 HAL_RXDMA_MULTICAST_ECHO, 655 HAL_RXDMA_AMSDU_ADDR_MISMATCH, 656 HAL_RXDMA_UNAUTHORIZED_WDS, 657 HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS, 658 HAL_RXDMA_ERR_WAR = 31, 659 HAL_RXDMA_ERR_MAX 660 }; 661 662 /* 663 * HW BM action settings in WBM release ring 664 */ 665 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 666 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 667 668 /** 669 * enum hal_rx_wbm_error_source - Indicates which module initiated the 670 * release of this buffer or descriptor 671 * 672 * @HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 673 * @HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 674 * @HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 675 * @HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 676 * @HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 677 */ 678 enum hal_rx_wbm_error_source { 679 HAL_RX_WBM_ERR_SRC_TQM = 0, 680 HAL_RX_WBM_ERR_SRC_RXDMA, 681 HAL_RX_WBM_ERR_SRC_REO, 682 HAL_RX_WBM_ERR_SRC_FW, 683 HAL_RX_WBM_ERR_SRC_SW, 684 }; 685 686 /** 687 * enum hal_rx_wbm_buf_type - Indicates that type of buffer or descriptor 688 * released 689 * 690 * @HAL_RX_WBM_BUF_TYPE_REL_BUF: 691 * @HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC: 692 * @HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC: 693 * @HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC: 694 * @HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC: 695 */ 696 enum hal_rx_wbm_buf_type { 697 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 698 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 699 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 700 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 701 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 702 }; 703 704 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 705 706 /** 707 * hal_rx_msdu_is_wlan_mcast() - Check if the buffer is for multicast address 708 * @hal_soc_hdl: hal soc handle 709 * @nbuf: Network buffer 710 * 711 * Return: flag to indicate whether the nbuf has MC/BC address 712 */ 713 static inline uint32_t 714 hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl, 715 qdf_nbuf_t nbuf) 716 { 717 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 718 719 return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf); 720 } 721 722 /** 723 * hal_rx_priv_info_set_in_tlv() - Save the private info to 724 * the reserved bytes of rx_tlv_hdr 725 * @hal_soc_hdl: hal soc handle 726 * @buf: start of rx_tlv_hdr 727 * @priv_data: private info to store 728 * @len: length of @priv_data 729 * 730 * Return: void 731 */ 732 static inline void 733 hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl, 734 uint8_t *buf, uint8_t *priv_data, 735 uint32_t len) 736 { 737 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 738 739 return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf, 740 priv_data, 741 len); 742 } 743 744 /** 745 * hal_rx_reo_ent_rxdma_push_reason_get() - Retrieves RXDMA push reason from 746 * reo_entrance_ring descriptor 747 * 748 * @reo_ent_desc: reo_entrance_ring descriptor 749 * 750 * Return: value of rxdma_push_reason 751 */ 752 static inline 753 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 754 { 755 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 756 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)), 757 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK, 758 HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB); 759 } 760 761 /** 762 * hal_rx_reo_ent_rxdma_error_code_get() - Retrieves RXDMA error code from 763 * reo_entrance_ring descriptor 764 * @reo_ent_desc: reo_entrance_ring descriptor 765 * 766 * Return: value of rxdma_error_code 767 */ 768 static inline 769 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 770 { 771 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 772 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)), 773 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK, 774 HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB); 775 } 776 777 /** 778 * hal_rx_priv_info_get_from_tlv() - retrieve the private data from 779 * the reserved bytes of rx_tlv_hdr. 780 * @hal_soc_hdl: hal soc handle 781 * @buf: start of rx_tlv_hdr 782 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 783 * @len: length of the buffer 784 * 785 * Return: void 786 */ 787 static inline void 788 hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl, 789 uint8_t *buf, uint8_t *wbm_er_info, 790 uint32_t len) 791 { 792 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 793 794 return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf, 795 wbm_er_info, 796 len); 797 } 798 799 static inline void 800 hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size, 801 uint16_t *rx_mon_pkt_tlv_size) 802 { 803 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 804 805 return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size, 806 rx_mon_pkt_tlv_size); 807 } 808 809 /** 810 * hal_rx_encryption_info_valid() - Returns encryption type. 811 * @hal_soc_hdl: hal soc handle 812 * @buf: rx_tlv_hdr of the received packet 813 * 814 * Return: encryption type 815 */ 816 static inline uint32_t 817 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 818 { 819 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 820 821 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 822 } 823 824 /** 825 * hal_rx_print_pn() - Prints the PN of rx packet. 826 * @hal_soc_hdl: hal soc handle 827 * @buf: rx_tlv_hdr of the received packet 828 * 829 * Return: void 830 */ 831 static inline void 832 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 833 { 834 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 835 836 hal_soc->ops->hal_rx_print_pn(buf); 837 } 838 839 /** 840 * hal_rx_msdu_end_l3_hdr_padding_get() - API to get the 841 * l3_header padding from rx_msdu_end TLV 842 * @hal_soc_hdl: hal_soc handle 843 * @buf: pointer to the start of RX PKT TLV headers 844 * 845 * Return: number of l3 header padding bytes 846 */ 847 static inline uint32_t 848 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 849 uint8_t *buf) 850 { 851 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 852 853 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 854 } 855 856 /** 857 * hal_rx_msdu_end_sa_idx_get() - API to get the sa_idx from rx_msdu_end TLV 858 * @hal_soc_hdl: hal_soc handle 859 * @buf: pointer to the start of RX PKT TLV headers 860 * 861 * Return: sa_idx (SA AST index) 862 */ 863 static inline uint16_t 864 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 865 uint8_t *buf) 866 { 867 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 868 869 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 870 } 871 872 /** 873 * hal_rx_msdu_end_sa_is_valid_get() - API to get the 874 * sa_is_valid bit from rx_msdu_end TLV 875 * @hal_soc_hdl: hal_soc handle 876 * @buf: pointer to the start of RX PKT TLV headers 877 * 878 * Return: sa_is_valid bit 879 */ 880 static inline uint8_t 881 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 882 uint8_t *buf) 883 { 884 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 885 886 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 887 } 888 889 /** 890 * hal_rx_tlv_msdu_len_set() - API to set the MSDU length from rx_msdu_start TLV 891 * @hal_soc_hdl: hal_soc handle 892 * @buf: pointer to the start of RX PKT TLV headers 893 * @len: msdu length 894 * 895 * Return: none 896 */ 897 static inline void 898 hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 899 uint32_t len) 900 { 901 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 902 903 return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len); 904 } 905 906 /** 907 * enum hal_rx_mpdu_info_sw_frame_group_id_type - Enum for group id in MPDU_INFO 908 * 909 * @HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 910 * @HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 911 * @HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 912 * @HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 913 * @HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 914 * @HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame 915 * @HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON: beacon frame 916 * @HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 917 * @HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame 918 * @HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame 919 * @HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame 920 * @HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 921 * @HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 922 */ 923 enum hal_rx_mpdu_info_sw_frame_group_id_type { 924 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 925 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 926 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 927 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 928 HAL_MPDU_SW_FRAME_GROUP_MGMT, 929 HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8, 930 HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12, 931 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 932 HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25, 933 HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28, 934 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31, 935 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 936 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 937 }; 938 939 /** 940 * hal_rx_mpdu_start_mpdu_qos_control_valid_get() - 941 * Retrieve qos control valid bit from the tlv. 942 * @hal_soc_hdl: hal_soc handle 943 * @buf: pointer to rx pkt TLV. 944 * 945 * Return: qos control value. 946 */ 947 static inline uint32_t 948 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 949 hal_soc_handle_t hal_soc_hdl, 950 uint8_t *buf) 951 { 952 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 953 954 if ((!hal_soc) || (!hal_soc->ops)) { 955 hal_err("hal handle is NULL"); 956 QDF_BUG(0); 957 return QDF_STATUS_E_INVAL; 958 } 959 960 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 961 return hal_soc->ops-> 962 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 963 964 return QDF_STATUS_E_INVAL; 965 } 966 967 /** 968 * hal_rx_is_unicast() - check packet is unicast frame or not. 969 * @hal_soc_hdl: hal_soc handle 970 * @buf: pointer to rx pkt TLV. 971 * 972 * Return: true on unicast. 973 */ 974 static inline bool 975 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 976 { 977 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 978 979 return hal_soc->ops->hal_rx_is_unicast(buf); 980 } 981 982 /** 983 * hal_rx_tid_get() - get tid based on qos control valid. 984 * @hal_soc_hdl: hal soc handle 985 * @buf: pointer to rx pkt TLV. 986 * 987 * Return: tid 988 */ 989 static inline uint32_t 990 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 991 { 992 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 993 994 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 995 } 996 997 /** 998 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 999 * @hal_soc_hdl: hal soc handle 1000 * @buf: pointer to rx pkt TLV. 1001 * 1002 * Return: sw peer_id 1003 */ 1004 static inline uint32_t 1005 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1006 uint8_t *buf) 1007 { 1008 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1009 1010 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1011 } 1012 1013 /** 1014 * hal_rx_tlv_peer_meta_data_get() - Retrieve PEER_META_DATA 1015 * @hal_soc_hdl: hal soc handle 1016 * @buf: pointer to rx pkt TLV. 1017 * 1018 * Return: peer meta data 1019 */ 1020 static inline uint32_t 1021 hal_rx_tlv_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl, 1022 uint8_t *buf) 1023 { 1024 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1025 1026 return hal_soc->ops->hal_rx_tlv_peer_meta_data_get(buf); 1027 } 1028 1029 /** 1030 * hal_rx_mpdu_get_to_ds() - API to get the tods info from rx_mpdu_start 1031 * @hal_soc_hdl: hal_soc handle 1032 * @buf: pointer to the start of RX PKT TLV header 1033 * 1034 * Return: uint32_t(to_ds) 1035 */ 1036 1037 static inline uint32_t 1038 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1039 { 1040 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1041 1042 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1043 } 1044 1045 1046 /** 1047 * hal_rx_mpdu_get_fr_ds() - API to get the from ds info 1048 * from rx_mpdu_start 1049 * @hal_soc_hdl: hal soc handle 1050 * @buf: pointer to the start of RX PKT TLV header 1051 * 1052 * Return: uint32_t(fr_ds) 1053 */ 1054 static inline uint32_t 1055 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1056 { 1057 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1058 1059 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1060 } 1061 1062 /** 1063 * hal_rx_mpdu_get_addr1() - API to check get address1 of the mpdu 1064 * @hal_soc_hdl: hal soc handle 1065 * @buf: pointer to the start of RX PKT TLV headera 1066 * @mac_addr: pointer to mac address 1067 * 1068 * Return: success/failure 1069 */ 1070 static inline 1071 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1072 uint8_t *buf, uint8_t *mac_addr) 1073 { 1074 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1075 1076 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1077 } 1078 1079 /** 1080 * hal_rx_mpdu_get_addr2() - API to check get address2 of the mpdu 1081 * in the packet 1082 * @hal_soc_hdl: hal soc handle 1083 * @buf: pointer to the start of RX PKT TLV header 1084 * @mac_addr: pointer to mac address 1085 * 1086 * Return: success/failure 1087 */ 1088 static inline 1089 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1090 uint8_t *buf, uint8_t *mac_addr) 1091 { 1092 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1093 1094 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1095 } 1096 1097 /** 1098 * hal_rx_mpdu_get_addr3() - API to get address3 of the mpdu 1099 * in the packet 1100 * @hal_soc_hdl: hal soc handle 1101 * @buf: pointer to the start of RX PKT TLV header 1102 * @mac_addr: pointer to mac address 1103 * 1104 * Return: success/failure 1105 */ 1106 static inline 1107 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1108 uint8_t *buf, uint8_t *mac_addr) 1109 { 1110 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1111 1112 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1113 } 1114 1115 /** 1116 * hal_rx_mpdu_get_addr4() - API to get address4 of the mpdu 1117 * in the packet 1118 * @hal_soc_hdl: hal_soc handle 1119 * @buf: pointer to the start of RX PKT TLV header 1120 * @mac_addr: pointer to mac address 1121 * Return: success/failure 1122 */ 1123 static inline 1124 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1125 uint8_t *buf, uint8_t *mac_addr) 1126 { 1127 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1128 1129 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1130 } 1131 1132 /** 1133 * hal_rx_msdu_end_da_idx_get() - API to get da_idx from rx_msdu_end TLV 1134 * @hal_soc_hdl: hal_soc handle 1135 * @buf: pointer to the start of RX PKT TLV headers 1136 * 1137 * Return: da index 1138 */ 1139 static inline uint16_t 1140 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1141 { 1142 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1143 1144 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1145 } 1146 1147 /** 1148 * hal_rx_msdu_end_da_is_valid_get() - API to check if da is valid 1149 * from rx_msdu_end TLV 1150 * @hal_soc_hdl: hal soc handle 1151 * @buf: pointer to the start of RX PKT TLV headers 1152 * 1153 * Return: da_is_valid 1154 */ 1155 static inline uint8_t 1156 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1157 uint8_t *buf) 1158 { 1159 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1160 1161 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1162 } 1163 1164 /** 1165 * hal_rx_msdu_end_da_is_mcbc_get() - API to check if pkt is MCBC 1166 * from rx_msdu_end TLV 1167 * @hal_soc_hdl: HAL SOC handle 1168 * @buf: pointer to the start of RX PKT TLV headers 1169 * 1170 * Return: da_is_mcbc 1171 */ 1172 static inline uint8_t 1173 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1174 { 1175 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1176 1177 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1178 } 1179 1180 /** 1181 * hal_rx_msdu_end_is_tkip_mic_err() - API to check if pkt has mic error 1182 * from rx_msdu_end TLV 1183 * @hal_soc_hdl: HAL SOC handle 1184 * @buf: pointer to the start of RX PKT TLV headers 1185 * 1186 * Return: tkip_mic_err 1187 */ 1188 static inline uint8_t 1189 hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl, 1190 uint8_t *buf) 1191 { 1192 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1193 1194 if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err) 1195 return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf); 1196 else 1197 return 0; 1198 } 1199 1200 /** 1201 * hal_rx_msdu_end_first_msdu_get() - API to get first msdu status 1202 * from rx_msdu_end TLV 1203 * @hal_soc_hdl: hal soc handle 1204 * @buf: pointer to the start of RX PKT TLV headers 1205 * 1206 * Return: first_msdu 1207 */ 1208 static inline uint8_t 1209 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1210 uint8_t *buf) 1211 { 1212 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1213 1214 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1215 } 1216 1217 /** 1218 * hal_rx_msdu_end_last_msdu_get() - API to get last msdu status 1219 * from rx_msdu_end TLV 1220 * @hal_soc_hdl: hal soc handle 1221 * @buf: pointer to the start of RX PKT TLV headers 1222 * 1223 * Return: last_msdu 1224 */ 1225 static inline uint8_t 1226 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1227 uint8_t *buf) 1228 { 1229 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1230 1231 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1232 } 1233 1234 /** 1235 * hal_rx_msdu_cce_match_get() - API to get CCE match from rx_msdu_end TLV 1236 * @hal_soc_hdl: HAL SOC handle 1237 * @buf: pointer to the start of RX PKT TLV headers 1238 * 1239 * Return: cce_meta_data 1240 */ 1241 static inline bool 1242 hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl, 1243 uint8_t *buf) 1244 { 1245 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1246 1247 return hal_soc->ops->hal_rx_msdu_cce_match_get(buf); 1248 } 1249 1250 /** 1251 * hal_rx_msdu_cce_metadata_get() - API to get CCE metadata 1252 * from rx_msdu_end TLV 1253 * @hal_soc_hdl: HAL SOC handle 1254 * @buf: pointer to the start of RX PKT TLV headers 1255 * 1256 * Return: cce_meta_data 1257 */ 1258 static inline uint16_t 1259 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1260 uint8_t *buf) 1261 { 1262 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1263 1264 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1265 } 1266 1267 /******************************************************************************* 1268 * RX REO ERROR APIS 1269 ******************************************************************************/ 1270 1271 /** 1272 * hal_rx_link_desc_msdu0_ptr() - Get pointer to rx_msdu details 1273 * @msdu_link_ptr: msdu link ptr 1274 * @hal_soc: pointer to hal_soc 1275 * 1276 * Return: Pointer to rx_msdu_details structure 1277 * 1278 */ 1279 static inline 1280 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1281 struct hal_soc *hal_soc) 1282 { 1283 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1284 } 1285 1286 /** 1287 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1288 * @msdu_details_ptr: Pointer to msdu_details_ptr 1289 * @hal_soc: pointer to hal_soc 1290 * 1291 * Return: Pointer to rx_msdu_desc_info structure. 1292 * 1293 */ 1294 static inline 1295 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1296 struct hal_soc *hal_soc) 1297 { 1298 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1299 } 1300 1301 /** 1302 * hal_rx_reo_buf_paddr_get() - Gets the physical address and 1303 * cookie from the REO destination ring element 1304 * @hal_soc_hdl: HAL SOC handle 1305 * @rx_desc: the current descriptor 1306 * @buf_info: structure to return the buffer information 1307 * 1308 * Return: void 1309 */ 1310 static inline 1311 void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1312 hal_ring_desc_t rx_desc, 1313 struct hal_buf_info *buf_info) 1314 { 1315 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1316 1317 if (hal_soc->ops->hal_rx_reo_buf_paddr_get) 1318 return hal_soc->ops->hal_rx_reo_buf_paddr_get( 1319 rx_desc, 1320 buf_info); 1321 1322 } 1323 1324 /** 1325 * hal_rx_wbm_rel_buf_paddr_get() - Gets the physical address and 1326 * cookie from the WBM release ring element 1327 * @hal_soc_hdl: HAL SOC handle 1328 * @rx_desc: the current descriptor 1329 * @buf_info: structure to return the buffer information 1330 * 1331 * Return: void 1332 */ 1333 static inline 1334 void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 1335 hal_ring_desc_t rx_desc, 1336 struct hal_buf_info *buf_info) 1337 { 1338 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1339 1340 if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get) 1341 return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc, 1342 buf_info); 1343 } 1344 1345 /** 1346 * hal_rx_buf_cookie_rbm_get() - Gets the physical address and cookie 1347 * from the REO entrance ring element 1348 * @hal_soc_hdl: hal soc handle 1349 * @buf_addr_info: pointer to buf_addr_info structure 1350 * @buf_info: structure to return the buffer information 1351 * 1352 * Return: void 1353 */ 1354 static inline 1355 void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl, 1356 uint32_t *buf_addr_info, 1357 struct hal_buf_info *buf_info) 1358 { 1359 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1360 1361 return hal_soc->ops->hal_rx_buf_cookie_rbm_get( 1362 buf_addr_info, 1363 buf_info); 1364 } 1365 1366 /** 1367 * hal_rx_msdu_list_get() - API to get the MSDU information 1368 * from the MSDU link descriptor 1369 * @hal_soc_hdl: hal soc handle 1370 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1371 * MSDU link descriptor (struct rx_msdu_link) 1372 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1373 * @num_msdus: Number of MSDUs in the MPDU 1374 * 1375 * Return: void 1376 */ 1377 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1378 void *msdu_link_desc, 1379 struct hal_rx_msdu_list *msdu_list, 1380 uint16_t *num_msdus) 1381 { 1382 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1383 struct rx_msdu_details *msdu_details; 1384 struct rx_msdu_desc_info *msdu_desc_info; 1385 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1386 int i; 1387 struct hal_buf_info buf_info; 1388 1389 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1390 1391 dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK", 1392 __func__, __LINE__, msdu_link, msdu_details); 1393 1394 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1395 /* num_msdus received in mpdu descriptor may be incorrect 1396 * sometimes due to HW issue. Check msdu buffer address also 1397 */ 1398 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 1399 &msdu_details[i].buffer_addr_info_details) == 0)) 1400 break; 1401 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1402 &msdu_details[i].buffer_addr_info_details) == 0) { 1403 /* set the last msdu bit in the prev msdu_desc_info */ 1404 msdu_desc_info = 1405 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1406 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1407 break; 1408 } 1409 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1410 hal_soc); 1411 1412 /* set first MSDU bit or the last MSDU bit */ 1413 if (!i) 1414 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1415 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1416 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1417 1418 msdu_list->msdu_info[i].msdu_flags = 1419 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 1420 msdu_list->msdu_info[i].msdu_len = 1421 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1422 1423 /* addr field in buf_info will not be valid */ 1424 hal_rx_buf_cookie_rbm_get( 1425 hal_soc_hdl, 1426 (uint32_t *)&msdu_details[i].buffer_addr_info_details, 1427 &buf_info); 1428 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 1429 msdu_list->rbm[i] = buf_info.rbm; 1430 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1431 &msdu_details[i].buffer_addr_info_details) | 1432 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1433 &msdu_details[i].buffer_addr_info_details) << 32; 1434 dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d", 1435 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1436 } 1437 *num_msdus = i; 1438 } 1439 1440 /** 1441 * hal_rx_reo_is_pn_error() - Indicate if this error was caused by a 1442 * PN check failure 1443 * @error_code: error code obtained from ring descriptor. 1444 * 1445 * Return: true: error caused by PN check, false: other error 1446 */ 1447 static inline bool hal_rx_reo_is_pn_error(uint32_t error_code) 1448 { 1449 1450 return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) || 1451 (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 1452 true : false; 1453 } 1454 1455 /** 1456 * hal_rx_reo_is_2k_jump() - Indicate if this error was caused by a 2K jump in 1457 * the sequence number 1458 * @error_code: error code obtained from ring descriptor. 1459 * 1460 * Return: true: error caused by 2K jump, false: other error 1461 */ 1462 static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code) 1463 { 1464 return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) || 1465 (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 1466 true : false; 1467 } 1468 1469 /** 1470 * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR 1471 * @error_code: error code obtained from ring descriptor. 1472 * 1473 * Return: true: error caused by OOR, false: other error 1474 */ 1475 static inline bool hal_rx_reo_is_oor_error(uint32_t error_code) 1476 { 1477 return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ? 1478 true : false; 1479 } 1480 1481 /** 1482 * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error 1483 * @error_code: error code obtained from ring descriptor. 1484 * 1485 * Return: true, if the error code is 2k-jump or OOR 1486 * false, for other error codes. 1487 */ 1488 static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code) 1489 { 1490 return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) || 1491 (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ? 1492 true : false; 1493 } 1494 1495 /** 1496 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 1497 * @src_srng_desc: hardware descriptor pointer 1498 * 1499 * This function will print wbm release descriptor 1500 * 1501 * Return: none 1502 */ 1503 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 1504 { 1505 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 1506 uint32_t i; 1507 1508 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1509 "Current Rx wbm release descriptor is"); 1510 1511 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 1512 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 1513 "DWORD[i] = 0x%x", wbm_comp[i]); 1514 } 1515 } 1516 1517 /** 1518 * hal_rx_msdu_link_desc_set() - Retrieves MSDU Link Descriptor to WBM 1519 * 1520 * @hal_soc_hdl: HAL version of the SOC pointer 1521 * @src_srng_desc: void pointer to the WBM Release Ring descriptor 1522 * @buf_addr_info: void pointer to the buffer_addr_info 1523 * @bm_action: put in IDLE list or release to MSDU_LIST 1524 * 1525 * Return: void 1526 */ 1527 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 1528 static inline 1529 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 1530 void *src_srng_desc, 1531 hal_buff_addrinfo_t buf_addr_info, 1532 uint8_t bm_action) 1533 { 1534 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1535 1536 if (hal_soc->ops->hal_rx_msdu_link_desc_set) 1537 return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl, 1538 src_srng_desc, 1539 buf_addr_info, 1540 bm_action); 1541 } 1542 1543 /** 1544 * HAL_RX_BUF_ADDR_INFO_GET() - Returns the address of the 1545 * BUFFER_ADDR_INFO, give the RX descriptor 1546 * (Assumption -- BUFFER_ADDR_INFO is the 1547 * first field in the descriptor structure) 1548 * @ring_desc: RX descriptor 1549 * 1550 * Return: pointer to buffer addr info 1551 */ 1552 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 1553 ((hal_link_desc_t)(ring_desc)) 1554 1555 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1556 1557 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 1558 1559 /******************************************************************************* 1560 * RX WBM ERROR APIS 1561 ******************************************************************************/ 1562 1563 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1564 (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 1565 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \ 1566 WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB) 1567 /** 1568 * enum hal_rx_wbm_reo_push_reason - Indicates why REO pushed 1569 * the frame to this release ring 1570 * 1571 * @HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 1572 * frame to this queue 1573 * @HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 1574 * received routing instructions. No error within REO was detected 1575 */ 1576 enum hal_rx_wbm_reo_push_reason { 1577 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 1578 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 1579 }; 1580 1581 1582 /** 1583 * enum hal_rx_wbm_rxdma_push_reason - Indicates why REO pushed the frame to 1584 * this release ring 1585 * 1586 * @HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 1587 * this frame to this queue 1588 * @HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 1589 * per received routing instructions. No error within RXDMA was detected 1590 * @HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH: 1591 */ 1592 enum hal_rx_wbm_rxdma_push_reason { 1593 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 1594 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 1595 HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH, 1596 }; 1597 1598 /** 1599 * hal_rx_dump_msdu_end_tlv() - dump RX msdu_end TLV in structured 1600 * human readable format. 1601 * @hal_soc: HAL soc 1602 * @pkt_tlvs: pointer the pkt_tlvs. 1603 * @dbg_level: log level. 1604 * 1605 * Return: void 1606 */ 1607 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 1608 void *pkt_tlvs, 1609 uint8_t dbg_level) 1610 { 1611 hal_soc->ops->hal_rx_dump_msdu_end_tlv(pkt_tlvs, dbg_level); 1612 } 1613 1614 /** 1615 * hal_rx_dump_rx_attention_tlv() - dump RX rx_attention TLV in structured 1616 * human readable format. 1617 * @hal_soc: HAL soc 1618 * @pkt_tlvs: pointer the pkt_tlvs. 1619 * @dbg_level: log level. 1620 * 1621 * Return: void 1622 */ 1623 static inline void hal_rx_dump_rx_attention_tlv(struct hal_soc *hal_soc, 1624 void *pkt_tlvs, 1625 uint8_t dbg_level) 1626 { 1627 hal_soc->ops->hal_rx_dump_rx_attention_tlv(pkt_tlvs, dbg_level); 1628 } 1629 1630 /** 1631 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 1632 * human readable format. 1633 * @hal_soc: HAL soc 1634 * @pkt_tlvs: pointer the pkt_tlvs. 1635 * @dbg_level: log level. 1636 * 1637 * Return: void 1638 */ 1639 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 1640 void *pkt_tlvs, 1641 uint8_t dbg_level) 1642 { 1643 hal_soc->ops->hal_rx_dump_msdu_start_tlv(pkt_tlvs, dbg_level); 1644 } 1645 1646 /** 1647 * hal_rx_dump_mpdu_start_tlv: dump RX mpdu_start TLV in structured 1648 * human readable format. 1649 * @hal_soc: HAL soc 1650 * @pkt_tlvs: pointer the pkt_tlvs. 1651 * @dbg_level: log level. 1652 * 1653 * Return: void 1654 */ 1655 static inline void hal_rx_dump_mpdu_start_tlv(struct hal_soc *hal_soc, 1656 void *pkt_tlvs, 1657 uint8_t dbg_level) 1658 { 1659 hal_soc->ops->hal_rx_dump_mpdu_start_tlv(pkt_tlvs, dbg_level); 1660 } 1661 1662 /** 1663 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 1664 * human readable format. 1665 * @hal_soc: HAL soc 1666 * @pkt_tlvs: pointer the pkt_tlvs. 1667 * @dbg_level: log level. 1668 * 1669 * Return: void 1670 */ 1671 static inline void hal_rx_dump_mpdu_end_tlv(struct hal_soc *hal_soc, 1672 void *pkt_tlvs, 1673 uint8_t dbg_level) 1674 { 1675 hal_soc->ops->hal_rx_dump_mpdu_end_tlv(pkt_tlvs, dbg_level); 1676 } 1677 1678 /** 1679 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt_hdr TLV in structured 1680 * human readable format. 1681 * @hal_soc: HAL soc 1682 * @pkt_tlvs: pointer the pkt_tlvs. 1683 * @dbg_level: log level. 1684 * 1685 * Return: void 1686 */ 1687 static inline void hal_rx_dump_pkt_hdr_tlv(struct hal_soc *hal_soc, 1688 void *pkt_tlvs, 1689 uint8_t dbg_level) 1690 { 1691 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 1692 } 1693 1694 /** 1695 * hal_srng_ring_id_get() - API to retrieve ring id from hal ring 1696 * structure 1697 * @hal_ring_hdl: handle to hal_srng structure 1698 * 1699 * Return: ring_id 1700 */ 1701 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 1702 { 1703 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 1704 } 1705 1706 #define DOT11_SEQ_FRAG_MASK 0x000f 1707 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 1708 1709 /** 1710 * hal_rx_get_rx_fragment_number() - Function to retrieve rx fragment number 1711 * @hal_soc: HAL soc 1712 * @buf: Network buffer 1713 * 1714 * Return: rx fragment number 1715 */ 1716 static inline 1717 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 1718 uint8_t *buf) 1719 { 1720 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 1721 } 1722 1723 /** 1724 * hal_rx_get_mpdu_sequence_control_valid() - Get mpdu sequence control valid 1725 * @hal_soc_hdl: hal soc handle 1726 * @buf: Network buffer 1727 * 1728 * Return: value of sequence control valid field 1729 */ 1730 static inline 1731 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 1732 uint8_t *buf) 1733 { 1734 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1735 1736 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 1737 } 1738 1739 /** 1740 * hal_rx_get_mpdu_frame_control_valid() - Retrieves mpdu frame control valid 1741 * @hal_soc_hdl: hal soc handle 1742 * @buf: Network buffer 1743 * 1744 * Return: value of frame control valid field 1745 */ 1746 static inline 1747 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 1748 uint8_t *buf) 1749 { 1750 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1751 1752 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 1753 } 1754 1755 /** 1756 * hal_rx_get_mpdu_mac_ad4_valid() - Retrieves if mpdu 4th addr is valid 1757 * @hal_soc_hdl: hal soc handle 1758 * @buf: Network buffer 1759 * 1760 * Return: value of mpdu 4th address valid field 1761 */ 1762 static inline 1763 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 1764 uint8_t *buf) 1765 { 1766 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1767 1768 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 1769 } 1770 1771 /** 1772 * hal_rx_clear_mpdu_desc_info() - Clears mpdu_desc_info 1773 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 1774 * 1775 * Return: None 1776 */ 1777 static inline void 1778 hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 1779 { 1780 qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info)); 1781 } 1782 1783 /** 1784 * hal_rx_wbm_err_info_get() - Retrieves WBM error code and reason and 1785 * save it to hal_wbm_err_desc_info structure passed by caller 1786 * @wbm_desc: wbm ring descriptor 1787 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 1788 * @hal_soc_hdl: HAL SOC handle 1789 * 1790 * Return: void 1791 */ 1792 static inline 1793 void hal_rx_wbm_err_info_get(void *wbm_desc, 1794 struct hal_wbm_err_desc_info *wbm_er_info, 1795 hal_soc_handle_t hal_soc_hdl) 1796 { 1797 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1798 1799 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 1800 } 1801 1802 /** 1803 * hal_rx_wbm_err_msdu_continuation_get() - Get wbm msdu continuation 1804 * bit from wbm release ring descriptor 1805 * @hal_soc_hdl: HAL SOC handle 1806 * @wbm_desc: wbm ring descriptor 1807 * 1808 * Return: uint8_t 1809 */ 1810 static inline 1811 uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl, 1812 void *wbm_desc) 1813 { 1814 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1815 1816 return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc); 1817 } 1818 1819 /** 1820 * hal_rx_mon_hw_desc_get_mpdu_status() - Retrieve MPDU status 1821 * @hal_soc_hdl: HAL SOC handle 1822 * @hw_desc_addr: Start address of Rx HW TLVs 1823 * @rs: Status for monitor mode 1824 * 1825 * Return: void 1826 */ 1827 static inline 1828 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 1829 void *hw_desc_addr, 1830 struct mon_rx_status *rs) 1831 { 1832 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1833 1834 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 1835 } 1836 1837 /** 1838 * hal_rx_get_tlv() - API to get the tlv 1839 * 1840 * @hal_soc: HAL version of the SOC pointer 1841 * @rx_tlv: TLV data extracted from the rx packet 1842 * 1843 * Return: uint8_t 1844 */ 1845 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 1846 { 1847 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 1848 } 1849 1850 /** 1851 * hal_rx_msdu_start_nss_get() - API to get the NSS 1852 * Interval from rx_msdu_start 1853 * @hal_soc_hdl: HAL SOC handle 1854 * @buf: pointer to the start of RX PKT TLV header 1855 * 1856 * Return: uint32_t(nss) 1857 */ 1858 static inline 1859 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1860 { 1861 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1862 1863 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 1864 } 1865 1866 /** 1867 * hal_rx_mpdu_start_tid_get() - Return tid info from the rx mpdu start 1868 * info details 1869 * @hal_soc_hdl: HAL SOC handle 1870 * @buf: Pointer to buffer containing rx pkt tlvs. 1871 * 1872 * 1873 */ 1874 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 1875 uint8_t *buf) 1876 { 1877 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1878 1879 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 1880 } 1881 1882 /** 1883 * hal_rx_msdu_start_reception_type_get() - API to get the reception type 1884 * Interval from rx_msdu_start 1885 * @hal_soc_hdl: hal_soc handle 1886 * @buf: pointer to the start of RX PKT TLV header 1887 * 1888 * Return: uint32_t(reception_type) 1889 */ 1890 static inline 1891 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 1892 uint8_t *buf) 1893 { 1894 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1895 1896 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 1897 } 1898 1899 /** 1900 * hal_reo_status_get_header() - Process reo desc info 1901 * @ring_desc: Pointer to reo descriptor 1902 * @b: tlv type info 1903 * @h: Pointer to hal_reo_status_header where info to be stored 1904 * @hal_soc: pointer to hal_soc structure 1905 * 1906 * Return: none. 1907 * 1908 */ 1909 static inline 1910 void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b, 1911 void *h, struct hal_soc *hal_soc) 1912 { 1913 hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h); 1914 } 1915 1916 /** 1917 * hal_rx_desc_is_first_msdu() - Check if first msdu 1918 * 1919 * @hal_soc_hdl: hal_soc handle 1920 * @hw_desc_addr: hardware descriptor address 1921 * 1922 * Return: 0 - success/ non-zero failure 1923 */ 1924 static inline 1925 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 1926 void *hw_desc_addr) 1927 { 1928 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1929 1930 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 1931 } 1932 1933 /** 1934 * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from 1935 * the rx tlv fields. 1936 * @hal_soc_hdl: HAL SoC handle 1937 * @buf: rx tlv start address [To be validated by caller] 1938 * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated. 1939 * 1940 * Return: None 1941 */ 1942 static inline void 1943 hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 1944 uint8_t *buf, 1945 void *mpdu_desc_info_hdl) 1946 { 1947 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1948 1949 if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info) 1950 return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf, 1951 mpdu_desc_info_hdl); 1952 } 1953 1954 static inline uint32_t 1955 hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 1956 { 1957 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1958 1959 return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr); 1960 } 1961 1962 static inline 1963 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 1964 uint8_t *rx_tlv_hdr) 1965 { 1966 uint8_t decap_format; 1967 1968 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 1969 decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl, 1970 rx_tlv_hdr); 1971 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 1972 return true; 1973 } 1974 1975 return false; 1976 } 1977 1978 /** 1979 * hal_rx_msdu_fse_metadata_get() - API to get FSE metadata 1980 * from rx_msdu_end TLV 1981 * @hal_soc_hdl: HAL SOC handle 1982 * @buf: pointer to the start of RX PKT TLV headers 1983 * 1984 * Return: fse metadata value from MSDU END TLV 1985 */ 1986 static inline uint32_t 1987 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 1988 uint8_t *buf) 1989 { 1990 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1991 1992 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 1993 } 1994 1995 /** 1996 * hal_rx_buffer_addr_info_get_paddr() - get paddr/sw_cookie from 1997 * <struct buffer_addr_info> structure 1998 * @buf_addr_info: pointer to <struct buffer_addr_info> structure 1999 * @buf_info: structure to return the buffer information including 2000 * paddr/cookie 2001 * 2002 * Return: None 2003 */ 2004 static inline 2005 void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info, 2006 struct hal_buf_info *buf_info) 2007 { 2008 buf_info->paddr = 2009 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 2010 ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 2011 } 2012 2013 /** 2014 * hal_rx_msdu_flow_idx_get() - API to get flow index from rx_msdu_end TLV 2015 * @hal_soc_hdl: HAL SOC handle 2016 * @buf: pointer to the start of RX PKT TLV headers 2017 * 2018 * Return: flow index value from MSDU END TLV 2019 */ 2020 static inline uint32_t 2021 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 2022 uint8_t *buf) 2023 { 2024 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2025 2026 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 2027 } 2028 2029 /** 2030 * hal_rx_msdu_get_reo_destination_indication() - API to get reo 2031 * destination index from rx_msdu_end TLV 2032 * @hal_soc_hdl: HAL SOC handle 2033 * @buf: pointer to the start of RX PKT TLV headers 2034 * @reo_destination_indication: pointer to return value of 2035 * reo_destination_indication 2036 * 2037 * Return: reo_destination_indication value from MSDU END TLV 2038 */ 2039 static inline void 2040 hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl, 2041 uint8_t *buf, 2042 uint32_t *reo_destination_indication) 2043 { 2044 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2045 2046 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf, 2047 reo_destination_indication); 2048 } 2049 2050 /** 2051 * hal_rx_msdu_flow_idx_timeout() - API to get flow index timeout 2052 * from rx_msdu_end TLV 2053 * @hal_soc_hdl: HAL SOC handle 2054 * @buf: pointer to the start of RX PKT TLV headers 2055 * 2056 * Return: flow index timeout value from MSDU END TLV 2057 */ 2058 static inline bool 2059 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 2060 uint8_t *buf) 2061 { 2062 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2063 2064 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 2065 } 2066 2067 /** 2068 * hal_rx_msdu_flow_idx_invalid() - API to get flow index invalid 2069 * from rx_msdu_end TLV 2070 * @hal_soc_hdl: HAL SOC handle 2071 * @buf: pointer to the start of RX PKT TLV headers 2072 * 2073 * Return: flow index invalid value from MSDU END TLV 2074 */ 2075 static inline bool 2076 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 2077 uint8_t *buf) 2078 { 2079 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2080 2081 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 2082 } 2083 2084 /** 2085 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 2086 * @hal_soc_hdl: hal_soc handle 2087 * @rx_tlv_hdr: Rx_tlv_hdr 2088 * @rxdma_dst_ring_desc: Rx HW descriptor 2089 * 2090 * Return: ppdu id 2091 */ 2092 static inline 2093 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 2094 void *rx_tlv_hdr, 2095 void *rxdma_dst_ring_desc) 2096 { 2097 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2098 2099 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr, 2100 rxdma_dst_ring_desc); 2101 } 2102 2103 /** 2104 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 2105 * @hal_soc_hdl: hal_soc handle 2106 * @buf: rx tlv address 2107 * 2108 * Return: sw peer id 2109 */ 2110 static inline 2111 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 2112 uint8_t *buf) 2113 { 2114 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2115 2116 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 2117 } 2118 2119 static inline 2120 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 2121 void *link_desc_addr) 2122 { 2123 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2124 2125 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 2126 } 2127 2128 static inline 2129 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 2130 void *msdu_addr) 2131 { 2132 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2133 2134 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 2135 } 2136 2137 static inline 2138 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2139 void *hw_addr) 2140 { 2141 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2142 2143 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 2144 } 2145 2146 static inline 2147 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 2148 void *hw_addr) 2149 { 2150 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2151 2152 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 2153 } 2154 2155 static inline 2156 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 2157 uint8_t *buf) 2158 { 2159 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2160 2161 return hal_soc->ops->hal_rx_get_fc_valid(buf); 2162 } 2163 2164 static inline 2165 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2166 { 2167 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2168 2169 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 2170 } 2171 2172 static inline 2173 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 2174 uint8_t *buf) 2175 { 2176 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2177 2178 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 2179 } 2180 2181 static inline 2182 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 2183 uint8_t *buf) 2184 { 2185 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2186 2187 return hal_soc->ops->hal_rx_get_filter_category(buf); 2188 } 2189 2190 static inline 2191 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 2192 uint8_t *buf) 2193 { 2194 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2195 2196 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 2197 } 2198 2199 /** 2200 * hal_reo_config() - Set reo config parameters 2201 * @hal_soc: hal soc handle 2202 * @reg_val: value to be set 2203 * @reo_params: reo parameters 2204 * 2205 * Return: void 2206 */ 2207 static inline 2208 void hal_reo_config(struct hal_soc *hal_soc, 2209 uint32_t reg_val, 2210 struct hal_reo_params *reo_params) 2211 { 2212 hal_soc->ops->hal_reo_config(hal_soc, 2213 reg_val, 2214 reo_params); 2215 } 2216 2217 /** 2218 * hal_rx_msdu_get_flow_params() - API to get flow index, 2219 * flow index invalid and flow index timeout from rx_msdu_end TLV 2220 * @hal_soc_hdl: HAL SOC handle 2221 * @buf: pointer to the start of RX PKT TLV headers 2222 * @flow_invalid: pointer to return value of flow_idx_valid 2223 * @flow_timeout: pointer to return value of flow_idx_timeout 2224 * @flow_index: pointer to return value of flow_idx 2225 * 2226 * Return: none 2227 */ 2228 static inline void 2229 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 2230 uint8_t *buf, 2231 bool *flow_invalid, 2232 bool *flow_timeout, 2233 uint32_t *flow_index) 2234 { 2235 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2236 2237 hal_soc->ops->hal_rx_msdu_get_flow_params(buf, 2238 flow_invalid, 2239 flow_timeout, 2240 flow_index); 2241 } 2242 2243 static inline 2244 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 2245 uint8_t *buf) 2246 { 2247 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2248 2249 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 2250 } 2251 2252 static inline 2253 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 2254 uint8_t *buf) 2255 { 2256 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2257 2258 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 2259 } 2260 2261 static inline void 2262 hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl, 2263 void *rx_tlv, 2264 void *ppdu_info) 2265 { 2266 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2267 2268 if (hal_soc->ops->hal_rx_get_bb_info) 2269 hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info); 2270 } 2271 2272 static inline void 2273 hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl, 2274 void *rx_tlv, 2275 void *ppdu_info) 2276 { 2277 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2278 2279 if (hal_soc->ops->hal_rx_get_rtt_info) 2280 hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info); 2281 } 2282 2283 /** 2284 * hal_rx_msdu_metadata_get() - API to get the 2285 * fast path information from rx_msdu_end TLV 2286 * 2287 * @hal_soc_hdl: DP soc handle 2288 * @buf: pointer to the start of RX PKT TLV headers 2289 * @msdu_md: Structure to hold msdu end information 2290 * Return: none 2291 */ 2292 static inline void 2293 hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2294 struct hal_rx_msdu_metadata *msdu_md) 2295 { 2296 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2297 2298 return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md); 2299 } 2300 2301 /** 2302 * hal_rx_get_fisa_cumulative_l4_checksum() - API to get cumulative_l4_checksum 2303 * from rx_msdu_end TLV 2304 * @hal_soc_hdl: HAL SOC handle 2305 * @buf: pointer to the start of RX PKT TLV headers 2306 * 2307 * Return: cumulative_l4_checksum 2308 */ 2309 static inline uint16_t 2310 hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl, 2311 uint8_t *buf) 2312 { 2313 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2314 2315 if (!hal_soc || !hal_soc->ops) { 2316 hal_err("hal handle is NULL"); 2317 QDF_BUG(0); 2318 return 0; 2319 } 2320 2321 if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum) 2322 return 0; 2323 2324 return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf); 2325 } 2326 2327 /** 2328 * hal_rx_get_fisa_cumulative_ip_length() - API to get cumulative_ip_length 2329 * from rx_msdu_end TLV 2330 * @hal_soc_hdl: HAL SOC handle 2331 * @buf: pointer to the start of RX PKT TLV headers 2332 * 2333 * Return: cumulative_ip_length 2334 */ 2335 static inline uint16_t 2336 hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl, 2337 uint8_t *buf) 2338 { 2339 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2340 2341 if (!hal_soc || !hal_soc->ops) { 2342 hal_err("hal handle is NULL"); 2343 QDF_BUG(0); 2344 return 0; 2345 } 2346 2347 if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length) 2348 return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf); 2349 2350 return 0; 2351 } 2352 2353 /** 2354 * hal_rx_get_udp_proto() - API to get UDP proto field 2355 * from rx_msdu_start TLV 2356 * @hal_soc_hdl: HAL SOC handle 2357 * @buf: pointer to the start of RX PKT TLV headers 2358 * 2359 * Return: UDP proto field value 2360 */ 2361 static inline bool 2362 hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2363 { 2364 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2365 2366 if (!hal_soc || !hal_soc->ops) { 2367 hal_err("hal handle is NULL"); 2368 QDF_BUG(0); 2369 return 0; 2370 } 2371 2372 if (hal_soc->ops->hal_rx_get_udp_proto) 2373 return hal_soc->ops->hal_rx_get_udp_proto(buf); 2374 2375 return 0; 2376 } 2377 2378 /** 2379 * hal_rx_get_fisa_flow_agg_continuation() - API to get fisa 2380 * flow_agg_continuation from rx_msdu_end TLV 2381 * @hal_soc_hdl: HAL SOC handle 2382 * @buf: pointer to the start of RX PKT TLV headers 2383 * 2384 * Return: flow_agg_continuation bit field value 2385 */ 2386 static inline bool 2387 hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl, 2388 uint8_t *buf) 2389 { 2390 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2391 2392 if (!hal_soc || !hal_soc->ops) { 2393 hal_err("hal handle is NULL"); 2394 QDF_BUG(0); 2395 return 0; 2396 } 2397 2398 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation) 2399 return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf); 2400 2401 return 0; 2402 } 2403 2404 /** 2405 * hal_rx_get_fisa_flow_agg_count() - API to get fisa flow_agg count from 2406 * rx_msdu_end TLV 2407 * @hal_soc_hdl: HAL SOC handle 2408 * @buf: pointer to the start of RX PKT TLV headers 2409 * 2410 * Return: flow_agg count value 2411 */ 2412 static inline uint8_t 2413 hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl, 2414 uint8_t *buf) 2415 { 2416 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2417 2418 if (!hal_soc || !hal_soc->ops) { 2419 hal_err("hal handle is NULL"); 2420 QDF_BUG(0); 2421 return 0; 2422 } 2423 2424 if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count) 2425 return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf); 2426 2427 return 0; 2428 } 2429 2430 /** 2431 * hal_rx_get_fisa_timeout() - API to get fisa time out from rx_msdu_end TLV 2432 * @hal_soc_hdl: HAL SOC handle 2433 * @buf: pointer to the start of RX PKT TLV headers 2434 * 2435 * Return: fisa flow_agg timeout bit value 2436 */ 2437 static inline bool 2438 hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2439 { 2440 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2441 2442 if (!hal_soc || !hal_soc->ops) { 2443 hal_err("hal handle is NULL"); 2444 QDF_BUG(0); 2445 return 0; 2446 } 2447 2448 if (hal_soc->ops->hal_rx_get_fisa_timeout) 2449 return hal_soc->ops->hal_rx_get_fisa_timeout(buf); 2450 2451 return 0; 2452 } 2453 2454 /** 2455 * hal_rx_mpdu_start_tlv_tag_valid() - API to check if RX_MPDU_START tlv 2456 * tag is valid 2457 * 2458 * @hal_soc_hdl: HAL SOC handle 2459 * @rx_tlv_hdr: start address of rx_pkt_tlvs 2460 * 2461 * Return: true if RX_MPDU_START tlv tag is valid, else false 2462 */ 2463 2464 static inline uint8_t 2465 hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl, 2466 void *rx_tlv_hdr) 2467 { 2468 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2469 2470 if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid) 2471 return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr); 2472 2473 return 0; 2474 } 2475 2476 /** 2477 * hal_rx_get_next_msdu_link_desc_buf_addr_info() - get next msdu link desc 2478 * buffer addr info 2479 * @link_desc_va: pointer to current msdu link Desc 2480 * @next_addr_info: buffer to save next msdu link Desc buffer addr info 2481 * 2482 * return: None 2483 */ 2484 static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info( 2485 void *link_desc_va, 2486 struct buffer_addr_info *next_addr_info) 2487 { 2488 struct rx_msdu_link *msdu_link = link_desc_va; 2489 2490 if (!msdu_link) { 2491 qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info)); 2492 return; 2493 } 2494 2495 *next_addr_info = msdu_link->next_msdu_link_desc_addr_info; 2496 } 2497 2498 /** 2499 * hal_rx_clear_next_msdu_link_desc_buf_addr_info() - clear next msdu link desc 2500 * buffer addr info 2501 * @link_desc_va: pointer to current msdu link Desc 2502 * 2503 * return: None 2504 */ 2505 static inline 2506 void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va) 2507 { 2508 struct rx_msdu_link *msdu_link = link_desc_va; 2509 2510 if (msdu_link) 2511 qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info, 2512 sizeof(msdu_link->next_msdu_link_desc_addr_info)); 2513 } 2514 2515 /** 2516 * hal_rx_is_buf_addr_info_valid() - check is the buf_addr_info valid 2517 * 2518 * @buf_addr_info: pointer to buf_addr_info structure 2519 * 2520 * return: true: has valid paddr, false: not. 2521 */ 2522 static inline 2523 bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info) 2524 { 2525 return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ? 2526 false : true; 2527 } 2528 2529 /** 2530 * hal_rx_msdu_end_offset_get() - Get the MSDU end offset from 2531 * rx_pkt_tlvs structure 2532 * 2533 * @hal_soc_hdl: HAL SOC handle 2534 * return: msdu_end_tlv offset value 2535 */ 2536 static inline 2537 uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2538 { 2539 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2540 2541 if (!hal_soc || !hal_soc->ops) { 2542 hal_err("hal handle is NULL"); 2543 QDF_BUG(0); 2544 return 0; 2545 } 2546 2547 return hal_soc->ops->hal_rx_msdu_end_offset_get(); 2548 } 2549 2550 /** 2551 * hal_rx_msdu_start_offset_get() - Get the MSDU start offset from 2552 * rx_pkt_tlvs structure 2553 * 2554 * @hal_soc_hdl: HAL SOC handle 2555 * return: msdu_start_tlv offset value 2556 */ 2557 static inline 2558 uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2559 { 2560 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2561 2562 if (!hal_soc || !hal_soc->ops) { 2563 hal_err("hal handle is NULL"); 2564 QDF_BUG(0); 2565 return 0; 2566 } 2567 2568 return hal_soc->ops->hal_rx_msdu_start_offset_get(); 2569 } 2570 2571 /** 2572 * hal_rx_mpdu_start_offset_get() - Get the MPDU start offset from 2573 * rx_pkt_tlvs structure 2574 * 2575 * @hal_soc_hdl: HAL SOC handle 2576 * return: mpdu_start_tlv offset value 2577 */ 2578 static inline 2579 uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl) 2580 { 2581 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2582 2583 if (!hal_soc || !hal_soc->ops) { 2584 hal_err("hal handle is NULL"); 2585 QDF_BUG(0); 2586 return 0; 2587 } 2588 2589 return hal_soc->ops->hal_rx_mpdu_start_offset_get(); 2590 } 2591 2592 static inline 2593 uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl) 2594 { 2595 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2596 2597 if (!hal_soc || !hal_soc->ops) { 2598 hal_err("hal handle is NULL"); 2599 QDF_BUG(0); 2600 return 0; 2601 } 2602 2603 return hal_soc->ops->hal_rx_pkt_tlv_offset_get(); 2604 } 2605 2606 /** 2607 * hal_rx_mpdu_end_offset_get() - Get the MPDU end offset from 2608 * rx_pkt_tlvs structure 2609 * 2610 * @hal_soc_hdl: HAL SOC handle 2611 * return: mpdu_end_tlv offset value 2612 */ 2613 static inline 2614 uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl) 2615 { 2616 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2617 2618 if (!hal_soc || !hal_soc->ops) { 2619 hal_err("hal handle is NULL"); 2620 QDF_BUG(0); 2621 return 0; 2622 } 2623 2624 return hal_soc->ops->hal_rx_mpdu_end_offset_get(); 2625 } 2626 2627 #ifdef CONFIG_WORD_BASED_TLV 2628 /** 2629 * hal_rx_mpdu_start_wmask_get() - Get the MPDU start word mask 2630 * 2631 * @hal_soc_hdl: HAL SOC handle 2632 * return: mpdu_start_tlv word mask value 2633 */ 2634 static inline 2635 uint32_t hal_rx_mpdu_start_wmask_get(hal_soc_handle_t hal_soc_hdl) 2636 { 2637 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2638 2639 if (!hal_soc || !hal_soc->ops) { 2640 hal_err("hal handle is NULL"); 2641 QDF_BUG(0); 2642 return 0; 2643 } 2644 2645 return hal_soc->ops->hal_rx_mpdu_start_wmask_get(); 2646 } 2647 2648 /** 2649 * hal_rx_msdu_end_wmask_get() - Get the MSDU END word mask 2650 * 2651 * @hal_soc_hdl: HAL SOC handle 2652 * return: msdu_end_tlv word mask value 2653 */ 2654 static inline 2655 uint32_t hal_rx_msdu_end_wmask_get(hal_soc_handle_t hal_soc_hdl) 2656 { 2657 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2658 2659 if (!hal_soc || !hal_soc->ops) { 2660 hal_err("hal handle is NULL"); 2661 QDF_BUG(0); 2662 return 0; 2663 } 2664 2665 return hal_soc->ops->hal_rx_msdu_end_wmask_get(); 2666 } 2667 #endif 2668 2669 /** 2670 * hal_rx_attn_offset_get() - Get the ATTENTION offset from 2671 * rx_pkt_tlvs structure 2672 * 2673 * @hal_soc_hdl: HAL SOC handle 2674 * return: attn_tlv offset value 2675 */ 2676 static inline 2677 uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl) 2678 { 2679 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2680 2681 if (!hal_soc || !hal_soc->ops) { 2682 hal_err("hal handle is NULL"); 2683 QDF_BUG(0); 2684 return 0; 2685 } 2686 2687 return hal_soc->ops->hal_rx_attn_offset_get(); 2688 } 2689 2690 /** 2691 * hal_rx_msdu_ext_desc_info_get_ptr() - Get msdu extension desc info ptr 2692 * @msdu_details_ptr: Pointer to msdu_details_ptr 2693 * @hal_soc: pointer to hal_soc 2694 * 2695 * Return: Pointer to rx_msdu_desc_info structure. 2696 * 2697 */ 2698 static inline 2699 void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr, 2700 struct hal_soc *hal_soc) 2701 { 2702 return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr( 2703 msdu_details_ptr); 2704 } 2705 2706 static inline void 2707 hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 2708 uint8_t *buf, uint8_t dbg_level) 2709 { 2710 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2711 2712 hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level); 2713 } 2714 2715 //TODO - Change the names to not include tlv names 2716 static inline uint16_t 2717 hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2718 { 2719 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2720 2721 return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf); 2722 } 2723 2724 static inline uint32_t 2725 hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2726 { 2727 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2728 2729 return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf); 2730 } 2731 2732 static inline uint32_t 2733 hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2734 { 2735 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2736 2737 return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf); 2738 } 2739 2740 static inline uint16_t 2741 hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2742 { 2743 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2744 2745 return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf); 2746 } 2747 2748 static inline int 2749 hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl, 2750 uint8_t *rx_pkt_tlv, 2751 struct hal_offload_info *offload_info) 2752 { 2753 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2754 2755 return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv, 2756 offload_info); 2757 2758 } 2759 2760 static inline int 2761 hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2762 void *proto_params) 2763 { 2764 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2765 2766 return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params); 2767 } 2768 2769 static inline int 2770 hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf, 2771 uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset) 2772 { 2773 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2774 2775 return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf, 2776 l3_hdr_offset, 2777 l4_hdr_offset); 2778 } 2779 2780 static inline uint32_t 2781 hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2782 { 2783 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2784 2785 return hal_soc->ops->hal_rx_tlv_mic_err_get(buf); 2786 } 2787 2788 /** 2789 * hal_rx_tlv_get_pkt_type() - API to get the pkt type 2790 * from rx_msdu_start 2791 * @hal_soc_hdl: hal_soc handle 2792 * @buf: pointer to the start of RX PKT TLV header 2793 * Return: uint32_t(pkt type) 2794 */ 2795 2796 static inline uint32_t 2797 hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2798 { 2799 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2800 2801 return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf); 2802 } 2803 2804 static inline void 2805 hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl, 2806 uint8_t *buf, uint64_t *pn_num) 2807 { 2808 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2809 2810 hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num); 2811 } 2812 2813 static inline uint8_t * 2814 hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc) 2815 { 2816 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2817 2818 if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr) 2819 return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc); 2820 2821 return NULL; 2822 } 2823 2824 static inline uint64_t 2825 hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc, 2826 uint8_t *buf) 2827 { 2828 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2829 2830 if (hal_soc->ops->hal_rx_get_qdesc_addr) 2831 return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf); 2832 2833 return 0; 2834 } 2835 2836 static inline void 2837 hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl, 2838 uint8_t *desc, uint32_t dst_ind) 2839 { 2840 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2841 2842 if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind) 2843 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind); 2844 } 2845 2846 static inline uint32_t 2847 hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2848 { 2849 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2850 2851 if (hal_soc->ops->hal_rx_tlv_get_is_decrypted) 2852 return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf); 2853 2854 return 0; 2855 } 2856 2857 static inline uint8_t * 2858 hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2859 { 2860 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2861 2862 return hal_soc->ops->hal_rx_pkt_hdr_get(buf); 2863 } 2864 2865 static inline uint8_t 2866 hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2867 { 2868 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2869 2870 if (hal_soc->ops->hal_rx_msdu_get_keyid) 2871 return hal_soc->ops->hal_rx_msdu_get_keyid(buf); 2872 2873 return 0; 2874 } 2875 2876 static inline uint32_t 2877 hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2878 { 2879 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2880 2881 if (hal_soc->ops->hal_rx_tlv_get_freq) 2882 return hal_soc->ops->hal_rx_tlv_get_freq(buf); 2883 2884 return 0; 2885 } 2886 2887 static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2888 void *desc, 2889 void *mpdu_desc_info, 2890 uint32_t val) 2891 { 2892 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2893 2894 if (hal_soc->ops->hal_mpdu_desc_info_set) 2895 return hal_soc->ops->hal_mpdu_desc_info_set( 2896 hal_soc_hdl, desc, mpdu_desc_info, val); 2897 } 2898 2899 static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl, 2900 void *msdu_desc_info, 2901 uint32_t val, uint32_t nbuf_len) 2902 { 2903 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2904 2905 if (hal_soc->ops->hal_msdu_desc_info_set) 2906 return hal_soc->ops->hal_msdu_desc_info_set( 2907 hal_soc_hdl, msdu_desc_info, val, nbuf_len); 2908 } 2909 2910 static inline uint32_t 2911 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 2912 { 2913 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2914 2915 if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get) 2916 return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get( 2917 hal_soc_hdl, msdu_link_desc); 2918 2919 return 0; 2920 } 2921 2922 static inline uint32_t 2923 hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2924 { 2925 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2926 2927 return hal_soc->ops->hal_rx_tlv_sgi_get(buf); 2928 } 2929 2930 static inline uint32_t 2931 hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2932 { 2933 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2934 2935 return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf); 2936 } 2937 2938 static inline uint32_t 2939 hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2940 { 2941 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2942 2943 return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf); 2944 } 2945 2946 static inline uint32_t 2947 hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2948 { 2949 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2950 2951 return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf); 2952 } 2953 2954 static inline uint32_t 2955 hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2956 { 2957 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2958 2959 return hal_soc->ops->hal_rx_tlv_bw_get(buf); 2960 } 2961 2962 static inline uint32_t 2963 hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl, 2964 hal_ring_desc_t ring_desc) 2965 { 2966 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2967 2968 return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc); 2969 } 2970 2971 /** 2972 * hal_rx_ret_buf_manager_get() - Returns the "return_buffer_manager" 2973 * from the BUFFER_ADDR_INFO structure 2974 * given a REO destination ring descriptor. 2975 * @hal_soc_hdl: hal soc handle 2976 * @ring_desc: RX(REO/WBM release) destination ring descriptor 2977 * 2978 * Return: uint8_t (value of the return_buffer_manager) 2979 */ 2980 static inline uint8_t 2981 hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl, 2982 hal_ring_desc_t ring_desc) 2983 { 2984 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2985 2986 return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc); 2987 } 2988 2989 /** 2990 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 2991 * rxdma ring entry. 2992 * @hal_soc_hdl: hal soc handle 2993 * @rxdma_entry: descriptor entry 2994 * @paddr: physical address of nbuf data pointer. 2995 * @cookie: SW cookie used as a index to SW rx desc. 2996 * @manager: who owns the nbuf (host, NSS, etc...). 2997 * 2998 */ 2999 static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 3000 void *rxdma_entry, 3001 qdf_dma_addr_t paddr, 3002 uint32_t cookie, 3003 uint8_t manager) 3004 { 3005 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3006 3007 return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry, 3008 paddr, 3009 cookie, 3010 manager); 3011 } 3012 3013 static inline uint32_t 3014 hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 3015 { 3016 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3017 3018 return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc); 3019 } 3020 3021 static inline void 3022 hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr, 3023 uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err) 3024 { 3025 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3026 3027 return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr, 3028 ip_csum_err, 3029 tcp_udp_csum_err); 3030 } 3031 3032 static inline void 3033 hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl, 3034 uint8_t *rx_tlv_hdr, 3035 struct hal_rx_pkt_capture_flags *flags) 3036 { 3037 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3038 3039 return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr, 3040 flags); 3041 } 3042 3043 static inline uint8_t 3044 hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 3045 { 3046 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3047 3048 return hal_soc->ops->hal_rx_err_status_get(rx_desc); 3049 } 3050 3051 static inline uint8_t 3052 hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc) 3053 { 3054 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3055 3056 return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc); 3057 } 3058 3059 /** 3060 * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor. 3061 * @hal_soc_hdl: HAL SoC handle 3062 * @ring_desc: REO ring descriptor 3063 * @prev_pn: Buffer to populate the previous PN 3064 * 3065 * Return: None 3066 */ 3067 static inline void 3068 hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc, 3069 uint64_t *prev_pn) 3070 { 3071 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3072 3073 if (hal_soc->ops->hal_rx_reo_prev_pn_get) 3074 return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn); 3075 } 3076 3077 /** 3078 * hal_rx_mpdu_info_ampdu_flag_get() - get ampdu flag bit from rx mpdu info 3079 * @hal_soc_hdl: hal soc handle 3080 * @buf: pointer to rx_pkt_tlvs 3081 * 3082 * No input validdataion, since this function is supposed to be 3083 * called from fastpath. 3084 * 3085 * Return: ampdu flag 3086 */ 3087 static inline bool 3088 hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3089 { 3090 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3091 3092 return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf); 3093 } 3094 3095 #ifdef REO_SHARED_QREF_TABLE_EN 3096 /** 3097 * hal_reo_shared_qaddr_write() - Write REo tid queue addr 3098 * LUT shared by SW and HW at the index given by peer id 3099 * and tid. 3100 * 3101 * @hal_soc_hdl: hal soc handle 3102 * @peer_id: peer_id 3103 * @tid: tid queue number 3104 * @hw_qdesc_paddr: reo queue addr 3105 */ 3106 static inline void 3107 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 3108 uint16_t peer_id, 3109 int tid, 3110 qdf_dma_addr_t hw_qdesc_paddr) 3111 { 3112 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3113 3114 if (hal_soc->ops->hal_reo_shared_qaddr_write) 3115 return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl, 3116 peer_id, tid, hw_qdesc_paddr); 3117 } 3118 3119 /** 3120 * hal_reo_shared_qaddr_init() - Initialize reo qref LUT 3121 * @hal_soc_hdl: Hal soc handle 3122 * @qref_reset: reset qref LUT 3123 * 3124 * Write MLO and Non MLO table start addr to HW reg 3125 * 3126 * Return: void 3127 */ 3128 static inline void 3129 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) 3130 { 3131 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3132 3133 if (hal_soc->ops->hal_reo_shared_qaddr_init) 3134 return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl, 3135 qref_reset); 3136 } 3137 3138 /** 3139 * hal_reo_shared_qaddr_cache_clear() - Set and unset 'clear_qdesc_array' 3140 * bit in reo reg for shared qref feature. This is done for every MLO 3141 * connection to clear HW reo internal storage for clearing stale entry 3142 * of prev peer having same peer id 3143 * 3144 * @hal_soc_hdl: Hal soc handle 3145 * 3146 * Write MLO and Non MLO table start addr to HW reg 3147 * 3148 * Return: void 3149 */ 3150 static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) 3151 { 3152 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3153 3154 if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear) 3155 return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl); 3156 } 3157 3158 #else 3159 static inline void 3160 hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl, 3161 uint16_t peer_id, 3162 int tid, 3163 qdf_dma_addr_t hw_qdesc_paddr) {} 3164 static inline void 3165 hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {} 3166 3167 static inline void 3168 hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {} 3169 3170 #endif /* REO_SHARED_QREF_TABLE_EN */ 3171 3172 static inline uint8_t 3173 hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl) 3174 { 3175 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3176 3177 return hal->reo_qref.reo_qref_table_en; 3178 } 3179 3180 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3181 static inline uint8_t 3182 hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3183 { 3184 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3185 3186 return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf); 3187 } 3188 #endif 3189 3190 static inline uint32_t 3191 hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3192 { 3193 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3194 3195 return hal_soc->ops->hal_rx_tlv_l3_type_get ? 3196 hal_soc->ops->hal_rx_tlv_l3_type_get(buf) : 3197 HAL_RX_TLV_L3_TYPE_INVALID; 3198 } 3199 3200 /** 3201 * hal_rx_phy_legacy_get_rssi() - API to get RSSI from TLV 3202 * @hal_soc_hdl: HAL soc handle 3203 * @buf: pointer to the start of WIFIPHYRX_RSSI_LEGACY_E TLV 3204 * 3205 * Return: value of RSSI 3206 */ 3207 static inline int8_t 3208 hal_rx_phy_legacy_get_rssi(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3209 { 3210 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3211 3212 return hal_soc->ops->hal_rx_phy_legacy_get_rssi(buf); 3213 } 3214 3215 /** 3216 * hal_get_tsf_time() - Get tsf time 3217 * @hal_soc_hdl: HAL soc handle 3218 * @tsf_id: 3219 * @mac_id: mac_id 3220 * @tsf: pointer to update tsf value 3221 * @tsf_sync_soc_time: pointer to update tsf sync time 3222 * 3223 * Return: None. 3224 */ 3225 static inline void 3226 hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 3227 uint32_t mac_id, uint64_t *tsf, 3228 uint64_t *tsf_sync_soc_time) 3229 { 3230 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3231 3232 if (hal_soc->ops->hal_get_tsf_time) 3233 hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id, 3234 tsf, tsf_sync_soc_time); 3235 } 3236 3237 /** 3238 * hal_rx_en_mcast_fp_data_filter() - Is mcast filter pass enabled 3239 * @hal_soc_hdl: HAL soc handle 3240 * 3241 * Return: false for BE MCC, true for WIN 3242 */ 3243 static inline 3244 bool hal_rx_en_mcast_fp_data_filter(hal_soc_handle_t hal_soc_hdl) 3245 { 3246 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3247 3248 return hal_soc->ops->hal_rx_en_mcast_fp_data_filter(); 3249 } 3250 3251 /** 3252 * hal_rx_get_phy_ppdu_id_size() - Get phy ppdu id size 3253 * @hal_soc_hdl: HAL soc handle 3254 * 3255 * Return: phy ppdu id size 3256 */ 3257 static inline uint8_t 3258 hal_rx_get_phy_ppdu_id_size(hal_soc_handle_t hal_soc_hdl) 3259 { 3260 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3261 3262 return hal_soc->ops->hal_rx_get_phy_ppdu_id_size(); 3263 } 3264 3265 #endif /* _HAL_RX_H */ 3266