1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_api.h> 23 24 #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET 25 #define HAL_RX_LSB(block, field) block##_##field##_LSB 26 #define HAL_RX_MASk(block, field) block##_##field##_MASK 27 28 #define HAL_RX_GET(_ptr, block, field) \ 29 (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \ 30 HAL_RX_MASk(block, field)) >> \ 31 HAL_RX_LSB(block, field)) 32 33 #ifdef NO_RX_PKT_HDR_TLV 34 /* RX_BUFFER_SIZE = 1536 data bytes + 256 RX TLV bytes. We are avoiding 35 * 128 bytes of RX_PKT_HEADER_TLV. 36 */ 37 #define RX_BUFFER_SIZE 1792 38 #else 39 /* RX_BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */ 40 #define RX_BUFFER_SIZE 2048 41 #endif 42 43 /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */ 44 #define HAL_RX_NON_QOS_TID 16 45 46 enum { 47 HAL_HW_RX_DECAP_FORMAT_RAW = 0, 48 HAL_HW_RX_DECAP_FORMAT_NWIFI, 49 HAL_HW_RX_DECAP_FORMAT_ETH2, 50 HAL_HW_RX_DECAP_FORMAT_8023, 51 }; 52 53 /** 54 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 55 * 56 * @reo_psh_rsn: REO push reason 57 * @reo_err_code: REO Error code 58 * @rxdma_psh_rsn: RXDMA push reason 59 * @rxdma_err_code: RXDMA Error code 60 * @reserved_1: Reserved bits 61 * @wbm_err_src: WBM error source 62 * @pool_id: pool ID, indicates which rxdma pool 63 * @reserved_2: Reserved bits 64 */ 65 struct hal_wbm_err_desc_info { 66 uint16_t reo_psh_rsn:2, 67 reo_err_code:5, 68 rxdma_psh_rsn:2, 69 rxdma_err_code:5, 70 reserved_1:2; 71 uint8_t wbm_err_src:3, 72 pool_id:2, 73 reserved_2:3; 74 }; 75 76 /** 77 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 78 * 79 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 80 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 81 */ 82 enum hal_reo_error_status { 83 HAL_REO_ERROR_DETECTED = 0, 84 HAL_REO_ROUTING_INSTRUCTION = 1, 85 }; 86 87 /** 88 * @msdu_flags: [0] first_msdu_in_mpdu 89 * [1] last_msdu_in_mpdu 90 * [2] msdu_continuation - MSDU spread across buffers 91 * [23] sa_is_valid - SA match in peer table 92 * [24] sa_idx_timeout - Timeout while searching for SA match 93 * [25] da_is_valid - Used to identtify intra-bss forwarding 94 * [26] da_is_MCBC 95 * [27] da_idx_timeout - Timeout while searching for DA match 96 * 97 */ 98 struct hal_rx_msdu_desc_info { 99 uint32_t msdu_flags; 100 uint16_t msdu_len; /* 14 bits for length */ 101 }; 102 103 /** 104 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 105 * 106 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 107 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 108 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 109 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 110 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 111 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 112 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 113 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 114 */ 115 enum hal_rx_msdu_desc_flags { 116 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 117 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 118 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 119 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 120 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 121 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 122 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 123 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 124 }; 125 126 /* 127 * @msdu_count: no. of msdus in the MPDU 128 * @mpdu_seq: MPDU sequence number 129 * @mpdu_flags [0] Fragment flag 130 * [1] MPDU_retry_bit 131 * [2] AMPDU flag 132 * [3] raw_ampdu 133 * @peer_meta_data: Upper bits containing peer id, vdev id 134 */ 135 struct hal_rx_mpdu_desc_info { 136 uint16_t msdu_count; 137 uint16_t mpdu_seq; /* 12 bits for length */ 138 uint32_t mpdu_flags; 139 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 140 }; 141 142 /** 143 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 144 * 145 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 146 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 147 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 148 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 149 */ 150 enum hal_rx_mpdu_desc_flags { 151 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 152 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 153 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 154 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 155 }; 156 157 /** 158 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 159 * BUFFER_ADDR_INFO structure 160 * 161 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 162 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 163 * descriptor list 164 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 165 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 166 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 167 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 168 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 169 */ 170 enum hal_rx_ret_buf_manager { 171 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 172 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 173 HAL_RX_BUF_RBM_FW_BM = 2, 174 HAL_RX_BUF_RBM_SW0_BM = 3, 175 HAL_RX_BUF_RBM_SW1_BM = 4, 176 HAL_RX_BUF_RBM_SW2_BM = 5, 177 HAL_RX_BUF_RBM_SW3_BM = 6, 178 }; 179 180 /* 181 * Given the offset of a field in bytes, returns uint8_t * 182 */ 183 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 184 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 185 186 /* 187 * Given the offset of a field in bytes, returns uint32_t * 188 */ 189 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 190 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 191 192 #define _HAL_MS(_word, _mask, _shift) \ 193 (((_word) & (_mask)) >> (_shift)) 194 195 /* 196 * macro to set the LSW of the nbuf data physical address 197 * to the rxdma ring entry 198 */ 199 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 200 ((*(((unsigned int *) buff_addr_info) + \ 201 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 202 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 203 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 204 205 /* 206 * macro to set the LSB of MSW of the nbuf data physical address 207 * to the rxdma ring entry 208 */ 209 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 210 ((*(((unsigned int *) buff_addr_info) + \ 211 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 212 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 213 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 214 215 /* 216 * macro to set the cookie into the rxdma ring entry 217 */ 218 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 219 ((*(((unsigned int *) buff_addr_info) + \ 220 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 221 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 222 ((*(((unsigned int *) buff_addr_info) + \ 223 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 224 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 225 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 226 227 /* 228 * macro to set the manager into the rxdma ring entry 229 */ 230 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 231 ((*(((unsigned int *) buff_addr_info) + \ 232 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 233 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 234 ((*(((unsigned int *) buff_addr_info) + \ 235 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 236 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 237 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 238 239 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 240 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 241 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 242 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 243 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 244 245 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 246 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 247 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 248 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 249 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 250 251 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 252 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 253 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 254 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 255 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 256 257 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 258 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 259 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 260 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 261 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 262 263 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 264 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 265 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 266 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 267 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 268 269 /* TODO: Convert the following structure fields accesseses to offsets */ 270 271 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 272 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 273 (((struct reo_destination_ring *) \ 274 reo_desc)->buf_or_link_desc_addr_info))) 275 276 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 277 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 278 (((struct reo_destination_ring *) \ 279 reo_desc)->buf_or_link_desc_addr_info))) 280 281 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 282 (HAL_RX_BUF_COOKIE_GET(& \ 283 (((struct reo_destination_ring *) \ 284 reo_desc)->buf_or_link_desc_addr_info))) 285 286 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 287 ((mpdu_info_ptr \ 288 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 289 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 290 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 291 292 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 293 ((mpdu_info_ptr \ 294 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 295 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 296 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 297 298 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 299 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 300 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 301 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 302 303 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 304 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 305 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 306 307 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 308 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 309 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 310 311 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 312 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 313 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 314 315 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 316 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 317 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 318 319 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 320 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 321 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 322 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 323 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 324 325 326 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 327 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 328 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 329 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 330 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 331 332 /* 333 * NOTE: None of the following _GET macros need a right 334 * shift by the corresponding _LSB. This is because, they are 335 * finally taken and "OR'ed" into a single word again. 336 */ 337 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 338 ((*(((uint32_t *)msdu_info_ptr) + \ 339 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 340 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 341 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 342 343 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 344 ((*(((uint32_t *)msdu_info_ptr) + \ 345 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 346 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 347 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 348 349 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 350 ((*(((uint32_t *)msdu_info_ptr) + \ 351 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 352 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 353 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 354 355 356 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 357 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 358 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 359 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 360 361 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 362 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 363 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 364 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 365 366 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 367 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 368 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 369 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 370 371 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 372 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 373 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 374 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 375 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 376 377 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 378 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 379 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 380 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 381 382 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 383 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 384 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 385 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 386 387 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 388 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 389 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 390 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 391 392 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 393 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 394 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 395 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 396 397 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 398 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 399 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 400 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 401 402 403 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 404 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 405 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 406 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 407 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 408 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 409 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 410 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 411 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 412 413 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 414 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 415 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 416 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 417 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 418 419 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 420 (*(uint32_t *)(((uint8_t *)_ptr) + \ 421 _wrd ## _ ## _field ## _OFFSET) |= \ 422 ((_val << _wrd ## _ ## _field ## _LSB) & \ 423 _wrd ## _ ## _field ## _MASK)) 424 425 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 426 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 427 _field, _val) 428 429 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 430 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 431 _field, _val) 432 433 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 434 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 435 _field, _val) 436 437 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 438 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 439 { 440 struct reo_destination_ring *reo_dst_ring; 441 uint32_t *mpdu_info; 442 443 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 444 445 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 446 447 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 448 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 449 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 450 mpdu_desc_info->peer_meta_data = 451 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 452 } 453 454 /* 455 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 456 * @ Specifically flags needed are: 457 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 458 * @ msdu_continuation, sa_is_valid, 459 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 460 * @ da_is_MCBC 461 * 462 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 463 * @ descriptor 464 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 465 * @ Return: void 466 */ 467 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 468 struct hal_rx_msdu_desc_info *msdu_desc_info) 469 { 470 struct reo_destination_ring *reo_dst_ring; 471 uint32_t *msdu_info; 472 473 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 474 475 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 476 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 477 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 478 } 479 480 /* 481 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 482 * rxdma ring entry. 483 * @rxdma_entry: descriptor entry 484 * @paddr: physical address of nbuf data pointer. 485 * @cookie: SW cookie used as a index to SW rx desc. 486 * @manager: who owns the nbuf (host, NSS, etc...). 487 * 488 */ 489 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 490 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 491 { 492 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 493 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 494 495 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 496 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 497 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 498 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 499 } 500 501 /* 502 * Structures & Macros to obtain fields from the TLV's in the Rx packet 503 * pre-header. 504 */ 505 506 /* 507 * Every Rx packet starts at an offset from the top of the buffer. 508 * If the host hasn't subscribed to any specific TLV, there is 509 * still space reserved for the following TLV's from the start of 510 * the buffer: 511 * -- RX ATTENTION 512 * -- RX MPDU START 513 * -- RX MSDU START 514 * -- RX MSDU END 515 * -- RX MPDU END 516 * -- RX PACKET HEADER (802.11) 517 * If the host subscribes to any of the TLV's above, that TLV 518 * if populated by the HW 519 */ 520 521 #define NUM_DWORDS_TAG 1 522 523 /* By default the packet header TLV is 128 bytes */ 524 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 525 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 526 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 527 528 #define RX_PKT_OFFSET_WORDS \ 529 ( \ 530 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 531 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 532 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 533 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 534 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 535 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 536 ) 537 538 #define RX_PKT_OFFSET_BYTES \ 539 (RX_PKT_OFFSET_WORDS << 2) 540 541 #define RX_PKT_HDR_TLV_LEN 120 542 543 /* 544 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 545 */ 546 struct rx_attention_tlv { 547 uint32_t tag; 548 struct rx_attention rx_attn; 549 }; 550 551 struct rx_mpdu_start_tlv { 552 uint32_t tag; 553 struct rx_mpdu_start rx_mpdu_start; 554 }; 555 556 struct rx_msdu_start_tlv { 557 uint32_t tag; 558 struct rx_msdu_start rx_msdu_start; 559 }; 560 561 struct rx_msdu_end_tlv { 562 uint32_t tag; 563 struct rx_msdu_end rx_msdu_end; 564 }; 565 566 struct rx_mpdu_end_tlv { 567 uint32_t tag; 568 struct rx_mpdu_end rx_mpdu_end; 569 }; 570 571 struct rx_pkt_hdr_tlv { 572 uint32_t tag; /* 4 B */ 573 uint32_t phy_ppdu_id; /* 4 B */ 574 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 575 }; 576 577 578 #define RXDMA_OPTIMIZATION 579 580 #ifdef RXDMA_OPTIMIZATION 581 /* 582 * The RX_PADDING_BYTES is required so that the TLV's don't 583 * spread across the 128 byte boundary 584 * RXDMA optimization requires: 585 * 1) MSDU_END & ATTENTION TLV's follow in that order 586 * 2) TLV's don't span across 128 byte lines 587 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 588 */ 589 #define RX_PADDING0_BYTES 4 590 #define RX_PADDING1_BYTES 16 591 struct rx_pkt_tlvs { 592 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 593 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 594 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 595 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 596 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 597 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 598 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 599 #ifndef NO_RX_PKT_HDR_TLV 600 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 601 #endif 602 }; 603 #else /* RXDMA_OPTIMIZATION */ 604 struct rx_pkt_tlvs { 605 struct rx_attention_tlv attn_tlv; 606 struct rx_mpdu_start_tlv mpdu_start_tlv; 607 struct rx_msdu_start_tlv msdu_start_tlv; 608 struct rx_msdu_end_tlv msdu_end_tlv; 609 struct rx_mpdu_end_tlv mpdu_end_tlv; 610 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 611 }; 612 #endif /* RXDMA_OPTIMIZATION */ 613 614 #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs)) 615 616 #ifdef NO_RX_PKT_HDR_TLV 617 static inline uint8_t 618 *hal_rx_pkt_hdr_get(uint8_t *buf) 619 { 620 return buf + RX_PKT_TLVS_LEN; 621 } 622 #else 623 static inline uint8_t 624 *hal_rx_pkt_hdr_get(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 628 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 629 630 } 631 #endif 632 633 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 634 635 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 636 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 637 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 638 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 639 RX_PKT_TLV_OFFSET(msdu_start_tlv) 640 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 641 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 642 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 643 644 static inline uint8_t 645 *hal_rx_padding0_get(uint8_t *buf) 646 { 647 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 648 649 return pkt_tlvs->rx_padding0; 650 } 651 652 /* 653 * hal_rx_encryption_info_valid(): Returns encryption type. 654 * 655 * @hal_soc_hdl: hal soc handle 656 * @buf: rx_tlv_hdr of the received packet 657 * 658 * Return: encryption type 659 */ 660 static inline uint32_t 661 hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 662 { 663 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 664 665 return hal_soc->ops->hal_rx_encryption_info_valid(buf); 666 667 } 668 669 /* 670 * hal_rx_print_pn: Prints the PN of rx packet. 671 * @hal_soc_hdl: hal soc handle 672 * @buf: rx_tlv_hdr of the received packet 673 * 674 * Return: void 675 */ 676 static inline void 677 hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 678 { 679 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 680 681 hal_soc->ops->hal_rx_print_pn(buf); 682 } 683 684 /* 685 * Get msdu_done bit from the RX_ATTENTION TLV 686 */ 687 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 688 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 689 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 690 RX_ATTENTION_2_MSDU_DONE_MASK, \ 691 RX_ATTENTION_2_MSDU_DONE_LSB)) 692 693 static inline uint32_t 694 hal_rx_attn_msdu_done_get(uint8_t *buf) 695 { 696 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 697 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 698 uint32_t msdu_done; 699 700 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 701 702 return msdu_done; 703 } 704 705 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 706 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 707 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 708 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 709 RX_ATTENTION_1_FIRST_MPDU_LSB)) 710 711 /* 712 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 713 * @buf: pointer to rx_pkt_tlvs 714 * 715 * reutm: uint32_t(first_msdu) 716 */ 717 static inline uint32_t 718 hal_rx_attn_first_mpdu_get(uint8_t *buf) 719 { 720 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 721 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 722 uint32_t first_mpdu; 723 724 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 725 726 return first_mpdu; 727 } 728 729 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 730 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 731 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 732 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 733 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 734 735 /* 736 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 737 * from rx attention 738 * @buf: pointer to rx_pkt_tlvs 739 * 740 * Return: tcp_udp_cksum_fail 741 */ 742 static inline bool 743 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 744 { 745 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 746 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 747 bool tcp_udp_cksum_fail; 748 749 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 750 751 return tcp_udp_cksum_fail; 752 } 753 754 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 755 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 756 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 757 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 758 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 759 760 /* 761 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 762 * from rx attention 763 * @buf: pointer to rx_pkt_tlvs 764 * 765 * Return: ip_cksum_fail 766 */ 767 static inline bool 768 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 769 { 770 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 771 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 772 bool ip_cksum_fail; 773 774 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 775 776 return ip_cksum_fail; 777 } 778 779 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 780 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 781 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 782 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 783 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 784 785 /* 786 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 787 * from rx attention 788 * @buf: pointer to rx_pkt_tlvs 789 * 790 * Return: phy_ppdu_id 791 */ 792 static inline uint16_t 793 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 794 { 795 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 796 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 797 uint16_t phy_ppdu_id; 798 799 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 800 801 return phy_ppdu_id; 802 } 803 804 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 805 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 806 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 807 RX_ATTENTION_1_CCE_MATCH_MASK, \ 808 RX_ATTENTION_1_CCE_MATCH_LSB)) 809 810 /* 811 * hal_rx_msdu_cce_match_get(): get CCE match bit 812 * from rx attention 813 * @buf: pointer to rx_pkt_tlvs 814 * Return: CCE match value 815 */ 816 static inline bool 817 hal_rx_msdu_cce_match_get(uint8_t *buf) 818 { 819 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 820 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 821 bool cce_match_val; 822 823 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 824 return cce_match_val; 825 } 826 827 /* 828 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 829 */ 830 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 831 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 832 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 833 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 834 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 835 836 static inline uint32_t 837 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 838 { 839 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 840 struct rx_mpdu_start *mpdu_start = 841 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 842 843 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 844 uint32_t peer_meta_data; 845 846 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 847 848 return peer_meta_data; 849 } 850 851 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 852 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 853 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 854 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 855 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 856 /** 857 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 858 * from rx mpdu info 859 * @buf: pointer to rx_pkt_tlvs 860 * 861 * Return: ampdu flag 862 */ 863 static inline bool 864 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_mpdu_start *mpdu_start = 868 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 869 870 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 871 bool ampdu_flag; 872 873 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 874 875 return ampdu_flag; 876 } 877 878 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 879 ((*(((uint32_t *)_rx_mpdu_info) + \ 880 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 881 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 882 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 883 884 /* 885 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 886 * 887 * @ buf: rx_tlv_hdr of the received packet 888 * @ peer_mdata: peer meta data to be set. 889 * @ Return: void 890 */ 891 static inline void 892 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 893 { 894 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 895 struct rx_mpdu_start *mpdu_start = 896 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 897 898 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 899 900 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 901 } 902 903 /** 904 * LRO information needed from the TLVs 905 */ 906 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 907 (_HAL_MS( \ 908 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 909 msdu_end_tlv.rx_msdu_end), \ 910 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 911 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 912 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 913 914 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 915 (_HAL_MS( \ 916 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 917 msdu_end_tlv.rx_msdu_end), \ 918 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 919 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 920 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 921 922 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 923 (_HAL_MS( \ 924 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 925 msdu_end_tlv.rx_msdu_end), \ 926 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 927 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 928 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 929 930 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 931 (_HAL_MS( \ 932 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 933 msdu_end_tlv.rx_msdu_end), \ 934 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 935 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 936 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 937 938 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 939 (_HAL_MS( \ 940 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 941 msdu_start_tlv.rx_msdu_start), \ 942 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 943 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 944 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 945 946 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 947 (_HAL_MS( \ 948 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 949 msdu_start_tlv.rx_msdu_start), \ 950 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 951 RX_MSDU_START_2_TCP_PROTO_MASK, \ 952 RX_MSDU_START_2_TCP_PROTO_LSB)) 953 954 #define HAL_RX_TLV_GET_IPV6(buf) \ 955 (_HAL_MS( \ 956 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 957 msdu_start_tlv.rx_msdu_start), \ 958 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 959 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 960 RX_MSDU_START_2_IPV6_PROTO_LSB)) 961 962 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 963 (_HAL_MS( \ 964 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 965 msdu_start_tlv.rx_msdu_start), \ 966 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 967 RX_MSDU_START_1_L3_OFFSET_MASK, \ 968 RX_MSDU_START_1_L3_OFFSET_LSB)) 969 970 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 971 (_HAL_MS( \ 972 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 973 msdu_start_tlv.rx_msdu_start), \ 974 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 975 RX_MSDU_START_1_L4_OFFSET_MASK, \ 976 RX_MSDU_START_1_L4_OFFSET_LSB)) 977 978 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 979 (_HAL_MS( \ 980 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 981 msdu_start_tlv.rx_msdu_start), \ 982 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 983 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 984 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 985 986 /** 987 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 988 * l3_header padding from rx_msdu_end TLV 989 * 990 * @buf: pointer to the start of RX PKT TLV headers 991 * Return: number of l3 header padding bytes 992 */ 993 static inline uint32_t 994 hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl, 995 uint8_t *buf) 996 { 997 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 998 999 return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf); 1000 } 1001 1002 /** 1003 * hal_rx_msdu_end_sa_idx_get(): API to get the 1004 * sa_idx from rx_msdu_end TLV 1005 * 1006 * @ buf: pointer to the start of RX PKT TLV headers 1007 * Return: sa_idx (SA AST index) 1008 */ 1009 static inline uint16_t 1010 hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl, 1011 uint8_t *buf) 1012 { 1013 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1014 1015 return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf); 1016 } 1017 1018 /** 1019 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1020 * sa_is_valid bit from rx_msdu_end TLV 1021 * 1022 * @ buf: pointer to the start of RX PKT TLV headers 1023 * Return: sa_is_valid bit 1024 */ 1025 static inline uint8_t 1026 hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1027 uint8_t *buf) 1028 { 1029 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1030 1031 return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf); 1032 } 1033 1034 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1035 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1036 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1037 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1038 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1039 1040 /** 1041 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1042 * from rx_msdu_start TLV 1043 * 1044 * @ buf: pointer to the start of RX PKT TLV headers 1045 * Return: msdu length 1046 */ 1047 static inline uint32_t 1048 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1049 { 1050 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1051 struct rx_msdu_start *msdu_start = 1052 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1053 uint32_t msdu_len; 1054 1055 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1056 1057 return msdu_len; 1058 } 1059 1060 /** 1061 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1062 * from rx_msdu_start TLV 1063 * 1064 * @buf: pointer to the start of RX PKT TLV headers 1065 * @len: msdu length 1066 * 1067 * Return: none 1068 */ 1069 static inline void 1070 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1071 { 1072 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1073 struct rx_msdu_start *msdu_start = 1074 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1075 void *wrd1; 1076 1077 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1078 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1079 *(uint32_t *)wrd1 |= len; 1080 } 1081 1082 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1083 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1084 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1085 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1086 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1087 1088 /* 1089 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1090 * Interval from rx_msdu_start 1091 * 1092 * @buf: pointer to the start of RX PKT TLV header 1093 * Return: uint32_t(bw) 1094 */ 1095 static inline uint32_t 1096 hal_rx_msdu_start_bw_get(uint8_t *buf) 1097 { 1098 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1099 struct rx_msdu_start *msdu_start = 1100 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1101 uint32_t bw; 1102 1103 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1104 1105 return bw; 1106 } 1107 1108 1109 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1110 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1111 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1112 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1113 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1114 1115 /** 1116 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1117 * from rx_msdu_start TLV 1118 * 1119 * @ buf: pointer to the start of RX PKT TLV headers 1120 * Return: toeplitz hash 1121 */ 1122 static inline uint32_t 1123 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1124 { 1125 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1126 struct rx_msdu_start *msdu_start = 1127 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1128 1129 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1130 } 1131 1132 /** 1133 * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO 1134 * 1135 * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame 1136 * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame 1137 * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame 1138 * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame 1139 * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame 1140 * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame 1141 * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported 1142 * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit 1143 */ 1144 enum hal_rx_mpdu_info_sw_frame_group_id_type { 1145 HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0, 1146 HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA, 1147 HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA, 1148 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA, 1149 HAL_MPDU_SW_FRAME_GROUP_MGMT, 1150 HAL_MPDU_SW_FRAME_GROUP_CTRL = 20, 1151 HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36, 1152 HAL_MPDU_SW_FRAME_GROUP_MAX = 37, 1153 }; 1154 1155 /** 1156 * hal_rx_mpdu_start_mpdu_qos_control_valid_get(): 1157 * Retrieve qos control valid bit from the tlv. 1158 * @hal_soc_hdl: hal_soc handle 1159 * @buf: pointer to rx pkt TLV. 1160 * 1161 * Return: qos control value. 1162 */ 1163 static inline uint32_t 1164 hal_rx_mpdu_start_mpdu_qos_control_valid_get( 1165 hal_soc_handle_t hal_soc_hdl, 1166 uint8_t *buf) 1167 { 1168 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1169 1170 if ((!hal_soc) || (!hal_soc->ops)) { 1171 hal_err("hal handle is NULL"); 1172 QDF_BUG(0); 1173 return QDF_STATUS_E_INVAL; 1174 } 1175 1176 if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get) 1177 return hal_soc->ops-> 1178 hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf); 1179 1180 return QDF_STATUS_E_INVAL; 1181 } 1182 1183 /** 1184 * hal_rx_is_unicast: check packet is unicast frame or not. 1185 * @hal_soc_hdl: hal_soc handle 1186 * @buf: pointer to rx pkt TLV. 1187 * 1188 * Return: true on unicast. 1189 */ 1190 static inline bool 1191 hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1192 { 1193 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1194 1195 return hal_soc->ops->hal_rx_is_unicast(buf); 1196 } 1197 1198 /** 1199 * hal_rx_tid_get: get tid based on qos control valid. 1200 * @hal_soc_hdl: hal soc handle 1201 * @buf: pointer to rx pkt TLV. 1202 * 1203 * Return: tid 1204 */ 1205 static inline uint32_t 1206 hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1207 { 1208 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1209 1210 return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf); 1211 } 1212 1213 /** 1214 * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id 1215 * @hal_soc_hdl: hal soc handle 1216 * @buf: pointer to rx pkt TLV. 1217 * 1218 * Return: sw peer_id 1219 */ 1220 static inline uint32_t 1221 hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 1222 uint8_t *buf) 1223 { 1224 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1225 1226 return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf); 1227 } 1228 1229 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1230 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1231 RX_MSDU_START_5_SGI_OFFSET)), \ 1232 RX_MSDU_START_5_SGI_MASK, \ 1233 RX_MSDU_START_5_SGI_LSB)) 1234 /** 1235 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1236 * Interval from rx_msdu_start TLV 1237 * 1238 * @buf: pointer to the start of RX PKT TLV headers 1239 * Return: uint32_t(sgi) 1240 */ 1241 static inline uint32_t 1242 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1243 { 1244 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1245 struct rx_msdu_start *msdu_start = 1246 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1247 uint32_t sgi; 1248 1249 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1250 1251 return sgi; 1252 } 1253 1254 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1255 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1256 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1257 RX_MSDU_START_5_RATE_MCS_MASK, \ 1258 RX_MSDU_START_5_RATE_MCS_LSB)) 1259 /** 1260 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1261 * from rx_msdu_start TLV 1262 * 1263 * @buf: pointer to the start of RX PKT TLV headers 1264 * Return: uint32_t(rate_mcs) 1265 */ 1266 static inline uint32_t 1267 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1268 { 1269 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1270 struct rx_msdu_start *msdu_start = 1271 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1272 uint32_t rate_mcs; 1273 1274 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1275 1276 return rate_mcs; 1277 } 1278 1279 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1280 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1281 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1282 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1283 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1284 1285 /* 1286 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1287 * packet from rx_attention 1288 * 1289 * @buf: pointer to the start of RX PKT TLV header 1290 * Return: uint32_t(decryt status) 1291 */ 1292 1293 static inline uint32_t 1294 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1295 { 1296 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1297 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1298 uint32_t is_decrypt = 0; 1299 uint32_t decrypt_status; 1300 1301 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1302 1303 if (!decrypt_status) 1304 is_decrypt = 1; 1305 1306 return is_decrypt; 1307 } 1308 1309 /* 1310 * Get key index from RX_MSDU_END 1311 */ 1312 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1313 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1314 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1315 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1316 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1317 /* 1318 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1319 * from rx_msdu_end 1320 * 1321 * @buf: pointer to the start of RX PKT TLV header 1322 * Return: uint32_t(key id) 1323 */ 1324 1325 static inline uint32_t 1326 hal_rx_msdu_get_keyid(uint8_t *buf) 1327 { 1328 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1329 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1330 uint32_t keyid_octet; 1331 1332 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1333 1334 return keyid_octet & 0x3; 1335 } 1336 1337 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1338 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1339 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1340 RX_MSDU_START_5_USER_RSSI_MASK, \ 1341 RX_MSDU_START_5_USER_RSSI_LSB)) 1342 /* 1343 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1344 * from rx_msdu_start 1345 * 1346 * @buf: pointer to the start of RX PKT TLV header 1347 * Return: uint32_t(rssi) 1348 */ 1349 1350 static inline uint32_t 1351 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1352 { 1353 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1354 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1355 uint32_t rssi; 1356 1357 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1358 1359 return rssi; 1360 1361 } 1362 1363 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1364 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1365 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1366 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1367 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1368 1369 /* 1370 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1371 * from rx_msdu_start 1372 * 1373 * @buf: pointer to the start of RX PKT TLV header 1374 * Return: uint32_t(frequency) 1375 */ 1376 1377 static inline uint32_t 1378 hal_rx_msdu_start_get_freq(uint8_t *buf) 1379 { 1380 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1381 struct rx_msdu_start *msdu_start = 1382 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1383 uint32_t freq; 1384 1385 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1386 1387 return freq; 1388 } 1389 1390 1391 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1392 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1393 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1394 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1395 RX_MSDU_START_5_PKT_TYPE_LSB)) 1396 1397 /* 1398 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1399 * from rx_msdu_start 1400 * 1401 * @buf: pointer to the start of RX PKT TLV header 1402 * Return: uint32_t(pkt type) 1403 */ 1404 1405 static inline uint32_t 1406 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1407 { 1408 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1409 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1410 uint32_t pkt_type; 1411 1412 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1413 1414 return pkt_type; 1415 } 1416 1417 /* 1418 * hal_rx_mpdu_get_tods(): API to get the tods info 1419 * from rx_mpdu_start 1420 * 1421 * @buf: pointer to the start of RX PKT TLV header 1422 * Return: uint32_t(to_ds) 1423 */ 1424 1425 static inline uint32_t 1426 hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1427 { 1428 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1429 1430 return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf); 1431 } 1432 1433 1434 /* 1435 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1436 * from rx_mpdu_start 1437 * @hal_soc_hdl: hal soc handle 1438 * @buf: pointer to the start of RX PKT TLV header 1439 * 1440 * Return: uint32_t(fr_ds) 1441 */ 1442 static inline uint32_t 1443 hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1444 { 1445 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1446 1447 return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); 1448 } 1449 1450 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1451 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1452 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1453 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1454 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1455 1456 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1457 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1458 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1459 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1460 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1461 1462 /* 1463 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1464 * @hal_soc_hdl: hal soc handle 1465 * @buf: pointer to the start of RX PKT TLV headera 1466 * @mac_addr: pointer to mac address 1467 * 1468 * Return: success/failure 1469 */ 1470 static inline 1471 QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl, 1472 uint8_t *buf, uint8_t *mac_addr) 1473 { 1474 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1475 1476 return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr); 1477 } 1478 1479 /* 1480 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1481 * in the packet 1482 * @hal_soc_hdl: hal soc handle 1483 * @buf: pointer to the start of RX PKT TLV header 1484 * @mac_addr: pointer to mac address 1485 * 1486 * Return: success/failure 1487 */ 1488 static inline 1489 QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl, 1490 uint8_t *buf, uint8_t *mac_addr) 1491 { 1492 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1493 1494 return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr); 1495 } 1496 1497 /* 1498 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1499 * in the packet 1500 * @hal_soc_hdl: hal soc handle 1501 * @buf: pointer to the start of RX PKT TLV header 1502 * @mac_addr: pointer to mac address 1503 * 1504 * Return: success/failure 1505 */ 1506 static inline 1507 QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl, 1508 uint8_t *buf, uint8_t *mac_addr) 1509 { 1510 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1511 1512 return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr); 1513 } 1514 1515 /* 1516 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1517 * in the packet 1518 * @hal_soc_hdl: hal_soc handle 1519 * @buf: pointer to the start of RX PKT TLV header 1520 * @mac_addr: pointer to mac address 1521 * Return: success/failure 1522 */ 1523 static inline 1524 QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl, 1525 uint8_t *buf, uint8_t *mac_addr) 1526 { 1527 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1528 1529 return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr); 1530 } 1531 1532 /** 1533 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1534 * from rx_msdu_end TLV 1535 * 1536 * @ buf: pointer to the start of RX PKT TLV headers 1537 * Return: da index 1538 */ 1539 static inline uint16_t 1540 hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1541 { 1542 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1543 1544 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1545 } 1546 1547 /** 1548 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1549 * from rx_msdu_end TLV 1550 * @hal_soc_hdl: hal soc handle 1551 * @ buf: pointer to the start of RX PKT TLV headers 1552 * 1553 * Return: da_is_valid 1554 */ 1555 static inline uint8_t 1556 hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl, 1557 uint8_t *buf) 1558 { 1559 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1560 1561 return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf); 1562 } 1563 1564 /** 1565 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1566 * from rx_msdu_end TLV 1567 * 1568 * @buf: pointer to the start of RX PKT TLV headers 1569 * 1570 * Return: da_is_mcbc 1571 */ 1572 static inline uint8_t 1573 hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1574 { 1575 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1576 1577 return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf); 1578 } 1579 1580 /** 1581 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1582 * from rx_msdu_end TLV 1583 * @hal_soc_hdl: hal soc handle 1584 * @buf: pointer to the start of RX PKT TLV headers 1585 * 1586 * Return: first_msdu 1587 */ 1588 static inline uint8_t 1589 hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl, 1590 uint8_t *buf) 1591 { 1592 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1593 1594 return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf); 1595 } 1596 1597 /** 1598 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1599 * from rx_msdu_end TLV 1600 * @hal_soc_hdl: hal soc handle 1601 * @buf: pointer to the start of RX PKT TLV headers 1602 * 1603 * Return: last_msdu 1604 */ 1605 static inline uint8_t 1606 hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl, 1607 uint8_t *buf) 1608 { 1609 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1610 1611 return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf); 1612 } 1613 1614 /** 1615 * hal_rx_msdu_cce_metadata_get: API to get CCE metadata 1616 * from rx_msdu_end TLV 1617 * @buf: pointer to the start of RX PKT TLV headers 1618 * Return: cce_meta_data 1619 */ 1620 static inline uint16_t 1621 hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl, 1622 uint8_t *buf) 1623 { 1624 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1625 1626 return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf); 1627 } 1628 1629 /******************************************************************************* 1630 * RX ERROR APIS 1631 ******************************************************************************/ 1632 1633 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1634 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1635 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1636 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1637 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1638 1639 /** 1640 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1641 * from rx_mpdu_end TLV 1642 * 1643 * @buf: pointer to the start of RX PKT TLV headers 1644 * Return: uint32_t(decrypt_err) 1645 */ 1646 static inline uint32_t 1647 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1648 { 1649 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1650 struct rx_mpdu_end *mpdu_end = 1651 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1652 uint32_t decrypt_err; 1653 1654 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1655 1656 return decrypt_err; 1657 } 1658 1659 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1660 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1661 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1662 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1663 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1664 1665 /** 1666 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1667 * from rx_mpdu_end TLV 1668 * 1669 * @buf: pointer to the start of RX PKT TLV headers 1670 * Return: uint32_t(mic_err) 1671 */ 1672 static inline uint32_t 1673 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1674 { 1675 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1676 struct rx_mpdu_end *mpdu_end = 1677 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1678 uint32_t mic_err; 1679 1680 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1681 1682 return mic_err; 1683 } 1684 1685 /******************************************************************************* 1686 * RX REO ERROR APIS 1687 ******************************************************************************/ 1688 1689 #define HAL_RX_NUM_MSDU_DESC 6 1690 #define HAL_RX_MAX_SAVED_RING_DESC 16 1691 1692 /* TODO: rework the structure */ 1693 struct hal_rx_msdu_list { 1694 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1695 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1696 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1697 /* physical address of the msdu */ 1698 uint64_t paddr[HAL_RX_NUM_MSDU_DESC]; 1699 }; 1700 1701 struct hal_buf_info { 1702 uint64_t paddr; 1703 uint32_t sw_cookie; 1704 }; 1705 1706 /** 1707 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1708 * @msdu_link_ptr - msdu link ptr 1709 * @hal - pointer to hal_soc 1710 * Return - Pointer to rx_msdu_details structure 1711 * 1712 */ 1713 static inline 1714 void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, 1715 struct hal_soc *hal_soc) 1716 { 1717 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1718 } 1719 1720 /** 1721 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1722 * @msdu_details_ptr - Pointer to msdu_details_ptr 1723 * @hal - pointer to hal_soc 1724 * Return - Pointer to rx_msdu_desc_info structure. 1725 * 1726 */ 1727 static inline 1728 void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, 1729 struct hal_soc *hal_soc) 1730 { 1731 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1732 } 1733 1734 /* This special cookie value will be used to indicate FW allocated buffers 1735 * received through RXDMA2SW ring for RXDMA WARs 1736 */ 1737 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1738 1739 /** 1740 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1741 * from the MSDU link descriptor 1742 * 1743 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1744 * MSDU link descriptor (struct rx_msdu_link) 1745 * 1746 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1747 * 1748 * @num_msdus: Number of MSDUs in the MPDU 1749 * 1750 * Return: void 1751 */ 1752 static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl, 1753 void *msdu_link_desc, 1754 struct hal_rx_msdu_list *msdu_list, 1755 uint16_t *num_msdus) 1756 { 1757 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1758 struct rx_msdu_details *msdu_details; 1759 struct rx_msdu_desc_info *msdu_desc_info; 1760 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1761 int i; 1762 1763 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1764 1765 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1766 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1767 __func__, __LINE__, msdu_link, msdu_details); 1768 1769 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1770 /* num_msdus received in mpdu descriptor may be incorrect 1771 * sometimes due to HW issue. Check msdu buffer address also 1772 */ 1773 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1774 &msdu_details[i].buffer_addr_info_details) == 0) { 1775 /* set the last msdu bit in the prev msdu_desc_info */ 1776 msdu_desc_info = 1777 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1778 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1779 break; 1780 } 1781 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1782 hal_soc); 1783 1784 /* set first MSDU bit or the last MSDU bit */ 1785 if (!i) 1786 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1787 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1788 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1789 1790 msdu_list->msdu_info[i].msdu_flags = 1791 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1792 msdu_list->msdu_info[i].msdu_len = 1793 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1794 msdu_list->sw_cookie[i] = 1795 HAL_RX_BUF_COOKIE_GET( 1796 &msdu_details[i].buffer_addr_info_details); 1797 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1798 &msdu_details[i].buffer_addr_info_details); 1799 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 1800 &msdu_details[i].buffer_addr_info_details) | 1801 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 1802 &msdu_details[i].buffer_addr_info_details) << 32; 1803 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1804 "[%s][%d] i=%d sw_cookie=%d", 1805 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1806 } 1807 *num_msdus = i; 1808 } 1809 1810 /** 1811 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1812 * destination ring ID from the msdu desc info 1813 * 1814 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1815 * the current descriptor 1816 * 1817 * Return: dst_ind (REO destination ring ID) 1818 */ 1819 static inline uint32_t 1820 hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc) 1821 { 1822 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1823 struct rx_msdu_details *msdu_details; 1824 struct rx_msdu_desc_info *msdu_desc_info; 1825 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1826 uint32_t dst_ind; 1827 1828 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1829 1830 /* The first msdu in the link should exsist */ 1831 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1832 hal_soc); 1833 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1834 return dst_ind; 1835 } 1836 1837 /** 1838 * hal_rx_reo_buf_paddr_get: Gets the physical address and 1839 * cookie from the REO destination ring element 1840 * 1841 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 1842 * the current descriptor 1843 * @ buf_info: structure to return the buffer information 1844 * Return: void 1845 */ 1846 static inline 1847 void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc, 1848 struct hal_buf_info *buf_info) 1849 { 1850 struct reo_destination_ring *reo_ring = 1851 (struct reo_destination_ring *)rx_desc; 1852 1853 buf_info->paddr = 1854 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 1855 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 1856 1857 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 1858 } 1859 1860 /** 1861 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 1862 * 1863 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 1864 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 1865 * descriptor 1866 */ 1867 enum hal_rx_reo_buf_type { 1868 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 1869 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 1870 }; 1871 1872 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 1873 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 1874 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 1875 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 1876 1877 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 1878 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 1879 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 1880 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 1881 1882 /** 1883 * enum hal_reo_error_code: Error code describing the type of error detected 1884 * 1885 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 1886 * REO_ENTRANCE ring is set to 0 1887 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 1888 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 1889 * having been setup 1890 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 1891 * Retry bit set: duplicate frame 1892 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 1893 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 1894 * received with 2K jump in SN 1895 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 1896 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 1897 * with SN falling within the OOR window 1898 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 1899 * OOR window 1900 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 1901 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 1902 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 1903 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1904 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 1905 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 1906 * of the pn_error_detected_flag been set in the REO Queue descriptor 1907 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 1908 * the queue descriptor(address) being blocked as SW/FW seems to be currently 1909 * in the process of making updates to this descriptor 1910 */ 1911 enum hal_reo_error_code { 1912 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 1913 HAL_REO_ERR_QUEUE_DESC_INVALID, 1914 HAL_REO_ERR_AMPDU_IN_NON_BA, 1915 HAL_REO_ERR_NON_BA_DUPLICATE, 1916 HAL_REO_ERR_BA_DUPLICATE, 1917 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 1918 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 1919 HAL_REO_ERR_REGULAR_FRAME_OOR, 1920 HAL_REO_ERR_BAR_FRAME_OOR, 1921 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 1922 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 1923 HAL_REO_ERR_PN_CHECK_FAILED, 1924 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 1925 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 1926 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 1927 HAL_REO_ERR_MAX 1928 }; 1929 1930 /** 1931 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 1932 * 1933 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 1934 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 1935 * overflow 1936 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 1937 * incomplete 1938 * MPDU from the PHY 1939 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 1940 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 1941 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 1942 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 1943 * encrypted but wasn’t 1944 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 1945 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 1946 * the max allowed 1947 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 1948 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 1949 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 1950 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 1951 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 1952 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 1953 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 1954 */ 1955 enum hal_rxdma_error_code { 1956 HAL_RXDMA_ERR_OVERFLOW = 0, 1957 HAL_RXDMA_ERR_MPDU_LENGTH, 1958 HAL_RXDMA_ERR_FCS, 1959 HAL_RXDMA_ERR_DECRYPT, 1960 HAL_RXDMA_ERR_TKIP_MIC, 1961 HAL_RXDMA_ERR_UNENCRYPTED, 1962 HAL_RXDMA_ERR_MSDU_LEN, 1963 HAL_RXDMA_ERR_MSDU_LIMIT, 1964 HAL_RXDMA_ERR_WIFI_PARSE, 1965 HAL_RXDMA_ERR_AMSDU_PARSE, 1966 HAL_RXDMA_ERR_SA_TIMEOUT, 1967 HAL_RXDMA_ERR_DA_TIMEOUT, 1968 HAL_RXDMA_ERR_FLOW_TIMEOUT, 1969 HAL_RXDMA_ERR_FLUSH_REQUEST, 1970 HAL_RXDMA_ERR_WAR = 31, 1971 HAL_RXDMA_ERR_MAX 1972 }; 1973 1974 /** 1975 * HW BM action settings in WBM release ring 1976 */ 1977 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 1978 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 1979 1980 /** 1981 * enum hal_rx_wbm_error_source: Indicates which module initiated the 1982 * release of this buffer or descriptor 1983 * 1984 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 1985 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 1986 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 1987 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 1988 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 1989 */ 1990 enum hal_rx_wbm_error_source { 1991 HAL_RX_WBM_ERR_SRC_TQM = 0, 1992 HAL_RX_WBM_ERR_SRC_RXDMA, 1993 HAL_RX_WBM_ERR_SRC_REO, 1994 HAL_RX_WBM_ERR_SRC_FW, 1995 HAL_RX_WBM_ERR_SRC_SW, 1996 }; 1997 1998 /** 1999 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2000 * released 2001 * 2002 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2003 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2004 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2005 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2006 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2007 */ 2008 enum hal_rx_wbm_buf_type { 2009 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2010 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2011 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2012 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2013 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2014 }; 2015 2016 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2017 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2018 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2019 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2020 2021 /** 2022 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2023 * PN check failure 2024 * 2025 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2026 * 2027 * Return: true: error caused by PN check, false: other error 2028 */ 2029 static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc) 2030 { 2031 struct reo_destination_ring *reo_desc = 2032 (struct reo_destination_ring *)rx_desc; 2033 2034 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2035 HAL_REO_ERR_PN_CHECK_FAILED) | 2036 (HAL_RX_REO_ERROR_GET(reo_desc) == 2037 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2038 true : false; 2039 } 2040 2041 /** 2042 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2043 * the sequence number 2044 * 2045 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2046 * 2047 * Return: true: error caused by 2K jump, false: other error 2048 */ 2049 static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc) 2050 { 2051 struct reo_destination_ring *reo_desc = 2052 (struct reo_destination_ring *)rx_desc; 2053 2054 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2055 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2056 (HAL_RX_REO_ERROR_GET(reo_desc) == 2057 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2058 true : false; 2059 } 2060 2061 #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 2062 /** 2063 * hal_dump_wbm_rel_desc() - dump wbm release descriptor 2064 * @hal_desc: hardware descriptor pointer 2065 * 2066 * This function will print wbm release descriptor 2067 * 2068 * Return: none 2069 */ 2070 static inline void hal_dump_wbm_rel_desc(void *src_srng_desc) 2071 { 2072 uint32_t *wbm_comp = (uint32_t *)src_srng_desc; 2073 uint32_t i; 2074 2075 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2076 "Current Rx wbm release descriptor is"); 2077 2078 for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) { 2079 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 2080 "DWORD[i] = 0x%x", wbm_comp[i]); 2081 } 2082 } 2083 2084 /** 2085 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2086 * 2087 * @ hal_soc_hdl : HAL version of the SOC pointer 2088 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2089 * @ buf_addr_info : void pointer to the buffer_addr_info 2090 * @ bm_action : put in IDLE list or release to MSDU_LIST 2091 * 2092 * Return: void 2093 */ 2094 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2095 static inline 2096 void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 2097 void *src_srng_desc, 2098 hal_link_desc_t buf_addr_info, 2099 uint8_t bm_action) 2100 { 2101 struct wbm_release_ring *wbm_rel_srng = 2102 (struct wbm_release_ring *)src_srng_desc; 2103 uint32_t addr_31_0; 2104 uint8_t addr_39_32; 2105 2106 /* Structure copy !!! */ 2107 wbm_rel_srng->released_buff_or_desc_addr_info = 2108 *((struct buffer_addr_info *)buf_addr_info); 2109 2110 addr_31_0 = 2111 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 2112 addr_39_32 = 2113 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 2114 2115 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2116 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2117 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2118 bm_action); 2119 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2120 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2121 2122 /* WBM error is indicated when any of the link descriptors given to 2123 * WBM has a NULL address, and one those paths is the link descriptors 2124 * released from host after processing RXDMA errors, 2125 * or from Rx defrag path, and we want to add an assert here to ensure 2126 * host is not releasing descriptors with NULL address. 2127 */ 2128 2129 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 2130 hal_dump_wbm_rel_desc(src_srng_desc); 2131 qdf_assert_always(0); 2132 } 2133 } 2134 2135 /* 2136 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2137 * REO entrance ring 2138 * 2139 * @ soc: HAL version of the SOC pointer 2140 * @ pa: Physical address of the MSDU Link Descriptor 2141 * @ cookie: SW cookie to get to the virtual address 2142 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2143 * to the error enabled REO queue 2144 * 2145 * Return: void 2146 */ 2147 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2148 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2149 { 2150 /* TODO */ 2151 } 2152 2153 /** 2154 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2155 * BUFFER_ADDR_INFO, give the RX descriptor 2156 * (Assumption -- BUFFER_ADDR_INFO is the 2157 * first field in the descriptor structure) 2158 */ 2159 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \ 2160 ((hal_link_desc_t)(ring_desc)) 2161 2162 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2163 2164 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2165 2166 /** 2167 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2168 * from the BUFFER_ADDR_INFO structure 2169 * given a REO destination ring descriptor. 2170 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2171 * 2172 * Return: uint8_t (value of the return_buffer_manager) 2173 */ 2174 static inline 2175 uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc) 2176 { 2177 /* 2178 * The following macro takes buf_addr_info as argument, 2179 * but since buf_addr_info is the first field in ring_desc 2180 * Hence the following call is OK 2181 */ 2182 return HAL_RX_BUF_RBM_GET(ring_desc); 2183 } 2184 2185 2186 /******************************************************************************* 2187 * RX WBM ERROR APIS 2188 ******************************************************************************/ 2189 2190 2191 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2192 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2193 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2194 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2195 2196 /** 2197 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2198 * the frame to this release ring 2199 * 2200 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2201 * frame to this queue 2202 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2203 * received routing instructions. No error within REO was detected 2204 */ 2205 enum hal_rx_wbm_reo_push_reason { 2206 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2207 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2208 }; 2209 2210 2211 /** 2212 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2213 * this release ring 2214 * 2215 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2216 * this frame to this queue 2217 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2218 * per received routing instructions. No error within RXDMA was detected 2219 */ 2220 enum hal_rx_wbm_rxdma_push_reason { 2221 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2222 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2223 }; 2224 2225 2226 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2227 (((*(((uint32_t *) wbm_desc) + \ 2228 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2229 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2230 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2231 2232 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2233 (((*(((uint32_t *) wbm_desc) + \ 2234 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2235 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2236 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2237 2238 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2239 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2240 wbm_desc)->released_buff_or_desc_addr_info) 2241 2242 /** 2243 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2244 * humman readable format. 2245 * @ rx_attn: pointer the rx_attention TLV in pkt. 2246 * @ dbg_level: log level. 2247 * 2248 * Return: void 2249 */ 2250 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2251 uint8_t dbg_level) 2252 { 2253 hal_verbose_debug( 2254 "rx_attention tlv (1/2) - " 2255 "rxpcu_mpdu_filter_in_category: %x " 2256 "sw_frame_group_id: %x " 2257 "reserved_0: %x " 2258 "phy_ppdu_id: %x " 2259 "first_mpdu : %x " 2260 "reserved_1a: %x " 2261 "mcast_bcast: %x " 2262 "ast_index_not_found: %x " 2263 "ast_index_timeout: %x " 2264 "power_mgmt: %x " 2265 "non_qos: %x " 2266 "null_data: %x " 2267 "mgmt_type: %x " 2268 "ctrl_type: %x " 2269 "more_data: %x " 2270 "eosp: %x " 2271 "a_msdu_error: %x " 2272 "fragment_flag: %x " 2273 "order: %x " 2274 "cce_match: %x " 2275 "overflow_err: %x " 2276 "msdu_length_err: %x " 2277 "tcp_udp_chksum_fail: %x " 2278 "ip_chksum_fail: %x " 2279 "sa_idx_invalid: %x " 2280 "da_idx_invalid: %x " 2281 "reserved_1b: %x " 2282 "rx_in_tx_decrypt_byp: %x ", 2283 rx_attn->rxpcu_mpdu_filter_in_category, 2284 rx_attn->sw_frame_group_id, 2285 rx_attn->reserved_0, 2286 rx_attn->phy_ppdu_id, 2287 rx_attn->first_mpdu, 2288 rx_attn->reserved_1a, 2289 rx_attn->mcast_bcast, 2290 rx_attn->ast_index_not_found, 2291 rx_attn->ast_index_timeout, 2292 rx_attn->power_mgmt, 2293 rx_attn->non_qos, 2294 rx_attn->null_data, 2295 rx_attn->mgmt_type, 2296 rx_attn->ctrl_type, 2297 rx_attn->more_data, 2298 rx_attn->eosp, 2299 rx_attn->a_msdu_error, 2300 rx_attn->fragment_flag, 2301 rx_attn->order, 2302 rx_attn->cce_match, 2303 rx_attn->overflow_err, 2304 rx_attn->msdu_length_err, 2305 rx_attn->tcp_udp_chksum_fail, 2306 rx_attn->ip_chksum_fail, 2307 rx_attn->sa_idx_invalid, 2308 rx_attn->da_idx_invalid, 2309 rx_attn->reserved_1b, 2310 rx_attn->rx_in_tx_decrypt_byp); 2311 2312 hal_verbose_debug( 2313 "rx_attention tlv (2/2) - " 2314 "encrypt_required: %x " 2315 "directed: %x " 2316 "buffer_fragment: %x " 2317 "mpdu_length_err: %x " 2318 "tkip_mic_err: %x " 2319 "decrypt_err: %x " 2320 "unencrypted_frame_err: %x " 2321 "fcs_err: %x " 2322 "flow_idx_timeout: %x " 2323 "flow_idx_invalid: %x " 2324 "wifi_parser_error: %x " 2325 "amsdu_parser_error: %x " 2326 "sa_idx_timeout: %x " 2327 "da_idx_timeout: %x " 2328 "msdu_limit_error: %x " 2329 "da_is_valid: %x " 2330 "da_is_mcbc: %x " 2331 "sa_is_valid: %x " 2332 "decrypt_status_code: %x " 2333 "rx_bitmap_not_updated: %x " 2334 "reserved_2: %x " 2335 "msdu_done: %x ", 2336 rx_attn->encrypt_required, 2337 rx_attn->directed, 2338 rx_attn->buffer_fragment, 2339 rx_attn->mpdu_length_err, 2340 rx_attn->tkip_mic_err, 2341 rx_attn->decrypt_err, 2342 rx_attn->unencrypted_frame_err, 2343 rx_attn->fcs_err, 2344 rx_attn->flow_idx_timeout, 2345 rx_attn->flow_idx_invalid, 2346 rx_attn->wifi_parser_error, 2347 rx_attn->amsdu_parser_error, 2348 rx_attn->sa_idx_timeout, 2349 rx_attn->da_idx_timeout, 2350 rx_attn->msdu_limit_error, 2351 rx_attn->da_is_valid, 2352 rx_attn->da_is_mcbc, 2353 rx_attn->sa_is_valid, 2354 rx_attn->decrypt_status_code, 2355 rx_attn->rx_bitmap_not_updated, 2356 rx_attn->reserved_2, 2357 rx_attn->msdu_done); 2358 } 2359 2360 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2361 uint8_t dbg_level, 2362 struct hal_soc *hal) 2363 { 2364 2365 hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 2366 } 2367 /** 2368 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2369 * human readable format. 2370 * @ msdu_end: pointer the msdu_end TLV in pkt. 2371 * @ dbg_level: log level. 2372 * 2373 * Return: void 2374 */ 2375 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2376 struct rx_msdu_end *msdu_end, 2377 uint8_t dbg_level) 2378 { 2379 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2380 } 2381 2382 /** 2383 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2384 * human readable format. 2385 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2386 * @ dbg_level: log level. 2387 * 2388 * Return: void 2389 */ 2390 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2391 uint8_t dbg_level) 2392 { 2393 hal_verbose_debug( 2394 "rx_mpdu_end tlv - " 2395 "rxpcu_mpdu_filter_in_category: %x " 2396 "sw_frame_group_id: %x " 2397 "phy_ppdu_id: %x " 2398 "unsup_ktype_short_frame: %x " 2399 "rx_in_tx_decrypt_byp: %x " 2400 "overflow_err: %x " 2401 "mpdu_length_err: %x " 2402 "tkip_mic_err: %x " 2403 "decrypt_err: %x " 2404 "unencrypted_frame_err: %x " 2405 "pn_fields_contain_valid_info: %x " 2406 "fcs_err: %x " 2407 "msdu_length_err: %x " 2408 "rxdma0_destination_ring: %x " 2409 "rxdma1_destination_ring: %x " 2410 "decrypt_status_code: %x " 2411 "rx_bitmap_not_updated: %x ", 2412 mpdu_end->rxpcu_mpdu_filter_in_category, 2413 mpdu_end->sw_frame_group_id, 2414 mpdu_end->phy_ppdu_id, 2415 mpdu_end->unsup_ktype_short_frame, 2416 mpdu_end->rx_in_tx_decrypt_byp, 2417 mpdu_end->overflow_err, 2418 mpdu_end->mpdu_length_err, 2419 mpdu_end->tkip_mic_err, 2420 mpdu_end->decrypt_err, 2421 mpdu_end->unencrypted_frame_err, 2422 mpdu_end->pn_fields_contain_valid_info, 2423 mpdu_end->fcs_err, 2424 mpdu_end->msdu_length_err, 2425 mpdu_end->rxdma0_destination_ring, 2426 mpdu_end->rxdma1_destination_ring, 2427 mpdu_end->decrypt_status_code, 2428 mpdu_end->rx_bitmap_not_updated); 2429 } 2430 2431 #ifdef NO_RX_PKT_HDR_TLV 2432 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2433 uint8_t dbg_level) 2434 { 2435 } 2436 #else 2437 /** 2438 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2439 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2440 * @ dbg_level: log level. 2441 * 2442 * Return: void 2443 */ 2444 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 2445 uint8_t dbg_level) 2446 { 2447 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 2448 2449 hal_verbose_debug( 2450 "\n---------------\n" 2451 "rx_pkt_hdr_tlv \n" 2452 "---------------\n" 2453 "phy_ppdu_id %d ", 2454 pkt_hdr_tlv->phy_ppdu_id); 2455 2456 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 2457 } 2458 #endif 2459 2460 /** 2461 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2462 * structure 2463 * @hal_ring: pointer to hal_srng structure 2464 * 2465 * Return: ring_id 2466 */ 2467 static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl) 2468 { 2469 return ((struct hal_srng *)hal_ring_hdl)->ring_id; 2470 } 2471 2472 /* Rx MSDU link pointer info */ 2473 struct hal_rx_msdu_link_ptr_info { 2474 struct rx_msdu_link msdu_link; 2475 struct hal_buf_info msdu_link_buf_info; 2476 }; 2477 2478 /** 2479 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2480 * 2481 * @nbuf: Pointer to data buffer field 2482 * Returns: pointer to rx_pkt_tlvs 2483 */ 2484 static inline 2485 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2486 { 2487 return (struct rx_pkt_tlvs *)rx_buf_start; 2488 } 2489 2490 /** 2491 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2492 * 2493 * @pkt_tlvs: Pointer to pkt_tlvs 2494 * Returns: pointer to rx_mpdu_info structure 2495 */ 2496 static inline 2497 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2498 { 2499 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2500 } 2501 2502 #define DOT11_SEQ_FRAG_MASK 0x000f 2503 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2504 2505 /** 2506 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2507 * 2508 * @nbuf: Network buffer 2509 * Returns: rx fragment number 2510 */ 2511 static inline 2512 uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc, 2513 uint8_t *buf) 2514 { 2515 return hal_soc->ops->hal_rx_get_rx_fragment_number(buf); 2516 } 2517 2518 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2519 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2520 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2521 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2522 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2523 /** 2524 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2525 * 2526 * @nbuf: Network buffer 2527 * Returns: rx more fragment bit 2528 */ 2529 static inline 2530 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2531 { 2532 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2533 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2534 uint16_t frame_ctrl = 0; 2535 2536 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2537 DOT11_FC1_MORE_FRAG_OFFSET; 2538 2539 /* more fragment bit if at offset bit 4 */ 2540 return frame_ctrl; 2541 } 2542 2543 /** 2544 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2545 * 2546 * @nbuf: Network buffer 2547 * Returns: rx more fragment bit 2548 * 2549 */ 2550 static inline 2551 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2552 { 2553 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2554 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2555 uint16_t frame_ctrl = 0; 2556 2557 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2558 2559 return frame_ctrl; 2560 } 2561 2562 /* 2563 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2564 * 2565 * @nbuf: Network buffer 2566 * Returns: flag to indicate whether the nbuf has MC/BC address 2567 */ 2568 static inline 2569 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2570 { 2571 uint8 *buf = qdf_nbuf_data(nbuf); 2572 2573 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2574 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2575 2576 return rx_attn->mcast_bcast; 2577 } 2578 2579 /* 2580 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2581 * @hal_soc_hdl: hal soc handle 2582 * @nbuf: Network buffer 2583 * 2584 * Return: value of sequence control valid field 2585 */ 2586 static inline 2587 uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl, 2588 uint8_t *buf) 2589 { 2590 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2591 2592 return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf); 2593 } 2594 2595 /* 2596 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2597 * @hal_soc_hdl: hal soc handle 2598 * @nbuf: Network buffer 2599 * 2600 * Returns: value of frame control valid field 2601 */ 2602 static inline 2603 uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl, 2604 uint8_t *buf) 2605 { 2606 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2607 2608 return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf); 2609 } 2610 2611 /** 2612 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2613 * @hal_soc_hdl: hal soc handle 2614 * @nbuf: Network buffer 2615 * Returns: value of mpdu 4th address valid field 2616 */ 2617 static inline 2618 bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl, 2619 uint8_t *buf) 2620 { 2621 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2622 2623 return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf); 2624 } 2625 2626 /* 2627 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 2628 * 2629 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 2630 * Returns: None 2631 */ 2632 static inline 2633 void hal_rx_clear_mpdu_desc_info( 2634 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 2635 { 2636 qdf_mem_zero(rx_mpdu_desc_info, 2637 sizeof(*rx_mpdu_desc_info)); 2638 } 2639 2640 /* 2641 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 2642 * 2643 * @msdu_link_ptr: HAL view of msdu link ptr 2644 * @size: number of msdu link pointers 2645 * Returns: None 2646 */ 2647 static inline 2648 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 2649 int size) 2650 { 2651 qdf_mem_zero(msdu_link_ptr, 2652 (sizeof(*msdu_link_ptr) * size)); 2653 } 2654 2655 /* 2656 * hal_rx_chain_msdu_links() - Chains msdu link pointers 2657 * @msdu_link_ptr: msdu link pointer 2658 * @mpdu_desc_info: mpdu descriptor info 2659 * 2660 * Build a list of msdus using msdu link pointer. If the 2661 * number of msdus are more, chain them together 2662 * 2663 * Returns: Number of processed msdus 2664 */ 2665 static inline 2666 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 2667 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2668 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 2669 { 2670 int j; 2671 struct rx_msdu_link *msdu_link_ptr = 2672 &msdu_link_ptr_info->msdu_link; 2673 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 2674 struct rx_msdu_details *msdu_details = 2675 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 2676 uint8_t num_msdus = mpdu_desc_info->msdu_count; 2677 struct rx_msdu_desc_info *msdu_desc_info; 2678 uint8_t fragno, more_frag; 2679 uint8_t *rx_desc_info; 2680 struct hal_rx_msdu_list msdu_list; 2681 2682 for (j = 0; j < num_msdus; j++) { 2683 msdu_desc_info = 2684 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 2685 hal_soc); 2686 msdu_list.msdu_info[j].msdu_flags = 2687 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 2688 msdu_list.msdu_info[j].msdu_len = 2689 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 2690 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 2691 &msdu_details[j].buffer_addr_info_details); 2692 } 2693 2694 /* Chain msdu links together */ 2695 if (prev_msdu_link_ptr) { 2696 /* 31-0 bits of the physical address */ 2697 prev_msdu_link_ptr-> 2698 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 2699 msdu_link_ptr_info->msdu_link_buf_info.paddr & 2700 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 2701 /* 39-32 bits of the physical address */ 2702 prev_msdu_link_ptr-> 2703 next_msdu_link_desc_addr_info.buffer_addr_39_32 2704 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 2705 >> 32) & 2706 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 2707 prev_msdu_link_ptr-> 2708 next_msdu_link_desc_addr_info.sw_buffer_cookie = 2709 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 2710 } 2711 2712 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 2713 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 2714 /* mark first and last MSDUs */ 2715 rx_desc_info = qdf_nbuf_data(msdu); 2716 fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info); 2717 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 2718 2719 /* TODO: create skb->fragslist[] */ 2720 2721 if (more_frag == 0) { 2722 msdu_list.msdu_info[num_msdus].msdu_flags |= 2723 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 2724 } else if (fragno == 1) { 2725 msdu_list.msdu_info[num_msdus].msdu_flags |= 2726 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 2727 2728 msdu_list.msdu_info[num_msdus].msdu_flags |= 2729 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 2730 } 2731 2732 num_msdus++; 2733 2734 /* Number of MSDUs per mpdu descriptor is updated */ 2735 mpdu_desc_info->msdu_count += num_msdus; 2736 } else { 2737 num_msdus = 0; 2738 prev_msdu_link_ptr = msdu_link_ptr; 2739 } 2740 2741 return num_msdus; 2742 } 2743 2744 /* 2745 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 2746 * 2747 * @ring_desc: HAL view of ring descriptor 2748 * @mpdu_des_info: saved mpdu desc info 2749 * @msdu_link_ptr: saved msdu link ptr 2750 * 2751 * API used explicitly for rx defrag to update ring desc with 2752 * mpdu desc info and msdu link ptr before reinjecting the 2753 * packet back to REO 2754 * 2755 * Returns: None 2756 */ 2757 static inline 2758 void hal_rx_defrag_update_src_ring_desc( 2759 hal_ring_desc_t ring_desc, 2760 void *saved_mpdu_desc_info, 2761 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 2762 { 2763 struct reo_entrance_ring *reo_ent_ring; 2764 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 2765 struct hal_buf_info buf_info; 2766 2767 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 2768 reo_ring_mpdu_desc_info = &reo_ent_ring-> 2769 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 2770 2771 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 2772 sizeof(*reo_ring_mpdu_desc_info)); 2773 2774 /* 2775 * TODO: Check for additional fields that need configuration in 2776 * reo_ring_mpdu_desc_info 2777 */ 2778 2779 /* Update msdu_link_ptr in the reo entrance ring */ 2780 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 2781 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 2782 buf_info.sw_cookie = 2783 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 2784 } 2785 2786 /* 2787 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 2788 * 2789 * @msdu_link_desc_va: msdu link descriptor handle 2790 * @msdu_link_ptr_info: HAL view of msdu link pointer info 2791 * 2792 * API used to save msdu link information along with physical 2793 * address. The API also copues the sw cookie. 2794 * 2795 * Returns: None 2796 */ 2797 static inline 2798 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 2799 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 2800 struct hal_buf_info *hbi) 2801 { 2802 struct rx_msdu_link *msdu_link_ptr = 2803 (struct rx_msdu_link *)msdu_link_desc_va; 2804 2805 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 2806 sizeof(struct rx_msdu_link)); 2807 2808 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 2809 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 2810 } 2811 2812 /* 2813 * hal_rx_get_desc_len(): Returns rx descriptor length 2814 * 2815 * Returns the size of rx_pkt_tlvs which follows the 2816 * data in the nbuf 2817 * 2818 * Returns: Length of rx descriptor 2819 */ 2820 static inline 2821 uint16_t hal_rx_get_desc_len(void) 2822 { 2823 return sizeof(struct rx_pkt_tlvs); 2824 } 2825 2826 /* 2827 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 2828 * reo_entrance_ring descriptor 2829 * 2830 * @reo_ent_desc: reo_entrance_ring descriptor 2831 * Returns: value of rxdma_push_reason 2832 */ 2833 static inline 2834 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc) 2835 { 2836 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2837 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 2838 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 2839 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 2840 } 2841 2842 /** 2843 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 2844 * reo_entrance_ring descriptor 2845 * @reo_ent_desc: reo_entrance_ring descriptor 2846 * Return: value of rxdma_error_code 2847 */ 2848 static inline 2849 uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc) 2850 { 2851 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 2852 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 2853 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 2854 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 2855 } 2856 2857 /** 2858 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 2859 * save it to hal_wbm_err_desc_info structure passed by caller 2860 * @wbm_desc: wbm ring descriptor 2861 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2862 * Return: void 2863 */ 2864 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 2865 struct hal_wbm_err_desc_info *wbm_er_info, 2866 hal_soc_handle_t hal_soc_hdl) 2867 { 2868 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2869 2870 hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info); 2871 } 2872 2873 /** 2874 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 2875 * the reserved bytes of rx_tlv_hdr 2876 * @buf: start of rx_tlv_hdr 2877 * @wbm_er_info: hal_wbm_err_desc_info structure 2878 * Return: void 2879 */ 2880 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 2881 struct hal_wbm_err_desc_info *wbm_er_info) 2882 { 2883 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2884 2885 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 2886 sizeof(struct hal_wbm_err_desc_info)); 2887 } 2888 2889 /** 2890 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 2891 * the reserved bytes of rx_tlv_hdr. 2892 * @buf: start of rx_tlv_hdr 2893 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 2894 * Return: void 2895 */ 2896 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 2897 struct hal_wbm_err_desc_info *wbm_er_info) 2898 { 2899 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2900 2901 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 2902 sizeof(struct hal_wbm_err_desc_info)); 2903 } 2904 2905 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 2906 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 2907 RX_MSDU_START_5_NSS_OFFSET)), \ 2908 RX_MSDU_START_5_NSS_MASK, \ 2909 RX_MSDU_START_5_NSS_LSB)) 2910 2911 /** 2912 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 2913 * 2914 * @ hal_soc: HAL version of the SOC pointer 2915 * @ hw_desc_addr: Start address of Rx HW TLVs 2916 * @ rs: Status for monitor mode 2917 * 2918 * Return: void 2919 */ 2920 static inline 2921 void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl, 2922 void *hw_desc_addr, 2923 struct mon_rx_status *rs) 2924 { 2925 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2926 2927 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 2928 } 2929 2930 /* 2931 * hal_rx_get_tlv(): API to get the tlv 2932 * 2933 * @hal_soc: HAL version of the SOC pointer 2934 * @rx_tlv: TLV data extracted from the rx packet 2935 * Return: uint8_t 2936 */ 2937 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 2938 { 2939 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 2940 } 2941 2942 /* 2943 * hal_rx_msdu_start_nss_get(): API to get the NSS 2944 * Interval from rx_msdu_start 2945 * 2946 * @hal_soc: HAL version of the SOC pointer 2947 * @buf: pointer to the start of RX PKT TLV header 2948 * Return: uint32_t(nss) 2949 */ 2950 static inline 2951 uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 2952 { 2953 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2954 2955 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 2956 } 2957 2958 /** 2959 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 2960 * human readable format. 2961 * @ msdu_start: pointer the msdu_start TLV in pkt. 2962 * @ dbg_level: log level. 2963 * 2964 * Return: void 2965 */ 2966 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 2967 struct rx_msdu_start *msdu_start, 2968 uint8_t dbg_level) 2969 { 2970 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 2971 } 2972 2973 /** 2974 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 2975 * info details 2976 * 2977 * @ buf - Pointer to buffer containing rx pkt tlvs. 2978 * 2979 * 2980 */ 2981 static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl, 2982 uint8_t *buf) 2983 { 2984 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 2985 2986 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 2987 } 2988 2989 /* 2990 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 2991 * Interval from rx_msdu_start 2992 * 2993 * @buf: pointer to the start of RX PKT TLV header 2994 * Return: uint32_t(reception_type) 2995 */ 2996 static inline 2997 uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl, 2998 uint8_t *buf) 2999 { 3000 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3001 3002 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3003 } 3004 3005 /** 3006 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3007 * RX TLVs 3008 * @ buf: pointer the pkt buffer. 3009 * @ dbg_level: log level. 3010 * 3011 * Return: void 3012 */ 3013 static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl, 3014 uint8_t *buf, uint8_t dbg_level) 3015 { 3016 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3017 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3018 struct rx_mpdu_start *mpdu_start = 3019 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3020 struct rx_msdu_start *msdu_start = 3021 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3022 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3023 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3024 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3025 3026 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3027 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 3028 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3029 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3030 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3031 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 3032 } 3033 3034 3035 /** 3036 * hal_reo_status_get_header_generic - Process reo desc info 3037 * @d - Pointer to reo descriptior 3038 * @b - tlv type info 3039 * @h - Pointer to hal_reo_status_header where info to be stored 3040 * @hal- pointer to hal_soc structure 3041 * Return - none. 3042 * 3043 */ 3044 static inline 3045 void hal_reo_status_get_header(uint32_t *d, int b, 3046 void *h, struct hal_soc *hal_soc) 3047 { 3048 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3049 } 3050 3051 /** 3052 * hal_rx_desc_is_first_msdu() - Check if first msdu 3053 * 3054 * @hal_soc_hdl: hal_soc handle 3055 * @hw_desc_addr: hardware descriptor address 3056 * 3057 * Return: 0 - success/ non-zero failure 3058 */ 3059 static inline 3060 uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl, 3061 void *hw_desc_addr) 3062 { 3063 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3064 3065 return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr); 3066 } 3067 3068 static inline 3069 uint32_t 3070 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 3071 struct rx_msdu_start *rx_msdu_start; 3072 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3073 3074 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 3075 3076 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 3077 } 3078 3079 #ifdef NO_RX_PKT_HDR_TLV 3080 static inline 3081 uint8_t * 3082 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3083 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 3084 "[%s][%d] decap format not raw", __func__, __LINE__); 3085 QDF_ASSERT(0); 3086 return 0; 3087 } 3088 #else 3089 static inline 3090 uint8_t * 3091 HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) { 3092 uint8_t *rx_pkt_hdr; 3093 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 3094 3095 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 3096 3097 return rx_pkt_hdr; 3098 } 3099 #endif 3100 3101 #ifdef NO_RX_PKT_HDR_TLV 3102 static inline 3103 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3104 uint8_t *rx_tlv_hdr) 3105 { 3106 uint8_t decap_format; 3107 3108 if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) { 3109 decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr); 3110 if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW) 3111 return true; 3112 } 3113 3114 return false; 3115 } 3116 #else 3117 static inline 3118 bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl, 3119 uint8_t *rx_tlv_hdr) 3120 { 3121 return true; 3122 } 3123 #endif 3124 3125 /** 3126 * hal_rx_msdu_fse_metadata_get: API to get FSE metadata 3127 * from rx_msdu_end TLV 3128 * @buf: pointer to the start of RX PKT TLV headers 3129 * 3130 * Return: fse metadata value from MSDU END TLV 3131 */ 3132 static inline uint32_t 3133 hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl, 3134 uint8_t *buf) 3135 { 3136 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3137 3138 return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf); 3139 } 3140 3141 /** 3142 * hal_rx_msdu_flow_idx_get: API to get flow index 3143 * from rx_msdu_end TLV 3144 * @buf: pointer to the start of RX PKT TLV headers 3145 * 3146 * Return: flow index value from MSDU END TLV 3147 */ 3148 static inline uint32_t 3149 hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl, 3150 uint8_t *buf) 3151 { 3152 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3153 3154 return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf); 3155 } 3156 3157 /** 3158 * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout 3159 * from rx_msdu_end TLV 3160 * @buf: pointer to the start of RX PKT TLV headers 3161 * 3162 * Return: flow index timeout value from MSDU END TLV 3163 */ 3164 static inline bool 3165 hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl, 3166 uint8_t *buf) 3167 { 3168 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3169 3170 return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf); 3171 } 3172 3173 /** 3174 * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid 3175 * from rx_msdu_end TLV 3176 * @buf: pointer to the start of RX PKT TLV headers 3177 * 3178 * Return: flow index invalid value from MSDU END TLV 3179 */ 3180 static inline bool 3181 hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl, 3182 uint8_t *buf) 3183 { 3184 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3185 3186 return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf); 3187 } 3188 3189 /** 3190 * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id 3191 * @hal_soc_hdl: hal_soc handle 3192 * @hw_desc_addr: hardware descriptor address 3193 * 3194 * Return: 0 - success/ non-zero failure 3195 */ 3196 static inline 3197 uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl, 3198 void *hw_desc_addr) 3199 { 3200 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3201 3202 return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(hw_desc_addr); 3203 } 3204 3205 /** 3206 * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id 3207 * @hal_soc_hdl: hal_soc handle 3208 * @buf: rx tlv address 3209 * 3210 * Return: sw peer id 3211 */ 3212 static inline 3213 uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl, 3214 uint8_t *buf) 3215 { 3216 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3217 3218 if ((!hal_soc) || (!hal_soc->ops)) { 3219 hal_err("hal handle is NULL"); 3220 QDF_BUG(0); 3221 return QDF_STATUS_E_INVAL; 3222 } 3223 3224 if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get) 3225 return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf); 3226 3227 return QDF_STATUS_E_INVAL; 3228 } 3229 3230 static inline 3231 void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl, 3232 void *link_desc_addr) 3233 { 3234 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3235 3236 return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr); 3237 } 3238 3239 static inline 3240 void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl, 3241 void *msdu_addr) 3242 { 3243 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3244 3245 return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr); 3246 } 3247 3248 static inline 3249 void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3250 void *hw_addr) 3251 { 3252 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3253 3254 return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr); 3255 } 3256 3257 static inline 3258 void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl, 3259 void *hw_addr) 3260 { 3261 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3262 3263 return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr); 3264 } 3265 3266 static inline 3267 uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl, 3268 uint8_t *buf) 3269 { 3270 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3271 3272 return hal_soc->ops->hal_rx_get_fc_valid(buf); 3273 } 3274 3275 static inline 3276 uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 3277 { 3278 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3279 3280 return hal_soc->ops->hal_rx_get_to_ds_flag(buf); 3281 } 3282 3283 static inline 3284 uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl, 3285 uint8_t *buf) 3286 { 3287 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3288 3289 return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf); 3290 } 3291 3292 static inline 3293 uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl, 3294 uint8_t *buf) 3295 { 3296 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3297 3298 return hal_soc->ops->hal_rx_get_filter_category(buf); 3299 } 3300 3301 static inline 3302 uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl, 3303 uint8_t *buf) 3304 { 3305 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3306 3307 return hal_soc->ops->hal_rx_get_ppdu_id(buf); 3308 } 3309 3310 /** 3311 * hal_reo_config(): Set reo config parameters 3312 * @soc: hal soc handle 3313 * @reg_val: value to be set 3314 * @reo_params: reo parameters 3315 * 3316 * Return: void 3317 */ 3318 static inline 3319 void hal_reo_config(struct hal_soc *hal_soc, 3320 uint32_t reg_val, 3321 struct hal_reo_params *reo_params) 3322 { 3323 hal_soc->ops->hal_reo_config(hal_soc, 3324 reg_val, 3325 reo_params); 3326 } 3327 3328 /** 3329 * hal_rx_msdu_get_flow_params: API to get flow index, 3330 * flow index invalid and flow index timeout from rx_msdu_end TLV 3331 * @buf: pointer to the start of RX PKT TLV headers 3332 * @flow_invalid: pointer to return value of flow_idx_valid 3333 * @flow_timeout: pointer to return value of flow_idx_timeout 3334 * @flow_index: pointer to return value of flow_idx 3335 * 3336 * Return: none 3337 */ 3338 static inline void 3339 hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl, 3340 uint8_t *buf, 3341 bool *flow_invalid, 3342 bool *flow_timeout, 3343 uint32_t *flow_index) 3344 { 3345 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3346 3347 if ((!hal_soc) || (!hal_soc->ops)) { 3348 hal_err("hal handle is NULL"); 3349 QDF_BUG(0); 3350 return; 3351 } 3352 3353 if (hal_soc->ops->hal_rx_msdu_get_flow_params) 3354 hal_soc->ops-> 3355 hal_rx_msdu_get_flow_params(buf, 3356 flow_invalid, 3357 flow_timeout, 3358 flow_index); 3359 } 3360 3361 static inline 3362 uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl, 3363 uint8_t *buf) 3364 { 3365 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3366 3367 return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); 3368 } 3369 3370 static inline 3371 uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl, 3372 uint8_t *buf) 3373 { 3374 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3375 3376 return hal_soc->ops->hal_rx_get_rx_sequence(buf); 3377 } 3378 #endif /* _HAL_RX_H */ 3379