1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_RX_H_ 20 #define _HAL_RX_H_ 21 22 #include <hal_internal.h> 23 24 /** 25 * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons 26 * 27 * @reo_psh_rsn: REO push reason 28 * @reo_err_code: REO Error code 29 * @rxdma_psh_rsn: RXDMA push reason 30 * @rxdma_err_code: RXDMA Error code 31 * @reserved_1: Reserved bits 32 * @wbm_err_src: WBM error source 33 * @pool_id: pool ID, indicates which rxdma pool 34 * @reserved_2: Reserved bits 35 */ 36 struct hal_wbm_err_desc_info { 37 uint16_t reo_psh_rsn:2, 38 reo_err_code:5, 39 rxdma_psh_rsn:2, 40 rxdma_err_code:5, 41 reserved_1:2; 42 uint8_t wbm_err_src:3, 43 pool_id:2, 44 reserved_2:3; 45 }; 46 47 /** 48 * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason" 49 * 50 * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected 51 * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing 52 */ 53 enum hal_reo_error_status { 54 HAL_REO_ERROR_DETECTED = 0, 55 HAL_REO_ROUTING_INSTRUCTION = 1, 56 }; 57 58 /** 59 * @msdu_flags: [0] first_msdu_in_mpdu 60 * [1] last_msdu_in_mpdu 61 * [2] msdu_continuation - MSDU spread across buffers 62 * [23] sa_is_valid - SA match in peer table 63 * [24] sa_idx_timeout - Timeout while searching for SA match 64 * [25] da_is_valid - Used to identtify intra-bss forwarding 65 * [26] da_is_MCBC 66 * [27] da_idx_timeout - Timeout while searching for DA match 67 * 68 */ 69 struct hal_rx_msdu_desc_info { 70 uint32_t msdu_flags; 71 uint16_t msdu_len; /* 14 bits for length */ 72 }; 73 74 /** 75 * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO 76 * 77 * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU 78 * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU 79 * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation 80 * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST 81 * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out 82 * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST 83 * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address 84 * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out 85 */ 86 enum hal_rx_msdu_desc_flags { 87 HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0), 88 HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1), 89 HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2), 90 HAL_MSDU_F_SA_IS_VALID = (0x1 << 23), 91 HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24), 92 HAL_MSDU_F_DA_IS_VALID = (0x1 << 25), 93 HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26), 94 HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27) 95 }; 96 97 /* 98 * @msdu_count: no. of msdus in the MPDU 99 * @mpdu_seq: MPDU sequence number 100 * @mpdu_flags [0] Fragment flag 101 * [1] MPDU_retry_bit 102 * [2] AMPDU flag 103 * [3] raw_ampdu 104 * @peer_meta_data: Upper bits containing peer id, vdev id 105 */ 106 struct hal_rx_mpdu_desc_info { 107 uint16_t msdu_count; 108 uint16_t mpdu_seq; /* 12 bits for length */ 109 uint32_t mpdu_flags; 110 uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */ 111 }; 112 113 /** 114 * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO 115 * 116 * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation) 117 * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU 118 * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU 119 * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU 120 */ 121 enum hal_rx_mpdu_desc_flags { 122 HAL_MPDU_F_FRAGMENT = (0x1 << 20), 123 HAL_MPDU_F_RETRY_BIT = (0x1 << 21), 124 HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22), 125 HAL_MPDU_F_RAW_AMPDU = (0x1 << 30) 126 }; 127 128 /** 129 * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in 130 * BUFFER_ADDR_INFO structure 131 * 132 * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 133 * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 134 * descriptor list 135 * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 136 * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 137 * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 138 * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 139 * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 140 */ 141 enum hal_rx_ret_buf_manager { 142 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0, 143 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1, 144 HAL_RX_BUF_RBM_FW_BM = 2, 145 HAL_RX_BUF_RBM_SW0_BM = 3, 146 HAL_RX_BUF_RBM_SW1_BM = 4, 147 HAL_RX_BUF_RBM_SW2_BM = 5, 148 HAL_RX_BUF_RBM_SW3_BM = 6, 149 }; 150 151 /* 152 * Given the offset of a field in bytes, returns uint8_t * 153 */ 154 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 155 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 156 157 /* 158 * Given the offset of a field in bytes, returns uint32_t * 159 */ 160 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 161 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 162 163 #define _HAL_MS(_word, _mask, _shift) \ 164 (((_word) & (_mask)) >> (_shift)) 165 166 /* 167 * macro to set the LSW of the nbuf data physical address 168 * to the rxdma ring entry 169 */ 170 #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 171 ((*(((unsigned int *) buff_addr_info) + \ 172 (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 173 (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 174 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 175 176 /* 177 * macro to set the LSB of MSW of the nbuf data physical address 178 * to the rxdma ring entry 179 */ 180 #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 181 ((*(((unsigned int *) buff_addr_info) + \ 182 (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 183 (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 184 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 185 186 /* 187 * macro to set the cookie into the rxdma ring entry 188 */ 189 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 190 ((*(((unsigned int *) buff_addr_info) + \ 191 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 192 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 193 ((*(((unsigned int *) buff_addr_info) + \ 194 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 195 (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 196 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 197 198 /* 199 * macro to set the manager into the rxdma ring entry 200 */ 201 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 202 ((*(((unsigned int *) buff_addr_info) + \ 203 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 204 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 205 ((*(((unsigned int *) buff_addr_info) + \ 206 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 207 (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 208 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 209 210 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 212 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 213 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 214 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 215 216 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 218 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 219 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 220 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 221 222 #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 224 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \ 225 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \ 226 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB)) 227 228 #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 230 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \ 231 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \ 232 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB)) 233 234 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 235 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 236 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 237 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 238 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 239 240 /* TODO: Convert the following structure fields accesseses to offsets */ 241 242 #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \ 243 (HAL_RX_BUFFER_ADDR_39_32_GET(& \ 244 (((struct reo_destination_ring *) \ 245 reo_desc)->buf_or_link_desc_addr_info))) 246 247 #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \ 248 (HAL_RX_BUFFER_ADDR_31_0_GET(& \ 249 (((struct reo_destination_ring *) \ 250 reo_desc)->buf_or_link_desc_addr_info))) 251 252 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 253 (HAL_RX_BUF_COOKIE_GET(& \ 254 (((struct reo_destination_ring *) \ 255 reo_desc)->buf_or_link_desc_addr_info))) 256 257 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 258 ((mpdu_info_ptr \ 259 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 260 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 261 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 262 263 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 264 ((mpdu_info_ptr \ 265 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 266 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 267 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 268 269 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 270 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 271 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 272 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 273 274 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 275 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 276 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 277 278 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 279 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 280 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 281 282 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 283 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 284 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 285 286 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 287 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 288 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 289 290 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 291 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 292 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 293 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 294 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 295 296 297 #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \ 298 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 299 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \ 300 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \ 301 RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB)) 302 303 /* 304 * NOTE: None of the following _GET macros need a right 305 * shift by the corresponding _LSB. This is because, they are 306 * finally taken and "OR'ed" into a single word again. 307 */ 308 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 309 ((*(((uint32_t *)msdu_info_ptr) + \ 310 (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 311 (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \ 312 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 313 314 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \ 315 ((*(((uint32_t *)msdu_info_ptr) + \ 316 (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \ 317 (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \ 318 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 319 320 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 321 ((*(((uint32_t *)msdu_info_ptr) + \ 322 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 323 (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 324 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 325 326 327 #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 328 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 329 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 330 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK) 331 332 #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \ 333 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 334 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \ 335 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK) 336 337 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 338 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 339 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 340 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 341 342 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 343 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 344 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 345 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 346 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 347 348 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 349 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 350 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 351 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 352 353 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 354 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 355 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 356 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 357 358 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 359 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 360 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 361 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 362 363 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 364 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 365 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 366 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 367 368 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 369 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 370 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 371 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 372 373 374 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 375 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 376 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 377 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 378 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 379 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 380 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 381 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 382 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 383 384 385 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 386 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 387 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 388 RX_MPDU_INFO_4_PN_31_0_MASK, \ 389 RX_MPDU_INFO_4_PN_31_0_LSB)) 390 391 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 392 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 393 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 394 RX_MPDU_INFO_5_PN_63_32_MASK, \ 395 RX_MPDU_INFO_5_PN_63_32_LSB)) 396 397 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 398 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 399 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 400 RX_MPDU_INFO_6_PN_95_64_MASK, \ 401 RX_MPDU_INFO_6_PN_95_64_LSB)) 402 403 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 404 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 405 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 406 RX_MPDU_INFO_7_PN_127_96_MASK, \ 407 RX_MPDU_INFO_7_PN_127_96_LSB)) 408 409 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 410 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 411 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 412 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 413 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 414 415 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 416 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 417 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 418 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 419 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 420 421 #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \ 422 (*(uint32_t *)(((uint8_t *)_ptr) + \ 423 _wrd ## _ ## _field ## _OFFSET) |= \ 424 ((_val << _wrd ## _ ## _field ## _LSB) & \ 425 _wrd ## _ ## _field ## _MASK)) 426 427 #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \ 428 HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \ 429 _field, _val) 430 431 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 432 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 433 _field, _val) 434 435 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 436 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 437 _field, _val) 438 439 static inline void hal_rx_mpdu_desc_info_get(void *desc_addr, 440 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 441 { 442 struct reo_destination_ring *reo_dst_ring; 443 uint32_t mpdu_info[NUM_OF_DWORDS_RX_MPDU_DESC_INFO]; 444 445 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 446 447 qdf_mem_copy(&mpdu_info, 448 (const void *)&reo_dst_ring->rx_mpdu_desc_info_details, 449 sizeof(struct rx_mpdu_desc_info)); 450 451 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 452 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 453 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 454 mpdu_desc_info->peer_meta_data = 455 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 456 } 457 458 /* 459 * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor. 460 * @ Specifically flags needed are: 461 * @ first_msdu_in_mpdu, last_msdu_in_mpdu, 462 * @ msdu_continuation, sa_is_valid, 463 * @ sa_idx_timeout, da_is_valid, da_idx_timeout, 464 * @ da_is_MCBC 465 * 466 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current 467 * @ descriptor 468 * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 469 * @ Return: void 470 */ 471 static inline void hal_rx_msdu_desc_info_get(void *desc_addr, 472 struct hal_rx_msdu_desc_info *msdu_desc_info) 473 { 474 struct reo_destination_ring *reo_dst_ring; 475 uint32_t msdu_info[NUM_OF_DWORDS_RX_MSDU_DESC_INFO]; 476 477 reo_dst_ring = (struct reo_destination_ring *) desc_addr; 478 479 qdf_mem_copy(&msdu_info, 480 (const void *)&reo_dst_ring->rx_msdu_desc_info_details, 481 sizeof(struct rx_msdu_desc_info)); 482 483 msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info); 484 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 485 } 486 487 /* 488 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 489 * rxdma ring entry. 490 * @rxdma_entry: descriptor entry 491 * @paddr: physical address of nbuf data pointer. 492 * @cookie: SW cookie used as a index to SW rx desc. 493 * @manager: who owns the nbuf (host, NSS, etc...). 494 * 495 */ 496 static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry, 497 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 498 { 499 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 500 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 501 502 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 503 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 504 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 505 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 506 } 507 508 /* 509 * Structures & Macros to obtain fields from the TLV's in the Rx packet 510 * pre-header. 511 */ 512 513 /* 514 * Every Rx packet starts at an offset from the top of the buffer. 515 * If the host hasn't subscribed to any specific TLV, there is 516 * still space reserved for the following TLV's from the start of 517 * the buffer: 518 * -- RX ATTENTION 519 * -- RX MPDU START 520 * -- RX MSDU START 521 * -- RX MSDU END 522 * -- RX MPDU END 523 * -- RX PACKET HEADER (802.11) 524 * If the host subscribes to any of the TLV's above, that TLV 525 * if populated by the HW 526 */ 527 528 #define NUM_DWORDS_TAG 1 529 530 /* By default the packet header TLV is 128 bytes */ 531 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 532 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 533 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 534 535 #define RX_PKT_OFFSET_WORDS \ 536 ( \ 537 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 538 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 539 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 540 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 541 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 542 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 543 ) 544 545 #define RX_PKT_OFFSET_BYTES \ 546 (RX_PKT_OFFSET_WORDS << 2) 547 548 #define RX_PKT_HDR_TLV_LEN 120 549 550 /* 551 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 552 */ 553 struct rx_attention_tlv { 554 uint32_t tag; 555 struct rx_attention rx_attn; 556 }; 557 558 struct rx_mpdu_start_tlv { 559 uint32_t tag; 560 struct rx_mpdu_start rx_mpdu_start; 561 }; 562 563 struct rx_msdu_start_tlv { 564 uint32_t tag; 565 struct rx_msdu_start rx_msdu_start; 566 }; 567 568 struct rx_msdu_end_tlv { 569 uint32_t tag; 570 struct rx_msdu_end rx_msdu_end; 571 }; 572 573 struct rx_mpdu_end_tlv { 574 uint32_t tag; 575 struct rx_mpdu_end rx_mpdu_end; 576 }; 577 578 struct rx_pkt_hdr_tlv { 579 uint32_t tag; /* 4 B */ 580 uint32_t phy_ppdu_id; /* 4 B */ 581 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 582 }; 583 584 585 #define RXDMA_OPTIMIZATION 586 587 #ifdef RXDMA_OPTIMIZATION 588 /* 589 * The RX_PADDING_BYTES is required so that the TLV's don't 590 * spread across the 128 byte boundary 591 * RXDMA optimization requires: 592 * 1) MSDU_END & ATTENTION TLV's follow in that order 593 * 2) TLV's don't span across 128 byte lines 594 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 595 */ 596 #if defined(WCSS_VERSION) && \ 597 ((defined(CONFIG_WIN) && (WCSS_VERSION >= 96)) || \ 598 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 599 #define RX_PADDING0_BYTES 4 600 #endif 601 #define RX_PADDING1_BYTES 16 602 struct rx_pkt_tlvs { 603 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 604 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 605 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 606 #if defined(WCSS_VERSION) && \ 607 ((defined(CONFIG_WIN) && (WCSS_VERSION >= 96)) || \ 608 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 609 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 610 #endif 611 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 612 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 613 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 614 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 615 }; 616 #else /* RXDMA_OPTIMIZATION */ 617 struct rx_pkt_tlvs { 618 struct rx_attention_tlv attn_tlv; 619 struct rx_mpdu_start_tlv mpdu_start_tlv; 620 struct rx_msdu_start_tlv msdu_start_tlv; 621 struct rx_msdu_end_tlv msdu_end_tlv; 622 struct rx_mpdu_end_tlv mpdu_end_tlv; 623 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 624 }; 625 #endif /* RXDMA_OPTIMIZATION */ 626 627 #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs)) 628 629 static inline uint8_t 630 *hal_rx_pkt_hdr_get(uint8_t *buf) 631 { 632 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 633 634 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 635 636 } 637 638 static inline uint8_t 639 *hal_rx_padding0_get(uint8_t *buf) 640 { 641 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 642 643 return pkt_tlvs->rx_padding0; 644 } 645 646 /* 647 * @ hal_rx_encryption_info_valid: Returns encryption type. 648 * 649 * @ buf: rx_tlv_hdr of the received packet 650 * @ Return: encryption type 651 */ 652 static inline uint32_t 653 hal_rx_encryption_info_valid(uint8_t *buf) 654 { 655 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 656 struct rx_mpdu_start *mpdu_start = 657 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 658 struct rx_mpdu_info *mpdu_info = &(mpdu_start->rx_mpdu_info_details); 659 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 660 661 return encryption_info; 662 } 663 664 /* 665 * @ hal_rx_print_pn: Prints the PN of rx packet. 666 * 667 * @ buf: rx_tlv_hdr of the received packet 668 * @ Return: void 669 */ 670 static inline void 671 hal_rx_print_pn(uint8_t *buf) 672 { 673 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 674 struct rx_mpdu_start *mpdu_start = 675 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 676 struct rx_mpdu_info *mpdu_info = &(mpdu_start->rx_mpdu_info_details); 677 678 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 679 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 680 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 681 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 682 683 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 684 "PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 685 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 686 } 687 688 /* 689 * Get msdu_done bit from the RX_ATTENTION TLV 690 */ 691 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 692 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 693 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 694 RX_ATTENTION_2_MSDU_DONE_MASK, \ 695 RX_ATTENTION_2_MSDU_DONE_LSB)) 696 697 static inline uint32_t 698 hal_rx_attn_msdu_done_get(uint8_t *buf) 699 { 700 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 701 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 702 uint32_t msdu_done; 703 704 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 705 706 return msdu_done; 707 } 708 709 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 710 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 711 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 712 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 713 RX_ATTENTION_1_FIRST_MPDU_LSB)) 714 715 /* 716 * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention 717 * @buf: pointer to rx_pkt_tlvs 718 * 719 * reutm: uint32_t(first_msdu) 720 */ 721 static inline uint32_t 722 hal_rx_attn_first_mpdu_get(uint8_t *buf) 723 { 724 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 725 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 726 uint32_t first_mpdu; 727 728 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 729 730 return first_mpdu; 731 } 732 733 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 734 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 735 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 736 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 737 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 738 739 /* 740 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 741 * from rx attention 742 * @buf: pointer to rx_pkt_tlvs 743 * 744 * Return: tcp_udp_cksum_fail 745 */ 746 static inline bool 747 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 748 { 749 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 750 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 751 bool tcp_udp_cksum_fail; 752 753 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 754 755 return tcp_udp_cksum_fail; 756 } 757 758 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 759 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 760 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 761 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 762 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 763 764 /* 765 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 766 * from rx attention 767 * @buf: pointer to rx_pkt_tlvs 768 * 769 * Return: ip_cksum_fail 770 */ 771 static inline bool 772 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 773 { 774 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 775 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 776 bool ip_cksum_fail; 777 778 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 779 780 return ip_cksum_fail; 781 } 782 783 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 784 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 785 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 786 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 787 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 788 789 /* 790 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 791 * from rx attention 792 * @buf: pointer to rx_pkt_tlvs 793 * 794 * Return: phy_ppdu_id 795 */ 796 static inline uint16_t 797 hal_rx_attn_phy_ppdu_id_get(uint8_t *buf) 798 { 799 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 800 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 801 uint16_t phy_ppdu_id; 802 803 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 804 805 return phy_ppdu_id; 806 } 807 808 /* 809 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 810 */ 811 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 812 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 813 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 814 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 815 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 816 817 static inline uint32_t 818 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 819 { 820 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 821 struct rx_mpdu_start *mpdu_start = 822 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 823 824 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 825 uint32_t peer_meta_data; 826 827 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 828 829 return peer_meta_data; 830 } 831 832 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 833 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 834 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 835 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 836 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 837 /** 838 * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit 839 * from rx mpdu info 840 * @buf: pointer to rx_pkt_tlvs 841 * 842 * Return: ampdu flag 843 */ 844 static inline bool 845 hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf) 846 { 847 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 848 struct rx_mpdu_start *mpdu_start = 849 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 850 851 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 852 bool ampdu_flag; 853 854 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 855 856 return ampdu_flag; 857 } 858 859 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 860 ((*(((uint32_t *)_rx_mpdu_info) + \ 861 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 862 (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 863 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 864 865 /* 866 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 867 * 868 * @ buf: rx_tlv_hdr of the received packet 869 * @ peer_mdata: peer meta data to be set. 870 * @ Return: void 871 */ 872 static inline void 873 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 874 { 875 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 876 struct rx_mpdu_start *mpdu_start = 877 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 878 879 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 880 881 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 882 } 883 884 #if defined(WCSS_VERSION) && \ 885 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 886 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 887 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 888 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 889 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 890 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 891 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 892 #else 893 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 894 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 895 RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET)), \ 896 RX_MSDU_END_9_L3_HEADER_PADDING_MASK, \ 897 RX_MSDU_END_9_L3_HEADER_PADDING_LSB)) 898 #endif 899 900 /** 901 * LRO information needed from the TLVs 902 */ 903 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 904 (_HAL_MS( \ 905 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 906 msdu_end_tlv.rx_msdu_end), \ 907 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 908 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 909 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 910 911 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 912 (_HAL_MS( \ 913 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 914 msdu_end_tlv.rx_msdu_end), \ 915 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 916 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 917 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 918 919 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 920 (_HAL_MS( \ 921 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 922 msdu_end_tlv.rx_msdu_end), \ 923 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 924 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 925 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 926 927 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 928 (_HAL_MS( \ 929 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 930 msdu_end_tlv.rx_msdu_end), \ 931 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 932 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 933 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 934 935 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 936 (_HAL_MS( \ 937 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 938 msdu_end_tlv.rx_msdu_end), \ 939 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 940 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 941 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 942 943 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 944 (_HAL_MS( \ 945 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 946 msdu_start_tlv.rx_msdu_start), \ 947 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 948 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 949 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 950 951 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 952 (_HAL_MS( \ 953 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 954 msdu_start_tlv.rx_msdu_start), \ 955 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 956 RX_MSDU_START_2_TCP_PROTO_MASK, \ 957 RX_MSDU_START_2_TCP_PROTO_LSB)) 958 959 #define HAL_RX_TLV_GET_IPV6(buf) \ 960 (_HAL_MS( \ 961 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 962 msdu_start_tlv.rx_msdu_start), \ 963 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 964 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 965 RX_MSDU_START_2_IPV6_PROTO_LSB)) 966 967 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 968 (_HAL_MS( \ 969 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 970 msdu_start_tlv.rx_msdu_start), \ 971 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 972 RX_MSDU_START_1_L3_OFFSET_MASK, \ 973 RX_MSDU_START_1_L3_OFFSET_LSB)) 974 975 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 976 (_HAL_MS( \ 977 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 978 msdu_start_tlv.rx_msdu_start), \ 979 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 980 RX_MSDU_START_1_L4_OFFSET_MASK, \ 981 RX_MSDU_START_1_L4_OFFSET_LSB)) 982 983 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 984 (_HAL_MS( \ 985 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 986 msdu_start_tlv.rx_msdu_start), \ 987 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 988 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 989 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 990 991 /** 992 * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the 993 * l3_header padding from rx_msdu_end TLV 994 * 995 * @ buf: pointer to the start of RX PKT TLV headers 996 * Return: number of l3 header padding bytes 997 */ 998 static inline uint32_t 999 hal_rx_msdu_end_l3_hdr_padding_get(uint8_t *buf) 1000 { 1001 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1002 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1003 uint32_t l3_header_padding; 1004 1005 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1006 1007 return l3_header_padding; 1008 } 1009 1010 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 1011 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1012 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 1013 RX_MSDU_END_13_SA_IDX_MASK, \ 1014 RX_MSDU_END_13_SA_IDX_LSB)) 1015 1016 /** 1017 * hal_rx_msdu_end_sa_idx_get(): API to get the 1018 * sa_idx from rx_msdu_end TLV 1019 * 1020 * @ buf: pointer to the start of RX PKT TLV headers 1021 * Return: sa_idx (SA AST index) 1022 */ 1023 static inline uint16_t 1024 hal_rx_msdu_end_sa_idx_get(uint8_t *buf) 1025 { 1026 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1027 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1028 uint16_t sa_idx; 1029 1030 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1031 1032 return sa_idx; 1033 } 1034 1035 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 1036 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1037 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 1038 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 1039 RX_MSDU_END_5_SA_IS_VALID_LSB)) 1040 1041 /** 1042 * hal_rx_msdu_end_sa_is_valid_get(): API to get the 1043 * sa_is_valid bit from rx_msdu_end TLV 1044 * 1045 * @ buf: pointer to the start of RX PKT TLV headers 1046 * Return: sa_is_valid bit 1047 */ 1048 static inline uint8_t 1049 hal_rx_msdu_end_sa_is_valid_get(uint8_t *buf) 1050 { 1051 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1052 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1053 uint8_t sa_is_valid; 1054 1055 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 1056 1057 return sa_is_valid; 1058 } 1059 1060 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 1061 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1062 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 1063 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 1064 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 1065 1066 /** 1067 * hal_rx_msdu_end_sa_sw_peer_id_get(): API to get the 1068 * sa_sw_peer_id from rx_msdu_end TLV 1069 * 1070 * @ buf: pointer to the start of RX PKT TLV headers 1071 * Return: sa_sw_peer_id index 1072 */ 1073 static inline uint32_t 1074 hal_rx_msdu_end_sa_sw_peer_id_get(uint8_t *buf) 1075 { 1076 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1077 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1078 uint32_t sa_sw_peer_id; 1079 1080 sa_sw_peer_id = HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1081 1082 return sa_sw_peer_id; 1083 } 1084 1085 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 1086 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1087 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 1088 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 1089 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 1090 1091 /** 1092 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 1093 * from rx_msdu_start TLV 1094 * 1095 * @ buf: pointer to the start of RX PKT TLV headers 1096 * Return: msdu length 1097 */ 1098 static inline uint32_t 1099 hal_rx_msdu_start_msdu_len_get(uint8_t *buf) 1100 { 1101 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1102 struct rx_msdu_start *msdu_start = 1103 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1104 uint32_t msdu_len; 1105 1106 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1107 1108 return msdu_len; 1109 } 1110 1111 /** 1112 * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length 1113 * from rx_msdu_start TLV 1114 * 1115 * @buf: pointer to the start of RX PKT TLV headers 1116 * @len: msdu length 1117 * 1118 * Return: none 1119 */ 1120 static inline void 1121 hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len) 1122 { 1123 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1124 struct rx_msdu_start *msdu_start = 1125 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1126 void *wrd1; 1127 1128 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 1129 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 1130 *(uint32_t *)wrd1 |= len; 1131 } 1132 1133 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 1134 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1135 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 1136 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 1137 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 1138 1139 /* 1140 * hal_rx_msdu_start_bw_get(): API to get the Bandwidth 1141 * Interval from rx_msdu_start 1142 * 1143 * @buf: pointer to the start of RX PKT TLV header 1144 * Return: uint32_t(bw) 1145 */ 1146 static inline uint32_t 1147 hal_rx_msdu_start_bw_get(uint8_t *buf) 1148 { 1149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1150 struct rx_msdu_start *msdu_start = 1151 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1152 uint32_t bw; 1153 1154 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 1155 1156 return bw; 1157 } 1158 1159 1160 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 1161 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1162 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 1163 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 1164 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 1165 1166 /** 1167 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 1168 * from rx_msdu_start TLV 1169 * 1170 * @ buf: pointer to the start of RX PKT TLV headers 1171 * Return: toeplitz hash 1172 */ 1173 static inline uint32_t 1174 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 1175 { 1176 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1177 struct rx_msdu_start *msdu_start = 1178 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1179 1180 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 1181 } 1182 1183 /* 1184 * Get qos_control_valid from RX_MPDU_START 1185 */ 1186 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 1187 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 1188 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 1189 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 1190 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 1191 1192 static inline uint32_t 1193 hal_rx_mpdu_start_mpdu_qos_control_valid_get(uint8_t *buf) 1194 { 1195 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1196 struct rx_mpdu_start *mpdu_start = 1197 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1198 uint32_t qos_control_valid; 1199 1200 qos_control_valid = HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1201 &(mpdu_start->rx_mpdu_info_details)); 1202 1203 return qos_control_valid; 1204 } 1205 1206 1207 /* 1208 * Get SW peer id from RX_MPDU_START 1209 */ 1210 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 1211 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 1212 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 1213 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 1214 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 1215 1216 static inline uint32_t 1217 hal_rx_mpdu_start_sw_peer_id_get(uint8_t *buf) 1218 { 1219 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1220 struct rx_mpdu_start *mpdu_start = 1221 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1222 uint32_t sw_peer_id; 1223 1224 sw_peer_id = HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 1225 &(mpdu_start->rx_mpdu_info_details)); 1226 1227 return sw_peer_id; 1228 } 1229 1230 #if defined(WCSS_VERSION) && \ 1231 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1232 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1233 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1234 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1235 RX_MSDU_START_5_SGI_OFFSET)), \ 1236 RX_MSDU_START_5_SGI_MASK, \ 1237 RX_MSDU_START_5_SGI_LSB)) 1238 #else 1239 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 1240 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1241 RX_MSDU_START_6_SGI_OFFSET)), \ 1242 RX_MSDU_START_6_SGI_MASK, \ 1243 RX_MSDU_START_6_SGI_LSB)) 1244 #endif 1245 /** 1246 * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd 1247 * Interval from rx_msdu_start TLV 1248 * 1249 * @buf: pointer to the start of RX PKT TLV headers 1250 * Return: uint32_t(sgi) 1251 */ 1252 static inline uint32_t 1253 hal_rx_msdu_start_sgi_get(uint8_t *buf) 1254 { 1255 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1256 struct rx_msdu_start *msdu_start = 1257 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1258 uint32_t sgi; 1259 1260 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 1261 1262 return sgi; 1263 } 1264 1265 #if defined(WCSS_VERSION) && \ 1266 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1267 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1268 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1269 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1270 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 1271 RX_MSDU_START_5_RATE_MCS_MASK, \ 1272 RX_MSDU_START_5_RATE_MCS_LSB)) 1273 #else 1274 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 1275 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 1276 RX_MSDU_START_6_RATE_MCS_OFFSET)), \ 1277 RX_MSDU_START_6_RATE_MCS_MASK, \ 1278 RX_MSDU_START_6_RATE_MCS_LSB)) 1279 #endif 1280 /** 1281 * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate 1282 * from rx_msdu_start TLV 1283 * 1284 * @buf: pointer to the start of RX PKT TLV headers 1285 * Return: uint32_t(rate_mcs) 1286 */ 1287 static inline uint32_t 1288 hal_rx_msdu_start_rate_mcs_get(uint8_t *buf) 1289 { 1290 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1291 struct rx_msdu_start *msdu_start = 1292 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1293 uint32_t rate_mcs; 1294 1295 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 1296 1297 return rate_mcs; 1298 } 1299 1300 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 1301 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1302 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 1303 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 1304 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 1305 1306 /* 1307 * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the 1308 * packet from rx_attention 1309 * 1310 * @buf: pointer to the start of RX PKT TLV header 1311 * Return: uint32_t(decryt status) 1312 */ 1313 1314 static inline uint32_t 1315 hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf) 1316 { 1317 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1318 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1319 uint32_t is_decrypt = 0; 1320 uint32_t decrypt_status; 1321 1322 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 1323 1324 if (!decrypt_status) 1325 is_decrypt = 1; 1326 1327 return is_decrypt; 1328 } 1329 1330 /* 1331 * Get key index from RX_MSDU_END 1332 */ 1333 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 1334 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1335 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 1336 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 1337 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 1338 /* 1339 * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet 1340 * from rx_msdu_end 1341 * 1342 * @buf: pointer to the start of RX PKT TLV header 1343 * Return: uint32_t(key id) 1344 */ 1345 1346 static inline uint32_t 1347 hal_rx_msdu_get_keyid(uint8_t *buf) 1348 { 1349 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1350 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1351 uint32_t keyid_octet; 1352 1353 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 1354 1355 return keyid_octet & 0x3; 1356 } 1357 1358 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 1359 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1360 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 1361 RX_MSDU_START_5_USER_RSSI_MASK, \ 1362 RX_MSDU_START_5_USER_RSSI_LSB)) 1363 /* 1364 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 1365 * from rx_msdu_start 1366 * 1367 * @buf: pointer to the start of RX PKT TLV header 1368 * Return: uint32_t(rssi) 1369 */ 1370 1371 static inline uint32_t 1372 hal_rx_msdu_start_get_rssi(uint8_t *buf) 1373 { 1374 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1375 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1376 uint32_t rssi; 1377 1378 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 1379 1380 return rssi; 1381 1382 } 1383 1384 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 1385 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1386 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 1387 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 1388 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 1389 1390 /* 1391 * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel 1392 * from rx_msdu_start 1393 * 1394 * @buf: pointer to the start of RX PKT TLV header 1395 * Return: uint32_t(frequency) 1396 */ 1397 1398 static inline uint32_t 1399 hal_rx_msdu_start_get_freq(uint8_t *buf) 1400 { 1401 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1402 struct rx_msdu_start *msdu_start = 1403 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1404 uint32_t freq; 1405 1406 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 1407 1408 return freq; 1409 } 1410 1411 1412 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 1413 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 1414 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 1415 RX_MSDU_START_5_PKT_TYPE_MASK, \ 1416 RX_MSDU_START_5_PKT_TYPE_LSB)) 1417 1418 /* 1419 * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type 1420 * from rx_msdu_start 1421 * 1422 * @buf: pointer to the start of RX PKT TLV header 1423 * Return: uint32_t(pkt type) 1424 */ 1425 1426 static inline uint32_t 1427 hal_rx_msdu_start_get_pkt_type(uint8_t *buf) 1428 { 1429 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1430 struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1431 uint32_t pkt_type; 1432 1433 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 1434 1435 return pkt_type; 1436 } 1437 1438 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 1439 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1440 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 1441 RX_MPDU_INFO_2_TO_DS_MASK, \ 1442 RX_MPDU_INFO_2_TO_DS_LSB)) 1443 1444 /* 1445 * hal_rx_mpdu_get_tods(): API to get the tods info 1446 * from rx_mpdu_start 1447 * 1448 * @buf: pointer to the start of RX PKT TLV header 1449 * Return: uint32_t(to_ds) 1450 */ 1451 1452 static inline uint32_t 1453 hal_rx_mpdu_get_to_ds(uint8_t *buf) 1454 { 1455 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1456 struct rx_mpdu_start *mpdu_start = 1457 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1458 1459 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1460 uint32_t to_ds; 1461 1462 to_ds = HAL_RX_MPDU_GET_TODS(mpdu_info); 1463 1464 return to_ds; 1465 } 1466 1467 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 1468 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1469 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 1470 RX_MPDU_INFO_2_FR_DS_MASK, \ 1471 RX_MPDU_INFO_2_FR_DS_LSB)) 1472 1473 /* 1474 * hal_rx_mpdu_get_fr_ds(): API to get the from ds info 1475 * from rx_mpdu_start 1476 * 1477 * @buf: pointer to the start of RX PKT TLV header 1478 * Return: uint32_t(fr_ds) 1479 */ 1480 1481 static inline uint32_t 1482 hal_rx_mpdu_get_fr_ds(uint8_t *buf) 1483 { 1484 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1485 struct rx_mpdu_start *mpdu_start = 1486 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1487 1488 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1489 uint32_t fr_ds; 1490 1491 fr_ds = HAL_RX_MPDU_GET_FROMDS(mpdu_info); 1492 1493 return fr_ds; 1494 } 1495 1496 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 1497 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1498 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 1499 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 1500 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 1501 1502 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 1503 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1504 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 1505 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 1506 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 1507 1508 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 1509 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1510 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 1511 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 1512 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 1513 1514 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 1515 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1516 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 1517 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 1518 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 1519 1520 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 1521 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1522 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 1523 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 1524 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 1525 1526 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 1527 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1528 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 1529 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 1530 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 1531 1532 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 1533 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1534 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 1535 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 1536 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 1537 1538 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 1539 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1540 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 1541 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 1542 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 1543 1544 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 1545 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1546 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 1547 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 1548 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 1549 1550 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 1551 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1552 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 1553 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 1554 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 1555 1556 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 1557 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1558 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 1559 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 1560 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 1561 1562 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 1563 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1564 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 1565 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 1566 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 1567 1568 /* 1569 * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu 1570 * 1571 * @buf: pointer to the start of RX PKT TLV headera 1572 * @mac_addr: pointer to mac address 1573 * Return: success/failure 1574 */ 1575 static inline 1576 QDF_STATUS hal_rx_mpdu_get_addr1(uint8_t *buf, uint8_t *mac_addr) 1577 { 1578 struct __attribute__((__packed__)) hal_addr1 { 1579 uint32_t ad1_31_0; 1580 uint16_t ad1_47_32; 1581 }; 1582 1583 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1584 struct rx_mpdu_start *mpdu_start = 1585 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1586 1587 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1588 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 1589 uint32_t mac_addr_ad1_valid; 1590 1591 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 1592 1593 if (mac_addr_ad1_valid) { 1594 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 1595 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 1596 return QDF_STATUS_SUCCESS; 1597 } 1598 1599 return QDF_STATUS_E_FAILURE; 1600 } 1601 1602 /* 1603 * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu 1604 * in the packet 1605 * 1606 * @buf: pointer to the start of RX PKT TLV header 1607 * @mac_addr: pointer to mac address 1608 * Return: success/failure 1609 */ 1610 static inline 1611 QDF_STATUS hal_rx_mpdu_get_addr2(uint8_t *buf, uint8_t *mac_addr) 1612 { 1613 struct __attribute__((__packed__)) hal_addr2 { 1614 uint16_t ad2_15_0; 1615 uint32_t ad2_47_16; 1616 }; 1617 1618 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1619 struct rx_mpdu_start *mpdu_start = 1620 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1621 1622 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1623 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 1624 uint32_t mac_addr_ad2_valid; 1625 1626 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 1627 1628 if (mac_addr_ad2_valid) { 1629 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 1630 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 1631 return QDF_STATUS_SUCCESS; 1632 } 1633 1634 return QDF_STATUS_E_FAILURE; 1635 } 1636 1637 /* 1638 * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu 1639 * in the packet 1640 * 1641 * @buf: pointer to the start of RX PKT TLV header 1642 * @mac_addr: pointer to mac address 1643 * Return: success/failure 1644 */ 1645 static inline 1646 QDF_STATUS hal_rx_mpdu_get_addr3(uint8_t *buf, uint8_t *mac_addr) 1647 { 1648 struct __attribute__((__packed__)) hal_addr3 { 1649 uint32_t ad3_31_0; 1650 uint16_t ad3_47_32; 1651 }; 1652 1653 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1654 struct rx_mpdu_start *mpdu_start = 1655 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1656 1657 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1658 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1659 uint32_t mac_addr_ad3_valid; 1660 1661 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1662 1663 if (mac_addr_ad3_valid) { 1664 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1665 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1666 return QDF_STATUS_SUCCESS; 1667 } 1668 1669 return QDF_STATUS_E_FAILURE; 1670 } 1671 1672 /* 1673 * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu 1674 * in the packet 1675 * 1676 * @buf: pointer to the start of RX PKT TLV header 1677 * @mac_addr: pointer to mac address 1678 * Return: success/failure 1679 */ 1680 static inline 1681 QDF_STATUS hal_rx_mpdu_get_addr4(uint8_t *buf, uint8_t *mac_addr) 1682 { 1683 struct __attribute__((__packed__)) hal_addr4 { 1684 uint32_t ad4_31_0; 1685 uint16_t ad4_47_32; 1686 }; 1687 1688 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1689 struct rx_mpdu_start *mpdu_start = 1690 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1691 1692 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1693 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1694 uint32_t mac_addr_ad4_valid; 1695 1696 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1697 1698 if (mac_addr_ad4_valid) { 1699 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1700 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1701 return QDF_STATUS_SUCCESS; 1702 } 1703 1704 return QDF_STATUS_E_FAILURE; 1705 } 1706 1707 /** 1708 * hal_rx_msdu_end_da_idx_get: API to get da_idx 1709 * from rx_msdu_end TLV 1710 * 1711 * @ buf: pointer to the start of RX PKT TLV headers 1712 * Return: da index 1713 */ 1714 static inline uint16_t 1715 hal_rx_msdu_end_da_idx_get(struct hal_soc *hal_soc, uint8_t *buf) 1716 { 1717 return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf); 1718 } 1719 1720 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 1721 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1722 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 1723 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 1724 RX_MSDU_END_5_DA_IS_VALID_LSB)) 1725 1726 /** 1727 * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid 1728 * from rx_msdu_end TLV 1729 * 1730 * @ buf: pointer to the start of RX PKT TLV headers 1731 * Return: da_is_valid 1732 */ 1733 static inline uint8_t 1734 hal_rx_msdu_end_da_is_valid_get(uint8_t *buf) 1735 { 1736 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1737 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1738 uint8_t da_is_valid; 1739 1740 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 1741 1742 return da_is_valid; 1743 } 1744 1745 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 1746 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1747 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 1748 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 1749 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 1750 1751 /** 1752 * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC 1753 * from rx_msdu_end TLV 1754 * 1755 * @ buf: pointer to the start of RX PKT TLV headers 1756 * Return: da_is_mcbc 1757 */ 1758 static inline uint8_t 1759 hal_rx_msdu_end_da_is_mcbc_get(uint8_t *buf) 1760 { 1761 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1762 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1763 uint8_t da_is_mcbc; 1764 1765 da_is_mcbc = HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 1766 1767 return da_is_mcbc; 1768 } 1769 1770 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 1771 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1772 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 1773 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 1774 RX_MSDU_END_5_FIRST_MSDU_LSB)) 1775 1776 /** 1777 * hal_rx_msdu_end_first_msdu_get: API to get first msdu status 1778 * from rx_msdu_end TLV 1779 * 1780 * @ buf: pointer to the start of RX PKT TLV headers 1781 * Return: first_msdu 1782 */ 1783 static inline uint8_t 1784 hal_rx_msdu_end_first_msdu_get(uint8_t *buf) 1785 { 1786 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1787 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1788 uint8_t first_msdu; 1789 1790 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 1791 1792 return first_msdu; 1793 } 1794 1795 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 1796 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 1797 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 1798 RX_MSDU_END_5_LAST_MSDU_MASK, \ 1799 RX_MSDU_END_5_LAST_MSDU_LSB)) 1800 1801 /** 1802 * hal_rx_msdu_end_last_msdu_get: API to get last msdu status 1803 * from rx_msdu_end TLV 1804 * 1805 * @ buf: pointer to the start of RX PKT TLV headers 1806 * Return: last_msdu 1807 */ 1808 static inline uint8_t 1809 hal_rx_msdu_end_last_msdu_get(uint8_t *buf) 1810 { 1811 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1812 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1813 uint8_t last_msdu; 1814 1815 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 1816 1817 return last_msdu; 1818 } 1819 /******************************************************************************* 1820 * RX ERROR APIS 1821 ******************************************************************************/ 1822 1823 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 1824 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1825 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 1826 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 1827 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 1828 1829 /** 1830 * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR 1831 * from rx_mpdu_end TLV 1832 * 1833 * @buf: pointer to the start of RX PKT TLV headers 1834 * Return: uint32_t(decrypt_err) 1835 */ 1836 static inline uint32_t 1837 hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf) 1838 { 1839 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1840 struct rx_mpdu_end *mpdu_end = 1841 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1842 uint32_t decrypt_err; 1843 1844 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 1845 1846 return decrypt_err; 1847 } 1848 1849 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 1850 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 1851 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 1852 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 1853 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 1854 1855 /** 1856 * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR 1857 * from rx_mpdu_end TLV 1858 * 1859 * @buf: pointer to the start of RX PKT TLV headers 1860 * Return: uint32_t(mic_err) 1861 */ 1862 static inline uint32_t 1863 hal_rx_mpdu_end_mic_err_get(uint8_t *buf) 1864 { 1865 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1866 struct rx_mpdu_end *mpdu_end = 1867 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 1868 uint32_t mic_err; 1869 1870 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 1871 1872 return mic_err; 1873 } 1874 1875 /******************************************************************************* 1876 * RX REO ERROR APIS 1877 ******************************************************************************/ 1878 1879 #define HAL_RX_NUM_MSDU_DESC 6 1880 #define HAL_RX_MAX_SAVED_RING_DESC 16 1881 1882 /* TODO: rework the structure */ 1883 struct hal_rx_msdu_list { 1884 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC]; 1885 uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC]; 1886 uint8_t rbm[HAL_RX_NUM_MSDU_DESC]; 1887 }; 1888 1889 struct hal_buf_info { 1890 uint64_t paddr; 1891 uint32_t sw_cookie; 1892 }; 1893 1894 /** 1895 * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details 1896 * @msdu_link_ptr - msdu link ptr 1897 * @hal - pointer to hal_soc 1898 * Return - Pointer to rx_msdu_details structure 1899 * 1900 */ 1901 static inline void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, void *hal) 1902 { 1903 struct hal_soc *hal_soc = (struct hal_soc *)hal; 1904 1905 return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr); 1906 } 1907 1908 /** 1909 * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr 1910 * @msdu_details_ptr - Pointer to msdu_details_ptr 1911 * @hal - pointer to hal_soc 1912 * Return - Pointer to rx_msdu_desc_info structure. 1913 * 1914 */ 1915 static inline void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, void *hal) 1916 { 1917 struct hal_soc *hal_soc = (struct hal_soc *)hal; 1918 1919 return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr); 1920 } 1921 1922 /* This special cookie value will be used to indicate FW allocated buffers 1923 * received through RXDMA2SW ring for RXDMA WARs 1924 */ 1925 #define HAL_RX_COOKIE_SPECIAL 0x1fffff 1926 1927 /** 1928 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 1929 * from the MSDU link descriptor 1930 * 1931 * @msdu_link_desc: Opaque pointer used by HAL to get to the 1932 * MSDU link descriptor (struct rx_msdu_link) 1933 * 1934 * @msdu_list: Return the list of MSDUs contained in this link descriptor 1935 * 1936 * @num_msdus: Number of MSDUs in the MPDU 1937 * 1938 * Return: void 1939 */ 1940 static inline void hal_rx_msdu_list_get(struct hal_soc *hal_soc, 1941 void *msdu_link_desc, 1942 struct hal_rx_msdu_list *msdu_list, 1943 uint16_t *num_msdus) 1944 { 1945 struct rx_msdu_details *msdu_details; 1946 struct rx_msdu_desc_info *msdu_desc_info; 1947 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1948 int i; 1949 1950 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1951 1952 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1953 "[%s][%d] msdu_link=%pK msdu_details=%pK", 1954 __func__, __LINE__, msdu_link, msdu_details); 1955 1956 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 1957 /* num_msdus received in mpdu descriptor may be incorrect 1958 * sometimes due to HW issue. Check msdu buffer address also 1959 */ 1960 if (HAL_RX_BUFFER_ADDR_31_0_GET( 1961 &msdu_details[i].buffer_addr_info_details) == 0) { 1962 /* set the last msdu bit in the prev msdu_desc_info */ 1963 msdu_desc_info = 1964 hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc); 1965 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1966 break; 1967 } 1968 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 1969 hal_soc); 1970 1971 /* set first MSDU bit or the last MSDU bit */ 1972 if (!i) 1973 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1974 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 1975 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 1976 1977 msdu_list->msdu_info[i].msdu_flags = 1978 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1979 msdu_list->msdu_info[i].msdu_len = 1980 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 1981 msdu_list->sw_cookie[i] = 1982 HAL_RX_BUF_COOKIE_GET( 1983 &msdu_details[i].buffer_addr_info_details); 1984 msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET( 1985 &msdu_details[i].buffer_addr_info_details); 1986 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1987 "[%s][%d] i=%d sw_cookie=%d", 1988 __func__, __LINE__, i, msdu_list->sw_cookie[i]); 1989 } 1990 *num_msdus = i; 1991 } 1992 1993 /** 1994 * hal_rx_msdu_reo_dst_ind_get: Gets the REO 1995 * destination ring ID from the msdu desc info 1996 * 1997 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1998 * the current descriptor 1999 * 2000 * Return: dst_ind (REO destination ring ID) 2001 */ 2002 static inline uint32_t 2003 hal_rx_msdu_reo_dst_ind_get(struct hal_soc *hal_soc, void *msdu_link_desc) 2004 { 2005 struct rx_msdu_details *msdu_details; 2006 struct rx_msdu_desc_info *msdu_desc_info; 2007 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 2008 uint32_t dst_ind; 2009 2010 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 2011 2012 /* The first msdu in the link should exsist */ 2013 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 2014 hal_soc); 2015 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 2016 return dst_ind; 2017 } 2018 2019 /** 2020 * hal_rx_reo_buf_paddr_get: Gets the physical address and 2021 * cookie from the REO destination ring element 2022 * 2023 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to 2024 * the current descriptor 2025 * @ buf_info: structure to return the buffer information 2026 * Return: void 2027 */ 2028 static inline void hal_rx_reo_buf_paddr_get(void *rx_desc, 2029 struct hal_buf_info *buf_info) 2030 { 2031 struct reo_destination_ring *reo_ring = 2032 (struct reo_destination_ring *)rx_desc; 2033 2034 buf_info->paddr = 2035 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 2036 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 2037 2038 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 2039 } 2040 2041 /** 2042 * enum hal_reo_error_code: Indicates that type of buffer or descriptor 2043 * 2044 * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer 2045 * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link 2046 * descriptor 2047 */ 2048 enum hal_rx_reo_buf_type { 2049 HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0, 2050 HAL_RX_REO_MSDU_LINK_DESC_TYPE, 2051 }; 2052 2053 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2054 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 2055 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 2056 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 2057 2058 /** 2059 * enum hal_reo_error_code: Error code describing the type of error detected 2060 * 2061 * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the 2062 * REO_ENTRANCE ring is set to 0 2063 * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set 2064 * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session 2065 * having been setup 2066 * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN, 2067 * Retry bit set: duplicate frame 2068 * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame 2069 * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame) 2070 * received with 2K jump in SN 2071 * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN 2072 * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received 2073 * with SN falling within the OOR window 2074 * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the 2075 * OOR window 2076 * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session 2077 * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN 2078 * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet 2079 * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2080 * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor 2081 * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result 2082 * of the pn_error_detected_flag been set in the REO Queue descriptor 2083 * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of 2084 * the queue descriptor(address) being blocked as SW/FW seems to be currently 2085 * in the process of making updates to this descriptor 2086 */ 2087 enum hal_reo_error_code { 2088 HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0, 2089 HAL_REO_ERR_QUEUE_DESC_INVALID, 2090 HAL_REO_ERR_AMPDU_IN_NON_BA, 2091 HAL_REO_ERR_NON_BA_DUPLICATE, 2092 HAL_REO_ERR_BA_DUPLICATE, 2093 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP, 2094 HAL_REO_ERR_BAR_FRAME_2K_JUMP, 2095 HAL_REO_ERR_REGULAR_FRAME_OOR, 2096 HAL_REO_ERR_BAR_FRAME_OOR, 2097 HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION, 2098 HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN, 2099 HAL_REO_ERR_PN_CHECK_FAILED, 2100 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET, 2101 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET, 2102 HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET, 2103 HAL_REO_ERR_MAX 2104 }; 2105 2106 /** 2107 * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected 2108 * 2109 * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow 2110 * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO 2111 * overflow 2112 * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving 2113 * incomplete 2114 * MPDU from the PHY 2115 * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed 2116 * @ HAL_RXDMA_ERR_DECRYPT : Decryption error 2117 * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error 2118 * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be 2119 * encrypted but wasn’t 2120 * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error 2121 * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded 2122 * the max allowed 2123 * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error 2124 * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error 2125 * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout 2126 * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout 2127 * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout 2128 * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request 2129 * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors 2130 */ 2131 enum hal_rxdma_error_code { 2132 HAL_RXDMA_ERR_OVERFLOW = 0, 2133 HAL_RXDMA_ERR_MPDU_LENGTH, 2134 HAL_RXDMA_ERR_FCS, 2135 HAL_RXDMA_ERR_DECRYPT, 2136 HAL_RXDMA_ERR_TKIP_MIC, 2137 HAL_RXDMA_ERR_UNENCRYPTED, 2138 HAL_RXDMA_ERR_MSDU_LEN, 2139 HAL_RXDMA_ERR_MSDU_LIMIT, 2140 HAL_RXDMA_ERR_WIFI_PARSE, 2141 HAL_RXDMA_ERR_AMSDU_PARSE, 2142 HAL_RXDMA_ERR_SA_TIMEOUT, 2143 HAL_RXDMA_ERR_DA_TIMEOUT, 2144 HAL_RXDMA_ERR_FLOW_TIMEOUT, 2145 HAL_RXDMA_ERR_FLUSH_REQUEST, 2146 HAL_RXDMA_ERR_WAR = 31, 2147 HAL_RXDMA_ERR_MAX 2148 }; 2149 2150 /** 2151 * HW BM action settings in WBM release ring 2152 */ 2153 #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0 2154 #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1 2155 2156 /** 2157 * enum hal_rx_wbm_error_source: Indicates which module initiated the 2158 * release of this buffer or descriptor 2159 * 2160 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2161 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2162 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2163 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2164 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2165 */ 2166 enum hal_rx_wbm_error_source { 2167 HAL_RX_WBM_ERR_SRC_TQM = 0, 2168 HAL_RX_WBM_ERR_SRC_RXDMA, 2169 HAL_RX_WBM_ERR_SRC_REO, 2170 HAL_RX_WBM_ERR_SRC_FW, 2171 HAL_RX_WBM_ERR_SRC_SW, 2172 }; 2173 2174 /** 2175 * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor 2176 * released 2177 * 2178 * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor 2179 * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor 2180 * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor 2181 * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor 2182 * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor 2183 */ 2184 enum hal_rx_wbm_buf_type { 2185 HAL_RX_WBM_BUF_TYPE_REL_BUF = 0, 2186 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC, 2187 HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC, 2188 HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC, 2189 HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC, 2190 }; 2191 2192 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \ 2193 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 2194 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 2195 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 2196 2197 /** 2198 * hal_rx_is_pn_error() - Indicate if this error was caused by a 2199 * PN check failure 2200 * 2201 * @reo_desc: opaque pointer used by HAL to get the REO destination entry 2202 * 2203 * Return: true: error caused by PN check, false: other error 2204 */ 2205 static inline bool hal_rx_reo_is_pn_error(void *rx_desc) 2206 { 2207 struct reo_destination_ring *reo_desc = 2208 (struct reo_destination_ring *)rx_desc; 2209 2210 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2211 HAL_REO_ERR_PN_CHECK_FAILED) | 2212 (HAL_RX_REO_ERROR_GET(reo_desc) == 2213 HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ? 2214 true : false; 2215 } 2216 2217 /** 2218 * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in 2219 * the sequence number 2220 * 2221 * @ring_desc: opaque pointer used by HAL to get the REO destination entry 2222 * 2223 * Return: true: error caused by 2K jump, false: other error 2224 */ 2225 static inline bool hal_rx_reo_is_2k_jump(void *rx_desc) 2226 { 2227 struct reo_destination_ring *reo_desc = 2228 (struct reo_destination_ring *)rx_desc; 2229 2230 return ((HAL_RX_REO_ERROR_GET(reo_desc) == 2231 HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) | 2232 (HAL_RX_REO_ERROR_GET(reo_desc) == 2233 HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ? 2234 true : false; 2235 } 2236 2237 /** 2238 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM 2239 * 2240 * @ soc : HAL version of the SOC pointer 2241 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 2242 * @ buf_addr_info : void pointer to the buffer_addr_info 2243 * @ bm_action : put in IDLE list or release to MSDU_LIST 2244 * 2245 * Return: void 2246 */ 2247 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 2248 static inline void hal_rx_msdu_link_desc_set(struct hal_soc *soc, 2249 void *src_srng_desc, void *buf_addr_info, 2250 uint8_t bm_action) 2251 { 2252 struct wbm_release_ring *wbm_rel_srng = 2253 (struct wbm_release_ring *)src_srng_desc; 2254 2255 /* Structure copy !!! */ 2256 wbm_rel_srng->released_buff_or_desc_addr_info = 2257 *((struct buffer_addr_info *)buf_addr_info); 2258 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2259 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 2260 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION, 2261 bm_action); 2262 HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, 2263 BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 2264 } 2265 2266 /* 2267 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 2268 * REO entrance ring 2269 * 2270 * @ soc: HAL version of the SOC pointer 2271 * @ pa: Physical address of the MSDU Link Descriptor 2272 * @ cookie: SW cookie to get to the virtual address 2273 * @ error_enabled_reo_q: Argument to determine whether this needs to go 2274 * to the error enabled REO queue 2275 * 2276 * Return: void 2277 */ 2278 static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 2279 uint64_t pa, uint32_t cookie, bool error_enabled_reo_q) 2280 { 2281 /* TODO */ 2282 } 2283 2284 /** 2285 * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the 2286 * BUFFER_ADDR_INFO, give the RX descriptor 2287 * (Assumption -- BUFFER_ADDR_INFO is the 2288 * first field in the descriptor structure) 2289 */ 2290 #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) ((void *)(ring_desc)) 2291 2292 #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2293 2294 #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET 2295 2296 /** 2297 * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager" 2298 * from the BUFFER_ADDR_INFO structure 2299 * given a REO destination ring descriptor. 2300 * @ ring_desc: RX(REO/WBM release) destination ring descriptor 2301 * 2302 * Return: uint8_t (value of the return_buffer_manager) 2303 */ 2304 static inline 2305 uint8_t hal_rx_ret_buf_manager_get(void *ring_desc) 2306 { 2307 /* 2308 * The following macro takes buf_addr_info as argument, 2309 * but since buf_addr_info is the first field in ring_desc 2310 * Hence the following call is OK 2311 */ 2312 return HAL_RX_BUF_RBM_GET(ring_desc); 2313 } 2314 2315 2316 /******************************************************************************* 2317 * RX WBM ERROR APIS 2318 ******************************************************************************/ 2319 2320 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2321 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 2322 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 2323 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 2324 2325 #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2326 (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \ 2327 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \ 2328 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB) 2329 2330 /** 2331 * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed 2332 * the frame to this release ring 2333 * 2334 * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this 2335 * frame to this queue 2336 * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per 2337 * received routing instructions. No error within REO was detected 2338 */ 2339 enum hal_rx_wbm_reo_push_reason { 2340 HAL_RX_WBM_REO_PSH_RSN_ERROR = 0, 2341 HAL_RX_WBM_REO_PSH_RSN_ROUTE, 2342 }; 2343 2344 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2345 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 2346 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 2347 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 2348 2349 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2350 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 2351 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 2352 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 2353 2354 /** 2355 * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to 2356 * this release ring 2357 * 2358 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed 2359 * this frame to this queue 2360 * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue 2361 * per received routing instructions. No error within RXDMA was detected 2362 */ 2363 enum hal_rx_wbm_rxdma_push_reason { 2364 HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0, 2365 HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE, 2366 }; 2367 2368 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 2369 (((*(((uint32_t *) wbm_desc) + \ 2370 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 2371 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 2372 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 2373 2374 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 2375 (((*(((uint32_t *) wbm_desc) + \ 2376 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 2377 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 2378 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 2379 2380 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 2381 (((*(((uint32_t *) wbm_desc) + \ 2382 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 2383 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 2384 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 2385 2386 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 2387 (((*(((uint32_t *) wbm_desc) + \ 2388 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 2389 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 2390 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 2391 2392 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 2393 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 2394 wbm_desc)->released_buff_or_desc_addr_info) 2395 2396 /** 2397 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 2398 * humman readable format. 2399 * @ rx_attn: pointer the rx_attention TLV in pkt. 2400 * @ dbg_level: log level. 2401 * 2402 * Return: void 2403 */ 2404 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 2405 uint8_t dbg_level) 2406 { 2407 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2408 "rx_attention tlv=" 2409 "rxpcu_mpdu_filter_in_category: %d " 2410 "sw_frame_group_id: %d " 2411 "reserved_0: %d " 2412 "phy_ppdu_id: %d " 2413 "first_mpdu : %d " 2414 "reserved_1a: %d " 2415 "mcast_bcast: %d " 2416 "ast_index_not_found: %d " 2417 "ast_index_timeout: %d " 2418 "power_mgmt: %d " 2419 "non_qos: %d " 2420 "null_data: %d " 2421 "mgmt_type: %d " 2422 "ctrl_type: %d " 2423 "more_data: %d " 2424 "eosp: %d " 2425 "a_msdu_error: %d " 2426 "fragment_flag: %d " 2427 "order: %d " 2428 "cce_match: %d " 2429 "overflow_err: %d " 2430 "msdu_length_err: %d " 2431 "tcp_udp_chksum_fail: %d " 2432 "ip_chksum_fail: %d " 2433 "sa_idx_invalid: %d " 2434 "da_idx_invalid: %d " 2435 "reserved_1b: %d " 2436 "rx_in_tx_decrypt_byp: %d " 2437 "encrypt_required: %d " 2438 "directed: %d " 2439 "buffer_fragment: %d " 2440 "mpdu_length_err: %d " 2441 "tkip_mic_err: %d " 2442 "decrypt_err: %d " 2443 "unencrypted_frame_err: %d " 2444 "fcs_err: %d " 2445 "flow_idx_timeout: %d " 2446 "flow_idx_invalid: %d " 2447 "wifi_parser_error: %d " 2448 "amsdu_parser_error: %d " 2449 "sa_idx_timeout: %d " 2450 "da_idx_timeout: %d " 2451 "msdu_limit_error: %d " 2452 "da_is_valid: %d " 2453 "da_is_mcbc: %d " 2454 "sa_is_valid: %d " 2455 "decrypt_status_code: %d " 2456 "rx_bitmap_not_updated: %d " 2457 "reserved_2: %d " 2458 "msdu_done: %d ", 2459 rx_attn->rxpcu_mpdu_filter_in_category, 2460 rx_attn->sw_frame_group_id, 2461 rx_attn->reserved_0, 2462 rx_attn->phy_ppdu_id, 2463 rx_attn->first_mpdu, 2464 rx_attn->reserved_1a, 2465 rx_attn->mcast_bcast, 2466 rx_attn->ast_index_not_found, 2467 rx_attn->ast_index_timeout, 2468 rx_attn->power_mgmt, 2469 rx_attn->non_qos, 2470 rx_attn->null_data, 2471 rx_attn->mgmt_type, 2472 rx_attn->ctrl_type, 2473 rx_attn->more_data, 2474 rx_attn->eosp, 2475 rx_attn->a_msdu_error, 2476 rx_attn->fragment_flag, 2477 rx_attn->order, 2478 rx_attn->cce_match, 2479 rx_attn->overflow_err, 2480 rx_attn->msdu_length_err, 2481 rx_attn->tcp_udp_chksum_fail, 2482 rx_attn->ip_chksum_fail, 2483 rx_attn->sa_idx_invalid, 2484 rx_attn->da_idx_invalid, 2485 rx_attn->reserved_1b, 2486 rx_attn->rx_in_tx_decrypt_byp, 2487 rx_attn->encrypt_required, 2488 rx_attn->directed, 2489 rx_attn->buffer_fragment, 2490 rx_attn->mpdu_length_err, 2491 rx_attn->tkip_mic_err, 2492 rx_attn->decrypt_err, 2493 rx_attn->unencrypted_frame_err, 2494 rx_attn->fcs_err, 2495 rx_attn->flow_idx_timeout, 2496 rx_attn->flow_idx_invalid, 2497 rx_attn->wifi_parser_error, 2498 rx_attn->amsdu_parser_error, 2499 rx_attn->sa_idx_timeout, 2500 rx_attn->da_idx_timeout, 2501 rx_attn->msdu_limit_error, 2502 rx_attn->da_is_valid, 2503 rx_attn->da_is_mcbc, 2504 rx_attn->sa_is_valid, 2505 rx_attn->decrypt_status_code, 2506 rx_attn->rx_bitmap_not_updated, 2507 rx_attn->reserved_2, 2508 rx_attn->msdu_done); 2509 2510 2511 } 2512 2513 /** 2514 * hal_rx_dump_mpdu_start_tlv: dump RX mpdu_start TLV in structured 2515 * human readable format. 2516 * @ mpdu_start: pointer the rx_attention TLV in pkt. 2517 * @ dbg_level: log level. 2518 * 2519 * Return: void 2520 */ 2521 static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start, 2522 uint8_t dbg_level) 2523 { 2524 struct rx_mpdu_info *mpdu_info = 2525 (struct rx_mpdu_info *) &mpdu_start->rx_mpdu_info_details; 2526 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2527 "rx_mpdu_start tlv - " 2528 "rxpcu_mpdu_filter_in_category: %d " 2529 "sw_frame_group_id: %d " 2530 "ndp_frame: %d " 2531 "phy_err: %d " 2532 "phy_err_during_mpdu_header: %d " 2533 "protocol_version_err: %d " 2534 "ast_based_lookup_valid: %d " 2535 "phy_ppdu_id: %d " 2536 "ast_index: %d " 2537 "sw_peer_id: %d " 2538 "mpdu_frame_control_valid: %d " 2539 "mpdu_duration_valid: %d " 2540 "mac_addr_ad1_valid: %d " 2541 "mac_addr_ad2_valid: %d " 2542 "mac_addr_ad3_valid: %d " 2543 "mac_addr_ad4_valid: %d " 2544 "mpdu_sequence_control_valid: %d " 2545 "mpdu_qos_control_valid: %d " 2546 "mpdu_ht_control_valid: %d " 2547 "frame_encryption_info_valid: %d " 2548 "fr_ds: %d " 2549 "to_ds: %d " 2550 "encrypted: %d " 2551 "mpdu_retry: %d " 2552 "mpdu_sequence_number: %d " 2553 "epd_en: %d " 2554 "all_frames_shall_be_encrypted: %d " 2555 "encrypt_type: %d " 2556 "mesh_sta: %d " 2557 "bssid_hit: %d " 2558 "bssid_number: %d " 2559 "tid: %d " 2560 "pn_31_0: %d " 2561 "pn_63_32: %d " 2562 "pn_95_64: %d " 2563 "pn_127_96: %d " 2564 "peer_meta_data: %d " 2565 "rxpt_classify_info.reo_destination_indication: %d " 2566 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %d " 2567 "rx_reo_queue_desc_addr_31_0: %d " 2568 "rx_reo_queue_desc_addr_39_32: %d " 2569 "receive_queue_number: %d " 2570 "pre_delim_err_warning: %d " 2571 "first_delim_err: %d " 2572 "key_id_octet: %d " 2573 "new_peer_entry: %d " 2574 "decrypt_needed: %d " 2575 "decap_type: %d " 2576 "rx_insert_vlan_c_tag_padding: %d " 2577 "rx_insert_vlan_s_tag_padding: %d " 2578 "strip_vlan_c_tag_decap: %d " 2579 "strip_vlan_s_tag_decap: %d " 2580 "pre_delim_count: %d " 2581 "ampdu_flag: %d " 2582 "bar_frame: %d " 2583 "mpdu_length: %d " 2584 "first_mpdu: %d " 2585 "mcast_bcast: %d " 2586 "ast_index_not_found: %d " 2587 "ast_index_timeout: %d " 2588 "power_mgmt: %d " 2589 "non_qos: %d " 2590 "null_data: %d " 2591 "mgmt_type: %d " 2592 "ctrl_type: %d " 2593 "more_data: %d " 2594 "eosp: %d " 2595 "fragment_flag: %d " 2596 "order: %d " 2597 "u_apsd_trigger: %d " 2598 "encrypt_required: %d " 2599 "directed: %d " 2600 "mpdu_frame_control_field: %d " 2601 "mpdu_duration_field: %d " 2602 "mac_addr_ad1_31_0: %d " 2603 "mac_addr_ad1_47_32: %d " 2604 "mac_addr_ad2_15_0: %d " 2605 "mac_addr_ad2_47_16: %d " 2606 "mac_addr_ad3_31_0: %d " 2607 "mac_addr_ad3_47_32: %d " 2608 "mpdu_sequence_control_field: %d " 2609 "mac_addr_ad4_31_0: %d " 2610 "mac_addr_ad4_47_32: %d " 2611 "mpdu_qos_control_field: %d " 2612 "mpdu_ht_control_field: %d ", 2613 mpdu_info->rxpcu_mpdu_filter_in_category, 2614 mpdu_info->sw_frame_group_id, 2615 mpdu_info->ndp_frame, 2616 mpdu_info->phy_err, 2617 mpdu_info->phy_err_during_mpdu_header, 2618 mpdu_info->protocol_version_err, 2619 mpdu_info->ast_based_lookup_valid, 2620 mpdu_info->phy_ppdu_id, 2621 mpdu_info->ast_index, 2622 mpdu_info->sw_peer_id, 2623 mpdu_info->mpdu_frame_control_valid, 2624 mpdu_info->mpdu_duration_valid, 2625 mpdu_info->mac_addr_ad1_valid, 2626 mpdu_info->mac_addr_ad2_valid, 2627 mpdu_info->mac_addr_ad3_valid, 2628 mpdu_info->mac_addr_ad4_valid, 2629 mpdu_info->mpdu_sequence_control_valid, 2630 mpdu_info->mpdu_qos_control_valid, 2631 mpdu_info->mpdu_ht_control_valid, 2632 mpdu_info->frame_encryption_info_valid, 2633 mpdu_info->fr_ds, 2634 mpdu_info->to_ds, 2635 mpdu_info->encrypted, 2636 mpdu_info->mpdu_retry, 2637 mpdu_info->mpdu_sequence_number, 2638 mpdu_info->epd_en, 2639 mpdu_info->all_frames_shall_be_encrypted, 2640 mpdu_info->encrypt_type, 2641 mpdu_info->mesh_sta, 2642 mpdu_info->bssid_hit, 2643 mpdu_info->bssid_number, 2644 mpdu_info->tid, 2645 mpdu_info->pn_31_0, 2646 mpdu_info->pn_63_32, 2647 mpdu_info->pn_95_64, 2648 mpdu_info->pn_127_96, 2649 mpdu_info->peer_meta_data, 2650 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 2651 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 2652 mpdu_info->rx_reo_queue_desc_addr_31_0, 2653 mpdu_info->rx_reo_queue_desc_addr_39_32, 2654 mpdu_info->receive_queue_number, 2655 mpdu_info->pre_delim_err_warning, 2656 mpdu_info->first_delim_err, 2657 mpdu_info->key_id_octet, 2658 mpdu_info->new_peer_entry, 2659 mpdu_info->decrypt_needed, 2660 mpdu_info->decap_type, 2661 mpdu_info->rx_insert_vlan_c_tag_padding, 2662 mpdu_info->rx_insert_vlan_s_tag_padding, 2663 mpdu_info->strip_vlan_c_tag_decap, 2664 mpdu_info->strip_vlan_s_tag_decap, 2665 mpdu_info->pre_delim_count, 2666 mpdu_info->ampdu_flag, 2667 mpdu_info->bar_frame, 2668 mpdu_info->mpdu_length, 2669 mpdu_info->first_mpdu, 2670 mpdu_info->mcast_bcast, 2671 mpdu_info->ast_index_not_found, 2672 mpdu_info->ast_index_timeout, 2673 mpdu_info->power_mgmt, 2674 mpdu_info->non_qos, 2675 mpdu_info->null_data, 2676 mpdu_info->mgmt_type, 2677 mpdu_info->ctrl_type, 2678 mpdu_info->more_data, 2679 mpdu_info->eosp, 2680 mpdu_info->fragment_flag, 2681 mpdu_info->order, 2682 mpdu_info->u_apsd_trigger, 2683 mpdu_info->encrypt_required, 2684 mpdu_info->directed, 2685 mpdu_info->mpdu_frame_control_field, 2686 mpdu_info->mpdu_duration_field, 2687 mpdu_info->mac_addr_ad1_31_0, 2688 mpdu_info->mac_addr_ad1_47_32, 2689 mpdu_info->mac_addr_ad2_15_0, 2690 mpdu_info->mac_addr_ad2_47_16, 2691 mpdu_info->mac_addr_ad3_31_0, 2692 mpdu_info->mac_addr_ad3_47_32, 2693 mpdu_info->mpdu_sequence_control_field, 2694 mpdu_info->mac_addr_ad4_31_0, 2695 mpdu_info->mac_addr_ad4_47_32, 2696 mpdu_info->mpdu_qos_control_field, 2697 mpdu_info->mpdu_ht_control_field); 2698 } 2699 2700 /** 2701 * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured 2702 * human readable format. 2703 * @ msdu_end: pointer the msdu_end TLV in pkt. 2704 * @ dbg_level: log level. 2705 * 2706 * Return: void 2707 */ 2708 static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc, 2709 struct rx_msdu_end *msdu_end, 2710 uint8_t dbg_level) 2711 { 2712 hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level); 2713 } 2714 2715 /** 2716 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 2717 * human readable format. 2718 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 2719 * @ dbg_level: log level. 2720 * 2721 * Return: void 2722 */ 2723 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 2724 uint8_t dbg_level) 2725 { 2726 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2727 "rx_mpdu_end tlv - " 2728 "rxpcu_mpdu_filter_in_category: %d " 2729 "sw_frame_group_id: %d " 2730 "phy_ppdu_id: %d " 2731 "unsup_ktype_short_frame: %d " 2732 "rx_in_tx_decrypt_byp: %d " 2733 "overflow_err: %d " 2734 "mpdu_length_err: %d " 2735 "tkip_mic_err: %d " 2736 "decrypt_err: %d " 2737 "unencrypted_frame_err: %d " 2738 "pn_fields_contain_valid_info: %d " 2739 "fcs_err: %d " 2740 "msdu_length_err: %d " 2741 "rxdma0_destination_ring: %d " 2742 "rxdma1_destination_ring: %d " 2743 "decrypt_status_code: %d " 2744 "rx_bitmap_not_updated: %d ", 2745 mpdu_end->rxpcu_mpdu_filter_in_category, 2746 mpdu_end->sw_frame_group_id, 2747 mpdu_end->phy_ppdu_id, 2748 mpdu_end->unsup_ktype_short_frame, 2749 mpdu_end->rx_in_tx_decrypt_byp, 2750 mpdu_end->overflow_err, 2751 mpdu_end->mpdu_length_err, 2752 mpdu_end->tkip_mic_err, 2753 mpdu_end->decrypt_err, 2754 mpdu_end->unencrypted_frame_err, 2755 mpdu_end->pn_fields_contain_valid_info, 2756 mpdu_end->fcs_err, 2757 mpdu_end->msdu_length_err, 2758 mpdu_end->rxdma0_destination_ring, 2759 mpdu_end->rxdma1_destination_ring, 2760 mpdu_end->decrypt_status_code, 2761 mpdu_end->rx_bitmap_not_updated); 2762 } 2763 2764 /** 2765 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 2766 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 2767 * @ dbg_level: log level. 2768 * 2769 * Return: void 2770 */ 2771 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_hdr_tlv *pkt_hdr_tlv, 2772 uint8_t dbg_level) 2773 { 2774 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 2775 "\n---------------\n" 2776 "rx_pkt_hdr_tlv \n" 2777 "---------------\n" 2778 "phy_ppdu_id %d ", 2779 pkt_hdr_tlv->phy_ppdu_id); 2780 2781 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, dbg_level, 2782 pkt_hdr_tlv->rx_pkt_hdr, 128); 2783 } 2784 2785 /** 2786 * hal_srng_ring_id_get: API to retrieve ring id from hal ring 2787 * structure 2788 * @hal_ring: pointer to hal_srng structure 2789 * 2790 * Return: ring_id 2791 */ 2792 static inline uint8_t hal_srng_ring_id_get(void *hal_ring) 2793 { 2794 return ((struct hal_srng *)hal_ring)->ring_id; 2795 } 2796 2797 /* Rx MSDU link pointer info */ 2798 struct hal_rx_msdu_link_ptr_info { 2799 struct rx_msdu_link msdu_link; 2800 struct hal_buf_info msdu_link_buf_info; 2801 }; 2802 2803 /** 2804 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 2805 * 2806 * @nbuf: Pointer to data buffer field 2807 * Returns: pointer to rx_pkt_tlvs 2808 */ 2809 static inline 2810 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 2811 { 2812 return (struct rx_pkt_tlvs *)rx_buf_start; 2813 } 2814 2815 /** 2816 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 2817 * 2818 * @pkt_tlvs: Pointer to pkt_tlvs 2819 * Returns: pointer to rx_mpdu_info structure 2820 */ 2821 static inline 2822 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 2823 { 2824 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 2825 } 2826 2827 /** 2828 * hal_rx_get_rx_sequence(): Function to retrieve rx sequence number 2829 * 2830 * @nbuf: Network buffer 2831 * Returns: rx sequence number 2832 */ 2833 #define DOT11_SEQ_FRAG_MASK 0x000f 2834 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04 2835 2836 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 2837 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2838 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 2839 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 2840 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 2841 static inline 2842 uint16_t hal_rx_get_rx_sequence(uint8_t *buf) 2843 { 2844 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2845 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2846 uint16_t seq_number = 0; 2847 2848 seq_number = 2849 HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) >> 4; 2850 2851 /* Skip first 4-bits for fragment number */ 2852 return seq_number; 2853 } 2854 2855 /** 2856 * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number 2857 * 2858 * @nbuf: Network buffer 2859 * Returns: rx fragment number 2860 */ 2861 static inline 2862 uint8_t hal_rx_get_rx_fragment_number(uint8_t *buf) 2863 { 2864 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2865 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2866 uint8_t frag_number = 0; 2867 2868 frag_number = HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 2869 DOT11_SEQ_FRAG_MASK; 2870 2871 /* Return first 4 bits as fragment number */ 2872 return frag_number; 2873 } 2874 2875 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 2876 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2877 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 2878 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 2879 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 2880 /** 2881 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 2882 * 2883 * @nbuf: Network buffer 2884 * Returns: rx more fragment bit 2885 */ 2886 static inline 2887 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 2888 { 2889 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2890 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2891 uint16_t frame_ctrl = 0; 2892 2893 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 2894 DOT11_FC1_MORE_FRAG_OFFSET; 2895 2896 /* more fragment bit if at offset bit 4 */ 2897 return frame_ctrl; 2898 } 2899 2900 /** 2901 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2902 * 2903 * @nbuf: Network buffer 2904 * Returns: rx more fragment bit 2905 * 2906 */ 2907 static inline 2908 uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf) 2909 { 2910 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2911 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2912 uint16_t frame_ctrl = 0; 2913 2914 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2915 2916 return frame_ctrl; 2917 } 2918 2919 /* 2920 * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address 2921 * 2922 * @nbuf: Network buffer 2923 * Returns: flag to indicate whether the nbuf has MC/BC address 2924 */ 2925 static inline 2926 uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf) 2927 { 2928 uint8 *buf = qdf_nbuf_data(nbuf); 2929 2930 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2931 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 2932 2933 return rx_attn->mcast_bcast; 2934 } 2935 2936 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 2937 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2938 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 2939 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 2940 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 2941 /* 2942 * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid 2943 * 2944 * @nbuf: Network buffer 2945 * Returns: value of sequence control valid field 2946 */ 2947 static inline 2948 uint8_t hal_rx_get_mpdu_sequence_control_valid(uint8_t *buf) 2949 { 2950 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2951 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2952 uint8_t seq_ctrl_valid = 0; 2953 2954 seq_ctrl_valid = 2955 HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 2956 2957 return seq_ctrl_valid; 2958 } 2959 2960 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 2961 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2962 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 2963 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 2964 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 2965 /* 2966 * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid 2967 * 2968 * @nbuf: Network buffer 2969 * Returns: value of frame control valid field 2970 */ 2971 static inline 2972 uint8_t hal_rx_get_mpdu_frame_control_valid(uint8_t *buf) 2973 { 2974 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2975 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2976 uint8_t frm_ctrl_valid = 0; 2977 2978 frm_ctrl_valid = 2979 HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 2980 2981 return frm_ctrl_valid; 2982 } 2983 2984 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 2985 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 2986 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 2987 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 2988 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 2989 /* 2990 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 2991 * 2992 * @nbuf: Network buffer 2993 * Returns: value of mpdu 4th address valid field 2994 */ 2995 static inline 2996 bool hal_rx_get_mpdu_mac_ad4_valid(uint8_t *buf) 2997 { 2998 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2999 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 3000 bool ad4_valid = 0; 3001 3002 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 3003 3004 return ad4_valid; 3005 } 3006 3007 /* 3008 * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info 3009 * 3010 * @rx_mpdu_desc_info: HAL view of rx mpdu desc info 3011 * Returns: None 3012 */ 3013 static inline 3014 void hal_rx_clear_mpdu_desc_info( 3015 struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info) 3016 { 3017 qdf_mem_zero(rx_mpdu_desc_info, 3018 sizeof(*rx_mpdu_desc_info)); 3019 } 3020 3021 /* 3022 * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr 3023 * 3024 * @msdu_link_ptr: HAL view of msdu link ptr 3025 * @size: number of msdu link pointers 3026 * Returns: None 3027 */ 3028 static inline 3029 void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr, 3030 int size) 3031 { 3032 qdf_mem_zero(msdu_link_ptr, 3033 (sizeof(*msdu_link_ptr) * size)); 3034 } 3035 3036 /* 3037 * hal_rx_chain_msdu_links() - Chains msdu link pointers 3038 * @msdu_link_ptr: msdu link pointer 3039 * @mpdu_desc_info: mpdu descriptor info 3040 * 3041 * Build a list of msdus using msdu link pointer. If the 3042 * number of msdus are more, chain them together 3043 * 3044 * Returns: Number of processed msdus 3045 */ 3046 static inline 3047 int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu, 3048 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 3049 struct hal_rx_mpdu_desc_info *mpdu_desc_info) 3050 { 3051 int j; 3052 struct rx_msdu_link *msdu_link_ptr = 3053 &msdu_link_ptr_info->msdu_link; 3054 struct rx_msdu_link *prev_msdu_link_ptr = NULL; 3055 struct rx_msdu_details *msdu_details = 3056 hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc); 3057 uint8_t num_msdus = mpdu_desc_info->msdu_count; 3058 struct rx_msdu_desc_info *msdu_desc_info; 3059 uint8_t fragno, more_frag; 3060 uint8_t *rx_desc_info; 3061 struct hal_rx_msdu_list msdu_list; 3062 3063 for (j = 0; j < num_msdus; j++) { 3064 msdu_desc_info = 3065 hal_rx_msdu_desc_info_get_ptr(&msdu_details[j], 3066 hal_soc); 3067 msdu_list.msdu_info[j].msdu_flags = 3068 HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 3069 msdu_list.msdu_info[j].msdu_len = 3070 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 3071 msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET( 3072 &msdu_details[j].buffer_addr_info_details); 3073 } 3074 3075 /* Chain msdu links together */ 3076 if (prev_msdu_link_ptr) { 3077 /* 31-0 bits of the physical address */ 3078 prev_msdu_link_ptr-> 3079 next_msdu_link_desc_addr_info.buffer_addr_31_0 = 3080 msdu_link_ptr_info->msdu_link_buf_info.paddr & 3081 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK; 3082 /* 39-32 bits of the physical address */ 3083 prev_msdu_link_ptr-> 3084 next_msdu_link_desc_addr_info.buffer_addr_39_32 3085 = ((msdu_link_ptr_info->msdu_link_buf_info.paddr 3086 >> 32) && 3087 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK); 3088 prev_msdu_link_ptr-> 3089 next_msdu_link_desc_addr_info.sw_buffer_cookie = 3090 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie; 3091 } 3092 3093 /* There is space for only 6 MSDUs in a MSDU link descriptor */ 3094 if (num_msdus < HAL_RX_NUM_MSDU_DESC) { 3095 /* mark first and last MSDUs */ 3096 rx_desc_info = qdf_nbuf_data(msdu); 3097 fragno = hal_rx_get_rx_fragment_number(rx_desc_info); 3098 more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info); 3099 3100 /* TODO: create skb->fragslist[] */ 3101 3102 if (more_frag == 0) { 3103 msdu_list.msdu_info[num_msdus].msdu_flags |= 3104 RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK; 3105 } else if (fragno == 1) { 3106 msdu_list.msdu_info[num_msdus].msdu_flags |= 3107 RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK; 3108 3109 msdu_list.msdu_info[num_msdus].msdu_flags |= 3110 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK; 3111 } 3112 3113 num_msdus++; 3114 3115 /* Number of MSDUs per mpdu descriptor is updated */ 3116 mpdu_desc_info->msdu_count += num_msdus; 3117 } else { 3118 num_msdus = 0; 3119 prev_msdu_link_ptr = msdu_link_ptr; 3120 } 3121 3122 return num_msdus; 3123 } 3124 3125 /* 3126 * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc 3127 * 3128 * @ring_desc: HAL view of ring descriptor 3129 * @mpdu_des_info: saved mpdu desc info 3130 * @msdu_link_ptr: saved msdu link ptr 3131 * 3132 * API used explicitly for rx defrag to update ring desc with 3133 * mpdu desc info and msdu link ptr before reinjecting the 3134 * packet back to REO 3135 * 3136 * Returns: None 3137 */ 3138 static inline 3139 void hal_rx_defrag_update_src_ring_desc(void *ring_desc, 3140 void *saved_mpdu_desc_info, 3141 struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr) 3142 { 3143 struct reo_entrance_ring *reo_ent_ring; 3144 struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info; 3145 struct hal_buf_info buf_info; 3146 3147 reo_ent_ring = (struct reo_entrance_ring *)ring_desc; 3148 reo_ring_mpdu_desc_info = &reo_ent_ring-> 3149 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 3150 3151 qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info, 3152 sizeof(*reo_ring_mpdu_desc_info)); 3153 3154 /* 3155 * TODO: Check for additional fields that need configuration in 3156 * reo_ring_mpdu_desc_info 3157 */ 3158 3159 /* Update msdu_link_ptr in the reo entrance ring */ 3160 hal_rx_reo_buf_paddr_get(ring_desc, &buf_info); 3161 buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr; 3162 buf_info.sw_cookie = 3163 saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie; 3164 } 3165 3166 /* 3167 * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc 3168 * 3169 * @msdu_link_desc_va: msdu link descriptor handle 3170 * @msdu_link_ptr_info: HAL view of msdu link pointer info 3171 * 3172 * API used to save msdu link information along with physical 3173 * address. The API also copues the sw cookie. 3174 * 3175 * Returns: None 3176 */ 3177 static inline 3178 void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va, 3179 struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info, 3180 struct hal_buf_info *hbi) 3181 { 3182 struct rx_msdu_link *msdu_link_ptr = 3183 (struct rx_msdu_link *)msdu_link_desc_va; 3184 3185 qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr, 3186 sizeof(struct rx_msdu_link)); 3187 3188 msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr; 3189 msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie; 3190 } 3191 3192 /* 3193 * hal_rx_get_desc_len(): Returns rx descriptor length 3194 * 3195 * Returns the size of rx_pkt_tlvs which follows the 3196 * data in the nbuf 3197 * 3198 * Returns: Length of rx descriptor 3199 */ 3200 static inline 3201 uint16_t hal_rx_get_desc_len(void) 3202 { 3203 return sizeof(struct rx_pkt_tlvs); 3204 } 3205 3206 /* 3207 * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from 3208 * reo_entrance_ring descriptor 3209 * 3210 * @reo_ent_desc: reo_entrance_ring descriptor 3211 * Returns: value of rxdma_push_reason 3212 */ 3213 static inline 3214 uint8_t hal_rx_reo_ent_rxdma_push_reason_get(void *reo_ent_desc) 3215 { 3216 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3217 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)), 3218 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK, 3219 REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB); 3220 } 3221 3222 /** 3223 * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from 3224 * reo_entrance_ring descriptor 3225 * @reo_ent_desc: reo_entrance_ring descriptor 3226 * Return: value of rxdma_error_code 3227 */ 3228 static inline 3229 uint8_t hal_rx_reo_ent_rxdma_error_code_get(void *reo_ent_desc) 3230 { 3231 return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, 3232 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)), 3233 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK, 3234 REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB); 3235 } 3236 3237 /** 3238 * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and 3239 * save it to hal_wbm_err_desc_info structure passed by caller 3240 * @wbm_desc: wbm ring descriptor 3241 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3242 * Return: void 3243 */ 3244 static inline void hal_rx_wbm_err_info_get(void *wbm_desc, 3245 struct hal_wbm_err_desc_info *wbm_er_info) 3246 { 3247 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 3248 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 3249 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 3250 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 3251 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 3252 } 3253 3254 /** 3255 * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to 3256 * the reserved bytes of rx_tlv_hdr 3257 * @buf: start of rx_tlv_hdr 3258 * @wbm_er_info: hal_wbm_err_desc_info structure 3259 * Return: void 3260 */ 3261 static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf, 3262 struct hal_wbm_err_desc_info *wbm_er_info) 3263 { 3264 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3265 3266 qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info, 3267 sizeof(struct hal_wbm_err_desc_info)); 3268 } 3269 3270 /** 3271 * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from 3272 * the reserved bytes of rx_tlv_hdr. 3273 * @buf: start of rx_tlv_hdr 3274 * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter. 3275 * Return: void 3276 */ 3277 static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf, 3278 struct hal_wbm_err_desc_info *wbm_er_info) 3279 { 3280 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3281 3282 qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0, 3283 sizeof(struct hal_wbm_err_desc_info)); 3284 } 3285 3286 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 3287 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 3288 RX_MSDU_START_5_NSS_OFFSET)), \ 3289 RX_MSDU_START_5_NSS_MASK, \ 3290 RX_MSDU_START_5_NSS_LSB)) 3291 3292 /** 3293 * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status 3294 * 3295 * @ hal_soc: HAL version of the SOC pointer 3296 * @ hw_desc_addr: Start address of Rx HW TLVs 3297 * @ rs: Status for monitor mode 3298 * 3299 * Return: void 3300 */ 3301 static inline void hal_rx_mon_hw_desc_get_mpdu_status(struct hal_soc *hal_soc, 3302 void *hw_desc_addr, 3303 struct mon_rx_status *rs) 3304 { 3305 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs); 3306 } 3307 3308 /* 3309 * hal_rx_get_tlv(): API to get the tlv 3310 * 3311 * @hal_soc: HAL version of the SOC pointer 3312 * @rx_tlv: TLV data extracted from the rx packet 3313 * Return: uint8_t 3314 */ 3315 static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv) 3316 { 3317 return hal_soc->ops->hal_rx_get_tlv(rx_tlv); 3318 } 3319 3320 /* 3321 * hal_rx_msdu_start_nss_get(): API to get the NSS 3322 * Interval from rx_msdu_start 3323 * 3324 * @hal_soc: HAL version of the SOC pointer 3325 * @buf: pointer to the start of RX PKT TLV header 3326 * Return: uint32_t(nss) 3327 */ 3328 static inline uint32_t hal_rx_msdu_start_nss_get(struct hal_soc *hal_soc, 3329 uint8_t *buf) 3330 { 3331 return hal_soc->ops->hal_rx_msdu_start_nss_get(buf); 3332 } 3333 3334 /** 3335 * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured 3336 * human readable format. 3337 * @ msdu_start: pointer the msdu_start TLV in pkt. 3338 * @ dbg_level: log level. 3339 * 3340 * Return: void 3341 */ 3342 static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc, 3343 struct rx_msdu_start *msdu_start, 3344 uint8_t dbg_level) 3345 { 3346 hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level); 3347 } 3348 3349 /** 3350 * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start 3351 * info details 3352 * 3353 * @ buf - Pointer to buffer containing rx pkt tlvs. 3354 * 3355 * 3356 */ 3357 static inline uint32_t hal_rx_mpdu_start_tid_get(struct hal_soc *hal_soc, 3358 uint8_t *buf) 3359 { 3360 return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf); 3361 } 3362 3363 /* 3364 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 3365 * Interval from rx_msdu_start 3366 * 3367 * @buf: pointer to the start of RX PKT TLV header 3368 * Return: uint32_t(reception_type) 3369 */ 3370 static inline 3371 uint32_t hal_rx_msdu_start_reception_type_get(struct hal_soc *hal_soc, 3372 uint8_t *buf) 3373 { 3374 return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf); 3375 } 3376 3377 /** 3378 * hal_rx_dump_pkt_tlvs: API to print all member elements of 3379 * RX TLVs 3380 * @ buf: pointer the pkt buffer. 3381 * @ dbg_level: log level. 3382 * 3383 * Return: void 3384 */ 3385 static inline void hal_rx_dump_pkt_tlvs(struct hal_soc *hal_soc, 3386 uint8_t *buf, uint8_t dbg_level) 3387 { 3388 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 3389 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 3390 struct rx_mpdu_start *mpdu_start = 3391 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 3392 struct rx_msdu_start *msdu_start = 3393 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 3394 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 3395 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 3396 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 3397 3398 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 3399 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level); 3400 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 3401 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 3402 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 3403 hal_rx_dump_pkt_hdr_tlv(pkt_hdr_tlv, dbg_level); 3404 } 3405 3406 3407 /** 3408 * hal_reo_status_get_header_generic - Process reo desc info 3409 * @d - Pointer to reo descriptior 3410 * @b - tlv type info 3411 * @h - Pointer to hal_reo_status_header where info to be stored 3412 * @hal- pointer to hal_soc structure 3413 * Return - none. 3414 * 3415 */ 3416 static inline void hal_reo_status_get_header(uint32_t *d, int b, 3417 void *h, void *hal) 3418 { 3419 struct hal_soc *hal_soc = (struct hal_soc *)hal; 3420 3421 hal_soc->ops->hal_reo_status_get_header(d, b, h); 3422 } 3423 3424 #endif /* _HAL_RX_H */ 3425