1 /* 2 * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_REO_H_ 20 #define _HAL_REO_H_ 21 22 #include <qdf_types.h> 23 /* HW headers */ 24 #include <reo_descriptor_threshold_reached_status.h> 25 #include <reo_flush_queue.h> 26 #include <reo_flush_timeout_list_status.h> 27 #include <reo_unblock_cache.h> 28 #include <reo_flush_cache.h> 29 #include <reo_flush_queue_status.h> 30 #include <reo_get_queue_stats.h> 31 #include <reo_unblock_cache_status.h> 32 #include <reo_flush_cache_status.h> 33 #include <reo_flush_timeout_list.h> 34 #include <reo_get_queue_stats_status.h> 35 #include <reo_update_rx_reo_queue.h> 36 #include <reo_update_rx_reo_queue_status.h> 37 #include <tlv_tag_def.h> 38 39 /* SW headers */ 40 #include "hal_api.h" 41 #include "hal_rx_hw_defines.h" 42 43 /*--------------------------------------------------------------------------- 44 Preprocessor definitions and constants 45 ---------------------------------------------------------------------------*/ 46 47 /* TLV values */ 48 #define HAL_REO_GET_QUEUE_STATS_TLV WIFIREO_GET_QUEUE_STATS_E 49 #define HAL_REO_FLUSH_QUEUE_TLV WIFIREO_FLUSH_QUEUE_E 50 #define HAL_REO_FLUSH_CACHE_TLV WIFIREO_FLUSH_CACHE_E 51 #define HAL_REO_UNBLOCK_CACHE_TLV WIFIREO_UNBLOCK_CACHE_E 52 #define HAL_REO_FLUSH_TIMEOUT_LIST_TLV WIFIREO_FLUSH_TIMEOUT_LIST_E 53 #define HAL_REO_RX_UPDATE_QUEUE_TLV WIFIREO_UPDATE_RX_REO_QUEUE_E 54 55 #define HAL_REO_QUEUE_STATS_STATUS_TLV WIFIREO_GET_QUEUE_STATS_STATUS_E 56 #define HAL_REO_FLUSH_QUEUE_STATUS_TLV WIFIREO_FLUSH_QUEUE_STATUS_E 57 #define HAL_REO_FLUSH_CACHE_STATUS_TLV WIFIREO_FLUSH_CACHE_STATUS_E 58 #define HAL_REO_UNBLK_CACHE_STATUS_TLV WIFIREO_UNBLOCK_CACHE_STATUS_E 59 #define HAL_REO_TIMOUT_LIST_STATUS_TLV WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E 60 #define HAL_REO_DESC_THRES_STATUS_TLV \ 61 WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E 62 #define HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E 63 64 #define HAL_SET_FIELD(block, field, value) \ 65 ((value << (block ## _ ## field ## _LSB)) & \ 66 (block ## _ ## field ## _MASK)) 67 68 #define HAL_GET_FIELD(block, field, value) \ 69 ((value & (block ## _ ## field ## _MASK)) >> \ 70 (block ## _ ## field ## _LSB)) 71 72 #define HAL_SET_TLV_HDR(desc, tag, len) \ 73 do { \ 74 ((struct tlv_32_hdr *) desc)->tlv_tag = tag; \ 75 ((struct tlv_32_hdr *) desc)->tlv_len = len; \ 76 } while (0) 77 78 #define HAL_GET_TLV(desc) (((struct tlv_32_hdr *) desc)->tlv_tag) 79 80 #define HAL_OFFSET_DW(_block, _field) (HAL_OFFSET(_block, _field) >> 2) 81 #define HAL_OFFSET_QW(_block, _field) (HAL_OFFSET(_block, _field) >> 3) 82 /* dword offsets in REO cmd TLV */ 83 #define CMD_HEADER_DW_OFFSET 0 84 85 /* TODO: See if the following definition is available in HW headers */ 86 #define HAL_REO_OWNED 4 87 #define HAL_REO_QUEUE_DESC 8 88 89 /* TODO: Using associated link desc counter 1 for Rx. Check with FW on 90 * how these counters are assigned 91 */ 92 #define HAL_RX_LINK_DESC_CNTR 1 93 /* TODO: Following definition should be from HW headers */ 94 #define HAL_DESC_REO_OWNED 4 95 96 #ifndef TID_TO_WME_AC 97 /** 98 * enum hal_wme_access_category: Access category enums 99 * @WME_AC_BE: best effort 100 * @WME_AC_BK: background 101 * @WME_AC_VI: video 102 * @WME_AC_VO: voice 103 */ 104 enum hal_wme_access_category { 105 WME_AC_BE, 106 WME_AC_BK, 107 WME_AC_VI, 108 WME_AC_VO 109 }; 110 111 #define TID_TO_WME_AC(_tid) ( \ 112 (((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 113 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 114 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 115 WME_AC_VO) 116 #endif 117 #define HAL_NON_QOS_TID 16 118 119 /** 120 * enum reo_unblock_cache_type: Enum for unblock type in REO unblock command 121 * @UNBLOCK_RES_INDEX: Unblock a block resource 122 * @UNBLOCK_CACHE: Unblock cache 123 */ 124 enum reo_unblock_cache_type { 125 UNBLOCK_RES_INDEX = 0, 126 UNBLOCK_CACHE = 1 127 }; 128 129 /** 130 * enum reo_thres_index_reg: Enum for reo descriptor usage counter for 131 * which threshold status is being indicated. 132 * @reo_desc_counter0_threshold: counter0 reached threshold 133 * @reo_desc_counter1_threshold: counter1 reached threshold 134 * @reo_desc_counter2_threshold: counter2 reached threshold 135 * @reo_desc_counter_sum_threshold: Total count reached threshold 136 */ 137 enum reo_thres_index_reg { 138 reo_desc_counter0_threshold = 0, 139 reo_desc_counter1_threshold = 1, 140 reo_desc_counter2_threshold = 2, 141 reo_desc_counter_sum_threshold = 3 142 }; 143 144 /** 145 * enum reo_cmd_exec_status: Enum for execution status of REO command 146 * 147 * @HAL_REO_CMD_SUCCESS: Command has successfully be executed 148 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue or cache 149 * was blocked 150 * @HAL_REO_CMD_FAILED: Command has encountered problems when executing, like 151 * the queue descriptor not being valid 152 */ 153 enum reo_cmd_exec_status { 154 HAL_REO_CMD_SUCCESS = 0, 155 HAL_REO_CMD_BLOCKED = 1, 156 HAL_REO_CMD_FAILED = 2, 157 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 158 HAL_REO_CMD_DRAIN = 0xff 159 }; 160 161 /** 162 * struct hal_reo_cmd_params_std: Standard REO command parameters 163 * @need_status: Status required for the command 164 * @addr_lo: Lower 32 bits of REO queue descriptor address 165 * @addr_hi: Upper 8 bits of REO queue descriptor address 166 */ 167 struct hal_reo_cmd_params_std { 168 bool need_status; 169 uint32_t addr_lo; 170 uint8_t addr_hi; 171 }; 172 173 /** 174 * struct hal_reo_cmd_get_queue_stats_params: Parameters to 175 * CMD_GET_QUEUE_STATScommand 176 * @clear: Clear stats after retreiving 177 */ 178 struct hal_reo_cmd_get_queue_stats_params { 179 bool clear; 180 }; 181 182 /** 183 * struct hal_reo_cmd_flush_queue_params: Parameters to CMD_FLUSH_QUEUE 184 * @use_after_flush: Block usage after flush till unblock command 185 * @index: Blocking resource to be used 186 */ 187 struct hal_reo_cmd_flush_queue_params { 188 bool block_use_after_flush; 189 uint8_t index; 190 }; 191 192 /** 193 * struct hal_reo_cmd_flush_cache_params: Parameters to CMD_FLUSH_CACHE 194 * @fwd_mpdus_in_queue: Forward MPDUs before flushing descriptor 195 * @rel_block_index: Release blocking resource used earlier 196 * @cache_block_res_index: Blocking resource to be used 197 * @flush_no_inval: Flush without invalidatig descriptor 198 * @use_after_flush: Block usage after flush till unblock command 199 * @flush_entire_cache: Flush entire REO cache 200 */ 201 struct hal_reo_cmd_flush_cache_params { 202 bool fwd_mpdus_in_queue; 203 bool rel_block_index; 204 uint8_t cache_block_res_index; 205 bool flush_no_inval; 206 bool block_use_after_flush; 207 bool flush_entire_cache; 208 }; 209 210 /** 211 * struct hal_reo_cmd_unblock_cache_params: Parameters to CMD_UNBLOCK_CACHE 212 * @type: Unblock type (enum reo_unblock_cache_type) 213 * @index: Blocking index to be released 214 */ 215 struct hal_reo_cmd_unblock_cache_params { 216 enum reo_unblock_cache_type type; 217 uint8_t index; 218 }; 219 220 /** 221 * struct hal_reo_cmd_flush_timeout_list_params: Parameters to 222 * CMD_FLUSH_TIMEOUT_LIST 223 * @ac_list: AC timeout list to be flushed 224 * @min_rel_desc: Min. number of link descriptors to be release 225 * @min_fwd_buf: Min. number of buffers to be forwarded 226 */ 227 struct hal_reo_cmd_flush_timeout_list_params { 228 uint8_t ac_list; 229 uint16_t min_rel_desc; 230 uint16_t min_fwd_buf; 231 }; 232 233 /** 234 * struct hal_reo_cmd_update_queue_params: Parameters to CMD_UPDATE_RX_REO_QUEUE 235 * @update_rx_queue_num: Update receive queue number 236 * @update_vld: Update valid bit 237 * @update_assoc_link_desc: Update associated link descriptor 238 * @update_disable_dup_detect: Update duplicate detection 239 * @update_soft_reorder_enab: Update soft reorder enable 240 * @update_ac: Update access category 241 * @update_bar: Update BAR received bit 242 * @update_rty: Update retry bit 243 * @update_chk_2k_mode: Update chk_2k_mode setting 244 * @update_oor_mode: Update OOR mode setting 245 * @update_ba_window_size: Update BA window size 246 * @update_pn_check_needed: Update pn_check_needed 247 * @update_pn_even: Update pn_even 248 * @update_pn_uneven: Update pn_uneven 249 * @update_pn_hand_enab: Update pn_handling_enable 250 * @update_pn_size: Update pn_size 251 * @update_ignore_ampdu: Update ignore_ampdu 252 * @update_svld: update svld 253 * @update_ssn: Update SSN 254 * @update_seq_2k_err_detect: Update seq_2k_err_detected flag 255 * @update_pn_err_detect: Update pn_err_detected flag 256 * @update_pn_valid: Update pn_valid 257 * @update_pn: Update PN 258 * @rx_queue_num: rx_queue_num to be updated 259 * @vld: valid bit to be updated 260 * @assoc_link_desc: assoc_link_desc counter 261 * @disable_dup_detect: disable_dup_detect to be updated 262 * @soft_reorder_enab: soft_reorder_enab to be updated 263 * @ac: AC to be updated 264 * @bar: BAR flag to be updated 265 * @rty: RTY flag to be updated 266 * @chk_2k_mode: check_2k_mode setting to be updated 267 * @oor_mode: oor_mode to be updated 268 * @pn_check_needed: pn_check_needed to be updated 269 * @pn_even: pn_even to be updated 270 * @pn_uneven: pn_uneven to be updated 271 * @pn_hand_enab: pn_handling_enable to be updated 272 * @ignore_ampdu: ignore_ampdu to be updated 273 * @ba_window_size: BA window size to be updated 274 * @pn_size: pn_size to be updated 275 * @svld: svld flag to be updated 276 * @ssn: SSN to be updated 277 * @seq_2k_err_detect: seq_2k_err_detected flag to be updated 278 * @pn_err_detect: pn_err_detected flag to be updated 279 * @pn_31_0: PN bits 31-0 280 * @pn_63_32: PN bits 63-32 281 * @pn_95_64: PN bits 95-64 282 * @pn_127_96: PN bits 127-96 283 */ 284 struct hal_reo_cmd_update_queue_params { 285 uint32_t update_rx_queue_num:1, 286 update_vld:1, 287 update_assoc_link_desc:1, 288 update_disable_dup_detect:1, 289 update_soft_reorder_enab:1, 290 update_ac:1, 291 update_bar:1, 292 update_rty:1, 293 update_chk_2k_mode:1, 294 update_oor_mode:1, 295 update_ba_window_size:1, 296 update_pn_check_needed:1, 297 update_pn_even:1, 298 update_pn_uneven:1, 299 update_pn_hand_enab:1, 300 update_pn_size:1, 301 update_ignore_ampdu:1, 302 update_svld:1, 303 update_ssn:1, 304 update_seq_2k_err_detect:1, 305 update_pn_err_detect:1, 306 update_pn_valid:1, 307 update_pn:1; 308 uint32_t rx_queue_num:16, 309 vld:1, 310 assoc_link_desc:2, 311 disable_dup_detect:1, 312 soft_reorder_enab:1, 313 ac:2, 314 bar:1, 315 rty:1, 316 chk_2k_mode:1, 317 oor_mode:1, 318 pn_check_needed:1, 319 pn_even:1, 320 pn_uneven:1, 321 pn_hand_enab:1, 322 ignore_ampdu:1; 323 uint32_t ba_window_size:9, 324 pn_size:8, 325 svld:1, 326 ssn:12, 327 seq_2k_err_detect:1, 328 pn_err_detect:1; 329 uint32_t pn_31_0:32; 330 uint32_t pn_63_32:32; 331 uint32_t pn_95_64:32; 332 uint32_t pn_127_96:32; 333 }; 334 335 /** 336 * struct hal_reo_cmd_params: Common structure to pass REO command parameters 337 * @hal_reo_cmd_params_std: Standard parameters 338 * @u: Union of various REO command parameters 339 */ 340 struct hal_reo_cmd_params { 341 struct hal_reo_cmd_params_std std; 342 union { 343 struct hal_reo_cmd_get_queue_stats_params stats_params; 344 struct hal_reo_cmd_flush_queue_params fl_queue_params; 345 struct hal_reo_cmd_flush_cache_params fl_cache_params; 346 struct hal_reo_cmd_unblock_cache_params unblk_cache_params; 347 struct hal_reo_cmd_flush_timeout_list_params fl_tim_list_params; 348 struct hal_reo_cmd_update_queue_params upd_queue_params; 349 } u; 350 }; 351 352 /** 353 * struct hal_reo_status_header: Common REO status header 354 * @cmd_num: Command number 355 * @exec_time: execution time 356 * @status: command execution status 357 * @tstamp: Timestamp of status updated 358 */ 359 struct hal_reo_status_header { 360 uint16_t cmd_num; 361 uint16_t exec_time; 362 enum reo_cmd_exec_status status; 363 uint32_t tstamp; 364 }; 365 366 /** 367 * struct hal_reo_queue_status: REO queue status structure 368 * @header: Common REO status header 369 * @ssn: SSN of current BA window 370 * @curr_idx: last forwarded pkt 371 * @pn_31_0, pn_63_32, pn_95_64, pn_127_96: 372 * PN number bits extracted from IV field 373 * @last_rx_enq_tstamp: Last enqueue timestamp 374 * @last_rx_deq_tstamp: Last dequeue timestamp 375 * @rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64 376 * @rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160 377 * @rx_bitmap_223_192, rx_bitmap_255_224: Each bit corresonds to a frame 378 * held in re-order queue 379 * @curr_mpdu_cnt, curr_msdu_cnt: Number of MPDUs and MSDUs in the queue 380 * @fwd_timeout_cnt: Frames forwarded due to timeout 381 * @fwd_bar_cnt: Frames forwarded BAR frame 382 * @dup_cnt: duplicate frames detected 383 * @frms_in_order_cnt: Frames received in order 384 * @bar_rcvd_cnt: BAR frame count 385 * @mpdu_frms_cnt, msdu_frms_cnt, total_cnt: MPDU, MSDU, total frames 386 processed by REO 387 * @late_recv_mpdu_cnt; received after window had moved on 388 * @win_jump_2k: 2K jump count 389 * @hole_cnt: sequence hole count 390 */ 391 struct hal_reo_queue_status { 392 struct hal_reo_status_header header; 393 uint16_t ssn; 394 uint8_t curr_idx; 395 uint32_t pn_31_0, pn_63_32, pn_95_64, pn_127_96; 396 uint32_t last_rx_enq_tstamp, last_rx_deq_tstamp; 397 uint32_t rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64; 398 uint32_t rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160; 399 uint32_t rx_bitmap_223_192, rx_bitmap_255_224; 400 uint8_t curr_mpdu_cnt, curr_msdu_cnt; 401 uint8_t fwd_timeout_cnt, fwd_bar_cnt; 402 uint16_t dup_cnt; 403 uint32_t frms_in_order_cnt; 404 uint8_t bar_rcvd_cnt; 405 uint32_t mpdu_frms_cnt, msdu_frms_cnt, total_cnt; 406 uint16_t late_recv_mpdu_cnt; 407 uint8_t win_jump_2k; 408 uint16_t hole_cnt; 409 }; 410 411 /** 412 * struct hal_reo_flush_queue_status: FLUSH_QUEUE status structure 413 * @header: Common REO status header 414 * @error: Error detected 415 */ 416 struct hal_reo_flush_queue_status { 417 struct hal_reo_status_header header; 418 bool error; 419 }; 420 421 /** 422 * struct hal_reo_flush_cache_status: FLUSH_CACHE status structure 423 * @header: Common REO status header 424 * @error: Error detected 425 * @block_error: Blocking related error 426 * @cache_flush_status: Cache hit/miss 427 * @cache_flush_status_desc_type: type of descriptor flushed 428 * @cache_flush_cnt: number of lines actually flushed 429 */ 430 struct hal_reo_flush_cache_status { 431 struct hal_reo_status_header header; 432 bool error; 433 uint8_t block_error; 434 bool cache_flush_status; 435 uint8_t cache_flush_status_desc_type; 436 uint8_t cache_flush_cnt; 437 }; 438 439 /** 440 * struct hal_reo_unblk_cache_status: UNBLOCK_CACHE status structure 441 * @header: Common REO status header 442 * @error: error detected 443 * unblock_type: resoure or cache 444 */ 445 struct hal_reo_unblk_cache_status { 446 struct hal_reo_status_header header; 447 bool error; 448 enum reo_unblock_cache_type unblock_type; 449 }; 450 451 /** 452 * struct hal_reo_flush_timeout_list_status: FLUSH_TIMEOUT_LIST status structure 453 * @header: Common REO status header 454 * @error: error detected 455 * @list_empty: timeout list empty 456 * @rel_desc_cnt: number of link descriptors released 457 * @fwd_buf_cnt: number of buffers forwarded to REO destination ring 458 */ 459 struct hal_reo_flush_timeout_list_status { 460 struct hal_reo_status_header header; 461 bool error; 462 bool list_empty; 463 uint16_t rel_desc_cnt; 464 uint16_t fwd_buf_cnt; 465 }; 466 467 /** 468 * struct hal_reo_desc_thres_reached_status: desc_thres_reached status structure 469 * @header: Common REO status header 470 * @thres_index: Index of descriptor threshold counter 471 * @link_desc_counter0, link_desc_counter1, link_desc_counter2: descriptor 472 * counter values 473 * @link_desc_counter_sum: overall descriptor count 474 */ 475 struct hal_reo_desc_thres_reached_status { 476 struct hal_reo_status_header header; 477 enum reo_thres_index_reg thres_index; 478 uint32_t link_desc_counter0, link_desc_counter1, link_desc_counter2; 479 uint32_t link_desc_counter_sum; 480 }; 481 482 /** 483 * struct hal_reo_update_rx_queue_status: UPDATE_RX_QUEUE status structure 484 * @header: Common REO status header 485 */ 486 struct hal_reo_update_rx_queue_status { 487 struct hal_reo_status_header header; 488 }; 489 490 /** 491 * union hal_reo_status: Union to pass REO status to callbacks 492 * @queue_status: Refer to struct hal_reo_queue_status 493 * @fl_cache_status: Refer to struct hal_reo_flush_cache_status 494 * @fl_queue_status: Refer to struct hal_reo_flush_queue_status 495 * @fl_timeout_status: Refer to struct hal_reo_flush_timeout_list_status 496 * @unblk_cache_status: Refer to struct hal_reo_unblk_cache_status 497 * @thres_status: struct hal_reo_desc_thres_reached_status 498 * @rx_queue_status: struct hal_reo_update_rx_queue_status 499 */ 500 union hal_reo_status { 501 struct hal_reo_queue_status queue_status; 502 struct hal_reo_flush_cache_status fl_cache_status; 503 struct hal_reo_flush_queue_status fl_queue_status; 504 struct hal_reo_flush_timeout_list_status fl_timeout_status; 505 struct hal_reo_unblk_cache_status unblk_cache_status; 506 struct hal_reo_desc_thres_reached_status thres_status; 507 struct hal_reo_update_rx_queue_status rx_queue_status; 508 }; 509 510 #ifdef HAL_DISABLE_NON_BA_2K_JUMP_ERROR 511 static inline uint32_t hal_update_non_ba_win_size(int tid, 512 uint32_t ba_window_size) 513 { 514 return ba_window_size; 515 } 516 #else 517 static inline uint32_t hal_update_non_ba_win_size(int tid, 518 uint32_t ba_window_size) 519 { 520 if ((ba_window_size == 1) && (tid != HAL_NON_QOS_TID)) 521 ba_window_size++; 522 523 return ba_window_size; 524 } 525 #endif 526 527 #define BLOCK_RES_MASK 0xF 528 static inline uint8_t hal_find_one_bit(uint8_t x) 529 { 530 uint8_t y = (x & (~x + 1)) & BLOCK_RES_MASK; 531 uint8_t pos; 532 533 for (pos = 0; y; y >>= 1) 534 pos++; 535 536 return pos-1; 537 } 538 539 static inline uint8_t hal_find_zero_bit(uint8_t x) 540 { 541 uint8_t y = (~x & (x+1)) & BLOCK_RES_MASK; 542 uint8_t pos; 543 544 for (pos = 0; y; y >>= 1) 545 pos++; 546 547 return pos-1; 548 } 549 550 /* REO command ring routines */ 551 552 /** 553 * hal_uniform_desc_hdr_setup - setup reo_queue_ext descritpro 554 * @owner - owner info 555 * @buffer_type - buffer type 556 */ 557 static inline void 558 hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner, uint32_t buffer_type) 559 { 560 HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, OWNER, 561 owner); 562 HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, BUFFER_TYPE, 563 buffer_type); 564 } 565 566 /** 567 * hal_reo_send_cmd() - Send reo cmd using the params provided. 568 * @hal_soc_hdl: HAL soc handle 569 * @hal_soc_hdl: srng handle 570 * @cmd: cmd ID 571 * @cmd_params: command params 572 * 573 * Return: cmd number 574 */ 575 static inline int 576 hal_reo_send_cmd(hal_soc_handle_t hal_soc_hdl, 577 hal_ring_handle_t hal_ring_hdl, 578 enum hal_reo_cmd_type cmd, 579 struct hal_reo_cmd_params *cmd_params) 580 { 581 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 582 583 if (!hal_soc || !hal_soc->ops) { 584 hal_err("hal handle is NULL"); 585 QDF_BUG(0); 586 return -EINVAL; 587 } 588 589 if (hal_soc->ops->hal_reo_send_cmd) 590 return hal_soc->ops->hal_reo_send_cmd(hal_soc_hdl, hal_ring_hdl, 591 cmd, cmd_params); 592 593 return -EINVAL; 594 } 595 596 static inline QDF_STATUS 597 hal_reo_status_update(hal_soc_handle_t hal_soc_hdl, 598 hal_ring_desc_t reo_desc, void *st_handle, 599 uint32_t tlv, int *num_ref) 600 { 601 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 602 603 if (hal_soc->ops->hal_reo_send_cmd) 604 return hal_soc->ops->hal_reo_status_update(hal_soc_hdl, 605 reo_desc, 606 st_handle, 607 tlv, num_ref); 608 return QDF_STATUS_E_FAILURE; 609 } 610 611 /* REO Status ring routines */ 612 static inline void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl, int tid, 613 uint32_t ba_window_size, 614 uint32_t start_seq, void *hw_qdesc_vaddr, 615 qdf_dma_addr_t hw_qdesc_paddr, 616 int pn_type) 617 { 618 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 619 620 if (!hal_soc || !hal_soc->ops) { 621 hal_err("hal handle is NULL"); 622 QDF_BUG(0); 623 return; 624 } 625 626 if (hal_soc->ops->hal_reo_qdesc_setup) 627 hal_soc->ops->hal_reo_qdesc_setup(hal_soc_hdl, tid, 628 ba_window_size, start_seq, 629 hw_qdesc_vaddr, 630 hw_qdesc_paddr, pn_type); 631 } 632 633 /** 634 * hal_get_ba_aging_timeout - Retrieve BA aging timeout 635 * 636 * @hal_soc: Opaque HAL SOC handle 637 * @ac: Access category 638 * @value: timeout duration in millisec 639 */ 640 static inline void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, 641 uint8_t ac, 642 uint32_t *value) 643 { 644 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 645 646 hal_soc->ops->hal_get_ba_aging_timeout(hal_soc_hdl, ac, value); 647 } 648 649 /** 650 * hal_set_aging_timeout - Set BA aging timeout 651 * 652 * @hal_soc: Opaque HAL SOC handle 653 * @ac: Access category in millisec 654 * @value: timeout duration value 655 */ 656 static inline void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, 657 uint8_t ac, 658 uint32_t value) 659 { 660 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 661 662 hal_soc->ops->hal_set_ba_aging_timeout(hal_soc_hdl, ac, value); 663 } 664 665 /** 666 * hal_get_reo_reg_base_offset() - Get REO register base offset 667 * @hal_soc_hdl: HAL soc handle 668 * 669 * Return: REO register base 670 */ 671 static inline uint32_t hal_get_reo_reg_base_offset(hal_soc_handle_t hal_soc_hdl) 672 { 673 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 674 675 return hal_soc->ops->hal_get_reo_reg_base_offset(); 676 } 677 678 static inline uint32_t 679 hal_gen_reo_remap_val(hal_soc_handle_t hal_soc_hdl, 680 enum hal_reo_remap_reg remap_reg, 681 uint8_t *ix0_map) 682 { 683 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 684 685 if (!hal_soc || !hal_soc->ops) { 686 hal_err("hal handle is NULL"); 687 QDF_BUG(0); 688 return 0; 689 } 690 691 if (hal_soc->ops->hal_gen_reo_remap_val) 692 return hal_soc->ops->hal_gen_reo_remap_val(remap_reg, ix0_map); 693 694 return 0; 695 } 696 697 static inline uint8_t 698 hal_get_tlv_hdr_size(hal_soc_handle_t hal_soc_hdl) 699 { 700 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 701 702 if (hal_soc->ops->hal_get_tlv_hdr_size) 703 return hal_soc->ops->hal_get_tlv_hdr_size(); 704 705 return 0; 706 } 707 /* Function Proto-types */ 708 709 /** 710 * hal_reo_init_cmd_ring() - Initialize descriptors of REO command SRNG 711 * with command number 712 * @hal_soc: Handle to HAL SoC structure 713 * @hal_ring: Handle to HAL SRNG structure 714 * Return: none 715 */ 716 void hal_reo_init_cmd_ring(hal_soc_handle_t hal_soc_hdl, 717 hal_ring_handle_t hal_ring_hdl); 718 #endif /* _HAL_REO_H */ 719