1 /* 2 * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_REO_H_ 21 #define _HAL_REO_H_ 22 23 #include <qdf_types.h> 24 /* HW headers */ 25 #include <reo_descriptor_threshold_reached_status.h> 26 #include <reo_flush_queue.h> 27 #include <reo_flush_timeout_list_status.h> 28 #include <reo_unblock_cache.h> 29 #include <reo_flush_cache.h> 30 #include <reo_flush_queue_status.h> 31 #include <reo_get_queue_stats.h> 32 #include <reo_unblock_cache_status.h> 33 #include <reo_flush_cache_status.h> 34 #include <reo_flush_timeout_list.h> 35 #include <reo_get_queue_stats_status.h> 36 #include <reo_update_rx_reo_queue.h> 37 #include <reo_update_rx_reo_queue_status.h> 38 #include <tlv_tag_def.h> 39 40 /* SW headers */ 41 #include "hal_api.h" 42 #include "hal_rx_hw_defines.h" 43 44 /*--------------------------------------------------------------------------- 45 Preprocessor definitions and constants 46 ---------------------------------------------------------------------------*/ 47 48 /* TLV values */ 49 #define HAL_REO_GET_QUEUE_STATS_TLV WIFIREO_GET_QUEUE_STATS_E 50 #define HAL_REO_FLUSH_QUEUE_TLV WIFIREO_FLUSH_QUEUE_E 51 #define HAL_REO_FLUSH_CACHE_TLV WIFIREO_FLUSH_CACHE_E 52 #define HAL_REO_UNBLOCK_CACHE_TLV WIFIREO_UNBLOCK_CACHE_E 53 #define HAL_REO_FLUSH_TIMEOUT_LIST_TLV WIFIREO_FLUSH_TIMEOUT_LIST_E 54 #define HAL_REO_RX_UPDATE_QUEUE_TLV WIFIREO_UPDATE_RX_REO_QUEUE_E 55 56 #define HAL_REO_QUEUE_STATS_STATUS_TLV WIFIREO_GET_QUEUE_STATS_STATUS_E 57 #define HAL_REO_FLUSH_QUEUE_STATUS_TLV WIFIREO_FLUSH_QUEUE_STATUS_E 58 #define HAL_REO_FLUSH_CACHE_STATUS_TLV WIFIREO_FLUSH_CACHE_STATUS_E 59 #define HAL_REO_UNBLK_CACHE_STATUS_TLV WIFIREO_UNBLOCK_CACHE_STATUS_E 60 #define HAL_REO_TIMOUT_LIST_STATUS_TLV WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E 61 #define HAL_REO_DESC_THRES_STATUS_TLV \ 62 WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E 63 #define HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E 64 65 #define HAL_SET_FIELD(block, field, value) \ 66 ((value << (block ## _ ## field ## _LSB)) & \ 67 (block ## _ ## field ## _MASK)) 68 69 #define HAL_GET_FIELD(block, field, value) \ 70 ((value & (block ## _ ## field ## _MASK)) >> \ 71 (block ## _ ## field ## _LSB)) 72 73 #define HAL_SET_TLV_HDR(desc, tag, len) \ 74 do { \ 75 ((struct tlv_32_hdr *) desc)->tlv_tag = tag; \ 76 ((struct tlv_32_hdr *) desc)->tlv_len = len; \ 77 } while (0) 78 79 #define HAL_GET_TLV(desc) (((struct tlv_32_hdr *) desc)->tlv_tag) 80 81 #define HAL_OFFSET_DW(_block, _field) (HAL_OFFSET(_block, _field) >> 2) 82 #define HAL_OFFSET_QW(_block, _field) (HAL_OFFSET(_block, _field) >> 3) 83 /* dword offsets in REO cmd TLV */ 84 #define CMD_HEADER_DW_OFFSET 0 85 86 /* TODO: See if the following definition is available in HW headers */ 87 #define HAL_REO_OWNED 4 88 #define HAL_REO_QUEUE_DESC 8 89 90 /* TODO: Using associated link desc counter 1 for Rx. Check with FW on 91 * how these counters are assigned 92 */ 93 #define HAL_RX_LINK_DESC_CNTR 1 94 /* TODO: Following definition should be from HW headers */ 95 #define HAL_DESC_REO_OWNED 4 96 97 #ifndef TID_TO_WME_AC 98 /** 99 * enum hal_wme_access_category: Access category enums 100 * @WME_AC_BE: best effort 101 * @WME_AC_BK: background 102 * @WME_AC_VI: video 103 * @WME_AC_VO: voice 104 */ 105 enum hal_wme_access_category { 106 WME_AC_BE, 107 WME_AC_BK, 108 WME_AC_VI, 109 WME_AC_VO 110 }; 111 112 #define TID_TO_WME_AC(_tid) ( \ 113 (((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 114 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 115 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 116 WME_AC_VO) 117 #endif 118 #define HAL_NON_QOS_TID 16 119 120 /** 121 * enum reo_unblock_cache_type: Enum for unblock type in REO unblock command 122 * @UNBLOCK_RES_INDEX: Unblock a block resource 123 * @UNBLOCK_CACHE: Unblock cache 124 */ 125 enum reo_unblock_cache_type { 126 UNBLOCK_RES_INDEX = 0, 127 UNBLOCK_CACHE = 1 128 }; 129 130 /** 131 * enum reo_thres_index_reg: Enum for reo descriptor usage counter for 132 * which threshold status is being indicated. 133 * @reo_desc_counter0_threshold: counter0 reached threshold 134 * @reo_desc_counter1_threshold: counter1 reached threshold 135 * @reo_desc_counter2_threshold: counter2 reached threshold 136 * @reo_desc_counter_sum_threshold: Total count reached threshold 137 */ 138 enum reo_thres_index_reg { 139 reo_desc_counter0_threshold = 0, 140 reo_desc_counter1_threshold = 1, 141 reo_desc_counter2_threshold = 2, 142 reo_desc_counter_sum_threshold = 3 143 }; 144 145 /** 146 * enum reo_cmd_exec_status: Enum for execution status of REO command 147 * 148 * @HAL_REO_CMD_SUCCESS: Command has successfully be executed 149 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue or cache 150 * was blocked 151 * @HAL_REO_CMD_FAILED: Command has encountered problems when executing, like 152 * the queue descriptor not being valid 153 */ 154 enum reo_cmd_exec_status { 155 HAL_REO_CMD_SUCCESS = 0, 156 HAL_REO_CMD_BLOCKED = 1, 157 HAL_REO_CMD_FAILED = 2, 158 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 159 HAL_REO_CMD_DRAIN = 0xff 160 }; 161 162 /** 163 * struct hal_reo_cmd_params_std: Standard REO command parameters 164 * @need_status: Status required for the command 165 * @addr_lo: Lower 32 bits of REO queue descriptor address 166 * @addr_hi: Upper 8 bits of REO queue descriptor address 167 */ 168 struct hal_reo_cmd_params_std { 169 bool need_status; 170 uint32_t addr_lo; 171 uint8_t addr_hi; 172 }; 173 174 /** 175 * struct hal_reo_cmd_get_queue_stats_params: Parameters to 176 * CMD_GET_QUEUE_STATScommand 177 * @clear: Clear stats after retrieving 178 */ 179 struct hal_reo_cmd_get_queue_stats_params { 180 bool clear; 181 }; 182 183 /** 184 * struct hal_reo_cmd_flush_queue_params: Parameters to CMD_FLUSH_QUEUE 185 * @use_after_flush: Block usage after flush till unblock command 186 * @index: Blocking resource to be used 187 */ 188 struct hal_reo_cmd_flush_queue_params { 189 bool block_use_after_flush; 190 uint8_t index; 191 }; 192 193 /** 194 * struct hal_reo_cmd_flush_cache_params: Parameters to CMD_FLUSH_CACHE 195 * @fwd_mpdus_in_queue: Forward MPDUs before flushing descriptor 196 * @rel_block_index: Release blocking resource used earlier 197 * @cache_block_res_index: Blocking resource to be used 198 * @flush_no_inval: Flush without invalidatig descriptor 199 * @use_after_flush: Block usage after flush till unblock command 200 * @flush_entire_cache: Flush entire REO cache 201 */ 202 struct hal_reo_cmd_flush_cache_params { 203 bool fwd_mpdus_in_queue; 204 bool rel_block_index; 205 uint8_t cache_block_res_index; 206 bool flush_no_inval; 207 bool block_use_after_flush; 208 bool flush_entire_cache; 209 }; 210 211 /** 212 * struct hal_reo_cmd_unblock_cache_params: Parameters to CMD_UNBLOCK_CACHE 213 * @type: Unblock type (enum reo_unblock_cache_type) 214 * @index: Blocking index to be released 215 */ 216 struct hal_reo_cmd_unblock_cache_params { 217 enum reo_unblock_cache_type type; 218 uint8_t index; 219 }; 220 221 /** 222 * struct hal_reo_cmd_flush_timeout_list_params: Parameters to 223 * CMD_FLUSH_TIMEOUT_LIST 224 * @ac_list: AC timeout list to be flushed 225 * @min_rel_desc: Min. number of link descriptors to be release 226 * @min_fwd_buf: Min. number of buffers to be forwarded 227 */ 228 struct hal_reo_cmd_flush_timeout_list_params { 229 uint8_t ac_list; 230 uint16_t min_rel_desc; 231 uint16_t min_fwd_buf; 232 }; 233 234 /** 235 * struct hal_reo_cmd_update_queue_params: Parameters to CMD_UPDATE_RX_REO_QUEUE 236 * @update_rx_queue_num: Update receive queue number 237 * @update_vld: Update valid bit 238 * @update_assoc_link_desc: Update associated link descriptor 239 * @update_disable_dup_detect: Update duplicate detection 240 * @update_soft_reorder_enab: Update soft reorder enable 241 * @update_ac: Update access category 242 * @update_bar: Update BAR received bit 243 * @update_rty: Update retry bit 244 * @update_chk_2k_mode: Update chk_2k_mode setting 245 * @update_oor_mode: Update OOR mode setting 246 * @update_ba_window_size: Update BA window size 247 * @update_pn_check_needed: Update pn_check_needed 248 * @update_pn_even: Update pn_even 249 * @update_pn_uneven: Update pn_uneven 250 * @update_pn_hand_enab: Update pn_handling_enable 251 * @update_pn_size: Update pn_size 252 * @update_ignore_ampdu: Update ignore_ampdu 253 * @update_svld: update svld 254 * @update_ssn: Update SSN 255 * @update_seq_2k_err_detect: Update seq_2k_err_detected flag 256 * @update_pn_err_detect: Update pn_err_detected flag 257 * @update_pn_valid: Update pn_valid 258 * @update_pn: Update PN 259 * @rx_queue_num: rx_queue_num to be updated 260 * @vld: valid bit to be updated 261 * @assoc_link_desc: assoc_link_desc counter 262 * @disable_dup_detect: disable_dup_detect to be updated 263 * @soft_reorder_enab: soft_reorder_enab to be updated 264 * @ac: AC to be updated 265 * @bar: BAR flag to be updated 266 * @rty: RTY flag to be updated 267 * @chk_2k_mode: check_2k_mode setting to be updated 268 * @oor_mode: oor_mode to be updated 269 * @pn_check_needed: pn_check_needed to be updated 270 * @pn_even: pn_even to be updated 271 * @pn_uneven: pn_uneven to be updated 272 * @pn_hand_enab: pn_handling_enable to be updated 273 * @ignore_ampdu: ignore_ampdu to be updated 274 * @ba_window_size: BA window size to be updated 275 * @pn_size: pn_size to be updated 276 * @svld: svld flag to be updated 277 * @ssn: SSN to be updated 278 * @seq_2k_err_detect: seq_2k_err_detected flag to be updated 279 * @pn_err_detect: pn_err_detected flag to be updated 280 * @pn_31_0: PN bits 31-0 281 * @pn_63_32: PN bits 63-32 282 * @pn_95_64: PN bits 95-64 283 * @pn_127_96: PN bits 127-96 284 */ 285 struct hal_reo_cmd_update_queue_params { 286 uint32_t update_rx_queue_num:1, 287 update_vld:1, 288 update_assoc_link_desc:1, 289 update_disable_dup_detect:1, 290 update_soft_reorder_enab:1, 291 update_ac:1, 292 update_bar:1, 293 update_rty:1, 294 update_chk_2k_mode:1, 295 update_oor_mode:1, 296 update_ba_window_size:1, 297 update_pn_check_needed:1, 298 update_pn_even:1, 299 update_pn_uneven:1, 300 update_pn_hand_enab:1, 301 update_pn_size:1, 302 update_ignore_ampdu:1, 303 update_svld:1, 304 update_ssn:1, 305 update_seq_2k_err_detect:1, 306 update_pn_err_detect:1, 307 update_pn_valid:1, 308 update_pn:1; 309 uint32_t rx_queue_num:16, 310 vld:1, 311 assoc_link_desc:2, 312 disable_dup_detect:1, 313 soft_reorder_enab:1, 314 ac:2, 315 bar:1, 316 rty:1, 317 chk_2k_mode:1, 318 oor_mode:1, 319 pn_check_needed:1, 320 pn_even:1, 321 pn_uneven:1, 322 pn_hand_enab:1, 323 ignore_ampdu:1; 324 uint32_t ba_window_size:15, 325 pn_size:2, 326 svld:1, 327 ssn:12, 328 seq_2k_err_detect:1, 329 pn_err_detect:1; 330 uint32_t pn_31_0:32; 331 uint32_t pn_63_32:32; 332 uint32_t pn_95_64:32; 333 uint32_t pn_127_96:32; 334 }; 335 336 /** 337 * struct hal_reo_cmd_params: Common structure to pass REO command parameters 338 * @hal_reo_cmd_params_std: Standard parameters 339 * @u: Union of various REO command parameters 340 */ 341 struct hal_reo_cmd_params { 342 struct hal_reo_cmd_params_std std; 343 union { 344 struct hal_reo_cmd_get_queue_stats_params stats_params; 345 struct hal_reo_cmd_flush_queue_params fl_queue_params; 346 struct hal_reo_cmd_flush_cache_params fl_cache_params; 347 struct hal_reo_cmd_unblock_cache_params unblk_cache_params; 348 struct hal_reo_cmd_flush_timeout_list_params fl_tim_list_params; 349 struct hal_reo_cmd_update_queue_params upd_queue_params; 350 } u; 351 }; 352 353 /** 354 * struct hal_reo_status_header: Common REO status header 355 * @cmd_num: Command number 356 * @exec_time: execution time 357 * @status: command execution status 358 * @tstamp: Timestamp of status updated 359 */ 360 struct hal_reo_status_header { 361 uint16_t cmd_num; 362 uint16_t exec_time; 363 enum reo_cmd_exec_status status; 364 uint32_t tstamp; 365 }; 366 367 /** 368 * struct hal_reo_queue_status: REO queue status structure 369 * @header: Common REO status header 370 * @ssn: SSN of current BA window 371 * @curr_idx: last forwarded pkt 372 * @pn_31_0, pn_63_32, pn_95_64, pn_127_96: 373 * PN number bits extracted from IV field 374 * @last_rx_enq_tstamp: Last enqueue timestamp 375 * @last_rx_deq_tstamp: Last dequeue timestamp 376 * @rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64 377 * @rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160 378 * @rx_bitmap_223_192, rx_bitmap_255_224: Each bit corresponds to a frame 379 * held in re-order queue 380 * @curr_mpdu_cnt, curr_msdu_cnt: Number of MPDUs and MSDUs in the queue 381 * @fwd_timeout_cnt: Frames forwarded due to timeout 382 * @fwd_bar_cnt: Frames forwarded BAR frame 383 * @dup_cnt: duplicate frames detected 384 * @frms_in_order_cnt: Frames received in order 385 * @bar_rcvd_cnt: BAR frame count 386 * @mpdu_frms_cnt, msdu_frms_cnt, total_cnt: MPDU, MSDU, total frames 387 processed by REO 388 * @late_recv_mpdu_cnt; received after window had moved on 389 * @win_jump_2k: 2K jump count 390 * @hole_cnt: sequence hole count 391 */ 392 struct hal_reo_queue_status { 393 struct hal_reo_status_header header; 394 uint16_t ssn; 395 uint8_t curr_idx; 396 uint32_t pn_31_0, pn_63_32, pn_95_64, pn_127_96; 397 uint32_t last_rx_enq_tstamp, last_rx_deq_tstamp; 398 uint32_t rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64; 399 uint32_t rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160; 400 uint32_t rx_bitmap_223_192, rx_bitmap_255_224; 401 uint8_t curr_mpdu_cnt, curr_msdu_cnt; 402 uint8_t fwd_timeout_cnt, fwd_bar_cnt; 403 uint16_t dup_cnt; 404 uint32_t frms_in_order_cnt; 405 uint8_t bar_rcvd_cnt; 406 uint32_t mpdu_frms_cnt, msdu_frms_cnt, total_cnt; 407 uint16_t late_recv_mpdu_cnt; 408 uint8_t win_jump_2k; 409 uint16_t hole_cnt; 410 }; 411 412 /** 413 * struct hal_reo_flush_queue_status: FLUSH_QUEUE status structure 414 * @header: Common REO status header 415 * @error: Error detected 416 */ 417 struct hal_reo_flush_queue_status { 418 struct hal_reo_status_header header; 419 bool error; 420 }; 421 422 /** 423 * struct hal_reo_flush_cache_status: FLUSH_CACHE status structure 424 * @header: Common REO status header 425 * @error: Error detected 426 * @block_error: Blocking related error 427 * @cache_flush_status: Cache hit/miss 428 * @cache_flush_status_desc_type: type of descriptor flushed 429 * @cache_flush_cnt: number of lines actually flushed 430 */ 431 struct hal_reo_flush_cache_status { 432 struct hal_reo_status_header header; 433 bool error; 434 uint8_t block_error; 435 bool cache_flush_status; 436 uint8_t cache_flush_status_desc_type; 437 uint8_t cache_flush_cnt; 438 }; 439 440 /** 441 * struct hal_reo_unblk_cache_status: UNBLOCK_CACHE status structure 442 * @header: Common REO status header 443 * @error: error detected 444 * unblock_type: resource or cache 445 */ 446 struct hal_reo_unblk_cache_status { 447 struct hal_reo_status_header header; 448 bool error; 449 enum reo_unblock_cache_type unblock_type; 450 }; 451 452 /** 453 * struct hal_reo_flush_timeout_list_status: FLUSH_TIMEOUT_LIST status structure 454 * @header: Common REO status header 455 * @error: error detected 456 * @list_empty: timeout list empty 457 * @rel_desc_cnt: number of link descriptors released 458 * @fwd_buf_cnt: number of buffers forwarded to REO destination ring 459 */ 460 struct hal_reo_flush_timeout_list_status { 461 struct hal_reo_status_header header; 462 bool error; 463 bool list_empty; 464 uint16_t rel_desc_cnt; 465 uint16_t fwd_buf_cnt; 466 }; 467 468 /** 469 * struct hal_reo_desc_thres_reached_status: desc_thres_reached status structure 470 * @header: Common REO status header 471 * @thres_index: Index of descriptor threshold counter 472 * @link_desc_counter0, link_desc_counter1, link_desc_counter2: descriptor 473 * counter values 474 * @link_desc_counter_sum: overall descriptor count 475 */ 476 struct hal_reo_desc_thres_reached_status { 477 struct hal_reo_status_header header; 478 enum reo_thres_index_reg thres_index; 479 uint32_t link_desc_counter0, link_desc_counter1, link_desc_counter2; 480 uint32_t link_desc_counter_sum; 481 }; 482 483 /** 484 * struct hal_reo_update_rx_queue_status: UPDATE_RX_QUEUE status structure 485 * @header: Common REO status header 486 */ 487 struct hal_reo_update_rx_queue_status { 488 struct hal_reo_status_header header; 489 }; 490 491 /** 492 * union hal_reo_status: Union to pass REO status to callbacks 493 * @queue_status: Refer to struct hal_reo_queue_status 494 * @fl_cache_status: Refer to struct hal_reo_flush_cache_status 495 * @fl_queue_status: Refer to struct hal_reo_flush_queue_status 496 * @fl_timeout_status: Refer to struct hal_reo_flush_timeout_list_status 497 * @unblk_cache_status: Refer to struct hal_reo_unblk_cache_status 498 * @thres_status: struct hal_reo_desc_thres_reached_status 499 * @rx_queue_status: struct hal_reo_update_rx_queue_status 500 */ 501 union hal_reo_status { 502 struct hal_reo_queue_status queue_status; 503 struct hal_reo_flush_cache_status fl_cache_status; 504 struct hal_reo_flush_queue_status fl_queue_status; 505 struct hal_reo_flush_timeout_list_status fl_timeout_status; 506 struct hal_reo_unblk_cache_status unblk_cache_status; 507 struct hal_reo_desc_thres_reached_status thres_status; 508 struct hal_reo_update_rx_queue_status rx_queue_status; 509 }; 510 511 #ifdef HAL_DISABLE_NON_BA_2K_JUMP_ERROR 512 static inline uint32_t hal_update_non_ba_win_size(int tid, 513 uint32_t ba_window_size) 514 { 515 return ba_window_size; 516 } 517 #else 518 static inline uint32_t hal_update_non_ba_win_size(int tid, 519 uint32_t ba_window_size) 520 { 521 if ((ba_window_size == 1) && (tid != HAL_NON_QOS_TID)) 522 ba_window_size++; 523 524 return ba_window_size; 525 } 526 #endif 527 528 #define BLOCK_RES_MASK 0xF 529 static inline uint8_t hal_find_one_bit(uint8_t x) 530 { 531 uint8_t y = (x & (~x + 1)) & BLOCK_RES_MASK; 532 uint8_t pos; 533 534 for (pos = 0; y; y >>= 1) 535 pos++; 536 537 return pos-1; 538 } 539 540 static inline uint8_t hal_find_zero_bit(uint8_t x) 541 { 542 uint8_t y = (~x & (x+1)) & BLOCK_RES_MASK; 543 uint8_t pos; 544 545 for (pos = 0; y; y >>= 1) 546 pos++; 547 548 return pos-1; 549 } 550 551 /* REO command ring routines */ 552 553 /** 554 * hal_uniform_desc_hdr_setup - setup reo_queue_ext descriptor 555 * @owner - owner info 556 * @buffer_type - buffer type 557 */ 558 static inline void 559 hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner, uint32_t buffer_type) 560 { 561 HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, OWNER, 562 owner); 563 HAL_DESC_SET_FIELD(desc, HAL_UNIFORM_DESCRIPTOR_HEADER, BUFFER_TYPE, 564 buffer_type); 565 } 566 567 /** 568 * hal_reo_send_cmd() - Send reo cmd using the params provided. 569 * @hal_soc_hdl: HAL soc handle 570 * @hal_ring_hdl: srng handle 571 * @cmd: cmd ID 572 * @cmd_params: command params 573 * 574 * Return: cmd number 575 */ 576 static inline int 577 hal_reo_send_cmd(hal_soc_handle_t hal_soc_hdl, 578 hal_ring_handle_t hal_ring_hdl, 579 enum hal_reo_cmd_type cmd, 580 struct hal_reo_cmd_params *cmd_params) 581 { 582 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 583 584 if (!hal_soc || !hal_soc->ops) { 585 hal_err("hal handle is NULL"); 586 QDF_BUG(0); 587 return -EINVAL; 588 } 589 590 if (hal_soc->ops->hal_reo_send_cmd) 591 return hal_soc->ops->hal_reo_send_cmd(hal_soc_hdl, hal_ring_hdl, 592 cmd, cmd_params); 593 594 return -EINVAL; 595 } 596 597 #ifdef DP_UMAC_HW_RESET_SUPPORT 598 /** 599 * hal_register_reo_send_cmd() - Register Reo send command callback. 600 * @hal_soc_hdl: HAL soc handle 601 * 602 * Return: void 603 */ 604 static inline void hal_register_reo_send_cmd(hal_soc_handle_t hal_soc_hdl) 605 { 606 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 607 608 if (!hal_soc || !hal_soc->ops) { 609 hal_err("hal handle is NULL"); 610 QDF_BUG(0); 611 return; 612 } 613 614 if (hal_soc->ops->hal_register_reo_send_cmd) 615 hal_soc->ops->hal_register_reo_send_cmd(hal_soc); 616 } 617 618 /** 619 * hal_unregister_reo_send_cmd() - Unregister Reo send command callback. 620 * @hal_soc_hdl: HAL soc handle 621 * 622 * Return: void 623 */ 624 static inline void 625 hal_unregister_reo_send_cmd(hal_soc_handle_t hal_soc_hdl) 626 { 627 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 628 629 if (!hal_soc || !hal_soc->ops) { 630 hal_err("hal handle is NULL"); 631 QDF_BUG(0); 632 return; 633 } 634 635 if (hal_soc->ops->hal_unregister_reo_send_cmd) 636 return hal_soc->ops->hal_unregister_reo_send_cmd(hal_soc); 637 } 638 639 static inline void 640 hal_reset_rx_reo_tid_queue(hal_soc_handle_t hal_soc_hdl, void *hw_qdesc_vaddr, 641 uint32_t size) 642 { 643 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 644 645 if (hal_soc->ops->hal_reset_rx_reo_tid_q) 646 hal_soc->ops->hal_reset_rx_reo_tid_q(hal_soc, hw_qdesc_vaddr, 647 size); 648 } 649 650 #endif 651 652 static inline QDF_STATUS 653 hal_reo_status_update(hal_soc_handle_t hal_soc_hdl, 654 hal_ring_desc_t reo_desc, void *st_handle, 655 uint32_t tlv, int *num_ref) 656 { 657 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 658 659 if (hal_soc->ops->hal_reo_send_cmd) 660 return hal_soc->ops->hal_reo_status_update(hal_soc_hdl, 661 reo_desc, 662 st_handle, 663 tlv, num_ref); 664 return QDF_STATUS_E_FAILURE; 665 } 666 667 /* REO Status ring routines */ 668 static inline void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl, int tid, 669 uint32_t ba_window_size, 670 uint32_t start_seq, void *hw_qdesc_vaddr, 671 qdf_dma_addr_t hw_qdesc_paddr, 672 int pn_type, uint8_t vdev_stats_id) 673 { 674 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 675 676 if (!hal_soc || !hal_soc->ops) { 677 hal_err("hal handle is NULL"); 678 QDF_BUG(0); 679 return; 680 } 681 682 if (hal_soc->ops->hal_reo_qdesc_setup) 683 hal_soc->ops->hal_reo_qdesc_setup(hal_soc_hdl, tid, 684 ba_window_size, start_seq, 685 hw_qdesc_vaddr, 686 hw_qdesc_paddr, pn_type, 687 vdev_stats_id); 688 } 689 690 /** 691 * hal_get_ba_aging_timeout - Retrieve BA aging timeout 692 * 693 * @hal_soc: Opaque HAL SOC handle 694 * @ac: Access category 695 * @value: timeout duration in millisec 696 */ 697 static inline void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, 698 uint8_t ac, 699 uint32_t *value) 700 { 701 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 702 703 hal_soc->ops->hal_get_ba_aging_timeout(hal_soc_hdl, ac, value); 704 } 705 706 /** 707 * hal_set_aging_timeout - Set BA aging timeout 708 * 709 * @hal_soc: Opaque HAL SOC handle 710 * @ac: Access category in millisec 711 * @value: timeout duration value 712 */ 713 static inline void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl, 714 uint8_t ac, 715 uint32_t value) 716 { 717 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 718 719 hal_soc->ops->hal_set_ba_aging_timeout(hal_soc_hdl, ac, value); 720 } 721 722 /** 723 * hal_get_reo_reg_base_offset() - Get REO register base offset 724 * @hal_soc_hdl: HAL soc handle 725 * 726 * Return: REO register base 727 */ 728 static inline uint32_t hal_get_reo_reg_base_offset(hal_soc_handle_t hal_soc_hdl) 729 { 730 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 731 732 return hal_soc->ops->hal_get_reo_reg_base_offset(); 733 } 734 735 static inline uint32_t 736 hal_gen_reo_remap_val(hal_soc_handle_t hal_soc_hdl, 737 enum hal_reo_remap_reg remap_reg, 738 uint8_t *ix0_map) 739 { 740 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 741 742 if (!hal_soc || !hal_soc->ops) { 743 hal_err("hal handle is NULL"); 744 QDF_BUG(0); 745 return 0; 746 } 747 748 if (hal_soc->ops->hal_gen_reo_remap_val) 749 return hal_soc->ops->hal_gen_reo_remap_val(remap_reg, ix0_map); 750 751 return 0; 752 } 753 754 static inline uint8_t 755 hal_get_tlv_hdr_size(hal_soc_handle_t hal_soc_hdl) 756 { 757 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 758 759 if (hal_soc->ops->hal_get_tlv_hdr_size) 760 return hal_soc->ops->hal_get_tlv_hdr_size(); 761 762 return 0; 763 } 764 /* Function Proto-types */ 765 766 /** 767 * hal_reo_init_cmd_ring() - Initialize descriptors of REO command SRNG 768 * with command number 769 * @hal_soc: Handle to HAL SoC structure 770 * @hal_ring: Handle to HAL SRNG structure 771 * Return: none 772 */ 773 void hal_reo_init_cmd_ring(hal_soc_handle_t hal_soc_hdl, 774 hal_ring_handle_t hal_ring_hdl); 775 776 #ifdef REO_SHARED_QREF_TABLE_EN 777 /** 778 * hal_reo_shared_qaddr_setup(): Setup reo qref LUT 779 * @hal_soc: Hal soc pointer 780 * 781 * Allocate MLO and Non MLO table for storing REO queue 782 * reference pointers 783 * 784 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 785 */ 786 static inline QDF_STATUS 787 hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl) 788 { 789 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 790 791 if (hal_soc->ops->hal_reo_shared_qaddr_setup) 792 return hal_soc->ops->hal_reo_shared_qaddr_setup(hal_soc_hdl); 793 794 return QDF_STATUS_SUCCESS; 795 } 796 797 /** 798 * hal_reo_shared_qaddr_detach(): Detach reo qref LUT 799 * @hal_soc: Hal soc pointer 800 * 801 * Detach MLO and Non MLO table start addr to HW reg 802 * 803 * Return: void 804 */ 805 static inline void 806 hal_reo_shared_qaddr_detach(hal_soc_handle_t hal_soc_hdl) 807 { 808 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 809 810 if (hal_soc->ops->hal_reo_shared_qaddr_detach) 811 return hal_soc->ops->hal_reo_shared_qaddr_detach(hal_soc_hdl); 812 } 813 814 #else 815 static inline QDF_STATUS 816 hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl) 817 { 818 return QDF_STATUS_SUCCESS; 819 } 820 821 static inline void 822 hal_reo_shared_qaddr_detach(hal_soc_handle_t hal_soc_hdl) {} 823 #endif /* REO_SHARED_QREF_TABLE_EN */ 824 #endif /* _HAL_REO_H */ 825