1 /* 2 * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_REO_H_ 20 #define _HAL_REO_H_ 21 22 #include <qdf_types.h> 23 /* HW headers */ 24 #include <reo_descriptor_threshold_reached_status.h> 25 #include <reo_flush_queue.h> 26 #include <reo_flush_timeout_list_status.h> 27 #include <reo_unblock_cache.h> 28 #include <reo_flush_cache.h> 29 #include <reo_flush_queue_status.h> 30 #include <reo_get_queue_stats.h> 31 #include <reo_unblock_cache_status.h> 32 #include <reo_flush_cache_status.h> 33 #include <reo_flush_timeout_list.h> 34 #include <reo_get_queue_stats_status.h> 35 #include <reo_update_rx_reo_queue.h> 36 #include <reo_update_rx_reo_queue_status.h> 37 #include <tlv_tag_def.h> 38 39 /* SW headers */ 40 #include "hal_api.h" 41 42 /*--------------------------------------------------------------------------- 43 Preprocessor definitions and constants 44 ---------------------------------------------------------------------------*/ 45 46 /* TLV values */ 47 #define HAL_REO_GET_QUEUE_STATS_TLV WIFIREO_GET_QUEUE_STATS_E 48 #define HAL_REO_FLUSH_QUEUE_TLV WIFIREO_FLUSH_QUEUE_E 49 #define HAL_REO_FLUSH_CACHE_TLV WIFIREO_FLUSH_CACHE_E 50 #define HAL_REO_UNBLOCK_CACHE_TLV WIFIREO_UNBLOCK_CACHE_E 51 #define HAL_REO_FLUSH_TIMEOUT_LIST_TLV WIFIREO_FLUSH_TIMEOUT_LIST_E 52 #define HAL_REO_RX_UPDATE_QUEUE_TLV WIFIREO_UPDATE_RX_REO_QUEUE_E 53 54 #define HAL_REO_QUEUE_STATS_STATUS_TLV WIFIREO_GET_QUEUE_STATS_STATUS_E 55 #define HAL_REO_FLUSH_QUEUE_STATUS_TLV WIFIREO_FLUSH_QUEUE_STATUS_E 56 #define HAL_REO_FLUSH_CACHE_STATUS_TLV WIFIREO_FLUSH_CACHE_STATUS_E 57 #define HAL_REO_UNBLK_CACHE_STATUS_TLV WIFIREO_UNBLOCK_CACHE_STATUS_E 58 #define HAL_REO_TIMOUT_LIST_STATUS_TLV WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E 59 #define HAL_REO_DESC_THRES_STATUS_TLV \ 60 WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E 61 #define HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E 62 63 #define HAL_SET_FIELD(block, field, value) \ 64 ((value << (block ## _ ## field ## _LSB)) & \ 65 (block ## _ ## field ## _MASK)) 66 67 #define HAL_GET_FIELD(block, field, value) \ 68 ((value & (block ## _ ## field ## _MASK)) >> \ 69 (block ## _ ## field ## _LSB)) 70 71 #define HAL_SET_TLV_HDR(desc, tag, len) \ 72 do { \ 73 ((struct tlv_32_hdr *) desc)->tlv_tag = tag; \ 74 ((struct tlv_32_hdr *) desc)->tlv_len = len; \ 75 } while (0) 76 77 #define HAL_GET_TLV(desc) (((struct tlv_32_hdr *) desc)->tlv_tag) 78 79 #define HAL_OFFSET_DW(_block, _field) (HAL_OFFSET(_block, _field) >> 2) 80 /* dword offsets in REO cmd TLV */ 81 #define CMD_HEADER_DW_OFFSET 0 82 83 #define HAL_REO_STATUS_GET_HEADER(d, b, h) do { \ 84 uint32_t val1 = d[HAL_OFFSET_DW(b ##_STATUS_0, \ 85 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; \ 86 h.cmd_num = \ 87 HAL_GET_FIELD( \ 88 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, \ 89 val1); \ 90 h.exec_time = \ 91 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, \ 92 CMD_EXECUTION_TIME, val1); \ 93 h.status = \ 94 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, \ 95 REO_CMD_EXECUTION_STATUS, val1); \ 96 val1 = d[HAL_OFFSET_DW(b ##_STATUS_1, \ 97 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; \ 98 h.tstamp = \ 99 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); \ 100 } while (0) 101 102 /** 103 * enum reo_unblock_cache_type: Enum for unblock type in REO unblock command 104 * @UNBLOCK_RES_INDEX: Unblock a block resource 105 * @UNBLOCK_CACHE: Unblock cache 106 */ 107 enum reo_unblock_cache_type { 108 UNBLOCK_RES_INDEX = 0, 109 UNBLOCK_CACHE = 1 110 }; 111 112 /** 113 * enum reo_thres_index_reg: Enum for reo descriptor usage counter for 114 * which threshold status is being indicated. 115 * @reo_desc_counter0_threshold: counter0 reached threshold 116 * @reo_desc_counter1_threshold: counter1 reached threshold 117 * @reo_desc_counter2_threshold: counter2 reached threshold 118 * @reo_desc_counter_sum_threshold: Total count reached threshold 119 */ 120 enum reo_thres_index_reg { 121 reo_desc_counter0_threshold = 0, 122 reo_desc_counter1_threshold = 1, 123 reo_desc_counter2_threshold = 2, 124 reo_desc_counter_sum_threshold = 3 125 }; 126 127 /** 128 * enum reo_cmd_exec_status: Enum for execution status of REO command 129 * 130 * @HAL_REO_CMD_SUCCESS: Command has successfully be executed 131 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue or cache 132 * was blocked 133 * @HAL_REO_CMD_FAILED: Command has encountered problems when executing, like 134 * the queue descriptor not being valid 135 */ 136 enum reo_cmd_exec_status { 137 HAL_REO_CMD_SUCCESS = 0, 138 HAL_REO_CMD_BLOCKED = 1, 139 HAL_REO_CMD_FAILED = 2, 140 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 141 HAL_REO_CMD_DRAIN = 0xff 142 }; 143 144 /** 145 * enum hal_reo_cmd_type: Enum for REO command type 146 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 147 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 148 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 149 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked 150 * earlier with a ‘REO_FLUSH_CACHE’ command 151 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 152 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 153 */ 154 enum hal_reo_cmd_type { 155 CMD_GET_QUEUE_STATS = 0, 156 CMD_FLUSH_QUEUE = 1, 157 CMD_FLUSH_CACHE = 2, 158 CMD_UNBLOCK_CACHE = 3, 159 CMD_FLUSH_TIMEOUT_LIST = 4, 160 CMD_UPDATE_RX_REO_QUEUE = 5 161 }; 162 163 /** 164 * struct hal_reo_cmd_params_std: Standard REO command parameters 165 * @need_status: Status required for the command 166 * @addr_lo: Lower 32 bits of REO queue descriptor address 167 * @addr_hi: Upper 8 bits of REO queue descriptor address 168 */ 169 struct hal_reo_cmd_params_std { 170 bool need_status; 171 uint32_t addr_lo; 172 uint8_t addr_hi; 173 }; 174 175 /** 176 * struct hal_reo_cmd_get_queue_stats_params: Parameters to 177 * CMD_GET_QUEUE_STATScommand 178 * @clear: Clear stats after retreiving 179 */ 180 struct hal_reo_cmd_get_queue_stats_params { 181 bool clear; 182 }; 183 184 /** 185 * struct hal_reo_cmd_flush_queue_params: Parameters to CMD_FLUSH_QUEUE 186 * @use_after_flush: Block usage after flush till unblock command 187 * @index: Blocking resource to be used 188 */ 189 struct hal_reo_cmd_flush_queue_params { 190 bool block_use_after_flush; 191 uint8_t index; 192 }; 193 194 /** 195 * struct hal_reo_cmd_flush_cache_params: Parameters to CMD_FLUSH_CACHE 196 * @fwd_mpdus_in_queue: Forward MPDUs before flushing descriptor 197 * @rel_block_index: Release blocking resource used earlier 198 * @cache_block_res_index: Blocking resource to be used 199 * @flush_no_inval: Flush without invalidatig descriptor 200 * @use_after_flush: Block usage after flush till unblock command 201 * @flush_all: Flush entire REO cache 202 */ 203 struct hal_reo_cmd_flush_cache_params { 204 bool fwd_mpdus_in_queue; 205 bool rel_block_index; 206 uint8_t cache_block_res_index; 207 bool flush_no_inval; 208 bool block_use_after_flush; 209 bool flush_all; 210 }; 211 212 /** 213 * struct hal_reo_cmd_unblock_cache_params: Parameters to CMD_UNBLOCK_CACHE 214 * @type: Unblock type (enum reo_unblock_cache_type) 215 * @index: Blocking index to be released 216 */ 217 struct hal_reo_cmd_unblock_cache_params { 218 enum reo_unblock_cache_type type; 219 uint8_t index; 220 }; 221 222 /** 223 * struct hal_reo_cmd_flush_timeout_list_params: Parameters to 224 * CMD_FLUSH_TIMEOUT_LIST 225 * @ac_list: AC timeout list to be flushed 226 * @min_rel_desc: Min. number of link descriptors to be release 227 * @min_fwd_buf: Min. number of buffers to be forwarded 228 */ 229 struct hal_reo_cmd_flush_timeout_list_params { 230 uint8_t ac_list; 231 uint16_t min_rel_desc; 232 uint16_t min_fwd_buf; 233 }; 234 235 /** 236 * struct hal_reo_cmd_update_queue_params: Parameters to CMD_UPDATE_RX_REO_QUEUE 237 * @update_rx_queue_num: Update receive queue number 238 * @update_vld: Update valid bit 239 * @update_assoc_link_desc: Update associated link descriptor 240 * @update_disable_dup_detect: Update duplicate detection 241 * @update_soft_reorder_enab: Update soft reorder enable 242 * @update_ac: Update access category 243 * @update_bar: Update BAR received bit 244 * @update_rty: Update retry bit 245 * @update_chk_2k_mode: Update chk_2k_mode setting 246 * @update_oor_mode: Update OOR mode setting 247 * @update_ba_window_size: Update BA window size 248 * @update_pn_check_needed: Update pn_check_needed 249 * @update_pn_even: Update pn_even 250 * @update_pn_uneven: Update pn_uneven 251 * @update_pn_hand_enab: Update pn_handling_enable 252 * @update_pn_size: Update pn_size 253 * @update_ignore_ampdu: Update ignore_ampdu 254 * @update_svld: update svld 255 * @update_ssn: Update SSN 256 * @update_seq_2k_err_detect: Update seq_2k_err_detected flag 257 * @update_pn_err_detect: Update pn_err_detected flag 258 * @update_pn_valid: Update pn_valid 259 * @update_pn: Update PN 260 * @rx_queue_num: rx_queue_num to be updated 261 * @vld: valid bit to be updated 262 * @assoc_link_desc: assoc_link_desc counter 263 * @disable_dup_detect: disable_dup_detect to be updated 264 * @soft_reorder_enab: soft_reorder_enab to be updated 265 * @ac: AC to be updated 266 * @bar: BAR flag to be updated 267 * @rty: RTY flag to be updated 268 * @chk_2k_mode: check_2k_mode setting to be updated 269 * @oor_mode: oor_mode to be updated 270 * @pn_check_needed: pn_check_needed to be updated 271 * @pn_even: pn_even to be updated 272 * @pn_uneven: pn_uneven to be updated 273 * @pn_hand_enab: pn_handling_enable to be updated 274 * @ignore_ampdu: ignore_ampdu to be updated 275 * @ba_window_size: BA window size to be updated 276 * @pn_size: pn_size to be updated 277 * @svld: svld flag to be updated 278 * @ssn: SSN to be updated 279 * @seq_2k_err_detect: seq_2k_err_detected flag to be updated 280 * @pn_err_detect: pn_err_detected flag to be updated 281 * @pn_31_0: PN bits 31-0 282 * @pn_63_32: PN bits 63-32 283 * @pn_95_64: PN bits 95-64 284 * @pn_127_96: PN bits 127-96 285 */ 286 struct hal_reo_cmd_update_queue_params { 287 uint32_t update_rx_queue_num:1, 288 update_vld:1, 289 update_assoc_link_desc:1, 290 update_disable_dup_detect:1, 291 update_soft_reorder_enab:1, 292 update_ac:1, 293 update_bar:1, 294 update_rty:1, 295 update_chk_2k_mode:1, 296 update_oor_mode:1, 297 update_ba_window_size:1, 298 update_pn_check_needed:1, 299 update_pn_even:1, 300 update_pn_uneven:1, 301 update_pn_hand_enab:1, 302 update_pn_size:1, 303 update_ignore_ampdu:1, 304 update_svld:1, 305 update_ssn:1, 306 update_seq_2k_err_detect:1, 307 update_pn_err_detect:1, 308 update_pn_valid:1, 309 update_pn:1; 310 uint32_t rx_queue_num:16, 311 vld:1, 312 assoc_link_desc:2, 313 disable_dup_detect:1, 314 soft_reorder_enab:1, 315 ac:2, 316 bar:1, 317 rty:1, 318 chk_2k_mode:1, 319 oor_mode:1, 320 pn_check_needed:1, 321 pn_even:1, 322 pn_uneven:1, 323 pn_hand_enab:1, 324 ignore_ampdu:1; 325 uint32_t ba_window_size:9, 326 pn_size:8, 327 svld:1, 328 ssn:12, 329 seq_2k_err_detect:1, 330 pn_err_detect:1; 331 uint32_t pn_31_0:32; 332 uint32_t pn_63_32:32; 333 uint32_t pn_95_64:32; 334 uint32_t pn_127_96:32; 335 }; 336 337 /** 338 * struct hal_reo_cmd_params: Common structure to pass REO command parameters 339 * @hal_reo_cmd_params_std: Standard parameters 340 * @u: Union of various REO command parameters 341 */ 342 struct hal_reo_cmd_params { 343 struct hal_reo_cmd_params_std std; 344 union { 345 struct hal_reo_cmd_get_queue_stats_params stats_params; 346 struct hal_reo_cmd_flush_queue_params fl_queue_params; 347 struct hal_reo_cmd_flush_cache_params fl_cache_params; 348 struct hal_reo_cmd_unblock_cache_params unblk_cache_params; 349 struct hal_reo_cmd_flush_timeout_list_params fl_tim_list_params; 350 struct hal_reo_cmd_update_queue_params upd_queue_params; 351 } u; 352 }; 353 354 /** 355 * struct hal_reo_status_header: Common REO status header 356 * @cmd_num: Command number 357 * @exec_time: execution time 358 * @status: command execution status 359 * @tstamp: Timestamp of status updated 360 */ 361 struct hal_reo_status_header { 362 uint16_t cmd_num; 363 uint16_t exec_time; 364 enum reo_cmd_exec_status status; 365 uint32_t tstamp; 366 }; 367 368 /** 369 * struct hal_reo_queue_status: REO queue status structure 370 * @header: Common REO status header 371 * @ssn: SSN of current BA window 372 * @curr_idx: last forwarded pkt 373 * @pn_31_0, pn_63_32, pn_95_64, pn_127_96: 374 * PN number bits extracted from IV field 375 * @last_rx_enq_tstamp: Last enqueue timestamp 376 * @last_rx_deq_tstamp: Last dequeue timestamp 377 * @rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64 378 * @rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160 379 * @rx_bitmap_223_192, rx_bitmap_255_224: Each bit corresonds to a frame 380 * held in re-order queue 381 * @curr_mpdu_cnt, curr_msdu_cnt: Number of MPDUs and MSDUs in the queue 382 * @fwd_timeout_cnt: Frames forwarded due to timeout 383 * @fwd_bar_cnt: Frames forwarded BAR frame 384 * @dup_cnt: duplicate frames detected 385 * @frms_in_order_cnt: Frames received in order 386 * @bar_rcvd_cnt: BAR frame count 387 * @mpdu_frms_cnt, msdu_frms_cnt, total_cnt: MPDU, MSDU, total frames 388 processed by REO 389 * @late_recv_mpdu_cnt; received after window had moved on 390 * @win_jump_2k: 2K jump count 391 * @hole_cnt: sequence hole count 392 */ 393 struct hal_reo_queue_status { 394 struct hal_reo_status_header header; 395 uint16_t ssn; 396 uint8_t curr_idx; 397 uint32_t pn_31_0, pn_63_32, pn_95_64, pn_127_96; 398 uint32_t last_rx_enq_tstamp, last_rx_deq_tstamp; 399 uint32_t rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64; 400 uint32_t rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160; 401 uint32_t rx_bitmap_223_192, rx_bitmap_255_224; 402 uint8_t curr_mpdu_cnt, curr_msdu_cnt; 403 uint8_t fwd_timeout_cnt, fwd_bar_cnt; 404 uint16_t dup_cnt; 405 uint32_t frms_in_order_cnt; 406 uint8_t bar_rcvd_cnt; 407 uint32_t mpdu_frms_cnt, msdu_frms_cnt, total_cnt; 408 uint16_t late_recv_mpdu_cnt; 409 uint8_t win_jump_2k; 410 uint16_t hole_cnt; 411 }; 412 413 /** 414 * struct hal_reo_flush_queue_status: FLUSH_QUEUE status structure 415 * @header: Common REO status header 416 * @error: Error detected 417 */ 418 struct hal_reo_flush_queue_status { 419 struct hal_reo_status_header header; 420 bool error; 421 }; 422 423 /** 424 * struct hal_reo_flush_cache_status: FLUSH_CACHE status structure 425 * @header: Common REO status header 426 * @error: Error detected 427 * @block_error: Blocking related error 428 * @cache_flush_status: Cache hit/miss 429 * @cache_flush_status_desc_type: type of descriptor flushed 430 * @cache_flush_cnt: number of lines actually flushed 431 */ 432 struct hal_reo_flush_cache_status { 433 struct hal_reo_status_header header; 434 bool error; 435 uint8_t block_error; 436 bool cache_flush_status; 437 uint8_t cache_flush_status_desc_type; 438 uint8_t cache_flush_cnt; 439 }; 440 441 /** 442 * struct hal_reo_unblk_cache_status: UNBLOCK_CACHE status structure 443 * @header: Common REO status header 444 * @error: error detected 445 * unblock_type: resoure or cache 446 */ 447 struct hal_reo_unblk_cache_status { 448 struct hal_reo_status_header header; 449 bool error; 450 enum reo_unblock_cache_type unblock_type; 451 }; 452 453 /** 454 * struct hal_reo_flush_timeout_list_status: FLUSH_TIMEOUT_LIST status structure 455 * @header: Common REO status header 456 * @error: error detected 457 * @list_empty: timeout list empty 458 * @rel_desc_cnt: number of link descriptors released 459 * @fwd_buf_cnt: number of buffers forwarded to REO destination ring 460 */ 461 struct hal_reo_flush_timeout_list_status { 462 struct hal_reo_status_header header; 463 bool error; 464 bool list_empty; 465 uint16_t rel_desc_cnt; 466 uint16_t fwd_buf_cnt; 467 }; 468 469 /** 470 * struct hal_reo_desc_thres_reached_status: desc_thres_reached status structure 471 * @header: Common REO status header 472 * @thres_index: Index of descriptor threshold counter 473 * @link_desc_counter0, link_desc_counter1, link_desc_counter2: descriptor 474 * counter values 475 * @link_desc_counter_sum: overall descriptor count 476 */ 477 struct hal_reo_desc_thres_reached_status { 478 struct hal_reo_status_header header; 479 enum reo_thres_index_reg thres_index; 480 uint32_t link_desc_counter0, link_desc_counter1, link_desc_counter2; 481 uint32_t link_desc_counter_sum; 482 }; 483 484 /** 485 * struct hal_reo_update_rx_queue_status: UPDATE_RX_QUEUE status structure 486 * @header: Common REO status header 487 */ 488 struct hal_reo_update_rx_queue_status { 489 struct hal_reo_status_header header; 490 }; 491 492 /** 493 * union hal_reo_status: Union to pass REO status to callbacks 494 * @queue_status: Refer to struct hal_reo_queue_status 495 * @fl_cache_status: Refer to struct hal_reo_flush_cache_status 496 * @fl_queue_status: Refer to struct hal_reo_flush_queue_status 497 * @fl_timeout_status: Refer to struct hal_reo_flush_timeout_list_status 498 * @unblk_cache_status: Refer to struct hal_reo_unblk_cache_status 499 * @thres_status: struct hal_reo_desc_thres_reached_status 500 * @rx_queue_status: struct hal_reo_update_rx_queue_status 501 */ 502 union hal_reo_status { 503 struct hal_reo_queue_status queue_status; 504 struct hal_reo_flush_cache_status fl_cache_status; 505 struct hal_reo_flush_queue_status fl_queue_status; 506 struct hal_reo_flush_timeout_list_status fl_timeout_status; 507 struct hal_reo_unblk_cache_status unblk_cache_status; 508 struct hal_reo_desc_thres_reached_status thres_status; 509 struct hal_reo_update_rx_queue_status rx_queue_status; 510 }; 511 512 /* Prototypes */ 513 /* REO command ring routines */ 514 int hal_reo_cmd_queue_stats(void *reo_ring, struct hal_soc *soc, 515 struct hal_reo_cmd_params *cmd); 516 int hal_reo_cmd_flush_queue(void *reo_ring, struct hal_soc *soc, 517 struct hal_reo_cmd_params *cmd); 518 int hal_reo_cmd_flush_cache(void *reo_ring, struct hal_soc *soc, 519 struct hal_reo_cmd_params *cmd); 520 int hal_reo_cmd_unblock_cache(void *reo_ring, struct hal_soc *soc, 521 struct hal_reo_cmd_params *cmd); 522 int hal_reo_cmd_flush_timeout_list(void *reo_ring, struct hal_soc *soc, 523 struct hal_reo_cmd_params *cmd); 524 int hal_reo_cmd_update_rx_queue(void *reo_ring, struct hal_soc *soc, 525 struct hal_reo_cmd_params *cmd); 526 527 /* REO status ring routines */ 528 void hal_reo_queue_stats_status(uint32_t *reo_desc, 529 struct hal_reo_queue_status *st); 530 void hal_reo_flush_queue_status(uint32_t *reo_desc, 531 struct hal_reo_flush_queue_status *st); 532 void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc, 533 struct hal_reo_flush_cache_status *st); 534 void hal_reo_unblock_cache_status(uint32_t *reo_desc, struct hal_soc *soc, 535 struct hal_reo_unblk_cache_status *st); 536 void hal_reo_flush_timeout_list_status( 537 uint32_t *reo_desc, 538 struct hal_reo_flush_timeout_list_status *st); 539 void hal_reo_desc_thres_reached_status( 540 uint32_t *reo_desc, 541 struct hal_reo_desc_thres_reached_status *st); 542 void hal_reo_rx_update_queue_status(uint32_t *reo_desc, 543 struct hal_reo_update_rx_queue_status *st); 544 545 void hal_reo_init_cmd_ring(struct hal_soc *soc, void *hal_srng); 546 547 #endif /* _HAL_REO_H */ 548