1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "hal_reo.h" 20 #include "hal_tx.h" 21 22 #define BLOCK_RES_MASK 0xF 23 static inline uint8_t hal_find_one_bit(uint8_t x) 24 { 25 uint8_t y = (x & (~x + 1)) & BLOCK_RES_MASK; 26 uint8_t pos; 27 28 for (pos = 0; y; y >>= 1) 29 pos++; 30 31 return pos-1; 32 } 33 34 static inline uint8_t hal_find_zero_bit(uint8_t x) 35 { 36 uint8_t y = (~x & (x+1)) & BLOCK_RES_MASK; 37 uint8_t pos; 38 39 for (pos = 0; y; y >>= 1) 40 pos++; 41 42 return pos-1; 43 } 44 45 inline void hal_reo_cmd_set_descr_addr(uint32_t *reo_desc, 46 enum hal_reo_cmd_type type, 47 uint32_t paddr_lo, 48 uint8_t paddr_hi) 49 { 50 switch (type) { 51 case CMD_GET_QUEUE_STATS: 52 HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_1, 53 RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo); 54 HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_2, 55 RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi); 56 break; 57 case CMD_FLUSH_QUEUE: 58 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_1, 59 FLUSH_DESC_ADDR_31_0, paddr_lo); 60 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2, 61 FLUSH_DESC_ADDR_39_32, paddr_hi); 62 break; 63 case CMD_FLUSH_CACHE: 64 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_1, 65 FLUSH_ADDR_31_0, paddr_lo); 66 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, 67 FLUSH_ADDR_39_32, paddr_hi); 68 break; 69 case CMD_UPDATE_RX_REO_QUEUE: 70 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_1, 71 RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo); 72 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 73 RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi); 74 break; 75 default: 76 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 77 "%s: Invalid REO command type\n", __func__); 78 break; 79 } 80 } 81 82 inline int hal_reo_cmd_queue_stats(void *reo_ring, struct hal_soc *soc, 83 struct hal_reo_cmd_params *cmd) 84 85 { 86 uint32_t *reo_desc, val; 87 88 hal_srng_access_start(soc, reo_ring); 89 reo_desc = hal_srng_src_get_next(soc, reo_ring); 90 if (!reo_desc) { 91 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 92 "%s: Out of cmd ring entries\n", __func__); 93 hal_srng_access_end(soc, reo_ring); 94 return -EBUSY; 95 } 96 97 HAL_SET_TLV_HDR(reo_desc, WIFIREO_GET_QUEUE_STATS_E, 98 sizeof(struct reo_get_queue_stats)); 99 100 /* Offsets of descriptor fields defined in HW headers start from 101 * the field after TLV header */ 102 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 103 qdf_mem_zero((void *)reo_desc, sizeof(struct reo_get_queue_stats)); 104 105 HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0, 106 REO_STATUS_REQUIRED, cmd->std.need_status); 107 108 hal_reo_cmd_set_descr_addr(reo_desc, CMD_GET_QUEUE_STATS, 109 cmd->std.addr_lo, 110 cmd->std.addr_hi); 111 112 HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_2, CLEAR_STATS, 113 cmd->u.stats_params.clear); 114 115 hal_srng_access_end(soc, reo_ring); 116 117 val = reo_desc[CMD_HEADER_DW_OFFSET]; 118 return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER, 119 val); 120 } 121 122 inline int hal_reo_cmd_flush_queue(void *reo_ring, struct hal_soc *soc, 123 struct hal_reo_cmd_params *cmd) 124 { 125 uint32_t *reo_desc, val; 126 127 hal_srng_access_start(soc, reo_ring); 128 reo_desc = hal_srng_src_get_next(soc, reo_ring); 129 if (!reo_desc) { 130 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 131 "%s: Out of cmd ring entries\n", __func__); 132 hal_srng_access_end(soc, reo_ring); 133 return -EBUSY; 134 } 135 136 HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_QUEUE_E, 137 sizeof(struct reo_flush_queue)); 138 139 /* Offsets of descriptor fields defined in HW headers start from 140 * the field after TLV header */ 141 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 142 qdf_mem_zero((void *)reo_desc, sizeof(struct reo_flush_queue)); 143 144 HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0, 145 REO_STATUS_REQUIRED, cmd->std.need_status); 146 147 hal_reo_cmd_set_descr_addr(reo_desc, CMD_FLUSH_QUEUE, cmd->std.addr_lo, 148 cmd->std.addr_hi); 149 150 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2, 151 BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH, 152 cmd->u.fl_queue_params.use_after_flush); 153 154 if (cmd->u.fl_queue_params.use_after_flush) { 155 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2, 156 BLOCK_RESOURCE_INDEX, cmd->u.fl_queue_params.index); 157 } 158 159 hal_srng_access_end(soc, reo_ring); 160 val = reo_desc[CMD_HEADER_DW_OFFSET]; 161 return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER, 162 val); 163 } 164 165 inline int hal_reo_cmd_flush_cache(void *reo_ring, struct hal_soc *soc, 166 struct hal_reo_cmd_params *cmd) 167 { 168 uint32_t *reo_desc, val; 169 struct hal_reo_cmd_flush_cache_params *cp; 170 uint8_t index; 171 172 cp = &cmd->u.fl_cache_params; 173 174 hal_srng_access_start(soc, reo_ring); 175 176 index = hal_find_zero_bit(soc->reo_res_bitmap); 177 /* We need a cache block resource for this operation, and REO HW has 178 * only 4 such blocking resources. These resources are managed using 179 * reo_res_bitmap, and we return failure if none is available. 180 */ 181 if (index > 3) { 182 qdf_print("%s, No blocking resource available!\n", __func__); 183 hal_srng_access_end(soc, reo_ring); 184 return -EBUSY; 185 } 186 soc->index = index; 187 188 reo_desc = hal_srng_src_get_next(soc, reo_ring); 189 if (!reo_desc) { 190 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 191 "%s: Out of cmd ring entries\n", __func__); 192 hal_srng_access_end(soc, reo_ring); 193 return -EBUSY; 194 } 195 196 HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_CACHE_E, 197 sizeof(struct reo_flush_cache)); 198 199 /* Offsets of descriptor fields defined in HW headers start from 200 * the field after TLV header */ 201 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 202 qdf_mem_zero((void *)reo_desc, sizeof(struct reo_flush_cache)); 203 204 HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0, 205 REO_STATUS_REQUIRED, cmd->std.need_status); 206 207 hal_reo_cmd_set_descr_addr(reo_desc, CMD_FLUSH_CACHE, cmd->std.addr_lo, 208 cmd->std.addr_hi); 209 210 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, 211 FORWARD_ALL_MPDUS_IN_QUEUE, cp->fwd_mpdus_in_queue); 212 213 /* set it to 0 for now */ 214 cp->rel_block_index = 0; 215 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, 216 RELEASE_CACHE_BLOCK_INDEX, cp->rel_block_index); 217 218 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, 219 CACHE_BLOCK_RESOURCE_INDEX, index); 220 221 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, 222 FLUSH_WITHOUT_INVALIDATE, cp->flush_no_inval); 223 224 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, 225 BLOCK_CACHE_USAGE_AFTER_FLUSH, cp->use_after_flush); 226 227 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, FLUSH_ENTIRE_CACHE, 228 cp->flush_all); 229 230 hal_srng_access_end(soc, reo_ring); 231 val = reo_desc[CMD_HEADER_DW_OFFSET]; 232 return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER, 233 val); 234 } 235 236 inline int hal_reo_cmd_unblock_cache(void *reo_ring, struct hal_soc *soc, 237 struct hal_reo_cmd_params *cmd) 238 239 { 240 uint32_t *reo_desc, val; 241 uint8_t index = 0; 242 243 hal_srng_access_start(soc, reo_ring); 244 245 if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) { 246 index = hal_find_one_bit(soc->reo_res_bitmap); 247 if (index > 3) { 248 hal_srng_access_end(soc, reo_ring); 249 qdf_print("%s: No blocking resource to unblock!\n", 250 __func__); 251 return -EBUSY; 252 } 253 } 254 255 reo_desc = hal_srng_src_get_next(soc, reo_ring); 256 if (!reo_desc) { 257 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 258 "%s: Out of cmd ring entries\n", __func__); 259 hal_srng_access_end(soc, reo_ring); 260 return -EBUSY; 261 } 262 263 HAL_SET_TLV_HDR(reo_desc, WIFIREO_UNBLOCK_CACHE_E, 264 sizeof(struct reo_unblock_cache)); 265 266 /* Offsets of descriptor fields defined in HW headers start from 267 * the field after TLV header */ 268 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 269 qdf_mem_zero((void *)reo_desc, sizeof(struct reo_unblock_cache)); 270 271 HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0, 272 REO_STATUS_REQUIRED, cmd->std.need_status); 273 274 HAL_DESC_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE_1, 275 UNBLOCK_TYPE, cmd->u.unblk_cache_params.type); 276 277 if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) { 278 HAL_DESC_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE_1, 279 CACHE_BLOCK_RESOURCE_INDEX, index); 280 soc->index = index; 281 } 282 283 hal_srng_access_end(soc, reo_ring); 284 val = reo_desc[CMD_HEADER_DW_OFFSET]; 285 return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER, 286 val); 287 } 288 289 inline int hal_reo_cmd_flush_timeout_list(void *reo_ring, struct hal_soc *soc, 290 struct hal_reo_cmd_params *cmd) 291 { 292 uint32_t *reo_desc, val; 293 294 hal_srng_access_start(soc, reo_ring); 295 reo_desc = hal_srng_src_get_next(soc, reo_ring); 296 if (!reo_desc) { 297 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 298 "%s: Out of cmd ring entries\n", __func__); 299 hal_srng_access_end(soc, reo_ring); 300 return -EBUSY; 301 } 302 303 HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_TIMEOUT_LIST_E, 304 sizeof(struct reo_flush_timeout_list)); 305 306 /* Offsets of descriptor fields defined in HW headers start from 307 * the field after TLV header */ 308 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 309 qdf_mem_zero((void *)reo_desc, sizeof(struct reo_flush_timeout_list)); 310 311 HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0, 312 REO_STATUS_REQUIRED, cmd->std.need_status); 313 314 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_1, AC_TIMOUT_LIST, 315 cmd->u.fl_tim_list_params.ac_list); 316 317 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_2, 318 MINIMUM_RELEASE_DESC_COUNT, 319 cmd->u.fl_tim_list_params.min_rel_desc); 320 321 HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_2, 322 MINIMUM_FORWARD_BUF_COUNT, 323 cmd->u.fl_tim_list_params.min_fwd_buf); 324 325 hal_srng_access_end(soc, reo_ring); 326 val = reo_desc[CMD_HEADER_DW_OFFSET]; 327 return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER, 328 val); 329 } 330 331 inline int hal_reo_cmd_update_rx_queue(void *reo_ring, struct hal_soc *soc, 332 struct hal_reo_cmd_params *cmd) 333 { 334 uint32_t *reo_desc, val; 335 struct hal_reo_cmd_update_queue_params *p; 336 337 p = &cmd->u.upd_queue_params; 338 339 hal_srng_access_start(soc, reo_ring); 340 reo_desc = hal_srng_src_get_next(soc, reo_ring); 341 if (!reo_desc) { 342 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 343 "%s: Out of cmd ring entries\n", __func__); 344 hal_srng_access_end(soc, reo_ring); 345 return -EBUSY; 346 } 347 348 HAL_SET_TLV_HDR(reo_desc, WIFIREO_UPDATE_RX_REO_QUEUE_E, 349 sizeof(struct reo_update_rx_reo_queue)); 350 351 /* Offsets of descriptor fields defined in HW headers start from 352 * the field after TLV header */ 353 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 354 qdf_mem_zero((void *)reo_desc, sizeof(struct reo_update_rx_reo_queue)); 355 356 HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0, 357 REO_STATUS_REQUIRED, cmd->std.need_status); 358 359 hal_reo_cmd_set_descr_addr(reo_desc, CMD_UPDATE_RX_REO_QUEUE, 360 cmd->std.addr_lo, cmd->std.addr_hi); 361 362 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 363 UPDATE_RECEIVE_QUEUE_NUMBER, p->update_rx_queue_num); 364 365 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, UPDATE_VLD, 366 p->update_vld); 367 368 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 369 UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER, 370 p->update_assoc_link_desc); 371 372 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 373 UPDATE_DISABLE_DUPLICATE_DETECTION, 374 p->update_disable_dup_detect); 375 376 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 377 UPDATE_DISABLE_DUPLICATE_DETECTION, 378 p->update_disable_dup_detect); 379 380 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 381 UPDATE_SOFT_REORDER_ENABLE, 382 p->update_soft_reorder_enab); 383 384 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 385 UPDATE_AC, p->update_ac); 386 387 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 388 UPDATE_BAR, p->update_bar); 389 390 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 391 UPDATE_BAR, p->update_bar); 392 393 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 394 UPDATE_RTY, p->update_rty); 395 396 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 397 UPDATE_CHK_2K_MODE, p->update_chk_2k_mode); 398 399 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 400 UPDATE_OOR_MODE, p->update_oor_mode); 401 402 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 403 UPDATE_BA_WINDOW_SIZE, p->update_ba_window_size); 404 405 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 406 UPDATE_PN_CHECK_NEEDED, p->update_pn_check_needed); 407 408 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 409 UPDATE_PN_SHALL_BE_EVEN, p->update_pn_even); 410 411 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 412 UPDATE_PN_SHALL_BE_UNEVEN, p->update_pn_uneven); 413 414 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 415 UPDATE_PN_HANDLING_ENABLE, p->update_pn_hand_enab); 416 417 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 418 UPDATE_PN_SIZE, p->update_pn_size); 419 420 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 421 UPDATE_IGNORE_AMPDU_FLAG, p->update_ignore_ampdu); 422 423 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 424 UPDATE_SVLD, p->update_svld); 425 426 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 427 UPDATE_SSN, p->update_ssn); 428 429 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 430 UPDATE_SEQ_2K_ERROR_DETECTED_FLAG, 431 p->update_seq_2k_err_detect); 432 433 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 434 UPDATE_PN_VALID, p->update_pn_valid); 435 436 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, 437 UPDATE_PN, p->update_pn); 438 439 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 440 RECEIVE_QUEUE_NUMBER, p->rx_queue_num); 441 442 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 443 VLD, p->vld); 444 445 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 446 ASSOCIATED_LINK_DESCRIPTOR_COUNTER, 447 p->assoc_link_desc); 448 449 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 450 DISABLE_DUPLICATE_DETECTION, p->disable_dup_detect); 451 452 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 453 SOFT_REORDER_ENABLE, p->soft_reorder_enab); 454 455 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, AC, p->ac); 456 457 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 458 BAR, p->bar); 459 460 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 461 CHK_2K_MODE, p->chk_2k_mode); 462 463 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 464 RTY, p->rty); 465 466 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 467 OOR_MODE, p->oor_mode); 468 469 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 470 PN_CHECK_NEEDED, p->pn_check_needed); 471 472 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 473 PN_SHALL_BE_EVEN, p->pn_even); 474 475 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 476 PN_SHALL_BE_UNEVEN, p->pn_uneven); 477 478 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 479 PN_HANDLING_ENABLE, p->pn_hand_enab); 480 481 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, 482 IGNORE_AMPDU_FLAG, p->ignore_ampdu); 483 484 if (p->ba_window_size < 1) 485 p->ba_window_size = 1; 486 487 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4, 488 BA_WINDOW_SIZE, p->ba_window_size - 1); 489 490 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4, 491 PN_SIZE, p->pn_size); 492 493 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4, 494 SVLD, p->svld); 495 496 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4, 497 SSN, p->ssn); 498 499 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4, 500 SEQ_2K_ERROR_DETECTED_FLAG, p->seq_2k_err_detect); 501 502 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4, 503 PN_ERROR_DETECTED_FLAG, p->pn_err_detect); 504 505 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_5, 506 PN_31_0, p->pn_31_0); 507 508 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_6, 509 PN_63_32, p->pn_63_32); 510 511 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_7, 512 PN_95_64, p->pn_95_64); 513 514 HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_8, 515 PN_127_96, p->pn_127_96); 516 517 hal_srng_access_end(soc, reo_ring); 518 val = reo_desc[CMD_HEADER_DW_OFFSET]; 519 return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER, 520 val); 521 } 522 523 inline void hal_reo_queue_stats_status(uint32_t *reo_desc, 524 struct hal_reo_queue_status *st) 525 { 526 uint32_t val; 527 528 /* Offsets of descriptor fields defined in HW headers start 529 * from the field after TLV header */ 530 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 531 532 /* header */ 533 HAL_REO_STATUS_GET_HEADER(reo_desc, REO_GET_QUEUE_STATS, st->header); 534 535 /* SSN */ 536 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2, SSN)]; 537 st->ssn = HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_2, SSN, val); 538 539 /* current index */ 540 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2, 541 CURRENT_INDEX)]; 542 st->curr_idx = 543 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_2, 544 CURRENT_INDEX, val); 545 546 /* PN bits */ 547 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_3, 548 PN_31_0)]; 549 st->pn_31_0 = 550 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_3, 551 PN_31_0, val); 552 553 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_4, 554 PN_63_32)]; 555 st->pn_63_32 = 556 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_4, 557 PN_63_32, val); 558 559 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_5, 560 PN_95_64)]; 561 st->pn_95_64 = 562 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_5, 563 PN_95_64, val); 564 565 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_6, 566 PN_127_96)]; 567 st->pn_127_96 = 568 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_6, 569 PN_127_96, val); 570 571 /* timestamps */ 572 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_7, 573 LAST_RX_ENQUEUE_TIMESTAMP)]; 574 st->last_rx_enq_tstamp = 575 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_7, 576 LAST_RX_ENQUEUE_TIMESTAMP, val); 577 578 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_8, 579 LAST_RX_DEQUEUE_TIMESTAMP)]; 580 st->last_rx_deq_tstamp = 581 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_8, 582 LAST_RX_DEQUEUE_TIMESTAMP, val); 583 584 /* rx bitmap */ 585 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_9, 586 RX_BITMAP_31_0)]; 587 st->rx_bitmap_31_0 = 588 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_9, 589 RX_BITMAP_31_0, val); 590 591 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_10, 592 RX_BITMAP_63_32)]; 593 st->rx_bitmap_63_32 = 594 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_10, 595 RX_BITMAP_63_32, val); 596 597 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_11, 598 RX_BITMAP_95_64)]; 599 st->rx_bitmap_95_64 = 600 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_11, 601 RX_BITMAP_95_64, val); 602 603 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_12, 604 RX_BITMAP_127_96)]; 605 st->rx_bitmap_127_96 = 606 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_12, 607 RX_BITMAP_127_96, val); 608 609 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_13, 610 RX_BITMAP_159_128)]; 611 st->rx_bitmap_159_128 = 612 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_13, 613 RX_BITMAP_159_128, val); 614 615 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_14, 616 RX_BITMAP_191_160)]; 617 st->rx_bitmap_191_160 = 618 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_14, 619 RX_BITMAP_191_160, val); 620 621 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_15, 622 RX_BITMAP_223_192)]; 623 st->rx_bitmap_223_192 = 624 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_15, 625 RX_BITMAP_223_192, val); 626 627 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_16, 628 RX_BITMAP_255_224)]; 629 st->rx_bitmap_255_224 = 630 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_16, 631 RX_BITMAP_255_224, val); 632 633 /* various counts */ 634 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_17, 635 CURRENT_MPDU_COUNT)]; 636 st->curr_mpdu_cnt = 637 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_17, 638 CURRENT_MPDU_COUNT, val); 639 640 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_17, 641 CURRENT_MSDU_COUNT)]; 642 st->curr_msdu_cnt = 643 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_17, 644 CURRENT_MSDU_COUNT, val); 645 646 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18, 647 TIMEOUT_COUNT)]; 648 st->fwd_timeout_cnt = 649 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18, 650 TIMEOUT_COUNT, val); 651 652 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18, 653 FORWARD_DUE_TO_BAR_COUNT)]; 654 st->fwd_bar_cnt = 655 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18, 656 FORWARD_DUE_TO_BAR_COUNT, val); 657 658 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18, 659 DUPLICATE_COUNT)]; 660 st->dup_cnt = 661 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18, 662 DUPLICATE_COUNT, val); 663 664 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_19, 665 FRAMES_IN_ORDER_COUNT)]; 666 st->frms_in_order_cnt = 667 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_19, 668 FRAMES_IN_ORDER_COUNT, val); 669 670 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_19, 671 BAR_RECEIVED_COUNT)]; 672 st->bar_rcvd_cnt = 673 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_19, 674 BAR_RECEIVED_COUNT, val); 675 676 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_20, 677 MPDU_FRAMES_PROCESSED_COUNT)]; 678 st->mpdu_frms_cnt = 679 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_20, 680 MPDU_FRAMES_PROCESSED_COUNT, val); 681 682 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_21, 683 MSDU_FRAMES_PROCESSED_COUNT)]; 684 st->msdu_frms_cnt = 685 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_21, 686 MSDU_FRAMES_PROCESSED_COUNT, val); 687 688 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_22, 689 TOTAL_PROCESSED_BYTE_COUNT)]; 690 st->total_cnt = 691 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_22, 692 TOTAL_PROCESSED_BYTE_COUNT, val); 693 694 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23, 695 LATE_RECEIVE_MPDU_COUNT)]; 696 st->late_recv_mpdu_cnt = 697 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23, 698 LATE_RECEIVE_MPDU_COUNT, val); 699 700 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23, 701 WINDOW_JUMP_2K)]; 702 st->win_jump_2k = 703 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23, 704 WINDOW_JUMP_2K, val); 705 706 val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23, 707 HOLE_COUNT)]; 708 st->hole_cnt = 709 HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23, 710 HOLE_COUNT, val); 711 } 712 713 inline void hal_reo_flush_queue_status(uint32_t *reo_desc, 714 struct hal_reo_flush_queue_status *st) 715 { 716 uint32_t val; 717 718 /* Offsets of descriptor fields defined in HW headers start 719 * from the field after TLV header */ 720 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 721 722 /* header */ 723 HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_QUEUE, st->header); 724 725 /* error bit */ 726 val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS_2, 727 ERROR_DETECTED)]; 728 st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS_2, ERROR_DETECTED, 729 val); 730 } 731 732 inline void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc, 733 struct hal_reo_flush_cache_status *st) 734 { 735 uint32_t val; 736 737 /* Offsets of descriptor fields defined in HW headers start 738 * from the field after TLV header */ 739 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 740 741 /* header */ 742 HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_CACHE, st->header); 743 744 /* error bit */ 745 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2, 746 ERROR_DETECTED)]; 747 st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS_2, ERROR_DETECTED, 748 val); 749 750 /* block error */ 751 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2, 752 BLOCK_ERROR_DETAILS)]; 753 st->block_error = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2, 754 BLOCK_ERROR_DETAILS, 755 val); 756 if (!st->block_error) 757 qdf_set_bit(soc->index, (unsigned long *)&soc->reo_res_bitmap); 758 759 /* cache flush status */ 760 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2, 761 CACHE_CONTROLLER_FLUSH_STATUS_HIT)]; 762 st->cache_flush_status = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2, 763 CACHE_CONTROLLER_FLUSH_STATUS_HIT, 764 val); 765 766 /* cache flush descriptor type */ 767 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2, 768 CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE)]; 769 st->cache_flush_status_desc_type = 770 HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2, 771 CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE, 772 val); 773 774 /* cache flush count */ 775 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2, 776 CACHE_CONTROLLER_FLUSH_COUNT)]; 777 st->cache_flush_cnt = 778 HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2, 779 CACHE_CONTROLLER_FLUSH_COUNT, 780 val); 781 782 } 783 784 inline void hal_reo_unblock_cache_status(uint32_t *reo_desc, 785 struct hal_soc *soc, 786 struct hal_reo_unblk_cache_status *st) 787 { 788 uint32_t val; 789 790 /* Offsets of descriptor fields defined in HW headers start 791 * from the field after TLV header */ 792 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 793 794 /* header */ 795 HAL_REO_STATUS_GET_HEADER(reo_desc, REO_UNBLOCK_CACHE, st->header); 796 797 /* error bit */ 798 val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2, 799 ERROR_DETECTED)]; 800 st->error = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS_2, 801 ERROR_DETECTED, 802 val); 803 804 /* unblock type */ 805 val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2, 806 UNBLOCK_TYPE)]; 807 st->unblock_type = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS_2, 808 UNBLOCK_TYPE, 809 val); 810 811 if (!st->error && (st->unblock_type == UNBLOCK_RES_INDEX)) 812 qdf_clear_bit(soc->index, 813 (unsigned long *)&soc->reo_res_bitmap); 814 } 815 816 inline void hal_reo_flush_timeout_list_status( 817 uint32_t *reo_desc, 818 struct hal_reo_flush_timeout_list_status *st) 819 820 { 821 uint32_t val; 822 823 /* Offsets of descriptor fields defined in HW headers start 824 * from the field after TLV header */ 825 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 826 827 /* header */ 828 HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_TIMEOUT_LIST, st->header); 829 830 /* error bit */ 831 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2, 832 ERROR_DETECTED)]; 833 st->error = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_2, 834 ERROR_DETECTED, 835 val); 836 837 /* list empty */ 838 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2, 839 TIMOUT_LIST_EMPTY)]; 840 st->list_empty = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_2, 841 TIMOUT_LIST_EMPTY, 842 val); 843 844 /* release descriptor count */ 845 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_3, 846 RELEASE_DESC_COUNT)]; 847 st->rel_desc_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_3, 848 RELEASE_DESC_COUNT, 849 val); 850 851 /* forward buf count */ 852 val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_3, 853 FORWARD_BUF_COUNT)]; 854 st->fwd_buf_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_3, 855 FORWARD_BUF_COUNT, 856 val); 857 } 858 859 inline void hal_reo_desc_thres_reached_status( 860 uint32_t *reo_desc, 861 struct hal_reo_desc_thres_reached_status *st) 862 { 863 uint32_t val; 864 865 /* Offsets of descriptor fields defined in HW headers start 866 * from the field after TLV header */ 867 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 868 869 /* header */ 870 HAL_REO_STATUS_GET_HEADER(reo_desc, 871 REO_DESCRIPTOR_THRESHOLD_REACHED, st->header); 872 873 /* threshold index */ 874 val = reo_desc[HAL_OFFSET_DW( 875 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2, 876 THRESHOLD_INDEX)]; 877 st->thres_index = HAL_GET_FIELD( 878 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2, 879 THRESHOLD_INDEX, 880 val); 881 882 /* link desc counters */ 883 val = reo_desc[HAL_OFFSET_DW( 884 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3, 885 LINK_DESCRIPTOR_COUNTER0)]; 886 st->link_desc_counter0 = HAL_GET_FIELD( 887 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3, 888 LINK_DESCRIPTOR_COUNTER0, 889 val); 890 891 val = reo_desc[HAL_OFFSET_DW( 892 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4, 893 LINK_DESCRIPTOR_COUNTER1)]; 894 st->link_desc_counter1 = HAL_GET_FIELD( 895 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4, 896 LINK_DESCRIPTOR_COUNTER1, 897 val); 898 899 val = reo_desc[HAL_OFFSET_DW( 900 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5, 901 LINK_DESCRIPTOR_COUNTER2)]; 902 st->link_desc_counter2 = HAL_GET_FIELD( 903 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5, 904 LINK_DESCRIPTOR_COUNTER2, 905 val); 906 907 val = reo_desc[HAL_OFFSET_DW( 908 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6, 909 LINK_DESCRIPTOR_COUNTER_SUM)]; 910 st->link_desc_counter_sum = HAL_GET_FIELD( 911 REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6, 912 LINK_DESCRIPTOR_COUNTER_SUM, 913 val); 914 } 915 916 inline void hal_reo_rx_update_queue_status(uint32_t *reo_desc, 917 struct hal_reo_update_rx_queue_status *st) 918 { 919 /* Offsets of descriptor fields defined in HW headers start 920 * from the field after TLV header */ 921 reo_desc += (sizeof(struct tlv_32_hdr) >> 2); 922 923 /* header */ 924 HAL_REO_STATUS_GET_HEADER(reo_desc, 925 REO_UPDATE_RX_REO_QUEUE, st->header); 926 } 927 928 /** 929 * hal_reo_init_cmd_ring() - Initialize descriptors of REO command SRNG 930 * with command number 931 * @hal_soc: Handle to HAL SoC structure 932 * @hal_ring: Handle to HAL SRNG structure 933 * 934 * Return: none 935 */ 936 inline void hal_reo_init_cmd_ring(struct hal_soc *soc, void *hal_srng) 937 { 938 int cmd_num; 939 uint32_t *desc_addr; 940 struct hal_srng_params srng_params; 941 uint32_t desc_size; 942 uint32_t num_desc; 943 944 hal_get_srng_params(soc, hal_srng, &srng_params); 945 946 desc_addr = (uint32_t *)(srng_params.ring_base_vaddr); 947 desc_addr += (sizeof(struct tlv_32_hdr) >> 2); 948 desc_size = hal_srng_get_entrysize(soc, REO_CMD) >> 2; 949 num_desc = srng_params.num_entries; 950 cmd_num = 1; 951 while (num_desc) { 952 /* Offsets of descriptor fields defined in HW headers start 953 * from the field after TLV header */ 954 HAL_DESC_SET_FIELD(desc_addr, UNIFORM_REO_CMD_HEADER_0, 955 REO_CMD_NUMBER, cmd_num); 956 desc_addr += desc_size; 957 num_desc--; cmd_num++; 958 } 959 960 soc->reo_res_bitmap = 0; 961 } 962