1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "pld_common.h" 27 28 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_TXRX, params) 29 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_TXRX, params) 30 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_TXRX, params) 31 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_TXRX, params) 32 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 33 #ifdef ENABLE_VERBOSE_DEBUG 34 extern bool is_hal_verbose_debug_enabled; 35 #define hal_verbose_debug(params...) \ 36 if (unlikely(is_hal_verbose_debug_enabled)) \ 37 do {\ 38 QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params); \ 39 } while (0) 40 #define hal_verbose_hex_dump(params...) \ 41 if (unlikely(is_hal_verbose_debug_enabled)) \ 42 do {\ 43 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, \ 44 QDF_TRACE_LEVEL_DEBUG, \ 45 params); \ 46 } while (0) 47 #else 48 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 49 #define hal_verbose_hex_dump(params...) \ 50 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, \ 51 params) 52 #endif 53 54 55 /* TBD: This should be movded to shared HW header file */ 56 enum hal_srng_ring_id { 57 /* UMAC rings */ 58 HAL_SRNG_REO2SW1 = 0, 59 HAL_SRNG_REO2SW2 = 1, 60 HAL_SRNG_REO2SW3 = 2, 61 HAL_SRNG_REO2SW4 = 3, 62 HAL_SRNG_REO2TCL = 4, 63 HAL_SRNG_SW2REO = 5, 64 /* 6-7 unused */ 65 HAL_SRNG_REO_CMD = 8, 66 HAL_SRNG_REO_STATUS = 9, 67 /* 10-15 unused */ 68 HAL_SRNG_SW2TCL1 = 16, 69 HAL_SRNG_SW2TCL2 = 17, 70 HAL_SRNG_SW2TCL3 = 18, 71 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 72 /* 20-23 unused */ 73 HAL_SRNG_SW2TCL_CMD = 24, 74 HAL_SRNG_TCL_STATUS = 25, 75 /* 26-31 unused */ 76 HAL_SRNG_CE_0_SRC = 32, 77 HAL_SRNG_CE_1_SRC = 33, 78 HAL_SRNG_CE_2_SRC = 34, 79 HAL_SRNG_CE_3_SRC = 35, 80 HAL_SRNG_CE_4_SRC = 36, 81 HAL_SRNG_CE_5_SRC = 37, 82 HAL_SRNG_CE_6_SRC = 38, 83 HAL_SRNG_CE_7_SRC = 39, 84 HAL_SRNG_CE_8_SRC = 40, 85 HAL_SRNG_CE_9_SRC = 41, 86 HAL_SRNG_CE_10_SRC = 42, 87 HAL_SRNG_CE_11_SRC = 43, 88 /* 44-55 unused */ 89 HAL_SRNG_CE_0_DST = 56, 90 HAL_SRNG_CE_1_DST = 57, 91 HAL_SRNG_CE_2_DST = 58, 92 HAL_SRNG_CE_3_DST = 59, 93 HAL_SRNG_CE_4_DST = 60, 94 HAL_SRNG_CE_5_DST = 61, 95 HAL_SRNG_CE_6_DST = 62, 96 HAL_SRNG_CE_7_DST = 63, 97 HAL_SRNG_CE_8_DST = 64, 98 HAL_SRNG_CE_9_DST = 65, 99 HAL_SRNG_CE_10_DST = 66, 100 HAL_SRNG_CE_11_DST = 67, 101 /* 68-79 unused */ 102 HAL_SRNG_CE_0_DST_STATUS = 80, 103 HAL_SRNG_CE_1_DST_STATUS = 81, 104 HAL_SRNG_CE_2_DST_STATUS = 82, 105 HAL_SRNG_CE_3_DST_STATUS = 83, 106 HAL_SRNG_CE_4_DST_STATUS = 84, 107 HAL_SRNG_CE_5_DST_STATUS = 85, 108 HAL_SRNG_CE_6_DST_STATUS = 86, 109 HAL_SRNG_CE_7_DST_STATUS = 87, 110 HAL_SRNG_CE_8_DST_STATUS = 88, 111 HAL_SRNG_CE_9_DST_STATUS = 89, 112 HAL_SRNG_CE_10_DST_STATUS = 90, 113 HAL_SRNG_CE_11_DST_STATUS = 91, 114 /* 92-103 unused */ 115 HAL_SRNG_WBM_IDLE_LINK = 104, 116 HAL_SRNG_WBM_SW_RELEASE = 105, 117 HAL_SRNG_WBM2SW0_RELEASE = 106, 118 HAL_SRNG_WBM2SW1_RELEASE = 107, 119 HAL_SRNG_WBM2SW2_RELEASE = 108, 120 HAL_SRNG_WBM2SW3_RELEASE = 109, 121 /* 110-127 unused */ 122 HAL_SRNG_UMAC_ID_END = 127, 123 /* LMAC rings - The following set will be replicated for each LMAC */ 124 HAL_SRNG_LMAC1_ID_START = 128, 125 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 126 #ifdef IPA_OFFLOAD 127 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 128 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 129 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 130 #else 131 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 132 #endif 133 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 134 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 135 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 136 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 137 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 138 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 139 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 140 #ifdef WLAN_FEATURE_CIF_CFR 141 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 142 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 143 #else 144 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 145 #endif 146 /* -142 unused */ 147 HAL_SRNG_LMAC1_ID_END = 143 148 }; 149 150 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 151 #define HAL_MAX_LMACS 3 152 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 153 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 154 155 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 156 157 enum hal_srng_dir { 158 HAL_SRNG_SRC_RING, 159 HAL_SRNG_DST_RING 160 }; 161 162 /* Lock wrappers for SRNG */ 163 #define hal_srng_lock_t qdf_spinlock_t 164 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 165 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 166 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 167 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 168 169 struct hal_soc; 170 #define MAX_SRNG_REG_GROUPS 2 171 172 /* Common SRNG ring structure for source and destination rings */ 173 struct hal_srng { 174 /* Unique SRNG ring ID */ 175 uint8_t ring_id; 176 177 /* Ring initialization done */ 178 uint8_t initialized; 179 180 /* Interrupt/MSI value assigned to this ring */ 181 int irq; 182 183 /* Physical base address of the ring */ 184 qdf_dma_addr_t ring_base_paddr; 185 186 /* Virtual base address of the ring */ 187 uint32_t *ring_base_vaddr; 188 189 /* Number of entries in ring */ 190 uint32_t num_entries; 191 192 /* Ring size */ 193 uint32_t ring_size; 194 195 /* Ring size mask */ 196 uint32_t ring_size_mask; 197 198 /* Size of ring entry */ 199 uint32_t entry_size; 200 201 /* Interrupt timer threshold – in micro seconds */ 202 uint32_t intr_timer_thres_us; 203 204 /* Interrupt batch counter threshold – in number of ring entries */ 205 uint32_t intr_batch_cntr_thres_entries; 206 207 /* MSI Address */ 208 qdf_dma_addr_t msi_addr; 209 210 /* MSI data */ 211 uint32_t msi_data; 212 213 /* Misc flags */ 214 uint32_t flags; 215 216 /* Lock for serializing ring index updates */ 217 hal_srng_lock_t lock; 218 219 /* Start offset of SRNG register groups for this ring 220 * TBD: See if this is required - register address can be derived 221 * from ring ID 222 */ 223 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 224 225 /* Source or Destination ring */ 226 enum hal_srng_dir ring_dir; 227 228 union { 229 struct { 230 /* SW tail pointer */ 231 uint32_t tp; 232 233 /* Shadow head pointer location to be updated by HW */ 234 uint32_t *hp_addr; 235 236 /* Cached head pointer */ 237 uint32_t cached_hp; 238 239 /* Tail pointer location to be updated by SW – This 240 * will be a register address and need not be 241 * accessed through SW structure */ 242 uint32_t *tp_addr; 243 244 /* Current SW loop cnt */ 245 uint32_t loop_cnt; 246 247 /* max transfer size */ 248 uint16_t max_buffer_length; 249 } dst_ring; 250 251 struct { 252 /* SW head pointer */ 253 uint32_t hp; 254 255 /* SW reap head pointer */ 256 uint32_t reap_hp; 257 258 /* Shadow tail pointer location to be updated by HW */ 259 uint32_t *tp_addr; 260 261 /* Cached tail pointer */ 262 uint32_t cached_tp; 263 264 /* Head pointer location to be updated by SW – This 265 * will be a register address and need not be accessed 266 * through SW structure */ 267 uint32_t *hp_addr; 268 269 /* Low threshold – in number of ring entries */ 270 uint32_t low_threshold; 271 } src_ring; 272 } u; 273 274 struct hal_soc *hal_soc; 275 }; 276 277 /* HW SRNG configuration table */ 278 struct hal_hw_srng_config { 279 int start_ring_id; 280 uint16_t max_rings; 281 uint16_t entry_size; 282 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 283 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 284 uint8_t lmac_ring; 285 enum hal_srng_dir ring_dir; 286 uint32_t max_size; 287 }; 288 289 #define MAX_SHADOW_REGISTERS 36 290 291 struct hal_hw_txrx_ops { 292 293 /* init and setup */ 294 void (*hal_srng_dst_hw_init)(void *hal, 295 struct hal_srng *srng); 296 void (*hal_srng_src_hw_init)(void *hal, 297 struct hal_srng *srng); 298 void (*hal_get_hw_hptp)(struct hal_soc *hal, void *hal_ring, 299 uint32_t *headp, uint32_t *tailp, 300 uint8_t ring_type); 301 void (*hal_reo_setup)(void *hal_soc, void *reoparams); 302 void (*hal_setup_link_idle_list)(void *hal_soc, 303 qdf_dma_addr_t scatter_bufs_base_paddr[], 304 void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs, 305 uint32_t scatter_buf_size, uint32_t last_buf_end_offset, 306 uint32_t num_entries); 307 308 /* tx */ 309 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 310 void (*hal_tx_set_dscp_tid_map)(void *hal_soc, uint8_t *map, 311 uint8_t id); 312 void (*hal_tx_update_dscp_tid)(void *hal_soc, uint8_t tid, uint8_t id, 313 uint8_t dscp); 314 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 315 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 316 uint8_t pool_id, uint32_t desc_id, uint8_t type); 317 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 318 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 319 void (*hal_tx_comp_get_status)(void *desc, void *ts, void *hal); 320 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 321 322 /* rx */ 323 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 324 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 325 struct mon_rx_status *rs); 326 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 327 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 328 void *ppdu_info_handle); 329 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 330 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 331 uint8_t dbg_level); 332 uint32_t (*hal_get_link_desc_size)(void); 333 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 334 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 335 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 336 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 337 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 338 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 339 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 340 void *ppdu_info, 341 void *hal); 342 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 343 void *wbm_er_info); 344 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 345 uint8_t dbg_level); 346 347 void (*hal_tx_set_pcp_tid_map)(void *hal_soc, uint8_t *map); 348 void (*hal_tx_update_pcp_tid_map)(void *hal_soc, uint8_t pcp, 349 uint8_t id); 350 void (*hal_tx_set_tidmap_prty)(void *hal_soc, uint8_t prio); 351 }; 352 353 /** 354 * HAL context to be used to access SRNG APIs (currently used by data path 355 * and transport (CE) modules) 356 */ 357 struct hal_soc { 358 /* HIF handle to access HW registers */ 359 void *hif_handle; 360 361 /* QDF device handle */ 362 qdf_device_t qdf_dev; 363 364 /* Device base address */ 365 void *dev_base_addr; 366 367 /* HAL internal state for all SRNG rings. 368 * TODO: See if this is required 369 */ 370 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 371 372 /* Remote pointer memory for HW/FW updates */ 373 uint32_t *shadow_rdptr_mem_vaddr; 374 qdf_dma_addr_t shadow_rdptr_mem_paddr; 375 376 /* Shared memory for ring pointer updates from host to FW */ 377 uint32_t *shadow_wrptr_mem_vaddr; 378 qdf_dma_addr_t shadow_wrptr_mem_paddr; 379 380 /* REO blocking resource index */ 381 uint8_t reo_res_bitmap; 382 uint8_t index; 383 uint32_t target_type; 384 385 /* shadow register configuration */ 386 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 387 int num_shadow_registers_configured; 388 bool use_register_windowing; 389 uint32_t register_window; 390 qdf_spinlock_t register_access_lock; 391 392 /* srng table */ 393 struct hal_hw_srng_config *hw_srng_table; 394 int32_t *hal_hw_reg_offset; 395 struct hal_hw_txrx_ops *ops; 396 }; 397 398 void hal_qca6390_attach(struct hal_soc *hal_soc); 399 void hal_qca6290_attach(struct hal_soc *hal_soc); 400 void hal_qca8074_attach(struct hal_soc *hal_soc); 401 #endif /* _HAL_INTERNAL_H_ */ 402