1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "pld_common.h" 27 28 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_TXRX, params) 29 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_TXRX, params) 30 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_TXRX, params) 31 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_TXRX, params) 32 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 33 34 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 35 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 36 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 37 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 38 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 39 40 #ifdef ENABLE_VERBOSE_DEBUG 41 extern bool is_hal_verbose_debug_enabled; 42 #define hal_verbose_debug(params...) \ 43 if (unlikely(is_hal_verbose_debug_enabled)) \ 44 do {\ 45 QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params); \ 46 } while (0) 47 #define hal_verbose_hex_dump(params...) \ 48 if (unlikely(is_hal_verbose_debug_enabled)) \ 49 do {\ 50 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, \ 51 QDF_TRACE_LEVEL_DEBUG, \ 52 params); \ 53 } while (0) 54 #else 55 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 56 #define hal_verbose_hex_dump(params...) \ 57 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, \ 58 params) 59 #endif 60 61 /* 62 * dp_hal_soc - opaque handle for DP HAL soc 63 */ 64 struct hal_soc_handle; 65 typedef struct hal_soc_handle *hal_soc_handle_t; 66 67 /* TBD: This should be movded to shared HW header file */ 68 enum hal_srng_ring_id { 69 /* UMAC rings */ 70 HAL_SRNG_REO2SW1 = 0, 71 HAL_SRNG_REO2SW2 = 1, 72 HAL_SRNG_REO2SW3 = 2, 73 HAL_SRNG_REO2SW4 = 3, 74 HAL_SRNG_REO2TCL = 4, 75 HAL_SRNG_SW2REO = 5, 76 /* 6-7 unused */ 77 HAL_SRNG_REO_CMD = 8, 78 HAL_SRNG_REO_STATUS = 9, 79 /* 10-15 unused */ 80 HAL_SRNG_SW2TCL1 = 16, 81 HAL_SRNG_SW2TCL2 = 17, 82 HAL_SRNG_SW2TCL3 = 18, 83 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 84 /* 20-23 unused */ 85 HAL_SRNG_SW2TCL_CMD = 24, 86 HAL_SRNG_TCL_STATUS = 25, 87 /* 26-31 unused */ 88 HAL_SRNG_CE_0_SRC = 32, 89 HAL_SRNG_CE_1_SRC = 33, 90 HAL_SRNG_CE_2_SRC = 34, 91 HAL_SRNG_CE_3_SRC = 35, 92 HAL_SRNG_CE_4_SRC = 36, 93 HAL_SRNG_CE_5_SRC = 37, 94 HAL_SRNG_CE_6_SRC = 38, 95 HAL_SRNG_CE_7_SRC = 39, 96 HAL_SRNG_CE_8_SRC = 40, 97 HAL_SRNG_CE_9_SRC = 41, 98 HAL_SRNG_CE_10_SRC = 42, 99 HAL_SRNG_CE_11_SRC = 43, 100 /* 44-55 unused */ 101 HAL_SRNG_CE_0_DST = 56, 102 HAL_SRNG_CE_1_DST = 57, 103 HAL_SRNG_CE_2_DST = 58, 104 HAL_SRNG_CE_3_DST = 59, 105 HAL_SRNG_CE_4_DST = 60, 106 HAL_SRNG_CE_5_DST = 61, 107 HAL_SRNG_CE_6_DST = 62, 108 HAL_SRNG_CE_7_DST = 63, 109 HAL_SRNG_CE_8_DST = 64, 110 HAL_SRNG_CE_9_DST = 65, 111 HAL_SRNG_CE_10_DST = 66, 112 HAL_SRNG_CE_11_DST = 67, 113 /* 68-79 unused */ 114 HAL_SRNG_CE_0_DST_STATUS = 80, 115 HAL_SRNG_CE_1_DST_STATUS = 81, 116 HAL_SRNG_CE_2_DST_STATUS = 82, 117 HAL_SRNG_CE_3_DST_STATUS = 83, 118 HAL_SRNG_CE_4_DST_STATUS = 84, 119 HAL_SRNG_CE_5_DST_STATUS = 85, 120 HAL_SRNG_CE_6_DST_STATUS = 86, 121 HAL_SRNG_CE_7_DST_STATUS = 87, 122 HAL_SRNG_CE_8_DST_STATUS = 88, 123 HAL_SRNG_CE_9_DST_STATUS = 89, 124 HAL_SRNG_CE_10_DST_STATUS = 90, 125 HAL_SRNG_CE_11_DST_STATUS = 91, 126 /* 92-103 unused */ 127 HAL_SRNG_WBM_IDLE_LINK = 104, 128 HAL_SRNG_WBM_SW_RELEASE = 105, 129 HAL_SRNG_WBM2SW0_RELEASE = 106, 130 HAL_SRNG_WBM2SW1_RELEASE = 107, 131 HAL_SRNG_WBM2SW2_RELEASE = 108, 132 HAL_SRNG_WBM2SW3_RELEASE = 109, 133 /* 110-127 unused */ 134 HAL_SRNG_UMAC_ID_END = 127, 135 /* LMAC rings - The following set will be replicated for each LMAC */ 136 HAL_SRNG_LMAC1_ID_START = 128, 137 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 138 #ifdef IPA_OFFLOAD 139 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 140 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 141 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 142 #else 143 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 144 #endif 145 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 146 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 147 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 148 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 149 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 150 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 151 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 152 #ifdef WLAN_FEATURE_CIF_CFR 153 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 154 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 155 #else 156 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 157 #endif 158 /* -142 unused */ 159 HAL_SRNG_LMAC1_ID_END = 143 160 }; 161 162 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 163 #define HAL_MAX_LMACS 3 164 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 165 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 166 167 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 168 169 enum hal_srng_dir { 170 HAL_SRNG_SRC_RING, 171 HAL_SRNG_DST_RING 172 }; 173 174 /* Lock wrappers for SRNG */ 175 #define hal_srng_lock_t qdf_spinlock_t 176 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 177 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 178 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 179 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 180 181 struct hal_soc; 182 183 /** 184 * dp_hal_ring - opaque handle for DP HAL SRNG 185 */ 186 struct hal_ring_handle; 187 typedef struct hal_ring_handle *hal_ring_handle_t; 188 189 #define MAX_SRNG_REG_GROUPS 2 190 191 /* Hal Srng bit mask 192 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 193 */ 194 #define HAL_SRNG_FLUSH_EVENT BIT(0) 195 196 /* Common SRNG ring structure for source and destination rings */ 197 struct hal_srng { 198 /* Unique SRNG ring ID */ 199 uint8_t ring_id; 200 201 /* Ring initialization done */ 202 uint8_t initialized; 203 204 /* Interrupt/MSI value assigned to this ring */ 205 int irq; 206 207 /* Physical base address of the ring */ 208 qdf_dma_addr_t ring_base_paddr; 209 210 /* Virtual base address of the ring */ 211 uint32_t *ring_base_vaddr; 212 213 /* Number of entries in ring */ 214 uint32_t num_entries; 215 216 /* Ring size */ 217 uint32_t ring_size; 218 219 /* Ring size mask */ 220 uint32_t ring_size_mask; 221 222 /* Size of ring entry */ 223 uint32_t entry_size; 224 225 /* Interrupt timer threshold – in micro seconds */ 226 uint32_t intr_timer_thres_us; 227 228 /* Interrupt batch counter threshold – in number of ring entries */ 229 uint32_t intr_batch_cntr_thres_entries; 230 231 /* MSI Address */ 232 qdf_dma_addr_t msi_addr; 233 234 /* MSI data */ 235 uint32_t msi_data; 236 237 /* Misc flags */ 238 uint32_t flags; 239 240 /* Lock for serializing ring index updates */ 241 hal_srng_lock_t lock; 242 243 /* Start offset of SRNG register groups for this ring 244 * TBD: See if this is required - register address can be derived 245 * from ring ID 246 */ 247 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 248 249 /* Source or Destination ring */ 250 enum hal_srng_dir ring_dir; 251 252 union { 253 struct { 254 /* SW tail pointer */ 255 uint32_t tp; 256 257 /* Shadow head pointer location to be updated by HW */ 258 uint32_t *hp_addr; 259 260 /* Cached head pointer */ 261 uint32_t cached_hp; 262 263 /* Tail pointer location to be updated by SW – This 264 * will be a register address and need not be 265 * accessed through SW structure */ 266 uint32_t *tp_addr; 267 268 /* Current SW loop cnt */ 269 uint32_t loop_cnt; 270 271 /* max transfer size */ 272 uint16_t max_buffer_length; 273 } dst_ring; 274 275 struct { 276 /* SW head pointer */ 277 uint32_t hp; 278 279 /* SW reap head pointer */ 280 uint32_t reap_hp; 281 282 /* Shadow tail pointer location to be updated by HW */ 283 uint32_t *tp_addr; 284 285 /* Cached tail pointer */ 286 uint32_t cached_tp; 287 288 /* Head pointer location to be updated by SW – This 289 * will be a register address and need not be accessed 290 * through SW structure */ 291 uint32_t *hp_addr; 292 293 /* Low threshold – in number of ring entries */ 294 uint32_t low_threshold; 295 } src_ring; 296 } u; 297 298 struct hal_soc *hal_soc; 299 300 /* Number of times hp/tp updated in runtime resume */ 301 uint32_t flush_count; 302 /* hal srng event flag*/ 303 unsigned long srng_event; 304 /* last flushed time stamp */ 305 uint64_t last_flush_ts; 306 }; 307 308 /* HW SRNG configuration table */ 309 struct hal_hw_srng_config { 310 int start_ring_id; 311 uint16_t max_rings; 312 uint16_t entry_size; 313 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 314 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 315 uint8_t lmac_ring; 316 enum hal_srng_dir ring_dir; 317 uint32_t max_size; 318 }; 319 320 #define MAX_SHADOW_REGISTERS 36 321 322 /* REO parameters to be passed to hal_reo_setup */ 323 struct hal_reo_params { 324 /** rx hash steering enabled or disabled */ 325 bool rx_hash_enabled; 326 /** reo remap 1 register */ 327 uint32_t remap1; 328 /** reo remap 2 register */ 329 uint32_t remap2; 330 /** fragment destination ring */ 331 uint8_t frag_dst_ring; 332 /** padding */ 333 uint8_t padding[3]; 334 }; 335 336 struct hal_hw_txrx_ops { 337 338 /* init and setup */ 339 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 340 struct hal_srng *srng); 341 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 342 struct hal_srng *srng); 343 void (*hal_get_hw_hptp)(struct hal_soc *hal, 344 hal_ring_handle_t hal_ring_hdl, 345 uint32_t *headp, uint32_t *tailp, 346 uint8_t ring_type); 347 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams); 348 void (*hal_setup_link_idle_list)( 349 struct hal_soc *hal_soc, 350 qdf_dma_addr_t scatter_bufs_base_paddr[], 351 void *scatter_bufs_base_vaddr[], 352 uint32_t num_scatter_bufs, 353 uint32_t scatter_buf_size, 354 uint32_t last_buf_end_offset, 355 uint32_t num_entries); 356 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 357 qdf_iomem_t addr); 358 359 /* tx */ 360 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 361 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 362 uint8_t id); 363 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 364 uint8_t id, 365 uint8_t dscp); 366 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 367 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 368 uint8_t pool_id, uint32_t desc_id, uint8_t type); 369 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 370 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 371 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 372 void (*hal_tx_comp_get_status)(void *desc, void *ts, 373 struct hal_soc *hal); 374 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 375 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 376 377 /* rx */ 378 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 379 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 380 struct mon_rx_status *rs); 381 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 382 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 383 void *ppdu_info_handle); 384 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 385 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 386 uint8_t dbg_level); 387 uint32_t (*hal_get_link_desc_size)(void); 388 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 389 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 390 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 391 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 392 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 393 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 394 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 395 void *ppdu_info, 396 hal_soc_handle_t hal_soc_hdl, 397 qdf_nbuf_t nbuf); 398 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 399 void *wbm_er_info); 400 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 401 uint8_t dbg_level); 402 403 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 404 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 405 uint8_t id); 406 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 407 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 408 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 409 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 410 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 411 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 412 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 413 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 414 void (*hal_rx_print_pn)(uint8_t *buf); 415 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 416 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 417 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 418 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 419 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 420 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 421 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 422 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 423 QDF_STATUS 424 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 425 QDF_STATUS 426 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 427 QDF_STATUS 428 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 429 QDF_STATUS 430 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 431 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 432 bool (*hal_rx_is_unicast)(uint8_t *buf); 433 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 434 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *hw_desc_addr); 435 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 436 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 437 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 438 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 439 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 440 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 441 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 442 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 443 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 444 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 445 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 446 void (*hal_reo_config)(struct hal_soc *soc, 447 uint32_t reg_val, 448 struct hal_reo_params *reo_params); 449 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 450 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 451 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 452 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 453 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 454 void 455 (*hal_rx_msdu_get_flow_params)( 456 uint8_t *buf, 457 bool *flow_invalid, 458 bool *flow_timeout, 459 uint32_t *flow_index); 460 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 461 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 462 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 463 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 464 }; 465 466 /** 467 * HAL context to be used to access SRNG APIs (currently used by data path 468 * and transport (CE) modules) 469 */ 470 struct hal_soc { 471 /* HIF handle to access HW registers */ 472 struct hif_opaque_softc *hif_handle; 473 474 /* QDF device handle */ 475 qdf_device_t qdf_dev; 476 477 /* Device base address */ 478 void *dev_base_addr; 479 480 /* HAL internal state for all SRNG rings. 481 * TODO: See if this is required 482 */ 483 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 484 485 /* Remote pointer memory for HW/FW updates */ 486 uint32_t *shadow_rdptr_mem_vaddr; 487 qdf_dma_addr_t shadow_rdptr_mem_paddr; 488 489 /* Shared memory for ring pointer updates from host to FW */ 490 uint32_t *shadow_wrptr_mem_vaddr; 491 qdf_dma_addr_t shadow_wrptr_mem_paddr; 492 493 /* REO blocking resource index */ 494 uint8_t reo_res_bitmap; 495 uint8_t index; 496 uint32_t target_type; 497 498 /* shadow register configuration */ 499 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 500 int num_shadow_registers_configured; 501 bool use_register_windowing; 502 uint32_t register_window; 503 qdf_spinlock_t register_access_lock; 504 505 /* Static window map configuration for multiple window write*/ 506 bool static_window_map; 507 508 /* srng table */ 509 struct hal_hw_srng_config *hw_srng_table; 510 int32_t *hal_hw_reg_offset; 511 struct hal_hw_txrx_ops *ops; 512 513 /* Indicate srngs initialization */ 514 bool init_phase; 515 }; 516 517 void hal_qca6490_attach(struct hal_soc *hal_soc); 518 void hal_qca6390_attach(struct hal_soc *hal_soc); 519 void hal_qca6290_attach(struct hal_soc *hal_soc); 520 void hal_qca8074_attach(struct hal_soc *hal_soc); 521 522 /* 523 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 524 * dp_hal_soc handle type 525 * @hal_soc - hal_soc type 526 * 527 * Return: hal_soc_handle_t type 528 */ 529 static inline 530 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 531 { 532 return (hal_soc_handle_t)hal_soc; 533 } 534 535 /* 536 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 537 * dp_hal_ring handle type 538 * @hal_srng - hal_srng type 539 * 540 * Return: hal_ring_handle_t type 541 */ 542 static inline 543 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 544 { 545 return (hal_ring_handle_t)hal_srng; 546 } 547 548 /* 549 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 550 * @hal_ring - hal_ring_handle_t type 551 * 552 * Return: hal_srng pointer type 553 */ 554 static inline 555 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 556 { 557 return (struct hal_srng *)hal_ring; 558 } 559 #endif /* _HAL_INTERNAL_H_ */ 560