1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer in the documentation and/or other materials provided 12 * with the distribution. 13 * * Neither the name of The Linux Foundation nor the names of its 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _HAL_INTERNAL_H_ 31 #define _HAL_INTERNAL_H_ 32 33 #include "qdf_types.h" 34 #include "qdf_lock.h" 35 #include "qdf_mem.h" 36 #include "qdf_nbuf.h" 37 #include "wcss_seq_hwiobase.h" 38 #include "tlv_hdr.h" 39 #include "tlv_tag_def.h" 40 #include "reo_destination_ring.h" 41 #include "reo_reg_seq_hwioreg.h" 42 #include "reo_entrance_ring.h" 43 #include "reo_get_queue_stats.h" 44 #include "reo_get_queue_stats_status.h" 45 #include "tcl_data_cmd.h" 46 #include "tcl_gse_cmd.h" 47 #include "tcl_status_ring.h" 48 #include "mac_tcl_reg_seq_hwioreg.h" 49 #include "ce_src_desc.h" 50 #include "ce_stat_desc.h" 51 #include "wfss_ce_reg_seq_hwioreg.h" 52 #include "wbm_link_descriptor_ring.h" 53 #include "wbm_reg_seq_hwioreg.h" 54 #include "wbm_buffer_ring.h" 55 #include "wbm_release_ring.h" 56 #include "rx_msdu_desc_info.h" 57 #include "rx_mpdu_start.h" 58 #include "rx_mpdu_end.h" 59 #include "rx_msdu_start.h" 60 #include "rx_msdu_end.h" 61 #include "rx_attention.h" 62 #include "rx_ppdu_start.h" 63 #include "rx_ppdu_start_user_info.h" 64 #include "rx_ppdu_end_user_stats.h" 65 #include "rx_ppdu_end_user_stats_ext.h" 66 #include "rx_mpdu_desc_info.h" 67 #include "rxpcu_ppdu_end_info.h" 68 #include "phyrx_he_sig_a_su.h" 69 #include "phyrx_he_sig_a_mu_dl.h" 70 #include "phyrx_he_sig_b1_mu.h" 71 #include "phyrx_he_sig_b2_mu.h" 72 #include "phyrx_he_sig_b2_ofdma.h" 73 #include "phyrx_l_sig_a.h" 74 #include "phyrx_l_sig_b.h" 75 #include "phyrx_vht_sig_a.h" 76 #include "phyrx_ht_sig.h" 77 #include "tx_msdu_extension.h" 78 #include "receive_rssi_info.h" 79 #include "phyrx_pkt_end.h" 80 #include "phyrx_rssi_legacy.h" 81 #include "wcss_version.h" 82 #include "pld_common.h" 83 #include "rx_msdu_link.h" 84 85 #ifdef QCA_WIFI_QCA6290_11AX 86 #include "phyrx_other_receive_info_ru_details.h" 87 #endif /* QCA_WIFI_QCA6290_11AX */ 88 89 /* TBD: This should be movded to shared HW header file */ 90 enum hal_srng_ring_id { 91 /* UMAC rings */ 92 HAL_SRNG_REO2SW1 = 0, 93 HAL_SRNG_REO2SW2 = 1, 94 HAL_SRNG_REO2SW3 = 2, 95 HAL_SRNG_REO2SW4 = 3, 96 HAL_SRNG_REO2TCL = 4, 97 HAL_SRNG_SW2REO = 5, 98 /* 6-7 unused */ 99 HAL_SRNG_REO_CMD = 8, 100 HAL_SRNG_REO_STATUS = 9, 101 /* 10-15 unused */ 102 HAL_SRNG_SW2TCL1 = 16, 103 HAL_SRNG_SW2TCL2 = 17, 104 HAL_SRNG_SW2TCL3 = 18, 105 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 106 /* 20-23 unused */ 107 HAL_SRNG_SW2TCL_CMD = 24, 108 HAL_SRNG_TCL_STATUS = 25, 109 /* 26-31 unused */ 110 HAL_SRNG_CE_0_SRC = 32, 111 HAL_SRNG_CE_1_SRC = 33, 112 HAL_SRNG_CE_2_SRC = 34, 113 HAL_SRNG_CE_3_SRC = 35, 114 HAL_SRNG_CE_4_SRC = 36, 115 HAL_SRNG_CE_5_SRC = 37, 116 HAL_SRNG_CE_6_SRC = 38, 117 HAL_SRNG_CE_7_SRC = 39, 118 HAL_SRNG_CE_8_SRC = 40, 119 HAL_SRNG_CE_9_SRC = 41, 120 HAL_SRNG_CE_10_SRC = 42, 121 HAL_SRNG_CE_11_SRC = 43, 122 /* 44-55 unused */ 123 HAL_SRNG_CE_0_DST = 56, 124 HAL_SRNG_CE_1_DST = 57, 125 HAL_SRNG_CE_2_DST = 58, 126 HAL_SRNG_CE_3_DST = 59, 127 HAL_SRNG_CE_4_DST = 60, 128 HAL_SRNG_CE_5_DST = 61, 129 HAL_SRNG_CE_6_DST = 62, 130 HAL_SRNG_CE_7_DST = 63, 131 HAL_SRNG_CE_8_DST = 64, 132 HAL_SRNG_CE_9_DST = 65, 133 HAL_SRNG_CE_10_DST = 66, 134 HAL_SRNG_CE_11_DST = 67, 135 /* 68-79 unused */ 136 HAL_SRNG_CE_0_DST_STATUS = 80, 137 HAL_SRNG_CE_1_DST_STATUS = 81, 138 HAL_SRNG_CE_2_DST_STATUS = 82, 139 HAL_SRNG_CE_3_DST_STATUS = 83, 140 HAL_SRNG_CE_4_DST_STATUS = 84, 141 HAL_SRNG_CE_5_DST_STATUS = 85, 142 HAL_SRNG_CE_6_DST_STATUS = 86, 143 HAL_SRNG_CE_7_DST_STATUS = 87, 144 HAL_SRNG_CE_8_DST_STATUS = 88, 145 HAL_SRNG_CE_9_DST_STATUS = 89, 146 HAL_SRNG_CE_10_DST_STATUS = 90, 147 HAL_SRNG_CE_11_DST_STATUS = 91, 148 /* 92-103 unused */ 149 HAL_SRNG_WBM_IDLE_LINK = 104, 150 HAL_SRNG_WBM_SW_RELEASE = 105, 151 HAL_SRNG_WBM2SW0_RELEASE = 106, 152 HAL_SRNG_WBM2SW1_RELEASE = 107, 153 HAL_SRNG_WBM2SW2_RELEASE = 108, 154 HAL_SRNG_WBM2SW3_RELEASE = 109, 155 /* 110-127 unused */ 156 HAL_SRNG_UMAC_ID_END = 127, 157 /* LMAC rings - The following set will be replicated for each LMAC */ 158 HAL_SRNG_LMAC1_ID_START = 128, 159 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 160 #ifdef IPA_OFFLOAD 161 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 162 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 163 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 164 #else 165 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 166 #endif 167 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 168 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 169 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 170 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 171 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 172 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 173 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 174 #ifdef WLAN_FEATURE_CIF_CFR 175 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 176 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 177 #else 178 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 179 #endif 180 /* -142 unused */ 181 HAL_SRNG_LMAC1_ID_END = 143 182 }; 183 184 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 185 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 186 187 #define HAL_MAX_LMACS 3 188 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 189 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 190 191 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 192 193 enum hal_srng_dir { 194 HAL_SRNG_SRC_RING, 195 HAL_SRNG_DST_RING 196 }; 197 198 /* Lock wrappers for SRNG */ 199 #define hal_srng_lock_t qdf_spinlock_t 200 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 201 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 202 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 203 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 204 205 #define MAX_SRNG_REG_GROUPS 2 206 207 /* Common SRNG ring structure for source and destination rings */ 208 struct hal_srng { 209 /* Unique SRNG ring ID */ 210 uint8_t ring_id; 211 212 /* Ring initialization done */ 213 uint8_t initialized; 214 215 /* Interrupt/MSI value assigned to this ring */ 216 int irq; 217 218 /* Physical base address of the ring */ 219 qdf_dma_addr_t ring_base_paddr; 220 221 /* Virtual base address of the ring */ 222 uint32_t *ring_base_vaddr; 223 224 /* Number of entries in ring */ 225 uint32_t num_entries; 226 227 /* Ring size */ 228 uint32_t ring_size; 229 230 /* Ring size mask */ 231 uint32_t ring_size_mask; 232 233 /* Size of ring entry */ 234 uint32_t entry_size; 235 236 /* Interrupt timer threshold – in micro seconds */ 237 uint32_t intr_timer_thres_us; 238 239 /* Interrupt batch counter threshold – in number of ring entries */ 240 uint32_t intr_batch_cntr_thres_entries; 241 242 /* MSI Address */ 243 qdf_dma_addr_t msi_addr; 244 245 /* MSI data */ 246 uint32_t msi_data; 247 248 /* Misc flags */ 249 uint32_t flags; 250 251 /* Lock for serializing ring index updates */ 252 hal_srng_lock_t lock; 253 254 /* Start offset of SRNG register groups for this ring 255 * TBD: See if this is required - register address can be derived 256 * from ring ID 257 */ 258 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 259 260 /* Source or Destination ring */ 261 enum hal_srng_dir ring_dir; 262 263 union { 264 struct { 265 /* SW tail pointer */ 266 uint32_t tp; 267 268 /* Shadow head pointer location to be updated by HW */ 269 uint32_t *hp_addr; 270 271 /* Cached head pointer */ 272 uint32_t cached_hp; 273 274 /* Tail pointer location to be updated by SW – This 275 * will be a register address and need not be 276 * accessed through SW structure */ 277 uint32_t *tp_addr; 278 279 /* Current SW loop cnt */ 280 uint32_t loop_cnt; 281 282 /* max transfer size */ 283 uint16_t max_buffer_length; 284 } dst_ring; 285 286 struct { 287 /* SW head pointer */ 288 uint32_t hp; 289 290 /* SW reap head pointer */ 291 uint32_t reap_hp; 292 293 /* Shadow tail pointer location to be updated by HW */ 294 uint32_t *tp_addr; 295 296 /* Cached tail pointer */ 297 uint32_t cached_tp; 298 299 /* Head pointer location to be updated by SW – This 300 * will be a register address and need not be accessed 301 * through SW structure */ 302 uint32_t *hp_addr; 303 304 /* Low threshold – in number of ring entries */ 305 uint32_t low_threshold; 306 } src_ring; 307 } u; 308 309 struct hal_soc *hal_soc; 310 }; 311 312 /* HW SRNG configuration table */ 313 struct hal_hw_srng_config { 314 int start_ring_id; 315 uint16_t max_rings; 316 uint16_t entry_size; 317 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 318 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 319 uint8_t lmac_ring; 320 enum hal_srng_dir ring_dir; 321 uint32_t max_size; 322 }; 323 324 /* calculate the register address offset from bar0 of shadow register x */ 325 #define SHADOW_REGISTER(x) (0x00003024 + (4*x)) 326 #define MAX_SHADOW_REGISTERS 36 327 328 /** 329 * HAL context to be used to access SRNG APIs (currently used by data path 330 * and transport (CE) modules) 331 */ 332 struct hal_soc { 333 /* HIF handle to access HW registers */ 334 void *hif_handle; 335 336 /* QDF device handle */ 337 qdf_device_t qdf_dev; 338 339 /* Device base address */ 340 void *dev_base_addr; 341 342 /* HAL internal state for all SRNG rings. 343 * TODO: See if this is required 344 */ 345 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 346 347 /* Remote pointer memory for HW/FW updates */ 348 uint32_t *shadow_rdptr_mem_vaddr; 349 qdf_dma_addr_t shadow_rdptr_mem_paddr; 350 351 /* Shared memory for ring pointer updates from host to FW */ 352 uint32_t *shadow_wrptr_mem_vaddr; 353 qdf_dma_addr_t shadow_wrptr_mem_paddr; 354 355 /* REO blocking resource index */ 356 uint8_t reo_res_bitmap; 357 uint8_t index; 358 359 /* shadow register configuration */ 360 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 361 int num_shadow_registers_configured; 362 bool use_register_windowing; 363 uint32_t register_window; 364 qdf_spinlock_t register_access_lock; 365 }; 366 367 /* TODO: Check if the following can be provided directly by HW headers */ 368 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 369 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 370 371 #define HAL_SRNG_LMAC_RING 0x80000000 372 373 #define HAL_DEFAULT_REO_TIMEOUT_MS 40 /* milliseconds */ 374 375 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ 376 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ 377 ~(_word ## _ ## _fld ## _MASK); \ 378 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ 379 ((_value) << _word ## _ ## _fld ## _LSB); \ 380 } while (0) 381 382 #define HAL_SM(_reg, _fld, _val) \ 383 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ 384 (_reg ## _ ## _fld ## _BMSK)) 385 386 #define HAL_MS(_reg, _fld, _val) \ 387 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ 388 (_reg ## _ ## _fld ## _SHFT)) 389 390 #define HAL_REG_WRITE(_soc, _reg, _value) \ 391 hal_write32_mb(_soc, (_reg), (_value)) 392 393 #define HAL_REG_READ(_soc, _offset) \ 394 hal_read32_mb(_soc, (_offset)) 395 396 #endif /* _HAL_INTERNAL_H_ */ 397