1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_atomic.h" 24 #include "qdf_lock.h" 25 #include "qdf_mem.h" 26 #include "qdf_nbuf.h" 27 #include "pld_common.h" 28 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 29 #include "qdf_defer.h" 30 #endif 31 32 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 33 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 34 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 35 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params) 36 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 37 38 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 39 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 40 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 41 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 43 44 #ifdef ENABLE_VERBOSE_DEBUG 45 extern bool is_hal_verbose_debug_enabled; 46 #define hal_verbose_debug(params...) \ 47 if (unlikely(is_hal_verbose_debug_enabled)) \ 48 do {\ 49 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 50 } while (0) 51 #define hal_verbose_hex_dump(params...) \ 52 if (unlikely(is_hal_verbose_debug_enabled)) \ 53 do {\ 54 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 55 QDF_TRACE_LEVEL_DEBUG, \ 56 params); \ 57 } while (0) 58 #else 59 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 60 #define hal_verbose_hex_dump(params...) \ 61 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 62 params) 63 #endif 64 65 /* 66 * dp_hal_soc - opaque handle for DP HAL soc 67 */ 68 struct hal_soc_handle; 69 typedef struct hal_soc_handle *hal_soc_handle_t; 70 71 /** 72 * hal_ring_desc - opaque handle for DP ring descriptor 73 */ 74 struct hal_ring_desc; 75 typedef struct hal_ring_desc *hal_ring_desc_t; 76 77 /** 78 * hal_link_desc - opaque handle for DP link descriptor 79 */ 80 struct hal_link_desc; 81 typedef struct hal_link_desc *hal_link_desc_t; 82 83 /** 84 * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor 85 */ 86 struct hal_rxdma_desc; 87 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 88 89 /** 90 * hal_buff_addrinfo - opaque handle for DP buffer address info 91 */ 92 struct hal_buff_addrinfo; 93 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 94 95 /** 96 * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info 97 */ 98 struct hal_rx_mon_desc_info; 99 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 100 101 /* TBD: This should be movded to shared HW header file */ 102 enum hal_srng_ring_id { 103 /* UMAC rings */ 104 HAL_SRNG_REO2SW1 = 0, 105 HAL_SRNG_REO2SW2 = 1, 106 HAL_SRNG_REO2SW3 = 2, 107 HAL_SRNG_REO2SW4 = 3, 108 HAL_SRNG_REO2TCL = 4, 109 HAL_SRNG_SW2REO = 5, 110 /* 6-7 unused */ 111 HAL_SRNG_REO_CMD = 8, 112 HAL_SRNG_REO_STATUS = 9, 113 /* 10-15 unused */ 114 HAL_SRNG_SW2TCL1 = 16, 115 HAL_SRNG_SW2TCL2 = 17, 116 HAL_SRNG_SW2TCL3 = 18, 117 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 118 /* 20-23 unused */ 119 HAL_SRNG_SW2TCL_CMD = 24, 120 HAL_SRNG_TCL_STATUS = 25, 121 /* 26-31 unused */ 122 HAL_SRNG_CE_0_SRC = 32, 123 HAL_SRNG_CE_1_SRC = 33, 124 HAL_SRNG_CE_2_SRC = 34, 125 HAL_SRNG_CE_3_SRC = 35, 126 HAL_SRNG_CE_4_SRC = 36, 127 HAL_SRNG_CE_5_SRC = 37, 128 HAL_SRNG_CE_6_SRC = 38, 129 HAL_SRNG_CE_7_SRC = 39, 130 HAL_SRNG_CE_8_SRC = 40, 131 HAL_SRNG_CE_9_SRC = 41, 132 HAL_SRNG_CE_10_SRC = 42, 133 HAL_SRNG_CE_11_SRC = 43, 134 /* 44-55 unused */ 135 HAL_SRNG_CE_0_DST = 56, 136 HAL_SRNG_CE_1_DST = 57, 137 HAL_SRNG_CE_2_DST = 58, 138 HAL_SRNG_CE_3_DST = 59, 139 HAL_SRNG_CE_4_DST = 60, 140 HAL_SRNG_CE_5_DST = 61, 141 HAL_SRNG_CE_6_DST = 62, 142 HAL_SRNG_CE_7_DST = 63, 143 HAL_SRNG_CE_8_DST = 64, 144 HAL_SRNG_CE_9_DST = 65, 145 HAL_SRNG_CE_10_DST = 66, 146 HAL_SRNG_CE_11_DST = 67, 147 /* 68-79 unused */ 148 HAL_SRNG_CE_0_DST_STATUS = 80, 149 HAL_SRNG_CE_1_DST_STATUS = 81, 150 HAL_SRNG_CE_2_DST_STATUS = 82, 151 HAL_SRNG_CE_3_DST_STATUS = 83, 152 HAL_SRNG_CE_4_DST_STATUS = 84, 153 HAL_SRNG_CE_5_DST_STATUS = 85, 154 HAL_SRNG_CE_6_DST_STATUS = 86, 155 HAL_SRNG_CE_7_DST_STATUS = 87, 156 HAL_SRNG_CE_8_DST_STATUS = 88, 157 HAL_SRNG_CE_9_DST_STATUS = 89, 158 HAL_SRNG_CE_10_DST_STATUS = 90, 159 HAL_SRNG_CE_11_DST_STATUS = 91, 160 /* 92-103 unused */ 161 HAL_SRNG_WBM_IDLE_LINK = 104, 162 HAL_SRNG_WBM_SW_RELEASE = 105, 163 HAL_SRNG_WBM2SW0_RELEASE = 106, 164 HAL_SRNG_WBM2SW1_RELEASE = 107, 165 HAL_SRNG_WBM2SW2_RELEASE = 108, 166 HAL_SRNG_WBM2SW3_RELEASE = 109, 167 /* 110-127 unused */ 168 HAL_SRNG_UMAC_ID_END = 127, 169 /* LMAC rings - The following set will be replicated for each LMAC */ 170 HAL_SRNG_LMAC1_ID_START = 128, 171 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 172 #ifdef IPA_OFFLOAD 173 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 174 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 175 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 176 #else 177 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 178 #endif 179 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 180 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 181 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 182 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 183 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 184 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 185 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 186 #ifdef WLAN_FEATURE_CIF_CFR 187 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 188 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 189 #else 190 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 191 #endif 192 /* -142 unused */ 193 HAL_SRNG_LMAC1_ID_END = 143 194 }; 195 196 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 197 #define HAL_MAX_LMACS 3 198 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 199 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 200 201 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 202 203 enum hal_srng_dir { 204 HAL_SRNG_SRC_RING, 205 HAL_SRNG_DST_RING 206 }; 207 208 /* Lock wrappers for SRNG */ 209 #define hal_srng_lock_t qdf_spinlock_t 210 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 211 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 212 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock) 213 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 214 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 215 216 struct hal_soc; 217 218 /** 219 * dp_hal_ring - opaque handle for DP HAL SRNG 220 */ 221 struct hal_ring_handle; 222 typedef struct hal_ring_handle *hal_ring_handle_t; 223 224 #define MAX_SRNG_REG_GROUPS 2 225 226 /* Hal Srng bit mask 227 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 228 */ 229 #define HAL_SRNG_FLUSH_EVENT BIT(0) 230 231 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 232 233 /** 234 * struct hal_reg_write_q_elem - delayed register write queue element 235 * @srng: hal_srng queued for a delayed write 236 * @addr: iomem address of the register 237 * @enqueue_val: register value at the time of delayed write enqueue 238 * @dequeue_val: register value at the time of delayed write dequeue 239 * @valid: whether this entry is valid or not 240 * @enqueue_time: enqueue time (qdf_log_timestamp) 241 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 242 * @dequeue_time: dequeue time (qdf_log_timestamp) 243 */ 244 struct hal_reg_write_q_elem { 245 struct hal_srng *srng; 246 void __iomem *addr; 247 uint32_t enqueue_val; 248 uint32_t dequeue_val; 249 uint8_t valid; 250 qdf_time_t enqueue_time; 251 qdf_time_t work_scheduled_time; 252 qdf_time_t dequeue_time; 253 }; 254 255 /** 256 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 257 * @enqueues: writes enqueued to delayed work 258 * @dequeues: writes dequeued from delayed work (not written yet) 259 * @coalesces: writes not enqueued since srng is already queued up 260 * @direct: writes not enqueued and written to register directly 261 */ 262 struct hal_reg_write_srng_stats { 263 uint32_t enqueues; 264 uint32_t dequeues; 265 uint32_t coalesces; 266 uint32_t direct; 267 }; 268 269 /** 270 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 271 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 272 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 273 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 274 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 275 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 276 */ 277 enum hal_reg_sched_delay { 278 REG_WRITE_SCHED_DELAY_SUB_100us, 279 REG_WRITE_SCHED_DELAY_SUB_1000us, 280 REG_WRITE_SCHED_DELAY_SUB_5000us, 281 REG_WRITE_SCHED_DELAY_GT_5000us, 282 REG_WRITE_SCHED_DELAY_HIST_MAX, 283 }; 284 285 /** 286 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 287 * @enqueues: writes enqueued to delayed work 288 * @dequeues: writes dequeued from delayed work (not written yet) 289 * @coalesces: writes not enqueued since srng is already queued up 290 * @direct: writes not enqueud and writted to register directly 291 * @prevent_l1_fails: prevent l1 API failed 292 * @q_depth: current queue depth in delayed register write queue 293 * @max_q_depth: maximum queue for delayed register write queue 294 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 295 */ 296 struct hal_reg_write_soc_stats { 297 qdf_atomic_t enqueues; 298 uint32_t dequeues; 299 qdf_atomic_t coalesces; 300 qdf_atomic_t direct; 301 uint32_t prevent_l1_fails; 302 qdf_atomic_t q_depth; 303 uint32_t max_q_depth; 304 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 305 }; 306 #endif 307 308 /* Common SRNG ring structure for source and destination rings */ 309 struct hal_srng { 310 /* Unique SRNG ring ID */ 311 uint8_t ring_id; 312 313 /* Ring initialization done */ 314 uint8_t initialized; 315 316 /* Interrupt/MSI value assigned to this ring */ 317 int irq; 318 319 /* Physical base address of the ring */ 320 qdf_dma_addr_t ring_base_paddr; 321 322 /* Virtual base address of the ring */ 323 uint32_t *ring_base_vaddr; 324 325 /* Number of entries in ring */ 326 uint32_t num_entries; 327 328 /* Ring size */ 329 uint32_t ring_size; 330 331 /* Ring size mask */ 332 uint32_t ring_size_mask; 333 334 /* Size of ring entry */ 335 uint32_t entry_size; 336 337 /* Interrupt timer threshold – in micro seconds */ 338 uint32_t intr_timer_thres_us; 339 340 /* Interrupt batch counter threshold – in number of ring entries */ 341 uint32_t intr_batch_cntr_thres_entries; 342 343 /* Applicable only for CE dest ring */ 344 uint32_t prefetch_timer; 345 346 /* MSI Address */ 347 qdf_dma_addr_t msi_addr; 348 349 /* MSI data */ 350 uint32_t msi_data; 351 352 /* Misc flags */ 353 uint32_t flags; 354 355 /* Lock for serializing ring index updates */ 356 hal_srng_lock_t lock; 357 358 /* Start offset of SRNG register groups for this ring 359 * TBD: See if this is required - register address can be derived 360 * from ring ID 361 */ 362 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 363 364 /* Source or Destination ring */ 365 enum hal_srng_dir ring_dir; 366 367 union { 368 struct { 369 /* SW tail pointer */ 370 uint32_t tp; 371 372 /* Shadow head pointer location to be updated by HW */ 373 uint32_t *hp_addr; 374 375 /* Cached head pointer */ 376 uint32_t cached_hp; 377 378 /* Tail pointer location to be updated by SW – This 379 * will be a register address and need not be 380 * accessed through SW structure */ 381 uint32_t *tp_addr; 382 383 /* Current SW loop cnt */ 384 uint32_t loop_cnt; 385 386 /* max transfer size */ 387 uint16_t max_buffer_length; 388 } dst_ring; 389 390 struct { 391 /* SW head pointer */ 392 uint32_t hp; 393 394 /* SW reap head pointer */ 395 uint32_t reap_hp; 396 397 /* Shadow tail pointer location to be updated by HW */ 398 uint32_t *tp_addr; 399 400 /* Cached tail pointer */ 401 uint32_t cached_tp; 402 403 /* Head pointer location to be updated by SW – This 404 * will be a register address and need not be accessed 405 * through SW structure */ 406 uint32_t *hp_addr; 407 408 /* Low threshold – in number of ring entries */ 409 uint32_t low_threshold; 410 } src_ring; 411 } u; 412 413 struct hal_soc *hal_soc; 414 415 /* Number of times hp/tp updated in runtime resume */ 416 uint32_t flush_count; 417 /* hal srng event flag*/ 418 unsigned long srng_event; 419 /* last flushed time stamp */ 420 uint64_t last_flush_ts; 421 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 422 /* flag to indicate whether srng is already queued for delayed write */ 423 uint8_t reg_write_in_progress; 424 425 /* srng specific delayed write stats */ 426 struct hal_reg_write_srng_stats wstats; 427 #endif 428 }; 429 430 /* HW SRNG configuration table */ 431 struct hal_hw_srng_config { 432 int start_ring_id; 433 uint16_t max_rings; 434 uint16_t entry_size; 435 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 436 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 437 uint8_t lmac_ring; 438 enum hal_srng_dir ring_dir; 439 uint32_t max_size; 440 }; 441 442 #define MAX_SHADOW_REGISTERS 36 443 #define MAX_GENERIC_SHADOW_REG 5 444 445 /** 446 * struct shadow_reg_config - Hal soc structure that contains 447 * the list of generic shadow registers 448 * @target_register: target reg offset 449 * @shadow_config_index: shadow config index in shadow config 450 * list sent to FW 451 * @va: virtual addr of shadow reg 452 * 453 * This structure holds the generic registers that are mapped to 454 * the shadow region and holds the mapping of the target 455 * register offset to shadow config index provided to FW during 456 * init 457 */ 458 struct shadow_reg_config { 459 uint32_t target_register; 460 int shadow_config_index; 461 uint64_t va; 462 }; 463 464 /* REO parameters to be passed to hal_reo_setup */ 465 struct hal_reo_params { 466 /** rx hash steering enabled or disabled */ 467 bool rx_hash_enabled; 468 /** reo remap 1 register */ 469 uint32_t remap1; 470 /** reo remap 2 register */ 471 uint32_t remap2; 472 /** fragment destination ring */ 473 uint8_t frag_dst_ring; 474 /* Destination for alternate */ 475 uint8_t alt_dst_ind_0; 476 /** padding */ 477 uint8_t padding[2]; 478 }; 479 480 struct hal_hw_txrx_ops { 481 482 /* init and setup */ 483 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 484 struct hal_srng *srng); 485 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 486 struct hal_srng *srng); 487 void (*hal_get_hw_hptp)(struct hal_soc *hal, 488 hal_ring_handle_t hal_ring_hdl, 489 uint32_t *headp, uint32_t *tailp, 490 uint8_t ring_type); 491 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams); 492 void (*hal_setup_link_idle_list)( 493 struct hal_soc *hal_soc, 494 qdf_dma_addr_t scatter_bufs_base_paddr[], 495 void *scatter_bufs_base_vaddr[], 496 uint32_t num_scatter_bufs, 497 uint32_t scatter_buf_size, 498 uint32_t last_buf_end_offset, 499 uint32_t num_entries); 500 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 501 qdf_iomem_t addr); 502 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 503 504 /* tx */ 505 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 506 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 507 uint8_t id); 508 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 509 uint8_t id, 510 uint8_t dscp); 511 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 512 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 513 uint8_t pool_id, uint32_t desc_id, uint8_t type); 514 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 515 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 516 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 517 void (*hal_tx_comp_get_status)(void *desc, void *ts, 518 struct hal_soc *hal); 519 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 520 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 521 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 522 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 523 hal_ring_handle_t hal_ring_hdl); 524 525 /* rx */ 526 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 527 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 528 struct mon_rx_status *rs); 529 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 530 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 531 void *ppdu_info_handle); 532 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 533 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 534 uint8_t dbg_level); 535 uint32_t (*hal_get_link_desc_size)(void); 536 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 537 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 538 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 539 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 540 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 541 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 542 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 543 void *ppdu_info, 544 hal_soc_handle_t hal_soc_hdl, 545 qdf_nbuf_t nbuf); 546 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 547 void *wbm_er_info); 548 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 549 uint8_t dbg_level); 550 551 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 552 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 553 uint8_t id); 554 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 555 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 556 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 557 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 558 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 559 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 560 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 561 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 562 void (*hal_rx_print_pn)(uint8_t *buf); 563 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 564 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 565 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 566 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 567 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 568 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 569 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 570 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 571 QDF_STATUS 572 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 573 QDF_STATUS 574 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 575 QDF_STATUS 576 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 577 QDF_STATUS 578 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 579 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 580 bool (*hal_rx_is_unicast)(uint8_t *buf); 581 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 582 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 583 void *rxdma_dst_ring_desc); 584 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 585 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 586 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 587 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 588 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 589 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 590 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 591 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 592 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 593 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 594 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 595 void (*hal_reo_config)(struct hal_soc *soc, 596 uint32_t reg_val, 597 struct hal_reo_params *reo_params); 598 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 599 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 600 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 601 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 602 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 603 void 604 (*hal_rx_msdu_get_flow_params)( 605 uint8_t *buf, 606 bool *flow_invalid, 607 bool *flow_timeout, 608 uint32_t *flow_index); 609 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 610 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 611 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 612 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 613 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 614 void *msdu_pkt_metadata); 615 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 616 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 617 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 618 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 619 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 620 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 621 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 622 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 623 hal_rx_mon_desc_info_t mon_desc_info); 624 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 625 uint32_t (*hal_rx_msdu_end_offset_get)(void); 626 uint32_t (*hal_rx_attn_offset_get)(void); 627 uint32_t (*hal_rx_msdu_start_offset_get)(void); 628 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 629 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 630 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 631 uint32_t table_offset, 632 uint8_t *rx_flow); 633 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 634 uint32_t num_rings, 635 uint32_t *remap1, 636 uint32_t *remap2); 637 uint32_t (*hal_rx_flow_setup_cmem_fse)( 638 struct hal_soc *soc, uint32_t cmem_ba, 639 uint32_t table_offset, uint8_t *rx_flow); 640 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc, 641 uint32_t fse_offset); 642 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc, 643 uint32_t fse_offset, 644 uint32_t *fse, qdf_size_t len); 645 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, 646 uint32_t *reo_destination_indication); 647 }; 648 649 /** 650 * struct hal_soc_stats - Hal layer stats 651 * @reg_write_fail: number of failed register writes 652 * @wstats: delayed register write stats 653 * @shadow_reg_write_fail: shadow reg write failure stats 654 * @shadow_reg_write_succ: shadow reg write success stats 655 * 656 * This structure holds all the statistics at HAL layer. 657 */ 658 struct hal_soc_stats { 659 uint32_t reg_write_fail; 660 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 661 struct hal_reg_write_soc_stats wstats; 662 #endif 663 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 664 uint32_t shadow_reg_write_fail; 665 uint32_t shadow_reg_write_succ; 666 #endif 667 }; 668 669 #ifdef ENABLE_HAL_REG_WR_HISTORY 670 /* The history size should always be a power of 2 */ 671 #define HAL_REG_WRITE_HIST_SIZE 8 672 673 /** 674 * struct hal_reg_write_fail_entry - Record of 675 * register write which failed. 676 * @timestamp: timestamp of reg write failure 677 * @reg_offset: offset of register where the write failed 678 * @write_val: the value which was to be written 679 * @read_val: the value read back from the register after write 680 */ 681 struct hal_reg_write_fail_entry { 682 uint64_t timestamp; 683 uint32_t reg_offset; 684 uint32_t write_val; 685 uint32_t read_val; 686 }; 687 688 /** 689 * struct hal_reg_write_fail_history - Hal layer history 690 * of all the register write failures. 691 * @index: index to add the new record 692 * @record: array of all the records in history 693 * 694 * This structure holds the history of register write 695 * failures at HAL layer. 696 */ 697 struct hal_reg_write_fail_history { 698 qdf_atomic_t index; 699 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 700 }; 701 #endif 702 703 /** 704 * struct hal_soc - HAL context to be used to access SRNG APIs 705 * (currently used by data path and 706 * transport (CE) modules) 707 * @list_shadow_reg_config: array of generic regs mapped to 708 * shadow regs 709 * @num_generic_shadow_regs_configured: number of generic regs 710 * mapped to shadow regs 711 */ 712 struct hal_soc { 713 /* HIF handle to access HW registers */ 714 struct hif_opaque_softc *hif_handle; 715 716 /* QDF device handle */ 717 qdf_device_t qdf_dev; 718 719 /* Device base address */ 720 void *dev_base_addr; 721 /* Device base address for ce - qca5018 target */ 722 void *dev_base_addr_ce; 723 724 /* HAL internal state for all SRNG rings. 725 * TODO: See if this is required 726 */ 727 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 728 729 /* Remote pointer memory for HW/FW updates */ 730 uint32_t *shadow_rdptr_mem_vaddr; 731 qdf_dma_addr_t shadow_rdptr_mem_paddr; 732 733 /* Shared memory for ring pointer updates from host to FW */ 734 uint32_t *shadow_wrptr_mem_vaddr; 735 qdf_dma_addr_t shadow_wrptr_mem_paddr; 736 737 /* REO blocking resource index */ 738 uint8_t reo_res_bitmap; 739 uint8_t index; 740 uint32_t target_type; 741 742 /* shadow register configuration */ 743 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 744 int num_shadow_registers_configured; 745 bool use_register_windowing; 746 uint32_t register_window; 747 qdf_spinlock_t register_access_lock; 748 749 /* Static window map configuration for multiple window write*/ 750 bool static_window_map; 751 752 /* srng table */ 753 struct hal_hw_srng_config *hw_srng_table; 754 int32_t *hal_hw_reg_offset; 755 struct hal_hw_txrx_ops *ops; 756 757 /* Indicate srngs initialization */ 758 bool init_phase; 759 /* Hal level stats */ 760 struct hal_soc_stats stats; 761 #ifdef ENABLE_HAL_REG_WR_HISTORY 762 struct hal_reg_write_fail_history *reg_wr_fail_hist; 763 #endif 764 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 765 /* queue(array) to hold register writes */ 766 struct hal_reg_write_q_elem *reg_write_queue; 767 /* delayed work to be queued into workqueue */ 768 qdf_work_t reg_write_work; 769 /* workqueue for delayed register writes */ 770 qdf_workqueue_t *reg_write_wq; 771 /* write index used by caller to enqueue delayed work */ 772 qdf_atomic_t write_idx; 773 /* read index used by worker thread to dequeue/write registers */ 774 uint32_t read_idx; 775 #endif 776 qdf_atomic_t active_work_cnt; 777 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 778 struct shadow_reg_config 779 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; 780 int num_generic_shadow_regs_configured; 781 #endif 782 }; 783 784 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 785 /** 786 * hal_delayed_reg_write() - delayed regiter write 787 * @hal_soc: HAL soc handle 788 * @srng: hal srng 789 * @addr: iomem address 790 * @value: value to be written 791 * 792 * Return: none 793 */ 794 void hal_delayed_reg_write(struct hal_soc *hal_soc, 795 struct hal_srng *srng, 796 void __iomem *addr, 797 uint32_t value); 798 #endif 799 800 void hal_qca6750_attach(struct hal_soc *hal_soc); 801 void hal_qca6490_attach(struct hal_soc *hal_soc); 802 void hal_qca6390_attach(struct hal_soc *hal_soc); 803 void hal_qca6290_attach(struct hal_soc *hal_soc); 804 void hal_qca8074_attach(struct hal_soc *hal_soc); 805 806 /* 807 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 808 * dp_hal_soc handle type 809 * @hal_soc - hal_soc type 810 * 811 * Return: hal_soc_handle_t type 812 */ 813 static inline 814 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 815 { 816 return (hal_soc_handle_t)hal_soc; 817 } 818 819 /* 820 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 821 * dp_hal_ring handle type 822 * @hal_srng - hal_srng type 823 * 824 * Return: hal_ring_handle_t type 825 */ 826 static inline 827 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 828 { 829 return (hal_ring_handle_t)hal_srng; 830 } 831 832 /* 833 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 834 * @hal_ring - hal_ring_handle_t type 835 * 836 * Return: hal_srng pointer type 837 */ 838 static inline 839 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 840 { 841 return (struct hal_srng *)hal_ring; 842 } 843 #endif /* _HAL_INTERNAL_H_ */ 844