1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_INTERNAL_H_ 21 #define _HAL_INTERNAL_H_ 22 23 #include "qdf_types.h" 24 #include "qdf_atomic.h" 25 #include "qdf_lock.h" 26 #include "qdf_mem.h" 27 #include "qdf_nbuf.h" 28 #include "pld_common.h" 29 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 30 #include "qdf_defer.h" 31 #include "qdf_timer.h" 32 #endif 33 34 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 35 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 36 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 37 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params) 38 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 39 40 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 41 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 43 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 44 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 45 46 #ifdef ENABLE_VERBOSE_DEBUG 47 extern bool is_hal_verbose_debug_enabled; 48 #define hal_verbose_debug(params...) \ 49 if (unlikely(is_hal_verbose_debug_enabled)) \ 50 do {\ 51 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 52 } while (0) 53 #define hal_verbose_hex_dump(params...) \ 54 if (unlikely(is_hal_verbose_debug_enabled)) \ 55 do {\ 56 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 57 QDF_TRACE_LEVEL_DEBUG, \ 58 params); \ 59 } while (0) 60 #else 61 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 62 #define hal_verbose_hex_dump(params...) \ 63 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 64 params) 65 #endif 66 67 /* 68 * Given the offset of a field in bytes, returns uint8_t * 69 */ 70 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 71 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 72 73 /* 74 * Given the offset of a field in bytes, returns uint32_t * 75 */ 76 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 77 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 78 79 /* 80 * Given the offset of a field in bytes, returns uint64_t * 81 */ 82 #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \ 83 (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3)) 84 85 #define _HAL_MS(_word, _mask, _shift) \ 86 (((_word) & (_mask)) >> (_shift)) 87 88 /* 89 * Get number of QWORDS possible for num. 90 * Its the caller's duty to make sure num is a multiple of QWORD (8) 91 */ 92 #define HAL_GET_NUM_QWORDS(num) ((num) >> 3) 93 94 /* 95 * Get number of DWORDS possible for num. 96 * Its the caller's duty to make sure num is a multiple of DWORD (8) 97 */ 98 #define HAL_GET_NUM_DWORDS(num) ((num) >> 2) 99 100 struct hal_hw_cc_config { 101 uint32_t lut_base_addr_31_0; 102 uint32_t cc_global_en:1, 103 page_4k_align:1, 104 cookie_offset_msb:5, 105 cookie_page_msb:5, 106 lut_base_addr_39_32:8, 107 wbm2sw6_cc_en:1, 108 wbm2sw5_cc_en:1, 109 wbm2sw4_cc_en:1, 110 wbm2sw3_cc_en:1, 111 wbm2sw2_cc_en:1, 112 wbm2sw1_cc_en:1, 113 wbm2sw0_cc_en:1, 114 wbm2fw_cc_en:1, 115 error_path_cookie_conv_en:1, 116 release_path_cookie_conv_en:1, 117 reserved:2; 118 }; 119 120 /* 121 * dp_hal_soc - opaque handle for DP HAL soc 122 */ 123 struct hal_soc_handle; 124 typedef struct hal_soc_handle *hal_soc_handle_t; 125 126 /** 127 * hal_ring_desc - opaque handle for DP ring descriptor 128 */ 129 struct hal_ring_desc; 130 typedef struct hal_ring_desc *hal_ring_desc_t; 131 132 /** 133 * hal_link_desc - opaque handle for DP link descriptor 134 */ 135 struct hal_link_desc; 136 typedef struct hal_link_desc *hal_link_desc_t; 137 138 /** 139 * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor 140 */ 141 struct hal_rxdma_desc; 142 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 143 144 /** 145 * hal_buff_addrinfo - opaque handle for DP buffer address info 146 */ 147 struct hal_buff_addrinfo; 148 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 149 150 /** 151 * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info 152 */ 153 struct hal_rx_mon_desc_info; 154 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 155 156 struct hal_buf_info; 157 typedef struct hal_buf_info *hal_buf_info_t; 158 159 struct rx_msdu_desc_info; 160 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t; 161 162 /** 163 * Opaque handler for PPE VP config. 164 */ 165 union hal_tx_ppe_vp_config; 166 union hal_tx_cmn_config_ppe; 167 union hal_tx_bank_config; 168 169 /* TBD: This should be movded to shared HW header file */ 170 enum hal_srng_ring_id { 171 /* UMAC rings */ 172 HAL_SRNG_REO2SW0 = 0, 173 HAL_SRNG_REO2SW1 = 1, 174 HAL_SRNG_REO2SW2 = 2, 175 HAL_SRNG_REO2SW3 = 3, 176 HAL_SRNG_REO2SW4 = 4, 177 HAL_SRNG_REO2SW5 = 5, 178 HAL_SRNG_REO2SW6 = 6, 179 HAL_SRNG_REO2SW7 = 7, 180 HAL_SRNG_REO2SW8 = 8, 181 HAL_SRNG_REO2TCL = 9, 182 HAL_SRNG_REO2PPE = 10, 183 /* 11-15 unused */ 184 HAL_SRNG_SW2REO = 16, 185 HAL_SRNG_SW2REO1 = 17, 186 HAL_SRNG_SW2REO2 = 18, 187 HAL_SRNG_SW2REO3 = 19, 188 HAL_SRNG_REO_CMD = 20, 189 HAL_SRNG_REO_STATUS = 21, 190 /* 22-23 unused */ 191 HAL_SRNG_SW2TCL1 = 24, 192 HAL_SRNG_SW2TCL2 = 25, 193 HAL_SRNG_SW2TCL3 = 26, 194 HAL_SRNG_SW2TCL4 = 27, 195 HAL_SRNG_SW2TCL5 = 28, 196 HAL_SRNG_SW2TCL6 = 29, 197 HAL_SRNG_PPE2TCL1 = 30, 198 /* 31-39 unused */ 199 HAL_SRNG_SW2TCL_CMD = 40, 200 HAL_SRNG_TCL_STATUS = 41, 201 HAL_SRNG_SW2TCL_CREDIT = 42, 202 /* 43-63 unused */ 203 HAL_SRNG_CE_0_SRC = 64, 204 HAL_SRNG_CE_1_SRC = 65, 205 HAL_SRNG_CE_2_SRC = 66, 206 HAL_SRNG_CE_3_SRC = 67, 207 HAL_SRNG_CE_4_SRC = 68, 208 HAL_SRNG_CE_5_SRC = 69, 209 HAL_SRNG_CE_6_SRC = 70, 210 HAL_SRNG_CE_7_SRC = 71, 211 HAL_SRNG_CE_8_SRC = 72, 212 HAL_SRNG_CE_9_SRC = 73, 213 HAL_SRNG_CE_10_SRC = 74, 214 HAL_SRNG_CE_11_SRC = 75, 215 HAL_SRNG_CE_12_SRC = 76, 216 HAL_SRNG_CE_13_SRC = 77, 217 HAL_SRNG_CE_14_SRC = 78, 218 HAL_SRNG_CE_15_SRC = 79, 219 /* 80 */ 220 HAL_SRNG_CE_0_DST = 81, 221 HAL_SRNG_CE_1_DST = 82, 222 HAL_SRNG_CE_2_DST = 83, 223 HAL_SRNG_CE_3_DST = 84, 224 HAL_SRNG_CE_4_DST = 85, 225 HAL_SRNG_CE_5_DST = 86, 226 HAL_SRNG_CE_6_DST = 87, 227 HAL_SRNG_CE_7_DST = 89, 228 HAL_SRNG_CE_8_DST = 90, 229 HAL_SRNG_CE_9_DST = 91, 230 HAL_SRNG_CE_10_DST = 92, 231 HAL_SRNG_CE_11_DST = 93, 232 HAL_SRNG_CE_12_DST = 94, 233 HAL_SRNG_CE_13_DST = 95, 234 HAL_SRNG_CE_14_DST = 96, 235 HAL_SRNG_CE_15_DST = 97, 236 /* 98-99 unused */ 237 HAL_SRNG_CE_0_DST_STATUS = 100, 238 HAL_SRNG_CE_1_DST_STATUS = 101, 239 HAL_SRNG_CE_2_DST_STATUS = 102, 240 HAL_SRNG_CE_3_DST_STATUS = 103, 241 HAL_SRNG_CE_4_DST_STATUS = 104, 242 HAL_SRNG_CE_5_DST_STATUS = 105, 243 HAL_SRNG_CE_6_DST_STATUS = 106, 244 HAL_SRNG_CE_7_DST_STATUS = 107, 245 HAL_SRNG_CE_8_DST_STATUS = 108, 246 HAL_SRNG_CE_9_DST_STATUS = 109, 247 HAL_SRNG_CE_10_DST_STATUS = 110, 248 HAL_SRNG_CE_11_DST_STATUS = 111, 249 HAL_SRNG_CE_12_DST_STATUS = 112, 250 HAL_SRNG_CE_13_DST_STATUS = 113, 251 HAL_SRNG_CE_14_DST_STATUS = 114, 252 HAL_SRNG_CE_15_DST_STATUS = 115, 253 /* 116-119 unused */ 254 HAL_SRNG_WBM_IDLE_LINK = 120, 255 HAL_SRNG_WBM_SW_RELEASE = 121, 256 HAL_SRNG_WBM_SW1_RELEASE = 122, 257 HAL_SRNG_WBM_PPE_RELEASE = 123, 258 /* 124-127 unused */ 259 HAL_SRNG_WBM2SW0_RELEASE = 128, 260 HAL_SRNG_WBM2SW1_RELEASE = 129, 261 HAL_SRNG_WBM2SW2_RELEASE = 130, 262 HAL_SRNG_WBM2SW3_RELEASE = 131, 263 HAL_SRNG_WBM2SW4_RELEASE = 132, 264 HAL_SRNG_WBM2SW5_RELEASE = 133, 265 HAL_SRNG_WBM2SW6_RELEASE = 134, 266 HAL_SRNG_WBM_ERROR_RELEASE = 135, 267 /* 136-158 unused */ 268 HAL_SRNG_UMAC_ID_END = 159, 269 /* Common DMAC rings shared by all LMACs */ 270 HAL_SRNG_SW2RXDMA_BUF0 = 160, 271 HAL_SRNG_SW2RXDMA_BUF1 = 161, 272 HAL_SRNG_SW2RXDMA_BUF2 = 162, 273 /* 163-167 unused */ 274 HAL_SRNG_SW2RXMON_BUF0 = 168, 275 /* 169-175 unused */ 276 /* 177-183 unused */ 277 HAL_SRNG_DMAC_CMN_ID_END = 183, 278 /* LMAC rings - The following set will be replicated for each LMAC */ 279 HAL_SRNG_LMAC1_ID_START = 184, 280 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 281 #ifdef IPA_OFFLOAD 282 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1, 283 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2, 284 #ifdef IPA_WDI3_VLAN_SUPPORT 285 HAL_SRNG_WMAC1_SW2RXDMA0_BUF3, 286 #endif 287 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 288 #else 289 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 290 #endif 291 HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 292 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF, 293 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 294 HAL_SRNG_WMAC1_RXDMA2SW0, 295 HAL_SRNG_WMAC1_RXDMA2SW1, 296 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1, 297 HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 298 #ifdef WLAN_FEATURE_CIF_CFR 299 HAL_SRNG_WIFI_POS_SRC_DMA_RING, 300 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 301 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 302 #else 303 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 304 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 305 #endif 306 HAL_SRNG_WMAC1_TXMON2SW0, 307 HAL_SRNG_SW2TXMON_BUF0, 308 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2), 309 }; 310 311 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 312 #define HAL_MAX_LMACS 3 313 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 314 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 315 316 #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS) 317 318 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ 319 enum hal_ring_type { 320 REO_DST = 0, 321 REO_EXCEPTION = 1, 322 REO_REINJECT = 2, 323 REO_CMD = 3, 324 REO_STATUS = 4, 325 TCL_DATA = 5, 326 TCL_CMD_CREDIT = 6, 327 TCL_STATUS = 7, 328 CE_SRC = 8, 329 CE_DST = 9, 330 CE_DST_STATUS = 10, 331 WBM_IDLE_LINK = 11, 332 SW2WBM_RELEASE = 12, 333 WBM2SW_RELEASE = 13, 334 RXDMA_BUF = 14, 335 RXDMA_DST = 15, 336 RXDMA_MONITOR_BUF = 16, 337 RXDMA_MONITOR_STATUS = 17, 338 RXDMA_MONITOR_DST = 18, 339 RXDMA_MONITOR_DESC = 19, 340 DIR_BUF_RX_DMA_SRC = 20, 341 #ifdef WLAN_FEATURE_CIF_CFR 342 WIFI_POS_SRC, 343 #endif 344 REO2PPE, 345 PPE2TCL, 346 PPE_RELEASE, 347 TX_MONITOR_BUF, 348 TX_MONITOR_DST, 349 SW2RXDMA_NEW, 350 MAX_RING_TYPES 351 }; 352 353 enum SRNG_REGISTERS { 354 DST_HP = 0, 355 DST_TP, 356 DST_ID, 357 DST_MISC, 358 DST_HP_ADDR_LSB, 359 DST_HP_ADDR_MSB, 360 DST_MSI1_BASE_LSB, 361 DST_MSI1_BASE_MSB, 362 DST_MSI1_DATA, 363 #ifdef CONFIG_BERYLLIUM 364 DST_MSI2_BASE_LSB, 365 DST_MSI2_BASE_MSB, 366 DST_MSI2_DATA, 367 #endif 368 DST_BASE_LSB, 369 DST_BASE_MSB, 370 DST_PRODUCER_INT_SETUP, 371 #ifdef CONFIG_BERYLLIUM 372 DST_PRODUCER_INT2_SETUP, 373 #endif 374 375 SRC_HP, 376 SRC_TP, 377 SRC_ID, 378 SRC_MISC, 379 SRC_TP_ADDR_LSB, 380 SRC_TP_ADDR_MSB, 381 SRC_MSI1_BASE_LSB, 382 SRC_MSI1_BASE_MSB, 383 SRC_MSI1_DATA, 384 SRC_BASE_LSB, 385 SRC_BASE_MSB, 386 SRC_CONSUMER_INT_SETUP_IX0, 387 SRC_CONSUMER_INT_SETUP_IX1, 388 #ifdef DP_UMAC_HW_RESET_SUPPORT 389 SRC_CONSUMER_PREFETCH_TIMER, 390 #endif 391 SRNG_REGISTER_MAX, 392 }; 393 394 enum hal_srng_dir { 395 HAL_SRNG_SRC_RING, 396 HAL_SRNG_DST_RING 397 }; 398 399 /** 400 * enum hal_reo_remap_reg - REO remap registers 401 * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0 402 * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1 403 * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2 404 * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3 405 */ 406 enum hal_reo_remap_reg { 407 HAL_REO_REMAP_REG_IX0, 408 HAL_REO_REMAP_REG_IX1, 409 HAL_REO_REMAP_REG_IX2, 410 HAL_REO_REMAP_REG_IX3 411 }; 412 413 /* Lock wrappers for SRNG */ 414 #define hal_srng_lock_t qdf_spinlock_t 415 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 416 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 417 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock) 418 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 419 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 420 421 struct hal_soc; 422 423 /** 424 * dp_hal_ring - opaque handle for DP HAL SRNG 425 */ 426 struct hal_ring_handle; 427 typedef struct hal_ring_handle *hal_ring_handle_t; 428 429 #define MAX_SRNG_REG_GROUPS 2 430 431 /* Hal Srng bit mask 432 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 433 */ 434 #define HAL_SRNG_FLUSH_EVENT BIT(0) 435 436 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 437 438 /** 439 * struct hal_reg_write_q_elem - delayed register write queue element 440 * @srng: hal_srng queued for a delayed write 441 * @addr: iomem address of the register 442 * @enqueue_val: register value at the time of delayed write enqueue 443 * @dequeue_val: register value at the time of delayed write dequeue 444 * @valid: whether this entry is valid or not 445 * @enqueue_time: enqueue time (qdf_log_timestamp) 446 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 447 * @dequeue_time: dequeue time (qdf_log_timestamp) 448 * @cpu_id: record cpuid when schedule work 449 */ 450 struct hal_reg_write_q_elem { 451 struct hal_srng *srng; 452 void __iomem *addr; 453 uint32_t enqueue_val; 454 uint32_t dequeue_val; 455 uint8_t valid; 456 qdf_time_t enqueue_time; 457 qdf_time_t work_scheduled_time; 458 qdf_time_t dequeue_time; 459 int cpu_id; 460 }; 461 462 /** 463 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 464 * @enqueues: writes enqueued to delayed work 465 * @dequeues: writes dequeued from delayed work (not written yet) 466 * @coalesces: writes not enqueued since srng is already queued up 467 * @direct: writes not enqueued and written to register directly 468 * @dequeue_delay: dequeue operation be delayed 469 */ 470 struct hal_reg_write_srng_stats { 471 uint32_t enqueues; 472 uint32_t dequeues; 473 uint32_t coalesces; 474 uint32_t direct; 475 uint32_t dequeue_delay; 476 }; 477 478 /** 479 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 480 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 481 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 482 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 483 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 484 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 485 */ 486 enum hal_reg_sched_delay { 487 REG_WRITE_SCHED_DELAY_SUB_100us, 488 REG_WRITE_SCHED_DELAY_SUB_1000us, 489 REG_WRITE_SCHED_DELAY_SUB_5000us, 490 REG_WRITE_SCHED_DELAY_GT_5000us, 491 REG_WRITE_SCHED_DELAY_HIST_MAX, 492 }; 493 494 /** 495 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 496 * @enqueues: writes enqueued to delayed work 497 * @dequeues: writes dequeued from delayed work (not written yet) 498 * @coalesces: writes not enqueued since srng is already queued up 499 * @direct: writes not enqueud and writted to register directly 500 * @prevent_l1_fails: prevent l1 API failed 501 * @q_depth: current queue depth in delayed register write queue 502 * @max_q_depth: maximum queue for delayed register write queue 503 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 504 * @dequeue_delay: dequeue operation be delayed 505 */ 506 struct hal_reg_write_soc_stats { 507 qdf_atomic_t enqueues; 508 uint32_t dequeues; 509 qdf_atomic_t coalesces; 510 qdf_atomic_t direct; 511 uint32_t prevent_l1_fails; 512 qdf_atomic_t q_depth; 513 uint32_t max_q_depth; 514 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 515 uint32_t dequeue_delay; 516 }; 517 #endif 518 519 struct hal_offload_info { 520 uint8_t lro_eligible; 521 uint8_t tcp_proto; 522 uint8_t tcp_pure_ack; 523 uint8_t ipv6_proto; 524 uint8_t tcp_offset; 525 uint16_t tcp_csum; 526 uint16_t tcp_win; 527 uint32_t tcp_seq_num; 528 uint32_t tcp_ack_num; 529 uint32_t flow_id; 530 }; 531 532 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 533 /** 534 * enum hal_srng_high_wm_bin - BIN for SRNG high watermark 535 * @HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT: <50% SRNG entries used 536 * @HAL_SRNG_HIGH_WM_BIN_50_to_60: 50-60% SRNG entries used 537 * @HAL_SRNG_HIGH_WM_BIN_60_to_70: 60-70% SRNG entries used 538 * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used 539 * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used 540 * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used 541 */ 542 enum hal_srng_high_wm_bin { 543 HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT, 544 HAL_SRNG_HIGH_WM_BIN_50_to_60, 545 HAL_SRNG_HIGH_WM_BIN_60_to_70, 546 HAL_SRNG_HIGH_WM_BIN_70_to_80, 547 HAL_SRNG_HIGH_WM_BIN_80_to_90, 548 HAL_SRNG_HIGH_WM_BIN_90_to_100, 549 HAL_SRNG_HIGH_WM_BIN_MAX, 550 }; 551 552 /** 553 * struct hal_srng_high_wm_info - SRNG usage high watermark info 554 * @val: highest number of entries used in SRNG 555 * @timestamp: Timestamp when the max num entries were in used for a SRNG 556 * @bin_thresh: threshold for each bins 557 * @bins: Bins for srng usage 558 */ 559 struct hal_srng_high_wm_info { 560 uint32_t val; 561 uint64_t timestamp; 562 uint32_t bin_thresh[HAL_SRNG_HIGH_WM_BIN_MAX]; 563 uint32_t bins[HAL_SRNG_HIGH_WM_BIN_MAX]; 564 }; 565 #endif 566 567 /* Common SRNG ring structure for source and destination rings */ 568 struct hal_srng { 569 /* Unique SRNG ring ID */ 570 uint8_t ring_id; 571 572 /* Ring initialization done */ 573 uint8_t initialized; 574 575 /* Interrupt/MSI value assigned to this ring */ 576 int irq; 577 578 /* Physical base address of the ring */ 579 qdf_dma_addr_t ring_base_paddr; 580 581 /* Virtual base address of the ring */ 582 uint32_t *ring_base_vaddr; 583 584 /* virtual address end */ 585 uint32_t *ring_vaddr_end; 586 587 /* Number of entries in ring */ 588 uint32_t num_entries; 589 590 /* Ring size */ 591 uint32_t ring_size; 592 593 /* Ring size mask */ 594 uint32_t ring_size_mask; 595 596 /* Size of ring entry */ 597 uint32_t entry_size; 598 599 /* Interrupt timer threshold – in micro seconds */ 600 uint32_t intr_timer_thres_us; 601 602 /* Interrupt batch counter threshold – in number of ring entries */ 603 uint32_t intr_batch_cntr_thres_entries; 604 605 /* Applicable only for CE dest ring */ 606 uint32_t prefetch_timer; 607 608 /* MSI Address */ 609 qdf_dma_addr_t msi_addr; 610 611 /* MSI data */ 612 uint32_t msi_data; 613 614 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 615 /* MSI2 Address */ 616 qdf_dma_addr_t msi2_addr; 617 618 /* MSI2 data */ 619 uint32_t msi2_data; 620 #endif 621 622 /* Misc flags */ 623 uint32_t flags; 624 625 /* Lock for serializing ring index updates */ 626 hal_srng_lock_t lock; 627 628 /* Start offset of SRNG register groups for this ring 629 * TBD: See if this is required - register address can be derived 630 * from ring ID 631 */ 632 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 633 634 /* Ring type/name */ 635 enum hal_ring_type ring_type; 636 637 /* Source or Destination ring */ 638 enum hal_srng_dir ring_dir; 639 640 union { 641 struct { 642 /* SW tail pointer */ 643 uint32_t tp; 644 645 /* Shadow head pointer location to be updated by HW */ 646 uint32_t *hp_addr; 647 648 /* Cached head pointer */ 649 uint32_t cached_hp; 650 651 /* Tail pointer location to be updated by SW – This 652 * will be a register address and need not be 653 * accessed through SW structure */ 654 uint32_t *tp_addr; 655 656 /* Current SW loop cnt */ 657 uint32_t loop_cnt; 658 659 /* max transfer size */ 660 uint16_t max_buffer_length; 661 662 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 663 /* near full IRQ supported */ 664 uint16_t nf_irq_support; 665 666 /* High threshold for Near full IRQ */ 667 uint16_t high_thresh; 668 #endif 669 } dst_ring; 670 671 struct { 672 /* SW head pointer */ 673 uint32_t hp; 674 675 /* SW reap head pointer */ 676 uint32_t reap_hp; 677 678 /* Shadow tail pointer location to be updated by HW */ 679 uint32_t *tp_addr; 680 681 /* Cached tail pointer */ 682 uint32_t cached_tp; 683 684 /* Head pointer location to be updated by SW – This 685 * will be a register address and need not be accessed 686 * through SW structure */ 687 uint32_t *hp_addr; 688 689 /* Low threshold – in number of ring entries */ 690 uint32_t low_threshold; 691 } src_ring; 692 } u; 693 694 struct hal_soc *hal_soc; 695 696 /* Number of times hp/tp updated in runtime resume */ 697 uint32_t flush_count; 698 /* hal srng event flag*/ 699 unsigned long srng_event; 700 /* last flushed time stamp */ 701 uint64_t last_flush_ts; 702 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 703 /* last ring desc entry cleared */ 704 uint32_t last_desc_cleared; 705 #endif 706 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 707 /* flag to indicate whether srng is already queued for delayed write */ 708 uint8_t reg_write_in_progress; 709 /* last dequeue elem time stamp */ 710 qdf_time_t last_dequeue_time; 711 712 /* srng specific delayed write stats */ 713 struct hal_reg_write_srng_stats wstats; 714 #endif 715 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 716 struct hal_srng_high_wm_info high_wm; 717 #endif 718 }; 719 720 /* HW SRNG configuration table */ 721 struct hal_hw_srng_config { 722 int start_ring_id; 723 uint16_t max_rings; 724 uint16_t entry_size; 725 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 726 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 727 uint8_t lmac_ring; 728 enum hal_srng_dir ring_dir; 729 uint32_t max_size; 730 bool nf_irq_support; 731 bool dmac_cmn_ring; 732 }; 733 734 #define MAX_SHADOW_REGISTERS 40 735 #define MAX_GENERIC_SHADOW_REG 5 736 737 /** 738 * struct shadow_reg_config - Hal soc structure that contains 739 * the list of generic shadow registers 740 * @target_register: target reg offset 741 * @shadow_config_index: shadow config index in shadow config 742 * list sent to FW 743 * @va: virtual addr of shadow reg 744 * 745 * This structure holds the generic registers that are mapped to 746 * the shadow region and holds the mapping of the target 747 * register offset to shadow config index provided to FW during 748 * init 749 */ 750 struct shadow_reg_config { 751 uint32_t target_register; 752 int shadow_config_index; 753 uint64_t va; 754 }; 755 756 /* REO parameters to be passed to hal_reo_setup */ 757 struct hal_reo_params { 758 /** rx hash steering enabled or disabled */ 759 bool rx_hash_enabled; 760 /** reo remap 0 register */ 761 uint32_t remap0; 762 /** reo remap 1 register */ 763 uint32_t remap1; 764 /** reo remap 2 register */ 765 uint32_t remap2; 766 /** fragment destination ring */ 767 uint8_t frag_dst_ring; 768 /* Destination for alternate */ 769 uint8_t alt_dst_ind_0; 770 /** padding */ 771 uint8_t padding[2]; 772 }; 773 774 /** 775 * enum hal_reo_cmd_type: Enum for REO command type 776 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 777 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 778 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 779 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked 780 * earlier with a ‘REO_FLUSH_CACHE’ command 781 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 782 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 783 */ 784 enum hal_reo_cmd_type { 785 CMD_GET_QUEUE_STATS = 0, 786 CMD_FLUSH_QUEUE = 1, 787 CMD_FLUSH_CACHE = 2, 788 CMD_UNBLOCK_CACHE = 3, 789 CMD_FLUSH_TIMEOUT_LIST = 4, 790 CMD_UPDATE_RX_REO_QUEUE = 5 791 }; 792 793 /** 794 * enum hal_tx_mcast_mlo_reinject_notify 795 * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW 796 * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM 797 */ 798 enum hal_tx_mcast_mlo_reinject_notify { 799 HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0, 800 HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY, 801 }; 802 803 /** 804 * enum hal_tx_vdev_mismatch_notify 805 * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM 806 * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW 807 */ 808 enum hal_tx_vdev_mismatch_notify { 809 HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0, 810 HAL_TX_VDEV_MISMATCH_FW_NOTIFY, 811 }; 812 813 struct hal_rx_pkt_capture_flags { 814 uint8_t encrypt_type; 815 uint8_t fragment_flag; 816 uint8_t fcs_err; 817 uint32_t chan_freq; 818 uint32_t rssi_comb; 819 uint64_t tsft; 820 }; 821 822 struct hal_hw_txrx_ops { 823 /* init and setup */ 824 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 825 struct hal_srng *srng, bool idle_check); 826 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 827 struct hal_srng *srng, bool idle_check); 828 829 void (*hal_srng_hw_disable)(struct hal_soc *hal, 830 struct hal_srng *srng); 831 void (*hal_get_hw_hptp)(struct hal_soc *hal, 832 hal_ring_handle_t hal_ring_hdl, 833 uint32_t *headp, uint32_t *tailp, 834 uint8_t ring_type); 835 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams, 836 int qref_reset); 837 void (*hal_setup_link_idle_list)( 838 struct hal_soc *hal_soc, 839 qdf_dma_addr_t scatter_bufs_base_paddr[], 840 void *scatter_bufs_base_vaddr[], 841 uint32_t num_scatter_bufs, 842 uint32_t scatter_buf_size, 843 uint32_t last_buf_end_offset, 844 uint32_t num_entries); 845 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 846 qdf_iomem_t addr); 847 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 848 uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc); 849 void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid, 850 uint32_t ba_window_size, 851 uint32_t start_seq, void *hw_qdesc_vaddr, 852 qdf_dma_addr_t hw_qdesc_paddr, 853 int pn_type, uint8_t vdev_stats_id); 854 uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg, 855 uint8_t *ix0_map); 856 857 /* tx */ 858 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 859 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 860 uint8_t id); 861 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 862 uint8_t id, 863 uint8_t dscp); 864 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 865 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 866 uint8_t pool_id, uint32_t desc_id, 867 uint8_t type); 868 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 869 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 870 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 871 void (*hal_tx_comp_get_status)(void *desc, void *ts, 872 struct hal_soc *hal); 873 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 874 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 875 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 876 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 877 hal_ring_handle_t hal_ring_hdl); 878 uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc); 879 uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)( 880 hal_soc_handle_t hal_soc_hdl); 881 882 void (*hal_reo_config_reo2ppe_dest_info)(hal_soc_handle_t hal_soc_hdl); 883 884 void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl, 885 union hal_tx_cmn_config_ppe *cmn_cfg); 886 void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl, 887 union hal_tx_ppe_vp_config *vp_cfg, 888 int ppe_vp_idx); 889 void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 890 uint32_t val, 891 uint8_t map_no); 892 void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 893 uint8_t pri, 894 uint8_t tid); 895 void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl); 896 void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl, 897 bool value, uint8_t ppe_vp_idx); 898 void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl, 899 hal_ring_handle_t hal_ring_hdl, 900 uint8_t rbm_id); 901 902 /* rx */ 903 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 904 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 905 struct mon_rx_status *rs); 906 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 907 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 908 void *ppdu_info_handle); 909 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 910 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 911 uint8_t dbg_level); 912 uint32_t (*hal_get_link_desc_size)(void); 913 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 914 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 915 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 916 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 917 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 918 void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b, 919 void *h); 920 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 921 void *ppdu_info, 922 hal_soc_handle_t hal_soc_hdl, 923 qdf_nbuf_t nbuf); 924 925 void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc, 926 struct hal_buf_info *buf_info); 927 928 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 929 void *wbm_er_info); 930 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 931 uint8_t dbg_level); 932 933 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 934 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 935 uint8_t id); 936 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 937 938 /* rx */ 939 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 940 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 941 uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf); 942 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 943 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 944 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 945 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 946 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 947 void (*hal_rx_print_pn)(uint8_t *buf); 948 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 949 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 950 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 951 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 952 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 953 uint32_t (*hal_rx_tlv_peer_meta_data_get)(uint8_t *buf); 954 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 955 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 956 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 957 QDF_STATUS 958 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 959 QDF_STATUS 960 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 961 QDF_STATUS 962 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 963 QDF_STATUS 964 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 965 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 966 bool (*hal_rx_is_unicast)(uint8_t *buf); 967 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 968 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 969 void *rxdma_dst_ring_desc); 970 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 971 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 972 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 973 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 974 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 975 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 976 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 977 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 978 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 979 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 980 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 981 void (*hal_reo_config)(struct hal_soc *soc, 982 uint32_t reg_val, 983 struct hal_reo_params *reo_params); 984 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 985 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 986 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 987 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 988 bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf); 989 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 990 void 991 (*hal_rx_msdu_get_flow_params)( 992 uint8_t *buf, 993 bool *flow_invalid, 994 bool *flow_timeout, 995 uint32_t *flow_index); 996 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 997 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 998 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 999 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 1000 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 1001 void *msdu_pkt_metadata); 1002 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 1003 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 1004 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 1005 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 1006 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 1007 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 1008 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 1009 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 1010 hal_rx_mon_desc_info_t mon_desc_info); 1011 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 1012 uint32_t (*hal_rx_msdu_end_offset_get)(void); 1013 uint32_t (*hal_rx_attn_offset_get)(void); 1014 uint32_t (*hal_rx_msdu_start_offset_get)(void); 1015 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 1016 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 1017 uint32_t (*hal_rx_pkt_tlv_offset_get)(void); 1018 uint32_t (*hal_rx_msdu_end_wmask_get)(void); 1019 uint32_t (*hal_rx_mpdu_start_wmask_get)(void); 1020 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 1021 uint32_t table_offset, 1022 uint8_t *rx_flow); 1023 void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst, 1024 uint32_t hal_hash, 1025 uint8_t *tuple_info); 1026 QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst, 1027 void *fse); 1028 uint32_t (*hal_rx_fst_get_fse_size)(void); 1029 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 1030 uint32_t num_rings, 1031 uint32_t *remap1, 1032 uint32_t *remap2); 1033 void (*hal_compute_reo_remap_ix0)(uint32_t *remap0); 1034 uint32_t (*hal_rx_flow_setup_cmem_fse)( 1035 struct hal_soc *soc, uint32_t cmem_ba, 1036 uint32_t table_offset, uint8_t *rx_flow); 1037 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc, 1038 uint32_t fse_offset); 1039 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc, 1040 uint32_t fse_offset, 1041 uint32_t *fse, qdf_size_t len); 1042 1043 void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset, 1044 uint32_t value); 1045 1046 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, 1047 uint32_t *reo_destination_indication); 1048 uint8_t (*hal_tx_get_num_tcl_banks)(void); 1049 uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid); 1050 uint16_t (*hal_get_rx_max_ba_window)(int tid); 1051 1052 void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie, 1053 qdf_dma_addr_t link_desc_paddr, 1054 uint8_t bm_id); 1055 void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl, 1056 hal_ring_handle_t hal_ring_hdl); 1057 void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr); 1058 void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 1059 uint8_t ac, uint32_t *value); 1060 void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 1061 uint8_t ac, uint32_t value); 1062 uint32_t (*hal_get_reo_reg_base_offset)(void); 1063 void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size, 1064 uint16_t *rx_mon_pkt_tlv_size); 1065 uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf); 1066 uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr); 1067 void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl, 1068 uint8_t *buf, uint8_t dbg_level); 1069 int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv, 1070 struct hal_offload_info *offload_info); 1071 uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf); 1072 uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf); 1073 uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf); 1074 uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf); 1075 int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params); 1076 int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset, 1077 uint32_t *l4_hdr_offset); 1078 uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf); 1079 uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf); 1080 void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num); 1081 void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn); 1082 uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf); 1083 uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl, 1084 void *msdu_link_desc); 1085 void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 1086 void *msdu_desc_info, uint32_t dst_ind, 1087 uint32_t nbuf_len); 1088 void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 1089 void *ent_desc, 1090 void *mpdu_desc_info, 1091 uint32_t seq_no); 1092 #ifdef DP_UMAC_HW_RESET_SUPPORT 1093 void (*hal_unregister_reo_send_cmd)(struct hal_soc *hal_soc); 1094 void (*hal_register_reo_send_cmd)(struct hal_soc *hal_soc); 1095 void (*hal_reset_rx_reo_tid_q)(struct hal_soc *hal_soc, 1096 void *hw_qdesc_vaddr, uint32_t size); 1097 #endif 1098 uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf); 1099 uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf); 1100 uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf); 1101 uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf); 1102 uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf); 1103 uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf); 1104 uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf); 1105 uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf); 1106 1107 uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc); 1108 uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc); 1109 void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl, 1110 void *src_srng_desc, 1111 hal_buff_addrinfo_t buf_addr_info, 1112 uint8_t bm_action); 1113 1114 void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl, 1115 hal_buf_info_t buf_info_hdl); 1116 void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc, 1117 struct hal_buf_info *buf_info); 1118 void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry, 1119 qdf_dma_addr_t paddr, 1120 uint32_t cookie, uint8_t manager); 1121 uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl); 1122 uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc); 1123 void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr, 1124 uint32_t *ip_csum_err, 1125 uint32_t *tcp_udp_csum_err); 1126 void (*hal_rx_mpdu_desc_info_get)(void *desc_addr, 1127 void *mpdu_desc_info_hdl); 1128 uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc); 1129 uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc); 1130 bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf); 1131 uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr); 1132 uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr); 1133 void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr, 1134 struct hal_rx_pkt_capture_flags *flags); 1135 uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr); 1136 uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr); 1137 void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf, 1138 uint8_t *priv_data, 1139 uint32_t len); 1140 void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf, 1141 uint8_t *priv_data, 1142 uint32_t len); 1143 void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len); 1144 void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf, 1145 void *mpdu_desc_info_hdl); 1146 uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc); 1147 uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc, 1148 uint8_t *buf); 1149 void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc, 1150 uint32_t dst_ind); 1151 1152 /* REO CMD and STATUS */ 1153 int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl, 1154 hal_ring_handle_t hal_ring_hdl, 1155 enum hal_reo_cmd_type cmd, 1156 void *params); 1157 QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl, 1158 hal_ring_desc_t reo_desc, 1159 void *st_handle, 1160 uint32_t tlv, int *num_ref); 1161 uint8_t (*hal_get_tlv_hdr_size)(void); 1162 uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id); 1163 1164 bool (*hal_txmon_is_mon_buf_addr_tlv)(void *tx_tlv_hdr); 1165 void (*hal_txmon_populate_packet_info)(void *tx_tlv_hdr, 1166 void *pkt_info); 1167 /* TX MONITOR */ 1168 #ifdef QCA_MONITOR_2_0_SUPPORT 1169 uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info, 1170 void *prot_ppdu_info, 1171 void *data_status_info, 1172 void *prot_status_info, 1173 void *tx_tlv_hdr, 1174 qdf_frag_t status_frag); 1175 uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr, 1176 uint8_t *num_users); 1177 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1178 void (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl); 1179 void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl, 1180 int qref_reset); 1181 void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl); 1182 void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl, 1183 uint16_t peer_id, 1184 int tid, 1185 qdf_dma_addr_t hw_qdesc_paddr); 1186 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1187 uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf); 1188 #endif 1189 void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl); 1190 uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf); 1191 void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl, 1192 enum hal_tx_vdev_mismatch_notify config); 1193 void (*hal_tx_mcast_mlo_reinject_routing_set)( 1194 hal_soc_handle_t hal_soc_hdl, 1195 enum hal_tx_mcast_mlo_reinject_notify config); 1196 void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl, 1197 struct hal_hw_cc_config 1198 *cc_cfg); 1199 void (*hal_tx_populate_bank_register)(hal_soc_handle_t hal_soc_hdl, 1200 union hal_tx_bank_config *config, 1201 uint8_t bank_id); 1202 void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl, 1203 uint8_t vdev_id, 1204 uint8_t mcast_ctrl_val); 1205 void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1206 uint32_t mac_id, uint64_t *tsf, 1207 uint64_t *tsf_sync_soc_time); 1208 }; 1209 1210 /** 1211 * struct hal_soc_stats - Hal layer stats 1212 * @reg_write_fail: number of failed register writes 1213 * @wstats: delayed register write stats 1214 * @shadow_reg_write_fail: shadow reg write failure stats 1215 * @shadow_reg_write_succ: shadow reg write success stats 1216 * 1217 * This structure holds all the statistics at HAL layer. 1218 */ 1219 struct hal_soc_stats { 1220 uint32_t reg_write_fail; 1221 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1222 struct hal_reg_write_soc_stats wstats; 1223 #endif 1224 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1225 uint32_t shadow_reg_write_fail; 1226 uint32_t shadow_reg_write_succ; 1227 #endif 1228 }; 1229 1230 #ifdef ENABLE_HAL_REG_WR_HISTORY 1231 /* The history size should always be a power of 2 */ 1232 #define HAL_REG_WRITE_HIST_SIZE 8 1233 1234 /** 1235 * struct hal_reg_write_fail_entry - Record of 1236 * register write which failed. 1237 * @timestamp: timestamp of reg write failure 1238 * @reg_offset: offset of register where the write failed 1239 * @write_val: the value which was to be written 1240 * @read_val: the value read back from the register after write 1241 */ 1242 struct hal_reg_write_fail_entry { 1243 uint64_t timestamp; 1244 uint32_t reg_offset; 1245 uint32_t write_val; 1246 uint32_t read_val; 1247 }; 1248 1249 /** 1250 * struct hal_reg_write_fail_history - Hal layer history 1251 * of all the register write failures. 1252 * @index: index to add the new record 1253 * @record: array of all the records in history 1254 * 1255 * This structure holds the history of register write 1256 * failures at HAL layer. 1257 */ 1258 struct hal_reg_write_fail_history { 1259 qdf_atomic_t index; 1260 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 1261 }; 1262 #endif 1263 1264 /** 1265 * struct reo_queue_ref_table - Reo qref LUT addr 1266 * @mlo_reo_qref_table_vaddr: MLO table vaddr 1267 * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr 1268 * @mlo_reo_qref_table_paddr: MLO table paddr 1269 * @non_mlo_reo_qref_table_paddr: Non MLO table paddr 1270 * @reo_qref_table_en: Enable flag 1271 */ 1272 struct reo_queue_ref_table { 1273 uint64_t *mlo_reo_qref_table_vaddr; 1274 uint64_t *non_mlo_reo_qref_table_vaddr; 1275 qdf_dma_addr_t mlo_reo_qref_table_paddr; 1276 qdf_dma_addr_t non_mlo_reo_qref_table_paddr; 1277 uint8_t reo_qref_table_en; 1278 }; 1279 1280 /** 1281 * union hal_shadow_reg_cfg - Shadow register config 1282 * @addr: Place holder where shadow address is saved 1283 * @v2: shadow config v2 format 1284 * @v3: shadow config v3 format 1285 */ 1286 union hal_shadow_reg_cfg { 1287 uint32_t addr; 1288 struct pld_shadow_reg_v2_cfg v2; 1289 #ifdef CONFIG_SHADOW_V3 1290 struct pld_shadow_reg_v3_cfg v3; 1291 #endif 1292 }; 1293 1294 #ifdef HAL_RECORD_SUSPEND_WRITE 1295 #define HAL_SUSPEND_WRITE_HISTORY_MAX 256 1296 1297 struct hal_suspend_write_record { 1298 uint64_t ts; 1299 uint8_t ring_id; 1300 uit32_t value; 1301 uint32_t direct_wcount; 1302 }; 1303 1304 struct hal_suspend_write_history { 1305 qdf_atomic_t index; 1306 struct hal_suspend_write_record record[HAL_SUSPEND_WRITE_HISTORY_MAX]; 1307 1308 }; 1309 #endif 1310 1311 /** 1312 * struct hal_soc - HAL context to be used to access SRNG APIs 1313 * (currently used by data path and 1314 * transport (CE) modules) 1315 * @list_shadow_reg_config: array of generic regs mapped to 1316 * shadow regs 1317 * @num_generic_shadow_regs_configured: number of generic regs 1318 * mapped to shadow regs 1319 */ 1320 struct hal_soc { 1321 /* HIF handle to access HW registers */ 1322 struct hif_opaque_softc *hif_handle; 1323 1324 /* QDF device handle */ 1325 qdf_device_t qdf_dev; 1326 1327 /* Device base address */ 1328 void *dev_base_addr; 1329 /* Device base address for ce - qca5018 target */ 1330 void *dev_base_addr_ce; 1331 1332 void *dev_base_addr_cmem; 1333 /* HAL internal state for all SRNG rings. 1334 * TODO: See if this is required 1335 */ 1336 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 1337 1338 /* Remote pointer memory for HW/FW updates */ 1339 uint32_t *shadow_rdptr_mem_vaddr; 1340 qdf_dma_addr_t shadow_rdptr_mem_paddr; 1341 1342 /* Shared memory for ring pointer updates from host to FW */ 1343 uint32_t *shadow_wrptr_mem_vaddr; 1344 qdf_dma_addr_t shadow_wrptr_mem_paddr; 1345 1346 /* REO blocking resource index */ 1347 uint8_t reo_res_bitmap; 1348 uint8_t index; 1349 uint32_t target_type; 1350 uint32_t version; 1351 1352 /* shadow register configuration */ 1353 union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS]; 1354 int num_shadow_registers_configured; 1355 bool use_register_windowing; 1356 uint32_t register_window; 1357 qdf_spinlock_t register_access_lock; 1358 1359 /* Static window map configuration for multiple window write*/ 1360 bool static_window_map; 1361 1362 /* srng table */ 1363 struct hal_hw_srng_config *hw_srng_table; 1364 int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX]; 1365 struct hal_hw_txrx_ops *ops; 1366 1367 /* Indicate srngs initialization */ 1368 bool init_phase; 1369 /* Hal level stats */ 1370 struct hal_soc_stats stats; 1371 #ifdef ENABLE_HAL_REG_WR_HISTORY 1372 struct hal_reg_write_fail_history *reg_wr_fail_hist; 1373 #endif 1374 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1375 /* queue(array) to hold register writes */ 1376 struct hal_reg_write_q_elem *reg_write_queue; 1377 /* delayed work to be queued into workqueue */ 1378 qdf_work_t reg_write_work; 1379 /* workqueue for delayed register writes */ 1380 qdf_workqueue_t *reg_write_wq; 1381 /* write index used by caller to enqueue delayed work */ 1382 qdf_atomic_t write_idx; 1383 /* read index used by worker thread to dequeue/write registers */ 1384 uint32_t read_idx; 1385 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */ 1386 qdf_atomic_t active_work_cnt; 1387 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1388 struct shadow_reg_config 1389 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; 1390 int num_generic_shadow_regs_configured; 1391 #endif 1392 /* flag to indicate cmn dmac rings in berryllium */ 1393 bool dmac_cmn_src_rxbuf_ring; 1394 /* Reo queue ref table items */ 1395 struct reo_queue_ref_table reo_qref; 1396 }; 1397 1398 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1399 /** 1400 * hal_delayed_reg_write() - delayed register write 1401 * @hal_soc: HAL soc handle 1402 * @srng: hal srng 1403 * @addr: iomem address 1404 * @value: value to be written 1405 * 1406 * Return: none 1407 */ 1408 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1409 struct hal_srng *srng, 1410 void __iomem *addr, 1411 uint32_t value); 1412 #endif 1413 1414 void hal_qca6750_attach(struct hal_soc *hal_soc); 1415 void hal_qca6490_attach(struct hal_soc *hal_soc); 1416 void hal_qca6390_attach(struct hal_soc *hal_soc); 1417 void hal_qca6290_attach(struct hal_soc *hal_soc); 1418 void hal_qca8074_attach(struct hal_soc *hal_soc); 1419 void hal_kiwi_attach(struct hal_soc *hal_soc); 1420 void hal_qcn9224v1_attach(struct hal_soc *hal_soc); 1421 void hal_qcn9224v2_attach(struct hal_soc *hal_soc); 1422 /* 1423 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 1424 * dp_hal_soc handle type 1425 * @hal_soc - hal_soc type 1426 * 1427 * Return: hal_soc_handle_t type 1428 */ 1429 static inline 1430 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 1431 { 1432 return (hal_soc_handle_t)hal_soc; 1433 } 1434 1435 /* 1436 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 1437 * dp_hal_ring handle type 1438 * @hal_srng - hal_srng type 1439 * 1440 * Return: hal_ring_handle_t type 1441 */ 1442 static inline 1443 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 1444 { 1445 return (hal_ring_handle_t)hal_srng; 1446 } 1447 1448 /* 1449 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 1450 * @hal_ring - hal_ring_handle_t type 1451 * 1452 * Return: hal_srng pointer type 1453 */ 1454 static inline 1455 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 1456 { 1457 return (struct hal_srng *)hal_ring; 1458 } 1459 1460 /* Size of REO queue reference table in Host 1461 * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference) 1462 * = 278528 bytes 1463 */ 1464 #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528 1465 /* Calculated based on 512 MLO peers */ 1466 #define REO_QUEUE_REF_ML_TABLE_SIZE 69632 1467 #define HAL_ML_PEER_ID_START 0x2000 1468 #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START) 1469 1470 /* 1471 * REO2PPE destination indication 1472 */ 1473 #define REO2PPE_DST_IND 6 1474 #define REO2PPE_DST_RING 11 1475 #define REO2PPE_RULE_FAIL_FB 0x2000 1476 1477 /** 1478 * enum hal_pkt_type - Type of packet type reported by HW 1479 * @HAL_DOT11A: 802.11a PPDU type 1480 * @HAL_DOT11B: 802.11b PPDU type 1481 * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type 1482 * @HAL_DOT11AC: 802.11ac PPDU type 1483 * @HAL_DOT11AX: 802.11ax PPDU type 1484 * @HAL_DOT11BA: 802.11ba (WUR) PPDU type 1485 * @HAL_DOT11BE: 802.11be PPDU type 1486 * @HAL_DOT11AZ: 802.11az (ranging) PPDU type 1487 * @HAL_DOT11N_GF: 802.11n Green Field PPDU type 1488 * 1489 * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data) 1490 * or WBM2SW ring entry's descriptor (TX data completion) 1491 */ 1492 enum hal_pkt_type { 1493 HAL_DOT11A = 0, 1494 HAL_DOT11B = 1, 1495 HAL_DOT11N_MM = 2, 1496 HAL_DOT11AC = 3, 1497 HAL_DOT11AX = 4, 1498 HAL_DOT11BA = 5, 1499 HAL_DOT11BE = 6, 1500 HAL_DOT11AZ = 7, 1501 HAL_DOT11N_GF = 8, 1502 HAL_DOT11_MAX, 1503 }; 1504 1505 #endif /* _HAL_INTERNAL_H_ */ 1506