1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_INTERNAL_H_ 21 #define _HAL_INTERNAL_H_ 22 23 #include "qdf_types.h" 24 #include "qdf_atomic.h" 25 #include "qdf_lock.h" 26 #include "qdf_mem.h" 27 #include "qdf_nbuf.h" 28 #include "pld_common.h" 29 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 30 #include "qdf_defer.h" 31 #include "qdf_timer.h" 32 #endif 33 34 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 35 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 36 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 37 #define hal_info(params...) \ 38 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_HAL, ## params) 39 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 40 41 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 43 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 44 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 45 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 46 47 #ifdef ENABLE_VERBOSE_DEBUG 48 extern bool is_hal_verbose_debug_enabled; 49 #define hal_verbose_debug(params...) \ 50 if (unlikely(is_hal_verbose_debug_enabled)) \ 51 do {\ 52 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 53 } while (0) 54 #define hal_verbose_hex_dump(params...) \ 55 if (unlikely(is_hal_verbose_debug_enabled)) \ 56 do {\ 57 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 58 QDF_TRACE_LEVEL_DEBUG, \ 59 params); \ 60 } while (0) 61 #else 62 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 63 #define hal_verbose_hex_dump(params...) \ 64 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 65 params) 66 #endif 67 68 /* 69 * Given the offset of a field in bytes, returns uint8_t * 70 */ 71 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 72 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 73 74 /* 75 * Given the offset of a field in bytes, returns uint32_t * 76 */ 77 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 78 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 79 80 /* 81 * Given the offset of a field in bytes, returns uint64_t * 82 */ 83 #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \ 84 (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3)) 85 86 #define _HAL_MS(_word, _mask, _shift) \ 87 (((_word) & (_mask)) >> (_shift)) 88 89 /* 90 * Get number of QWORDS possible for num. 91 * Its the caller's duty to make sure num is a multiple of QWORD (8) 92 */ 93 #define HAL_GET_NUM_QWORDS(num) ((num) >> 3) 94 95 /* 96 * Get number of DWORDS possible for num. 97 * Its the caller's duty to make sure num is a multiple of DWORD (8) 98 */ 99 #define HAL_GET_NUM_DWORDS(num) ((num) >> 2) 100 101 struct hal_hw_cc_config { 102 uint32_t lut_base_addr_31_0; 103 uint32_t cc_global_en:1, 104 page_4k_align:1, 105 cookie_offset_msb:5, 106 cookie_page_msb:5, 107 lut_base_addr_39_32:8, 108 wbm2sw6_cc_en:1, 109 wbm2sw5_cc_en:1, 110 wbm2sw4_cc_en:1, 111 wbm2sw3_cc_en:1, 112 wbm2sw2_cc_en:1, 113 wbm2sw1_cc_en:1, 114 wbm2sw0_cc_en:1, 115 wbm2fw_cc_en:1, 116 error_path_cookie_conv_en:1, 117 release_path_cookie_conv_en:1, 118 reserved:2; 119 }; 120 121 struct hal_soc_handle; 122 /* 123 * typedef hal_soc_handle_t - opaque handle for DP HAL soc 124 */ 125 typedef struct hal_soc_handle *hal_soc_handle_t; 126 127 struct hal_ring_desc; 128 /* 129 * typedef hal_ring_desc_t - opaque handle for DP ring descriptor 130 */ 131 typedef struct hal_ring_desc *hal_ring_desc_t; 132 133 struct hal_link_desc; 134 /* 135 * typedef hal_link_desc_t - opaque handle for DP link descriptor 136 */ 137 typedef struct hal_link_desc *hal_link_desc_t; 138 139 struct hal_rxdma_desc; 140 /* 141 * typedef hal_rxdma_desc_t - opaque handle for DP rxdma dst ring descriptor 142 */ 143 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 144 145 struct hal_buff_addrinfo; 146 /* 147 * typedef hal_buff_addrinfo_t - opaque handle for DP buffer address info 148 */ 149 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 150 151 struct hal_rx_mon_desc_info; 152 /* 153 * typedef hal_rx_mon_desc_info_t - opaque handle for sw monitor ring desc info 154 */ 155 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 156 157 struct hal_buf_info; 158 /* 159 * typedef hal_buf_info_t - opaque handle for HAL buffer info 160 */ 161 typedef struct hal_buf_info *hal_buf_info_t; 162 163 struct rx_msdu_desc_info; 164 /* 165 * typedef rx_msdu_desc_info_t - opaque handle for rx MSDU descriptor info 166 */ 167 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t; 168 169 /* 170 * Opaque handler for PPE VP config. 171 */ 172 union hal_tx_ppe_vp_config; 173 union hal_tx_cmn_config_ppe; 174 union hal_tx_bank_config; 175 union hal_tx_ppe_idx_map_config; 176 177 #ifndef WLAN_SOFTUMAC_SUPPORT 178 /* TBD: This should be movded to shared HW header file */ 179 enum hal_srng_ring_id { 180 /* UMAC rings */ 181 HAL_SRNG_REO2SW0 = 0, 182 HAL_SRNG_REO2SW1 = 1, 183 HAL_SRNG_REO2SW2 = 2, 184 HAL_SRNG_REO2SW3 = 3, 185 HAL_SRNG_REO2SW4 = 4, 186 HAL_SRNG_REO2SW5 = 5, 187 HAL_SRNG_REO2SW6 = 6, 188 HAL_SRNG_REO2SW7 = 7, 189 HAL_SRNG_REO2SW8 = 8, 190 HAL_SRNG_REO2TCL = 9, 191 HAL_SRNG_REO2PPE = 10, 192 /* 11-15 unused */ 193 HAL_SRNG_SW2REO = 16, 194 HAL_SRNG_SW2REO1 = 17, 195 HAL_SRNG_SW2REO2 = 18, 196 HAL_SRNG_SW2REO3 = 19, 197 HAL_SRNG_REO_CMD = 20, 198 HAL_SRNG_REO_STATUS = 21, 199 /* 22-23 unused */ 200 HAL_SRNG_SW2TCL1 = 24, 201 HAL_SRNG_SW2TCL2 = 25, 202 HAL_SRNG_SW2TCL3 = 26, 203 HAL_SRNG_SW2TCL4 = 27, 204 HAL_SRNG_SW2TCL5 = 28, 205 HAL_SRNG_SW2TCL6 = 29, 206 HAL_SRNG_PPE2TCL1 = 30, 207 /* 31-39 unused */ 208 HAL_SRNG_SW2TCL_CMD = 40, 209 HAL_SRNG_TCL_STATUS = 41, 210 HAL_SRNG_SW2TCL_CREDIT = 42, 211 /* 43-63 unused */ 212 HAL_SRNG_CE_0_SRC = 64, 213 HAL_SRNG_CE_1_SRC = 65, 214 HAL_SRNG_CE_2_SRC = 66, 215 HAL_SRNG_CE_3_SRC = 67, 216 HAL_SRNG_CE_4_SRC = 68, 217 HAL_SRNG_CE_5_SRC = 69, 218 HAL_SRNG_CE_6_SRC = 70, 219 HAL_SRNG_CE_7_SRC = 71, 220 HAL_SRNG_CE_8_SRC = 72, 221 HAL_SRNG_CE_9_SRC = 73, 222 HAL_SRNG_CE_10_SRC = 74, 223 HAL_SRNG_CE_11_SRC = 75, 224 HAL_SRNG_CE_12_SRC = 76, 225 HAL_SRNG_CE_13_SRC = 77, 226 HAL_SRNG_CE_14_SRC = 78, 227 HAL_SRNG_CE_15_SRC = 79, 228 /* 80 */ 229 HAL_SRNG_CE_0_DST = 81, 230 HAL_SRNG_CE_1_DST = 82, 231 HAL_SRNG_CE_2_DST = 83, 232 HAL_SRNG_CE_3_DST = 84, 233 HAL_SRNG_CE_4_DST = 85, 234 HAL_SRNG_CE_5_DST = 86, 235 HAL_SRNG_CE_6_DST = 87, 236 HAL_SRNG_CE_7_DST = 89, 237 HAL_SRNG_CE_8_DST = 90, 238 HAL_SRNG_CE_9_DST = 91, 239 HAL_SRNG_CE_10_DST = 92, 240 HAL_SRNG_CE_11_DST = 93, 241 HAL_SRNG_CE_12_DST = 94, 242 HAL_SRNG_CE_13_DST = 95, 243 HAL_SRNG_CE_14_DST = 96, 244 HAL_SRNG_CE_15_DST = 97, 245 /* 98-99 unused */ 246 HAL_SRNG_CE_0_DST_STATUS = 100, 247 HAL_SRNG_CE_1_DST_STATUS = 101, 248 HAL_SRNG_CE_2_DST_STATUS = 102, 249 HAL_SRNG_CE_3_DST_STATUS = 103, 250 HAL_SRNG_CE_4_DST_STATUS = 104, 251 HAL_SRNG_CE_5_DST_STATUS = 105, 252 HAL_SRNG_CE_6_DST_STATUS = 106, 253 HAL_SRNG_CE_7_DST_STATUS = 107, 254 HAL_SRNG_CE_8_DST_STATUS = 108, 255 HAL_SRNG_CE_9_DST_STATUS = 109, 256 HAL_SRNG_CE_10_DST_STATUS = 110, 257 HAL_SRNG_CE_11_DST_STATUS = 111, 258 HAL_SRNG_CE_12_DST_STATUS = 112, 259 HAL_SRNG_CE_13_DST_STATUS = 113, 260 HAL_SRNG_CE_14_DST_STATUS = 114, 261 HAL_SRNG_CE_15_DST_STATUS = 115, 262 /* 116-119 unused */ 263 HAL_SRNG_WBM_IDLE_LINK = 120, 264 HAL_SRNG_WBM_SW_RELEASE = 121, 265 HAL_SRNG_WBM_SW1_RELEASE = 122, 266 HAL_SRNG_WBM_PPE_RELEASE = 123, 267 /* 124-127 unused */ 268 HAL_SRNG_WBM2SW0_RELEASE = 128, 269 HAL_SRNG_WBM2SW1_RELEASE = 129, 270 HAL_SRNG_WBM2SW2_RELEASE = 130, 271 HAL_SRNG_WBM2SW3_RELEASE = 131, 272 HAL_SRNG_WBM2SW4_RELEASE = 132, 273 HAL_SRNG_WBM2SW5_RELEASE = 133, 274 HAL_SRNG_WBM2SW6_RELEASE = 134, 275 HAL_SRNG_WBM_ERROR_RELEASE = 135, 276 /* 136-158 unused */ 277 HAL_SRNG_UMAC_ID_END = 159, 278 /* Common DMAC rings shared by all LMACs */ 279 HAL_SRNG_SW2RXDMA_BUF0 = 160, 280 HAL_SRNG_SW2RXDMA_BUF1 = 161, 281 HAL_SRNG_SW2RXDMA_BUF2 = 162, 282 /* 163-167 unused */ 283 HAL_SRNG_SW2RXMON_BUF0 = 168, 284 /* 169-175 unused */ 285 /* 177-183 unused */ 286 HAL_SRNG_DMAC_CMN_ID_END = 183, 287 /* LMAC rings - The following set will be replicated for each LMAC */ 288 HAL_SRNG_LMAC1_ID_START = 184, 289 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 290 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 291 #ifdef IPA_OFFLOAD 292 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1, 293 #ifdef IPA_WDI3_VLAN_SUPPORT 294 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2, 295 #endif 296 #endif 297 #ifdef FEATURE_DIRECT_LINK 298 HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING, 299 #endif 300 HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 301 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF, 302 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 303 HAL_SRNG_WMAC1_RXDMA2SW0, 304 HAL_SRNG_WMAC1_RXDMA2SW1, 305 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1, 306 HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 307 #ifdef WLAN_FEATURE_CIF_CFR 308 HAL_SRNG_WIFI_POS_SRC_DMA_RING, 309 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 310 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 311 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING2, 312 #else 313 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 314 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 315 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING2, 316 #endif 317 HAL_SRNG_WMAC1_TXMON2SW0, 318 HAL_SRNG_SW2TXMON_BUF0, 319 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2), 320 }; 321 #else 322 /* lmac rings are remains same for evros */ 323 enum hal_srng_ring_id { 324 HAL_SRNG_LMAC1_ID_START, 325 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 326 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 327 #ifdef IPA_OFFLOAD 328 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1, 329 #ifdef IPA_WDI3_VLAN_SUPPORT 330 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2, 331 #endif 332 #endif 333 #ifdef FEATURE_DIRECT_LINK 334 HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING, 335 #endif 336 HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 337 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF, 338 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 339 HAL_SRNG_WMAC1_RXDMA2SW0, 340 HAL_SRNG_WMAC1_RXDMA2SW1, 341 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1, 342 HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 343 #ifdef WLAN_FEATURE_CIF_CFR 344 HAL_SRNG_WIFI_POS_SRC_DMA_RING, 345 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 346 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 347 #else 348 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 349 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 350 #endif 351 HAL_SRNG_WMAC1_TXMON2SW0, 352 HAL_SRNG_SW2TXMON_BUF0, 353 HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING = HAL_SRNG_SW2TXMON_BUF0 + 2, 354 HAL_SRNG_LMAC1_ID_END = HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING, 355 }; 356 357 #define HAL_SRNG_DMAC_CMN_ID_END 0 358 #define HAL_SRNG_WBM_IDLE_LINK 120 359 #endif 360 361 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 362 #define HAL_MAX_LMACS 3 363 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 364 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 365 366 #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS) 367 368 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ 369 enum hal_ring_type { 370 REO_DST = 0, 371 REO_EXCEPTION = 1, 372 REO_REINJECT = 2, 373 REO_CMD = 3, 374 REO_STATUS = 4, 375 TCL_DATA = 5, 376 TCL_CMD_CREDIT = 6, 377 TCL_STATUS = 7, 378 CE_SRC = 8, 379 CE_DST = 9, 380 CE_DST_STATUS = 10, 381 WBM_IDLE_LINK = 11, 382 SW2WBM_RELEASE = 12, 383 WBM2SW_RELEASE = 13, 384 RXDMA_BUF = 14, 385 RXDMA_DST = 15, 386 RXDMA_MONITOR_BUF = 16, 387 RXDMA_MONITOR_STATUS = 17, 388 RXDMA_MONITOR_DST = 18, 389 RXDMA_MONITOR_DESC = 19, 390 DIR_BUF_RX_DMA_SRC = 20, 391 #ifdef WLAN_FEATURE_CIF_CFR 392 WIFI_POS_SRC, 393 #endif 394 REO2PPE, 395 PPE2TCL, 396 PPE_RELEASE, 397 TX_MONITOR_BUF, 398 TX_MONITOR_DST, 399 SW2RXDMA_NEW, 400 SW2RXDMA_LINK_RELEASE, 401 MAX_RING_TYPES 402 }; 403 404 enum SRNG_REGISTERS { 405 DST_HP = 0, 406 DST_TP, 407 DST_ID, 408 DST_MISC, 409 DST_HP_ADDR_LSB, 410 DST_HP_ADDR_MSB, 411 DST_MSI1_BASE_LSB, 412 DST_MSI1_BASE_MSB, 413 DST_MSI1_DATA, 414 DST_MISC_1, 415 #ifdef CONFIG_BERYLLIUM 416 DST_MSI2_BASE_LSB, 417 DST_MSI2_BASE_MSB, 418 DST_MSI2_DATA, 419 #endif 420 DST_BASE_LSB, 421 DST_BASE_MSB, 422 DST_PRODUCER_INT_SETUP, 423 #ifdef CONFIG_BERYLLIUM 424 DST_PRODUCER_INT2_SETUP, 425 #endif 426 427 SRC_HP, 428 SRC_TP, 429 SRC_ID, 430 SRC_MISC, 431 SRC_TP_ADDR_LSB, 432 SRC_TP_ADDR_MSB, 433 SRC_MSI1_BASE_LSB, 434 SRC_MSI1_BASE_MSB, 435 SRC_MSI1_DATA, 436 SRC_BASE_LSB, 437 SRC_BASE_MSB, 438 SRC_CONSUMER_INT_SETUP_IX0, 439 SRC_CONSUMER_INT_SETUP_IX1, 440 #ifdef DP_UMAC_HW_RESET_SUPPORT 441 SRC_CONSUMER_PREFETCH_TIMER, 442 #endif 443 SRNG_REGISTER_MAX, 444 }; 445 446 enum hal_srng_dir { 447 HAL_SRNG_SRC_RING, 448 HAL_SRNG_DST_RING 449 }; 450 451 /** 452 * enum hal_reo_remap_reg - REO remap registers 453 * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0 454 * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1 455 * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2 456 * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3 457 */ 458 enum hal_reo_remap_reg { 459 HAL_REO_REMAP_REG_IX0, 460 HAL_REO_REMAP_REG_IX1, 461 HAL_REO_REMAP_REG_IX2, 462 HAL_REO_REMAP_REG_IX3 463 }; 464 465 /* Lock wrappers for SRNG */ 466 #define hal_srng_lock_t qdf_spinlock_t 467 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 468 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 469 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock) 470 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 471 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 472 473 struct hal_soc; 474 struct hal_ring_handle; 475 476 /* 477 * typedef hal_ring_handle_t - opaque handle for DP HAL SRNG 478 */ 479 typedef struct hal_ring_handle *hal_ring_handle_t; 480 481 #define MAX_SRNG_REG_GROUPS 2 482 483 /* Hal Srng bit mask 484 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 485 */ 486 #define HAL_SRNG_FLUSH_EVENT BIT(0) 487 488 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 489 490 /** 491 * struct hal_reg_write_q_elem - delayed register write queue element 492 * @srng: hal_srng queued for a delayed write 493 * @addr: iomem address of the register 494 * @enqueue_val: register value at the time of delayed write enqueue 495 * @dequeue_val: register value at the time of delayed write dequeue 496 * @valid: whether this entry is valid or not 497 * @enqueue_time: enqueue time (qdf_log_timestamp) 498 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 499 * @dequeue_time: dequeue time (qdf_log_timestamp) 500 * @cpu_id: record cpuid when schedule work 501 * @ring_id: saved srng id 502 */ 503 struct hal_reg_write_q_elem { 504 struct hal_srng *srng; 505 void __iomem *addr; 506 uint32_t enqueue_val; 507 uint32_t dequeue_val; 508 uint8_t valid; 509 qdf_time_t enqueue_time; 510 qdf_time_t work_scheduled_time; 511 qdf_time_t dequeue_time; 512 int cpu_id; 513 qdf_atomic_t ring_id; 514 }; 515 516 /** 517 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 518 * @enqueues: writes enqueued to delayed work 519 * @dequeues: writes dequeued from delayed work (not written yet) 520 * @coalesces: writes not enqueued since srng is already queued up 521 * @direct: writes not enqueued and written to register directly 522 * @dequeue_delay: dequeue operation be delayed 523 */ 524 struct hal_reg_write_srng_stats { 525 uint32_t enqueues; 526 uint32_t dequeues; 527 uint32_t coalesces; 528 uint32_t direct; 529 uint32_t dequeue_delay; 530 }; 531 532 /** 533 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 534 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 535 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 536 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 537 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 538 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 539 */ 540 enum hal_reg_sched_delay { 541 REG_WRITE_SCHED_DELAY_SUB_100us, 542 REG_WRITE_SCHED_DELAY_SUB_1000us, 543 REG_WRITE_SCHED_DELAY_SUB_5000us, 544 REG_WRITE_SCHED_DELAY_GT_5000us, 545 REG_WRITE_SCHED_DELAY_HIST_MAX, 546 }; 547 548 /** 549 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 550 * @enqueues: writes enqueued to delayed work 551 * @dequeues: writes dequeued from delayed work (not written yet) 552 * @coalesces: writes not enqueued since srng is already queued up 553 * @direct: writes not enqueud and writted to register directly 554 * @prevent_l1_fails: prevent l1 API failed 555 * @q_depth: current queue depth in delayed register write queue 556 * @max_q_depth: maximum queue for delayed register write queue 557 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 558 * @dequeue_delay: dequeue operation be delayed 559 */ 560 struct hal_reg_write_soc_stats { 561 qdf_atomic_t enqueues; 562 uint32_t dequeues; 563 qdf_atomic_t coalesces; 564 qdf_atomic_t direct; 565 uint32_t prevent_l1_fails; 566 qdf_atomic_t q_depth; 567 uint32_t max_q_depth; 568 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 569 uint32_t dequeue_delay; 570 }; 571 #endif 572 573 struct hal_offload_info { 574 uint8_t lro_eligible; 575 uint8_t tcp_proto; 576 uint8_t tcp_pure_ack; 577 uint8_t ipv6_proto; 578 uint8_t tcp_offset; 579 uint16_t tcp_csum; 580 uint16_t tcp_win; 581 uint32_t tcp_seq_num; 582 uint32_t tcp_ack_num; 583 uint32_t flow_id; 584 }; 585 586 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 587 /** 588 * enum hal_srng_high_wm_bin - BIN for SRNG high watermark 589 * @HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT: <50% SRNG entries used 590 * @HAL_SRNG_HIGH_WM_BIN_50_to_60: 50-60% SRNG entries used 591 * @HAL_SRNG_HIGH_WM_BIN_60_to_70: 60-70% SRNG entries used 592 * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used 593 * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used 594 * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used 595 * @HAL_SRNG_HIGH_WM_BIN_MAX: maximum enumeration 596 */ 597 enum hal_srng_high_wm_bin { 598 HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT, 599 HAL_SRNG_HIGH_WM_BIN_50_to_60, 600 HAL_SRNG_HIGH_WM_BIN_60_to_70, 601 HAL_SRNG_HIGH_WM_BIN_70_to_80, 602 HAL_SRNG_HIGH_WM_BIN_80_to_90, 603 HAL_SRNG_HIGH_WM_BIN_90_to_100, 604 HAL_SRNG_HIGH_WM_BIN_MAX, 605 }; 606 607 /** 608 * struct hal_srng_high_wm_info - SRNG usage high watermark info 609 * @val: highest number of entries used in SRNG 610 * @timestamp: Timestamp when the max num entries were in used for a SRNG 611 * @bin_thresh: threshold for each bins 612 * @bins: Bins for srng usage 613 */ 614 struct hal_srng_high_wm_info { 615 uint32_t val; 616 uint64_t timestamp; 617 uint32_t bin_thresh[HAL_SRNG_HIGH_WM_BIN_MAX]; 618 uint32_t bins[HAL_SRNG_HIGH_WM_BIN_MAX]; 619 }; 620 #endif 621 622 #define DEFAULT_TSF_ID 1 623 624 /** 625 * enum hal_scratch_reg_enum - Enum to indicate scratch register values 626 * @PMM_QTIMER_GLOBAL_OFFSET_LO_US: QTIMER GLOBAL OFFSET LOW 627 * @PMM_QTIMER_GLOBAL_OFFSET_HI_US: QTIMER GLOBAL OFFSET HIGH 628 * @PMM_MAC0_TSF1_OFFSET_LO_US: MAC0 TSF1 OFFSET LOW 629 * @PMM_MAC0_TSF1_OFFSET_HI_US: MAC0 TSF1 OFFSET HIGH 630 * @PMM_MAC0_TSF2_OFFSET_LO_US: MAC0 TSF2 OFFSET LOW 631 * @PMM_MAC0_TSF2_OFFSET_HI_US: MAC0 TSF2 OFFSET HIGH 632 * @PMM_MAC1_TSF1_OFFSET_LO_US: MAC1 TSF1 OFFSET LOW 633 * @PMM_MAC1_TSF1_OFFSET_HI_US: MAC1 TSF1 OFFSET HIGH 634 * @PMM_MAC1_TSF2_OFFSET_LO_US: MAC1 TSF2 OFFSET LOW 635 * @PMM_MAC1_TSF2_OFFSET_HI_US: MAC1 TSF2 OFFSET HIGH 636 * @PMM_MLO_OFFSET_LO_US: MLO OFFSET LOW 637 * @PMM_MLO_OFFSET_HI_US: MLO OFFSET HIGH 638 * @PMM_TQM_CLOCK_OFFSET_LO_US: TQM CLOCK OFFSET LOW 639 * @PMM_TQM_CLOCK_OFFSET_HI_US: TQM CLOCK OFFSET HIGH 640 * @PMM_Q6_CRASH_REASON: Q6 CRASH REASON 641 * @PMM_SCRATCH_TWT_OFFSET: TWT OFFSET 642 * @PMM_PMM_REG_MAX: Max PMM REG value 643 */ 644 enum hal_scratch_reg_enum { 645 PMM_QTIMER_GLOBAL_OFFSET_LO_US, 646 PMM_QTIMER_GLOBAL_OFFSET_HI_US, 647 PMM_MAC0_TSF1_OFFSET_LO_US, 648 PMM_MAC0_TSF1_OFFSET_HI_US, 649 PMM_MAC0_TSF2_OFFSET_LO_US, 650 PMM_MAC0_TSF2_OFFSET_HI_US, 651 PMM_MAC1_TSF1_OFFSET_LO_US, 652 PMM_MAC1_TSF1_OFFSET_HI_US, 653 PMM_MAC1_TSF2_OFFSET_LO_US, 654 PMM_MAC1_TSF2_OFFSET_HI_US, 655 PMM_MLO_OFFSET_LO_US, 656 PMM_MLO_OFFSET_HI_US, 657 PMM_TQM_CLOCK_OFFSET_LO_US, 658 PMM_TQM_CLOCK_OFFSET_HI_US, 659 PMM_Q6_CRASH_REASON, 660 PMM_SCRATCH_TWT_OFFSET, 661 PMM_PMM_REG_MAX 662 }; 663 664 /** 665 * hal_get_tsf_enum(): API to get the enum corresponding to the mac and tsf id 666 * 667 * @tsf_id: tsf id 668 * @mac_id: mac id 669 * @tsf_enum_low: Pointer to update low scratch register 670 * @tsf_enum_hi: Pointer to update hi scratch register 671 * 672 * Return: void 673 */ 674 static inline void 675 hal_get_tsf_enum(uint32_t tsf_id, uint32_t mac_id, 676 enum hal_scratch_reg_enum *tsf_enum_low, 677 enum hal_scratch_reg_enum *tsf_enum_hi) 678 { 679 if (mac_id == 0) { 680 if (tsf_id == 0) { 681 *tsf_enum_low = PMM_MAC0_TSF1_OFFSET_LO_US; 682 *tsf_enum_hi = PMM_MAC0_TSF1_OFFSET_HI_US; 683 } else if (tsf_id == 1) { 684 *tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US; 685 *tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US; 686 } 687 } else if (mac_id == 1) { 688 if (tsf_id == 0) { 689 *tsf_enum_low = PMM_MAC1_TSF1_OFFSET_LO_US; 690 *tsf_enum_hi = PMM_MAC1_TSF1_OFFSET_HI_US; 691 } else if (tsf_id == 1) { 692 *tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US; 693 *tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US; 694 } 695 } 696 } 697 698 #ifdef HAL_SRNG_REG_HIS_DEBUG 699 700 #define HAL_SRNG_REG_MAX_ENTRIES 64 701 702 /** 703 * struct hal_srng_reg_his_entry - history entry for single srng pointer 704 * register update 705 * @write_time: register write timestamp 706 * @write_value: register write value 707 */ 708 struct hal_srng_reg_his_entry { 709 qdf_time_t write_time; 710 uint32_t write_value; 711 }; 712 713 /** 714 * struct hal_srng_reg_his_ctx - context for srng pointer writing history 715 * @current_idx: the index which has recorded srng pointer writing 716 * @reg_his_arr: array to record the history 717 */ 718 struct hal_srng_reg_his_ctx { 719 qdf_atomic_t current_idx; 720 struct hal_srng_reg_his_entry reg_his_arr[HAL_SRNG_REG_MAX_ENTRIES]; 721 }; 722 #endif 723 724 /* Common SRNG ring structure for source and destination rings */ 725 struct hal_srng { 726 /* Unique SRNG ring ID */ 727 uint8_t ring_id; 728 729 /* Ring initialization done */ 730 uint8_t initialized; 731 732 /* Interrupt/MSI value assigned to this ring */ 733 int irq; 734 735 /* Physical base address of the ring */ 736 qdf_dma_addr_t ring_base_paddr; 737 738 /* Virtual base address of the ring */ 739 uint32_t *ring_base_vaddr; 740 741 /* virtual address end */ 742 uint32_t *ring_vaddr_end; 743 744 /* Number of entries in ring */ 745 uint32_t num_entries; 746 747 /* Ring size */ 748 uint32_t ring_size; 749 750 /* Ring size mask */ 751 uint32_t ring_size_mask; 752 753 /* Size of ring entry */ 754 uint32_t entry_size; 755 756 /* Interrupt timer threshold – in micro seconds */ 757 uint32_t intr_timer_thres_us; 758 759 /* Interrupt batch counter threshold – in number of ring entries */ 760 uint32_t intr_batch_cntr_thres_entries; 761 762 /* Applicable only for CE dest ring */ 763 uint32_t prefetch_timer; 764 765 /* MSI Address */ 766 qdf_dma_addr_t msi_addr; 767 768 /* MSI data */ 769 uint32_t msi_data; 770 771 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 772 /* MSI2 Address */ 773 qdf_dma_addr_t msi2_addr; 774 775 /* MSI2 data */ 776 uint32_t msi2_data; 777 #endif 778 779 /* Misc flags */ 780 uint32_t flags; 781 782 /* Lock for serializing ring index updates */ 783 hal_srng_lock_t lock; 784 785 /* Start offset of SRNG register groups for this ring 786 * TBD: See if this is required - register address can be derived 787 * from ring ID 788 */ 789 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 790 791 /* Ring type/name */ 792 enum hal_ring_type ring_type; 793 794 /* Source or Destination ring */ 795 enum hal_srng_dir ring_dir; 796 797 union { 798 struct { 799 /* SW tail pointer */ 800 uint32_t tp; 801 802 /* Shadow head pointer location to be updated by HW */ 803 uint32_t *hp_addr; 804 805 /* Cached head pointer */ 806 uint32_t cached_hp; 807 808 /* Tail pointer location to be updated by SW – This 809 * will be a register address and need not be 810 * accessed through SW structure */ 811 uint32_t *tp_addr; 812 813 /* Current SW loop cnt */ 814 uint32_t loop_cnt; 815 816 /* max transfer size */ 817 uint16_t max_buffer_length; 818 819 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 820 /* near full IRQ supported */ 821 uint16_t nf_irq_support; 822 823 /* High threshold for Near full IRQ */ 824 uint16_t high_thresh; 825 #endif 826 } dst_ring; 827 828 struct { 829 /* SW head pointer */ 830 uint32_t hp; 831 832 /* SW reap head pointer */ 833 uint32_t reap_hp; 834 835 /* Shadow tail pointer location to be updated by HW */ 836 uint32_t *tp_addr; 837 838 /* Cached tail pointer */ 839 uint32_t cached_tp; 840 841 /* Head pointer location to be updated by SW – This 842 * will be a register address and need not be accessed 843 * through SW structure */ 844 uint32_t *hp_addr; 845 846 /* Low threshold – in number of ring entries */ 847 uint32_t low_threshold; 848 } src_ring; 849 } u; 850 851 struct hal_soc *hal_soc; 852 853 /* Number of times hp/tp updated in runtime resume */ 854 uint32_t flush_count; 855 /* hal srng event flag*/ 856 unsigned long srng_event; 857 /* last flushed time stamp */ 858 uint64_t last_flush_ts; 859 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 860 /* last ring desc entry cleared */ 861 uint32_t last_desc_cleared; 862 #endif 863 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 864 /* flag to indicate whether srng is already queued for delayed write */ 865 uint8_t reg_write_in_progress; 866 /* last dequeue elem time stamp */ 867 qdf_time_t last_dequeue_time; 868 869 /* srng specific delayed write stats */ 870 struct hal_reg_write_srng_stats wstats; 871 #endif 872 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 873 struct hal_srng_high_wm_info high_wm; 874 #endif 875 /* Timer threshold to issue ring pointer update - in micro seconds */ 876 uint16_t pointer_timer_threshold; 877 /* Number threshold of ring entries to issue pointer update */ 878 uint8_t pointer_num_threshold; 879 #ifdef HAL_SRNG_REG_HIS_DEBUG 880 /* pointer register writing history for this srng */ 881 struct hal_srng_reg_his_ctx *reg_his_ctx; 882 #endif 883 }; 884 885 #ifdef HAL_SRNG_REG_HIS_DEBUG 886 /** 887 * hal_srng_reg_his_init() - SRNG register history context initialize 888 * 889 * @srng: SRNG handle pointer 890 * 891 * Return: None 892 */ 893 static inline 894 void hal_srng_reg_his_init(struct hal_srng *srng) 895 { 896 qdf_atomic_set(&srng->reg_his_ctx->current_idx, -1); 897 } 898 899 /** 900 * hal_srng_reg_his_add() - add pointer writing history to SRNG 901 * 902 * @srng: SRNG handle pointer 903 * @reg_val: pointer value to write 904 * 905 * Return: None 906 */ 907 static inline 908 void hal_srng_reg_his_add(struct hal_srng *srng, uint32_t reg_val) 909 { 910 uint32_t write_idx; 911 struct hal_srng_reg_his_entry *reg_his_entry; 912 913 write_idx = qdf_atomic_inc_return(&srng->reg_his_ctx->current_idx); 914 write_idx = write_idx & (HAL_SRNG_REG_MAX_ENTRIES - 1); 915 916 reg_his_entry = &srng->reg_his_ctx->reg_his_arr[write_idx]; 917 918 reg_his_entry->write_time = qdf_get_log_timestamp(); 919 reg_his_entry->write_value = reg_val; 920 } 921 #else 922 static inline 923 void hal_srng_reg_his_init(struct hal_srng *srng) 924 { 925 } 926 927 static inline 928 void hal_srng_reg_his_add(struct hal_srng *srng, uint32_t reg_val) 929 { 930 } 931 #endif 932 933 /* HW SRNG configuration table */ 934 struct hal_hw_srng_config { 935 int start_ring_id; 936 uint16_t max_rings; 937 uint16_t entry_size; 938 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 939 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 940 uint8_t lmac_ring; 941 enum hal_srng_dir ring_dir; 942 uint32_t max_size; 943 bool nf_irq_support; 944 bool dmac_cmn_ring; 945 }; 946 947 #define MAX_SHADOW_REGISTERS 40 948 #define MAX_GENERIC_SHADOW_REG 5 949 950 /** 951 * struct shadow_reg_config - Hal soc structure that contains 952 * the list of generic shadow registers 953 * @target_register: target reg offset 954 * @shadow_config_index: shadow config index in shadow config 955 * list sent to FW 956 * @va: virtual addr of shadow reg 957 * 958 * This structure holds the generic registers that are mapped to 959 * the shadow region and holds the mapping of the target 960 * register offset to shadow config index provided to FW during 961 * init 962 */ 963 struct shadow_reg_config { 964 uint32_t target_register; 965 int shadow_config_index; 966 uint64_t va; 967 }; 968 969 /* REO parameters to be passed to hal_reo_setup */ 970 struct hal_reo_params { 971 /** rx hash steering enabled or disabled */ 972 bool rx_hash_enabled; 973 /** reo remap 0 register */ 974 uint32_t remap0; 975 /** reo remap 1 register */ 976 uint32_t remap1; 977 /** reo remap 2 register */ 978 uint32_t remap2; 979 /** fragment destination ring */ 980 uint8_t frag_dst_ring; 981 /* Destination for alternate */ 982 uint8_t alt_dst_ind_0; 983 /* reo_qref struct for mlo and non mlo table */ 984 struct reo_queue_ref_table *reo_qref; 985 }; 986 987 /** 988 * enum hal_reo_cmd_type: Enum for REO command type 989 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 990 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 991 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 992 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked 993 * earlier with a ‘REO_FLUSH_CACHE’ command 994 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 995 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 996 */ 997 enum hal_reo_cmd_type { 998 CMD_GET_QUEUE_STATS = 0, 999 CMD_FLUSH_QUEUE = 1, 1000 CMD_FLUSH_CACHE = 2, 1001 CMD_UNBLOCK_CACHE = 3, 1002 CMD_FLUSH_TIMEOUT_LIST = 4, 1003 CMD_UPDATE_RX_REO_QUEUE = 5 1004 }; 1005 1006 /** 1007 * enum hal_tx_mcast_mlo_reinject_notify 1008 * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW 1009 * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM 1010 */ 1011 enum hal_tx_mcast_mlo_reinject_notify { 1012 HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0, 1013 HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY, 1014 }; 1015 1016 /** 1017 * enum hal_tx_vdev_mismatch_notify 1018 * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM 1019 * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW 1020 */ 1021 enum hal_tx_vdev_mismatch_notify { 1022 HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0, 1023 HAL_TX_VDEV_MISMATCH_FW_NOTIFY, 1024 }; 1025 1026 struct hal_rx_pkt_capture_flags { 1027 uint8_t encrypt_type; 1028 uint8_t fragment_flag; 1029 uint8_t fcs_err; 1030 uint32_t chan_freq; 1031 uint32_t rssi_comb; 1032 uint64_t tsft; 1033 }; 1034 1035 /** 1036 * struct reo_queue_ref_table - Reo qref LUT addr 1037 * @mlo_reo_qref_table_vaddr: MLO table vaddr 1038 * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr 1039 * @mlo_reo_qref_table_paddr: MLO table paddr 1040 * @non_mlo_reo_qref_table_paddr: Non MLO table paddr 1041 * @reo_qref_table_en: Enable flag 1042 */ 1043 struct reo_queue_ref_table { 1044 uint64_t *mlo_reo_qref_table_vaddr; 1045 uint64_t *non_mlo_reo_qref_table_vaddr; 1046 qdf_dma_addr_t mlo_reo_qref_table_paddr; 1047 qdf_dma_addr_t non_mlo_reo_qref_table_paddr; 1048 uint8_t reo_qref_table_en; 1049 }; 1050 1051 struct hal_hw_txrx_ops { 1052 /* init and setup */ 1053 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 1054 struct hal_srng *srng, bool idle_check, 1055 uint32_t idx); 1056 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 1057 struct hal_srng *srng, bool idle_check, 1058 uint32_t idx); 1059 1060 void (*hal_srng_hw_disable)(struct hal_soc *hal, 1061 struct hal_srng *srng); 1062 void (*hal_get_hw_hptp)(struct hal_soc *hal, 1063 hal_ring_handle_t hal_ring_hdl, 1064 uint32_t *headp, uint32_t *tailp, 1065 uint8_t ring_type); 1066 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams, 1067 int qref_reset); 1068 void (*hal_setup_link_idle_list)( 1069 struct hal_soc *hal_soc, 1070 qdf_dma_addr_t scatter_bufs_base_paddr[], 1071 void *scatter_bufs_base_vaddr[], 1072 uint32_t num_scatter_bufs, 1073 uint32_t scatter_buf_size, 1074 uint32_t last_buf_end_offset, 1075 uint32_t num_entries); 1076 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 1077 qdf_iomem_t addr); 1078 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 1079 uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc); 1080 void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid, 1081 uint32_t ba_window_size, 1082 uint32_t start_seq, void *hw_qdesc_vaddr, 1083 qdf_dma_addr_t hw_qdesc_paddr, 1084 int pn_type, uint8_t vdev_stats_id); 1085 uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg, 1086 uint8_t *ix0_map); 1087 1088 /* tx */ 1089 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 1090 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 1091 uint8_t id); 1092 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 1093 uint8_t id, 1094 uint8_t dscp); 1095 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 1096 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 1097 uint8_t pool_id, uint32_t desc_id, 1098 uint8_t type); 1099 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 1100 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 1101 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 1102 void (*hal_tx_comp_get_status)(void *desc, void *ts, 1103 struct hal_soc *hal); 1104 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 1105 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 1106 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 1107 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 1108 hal_ring_handle_t hal_ring_hdl); 1109 uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc); 1110 uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)( 1111 hal_soc_handle_t hal_soc_hdl); 1112 1113 void (*hal_reo_config_reo2ppe_dest_info)(hal_soc_handle_t hal_soc_hdl); 1114 1115 void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl, 1116 union hal_tx_cmn_config_ppe *cmn_cfg); 1117 void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl, 1118 union hal_tx_ppe_vp_config *vp_cfg, 1119 int ppe_vp_idx); 1120 void (*hal_ppeds_cfg_ast_override_map_reg)(hal_soc_handle_t hal_soc_hdl, 1121 uint8_t idx, union hal_tx_ppe_idx_map_config *ppeds_idx_map); 1122 void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 1123 uint32_t val, 1124 uint8_t map_no); 1125 void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 1126 uint8_t pri, 1127 uint8_t tid); 1128 void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl); 1129 void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl, 1130 bool value, uint8_t ppe_vp_idx); 1131 void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl, 1132 hal_ring_handle_t hal_ring_hdl, 1133 uint8_t rbm_id); 1134 1135 /* rx */ 1136 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 1137 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 1138 struct mon_rx_status *rs); 1139 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 1140 int8_t (*hal_rx_phy_legacy_get_rssi)(uint8_t *rx_tlv); 1141 1142 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 1143 void *ppdu_info_handle); 1144 void (*hal_rx_dump_msdu_end_tlv)(void *pkt_tlvs, uint8_t dbg_level); 1145 void (*hal_rx_dump_rx_attention_tlv)(void *pkt_tlvs, uint8_t dbg_level); 1146 void (*hal_rx_dump_msdu_start_tlv)(void *pkt_tlvs, uint8_t dbg_level); 1147 void (*hal_rx_dump_mpdu_start_tlv)(void *pkt_tlvs, uint8_t dbg_level); 1148 void (*hal_rx_dump_mpdu_end_tlv)(void *pkt_tlvs, uint8_t dbg_level); 1149 void (*hal_rx_dump_pkt_hdr_tlv)(void *pkt_tlvs, uint8_t dbg_level); 1150 uint32_t (*hal_get_link_desc_size)(void); 1151 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 1152 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 1153 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 1154 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 1155 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 1156 void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b, 1157 void *h); 1158 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 1159 void *ppdu_info, 1160 hal_soc_handle_t hal_soc_hdl, 1161 qdf_nbuf_t nbuf); 1162 1163 void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc, 1164 struct hal_buf_info *buf_info); 1165 1166 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 1167 void *wbm_er_info); 1168 1169 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 1170 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 1171 uint8_t id); 1172 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 1173 1174 /* rx */ 1175 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 1176 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 1177 uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf); 1178 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 1179 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 1180 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 1181 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 1182 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 1183 void (*hal_rx_print_pn)(uint8_t *buf); 1184 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 1185 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 1186 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 1187 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 1188 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 1189 uint32_t (*hal_rx_tlv_peer_meta_data_get)(uint8_t *buf); 1190 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 1191 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 1192 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 1193 QDF_STATUS 1194 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 1195 QDF_STATUS 1196 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 1197 QDF_STATUS 1198 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 1199 QDF_STATUS 1200 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 1201 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 1202 bool (*hal_rx_is_unicast)(uint8_t *buf); 1203 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 1204 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 1205 void *rxdma_dst_ring_desc); 1206 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 1207 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 1208 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 1209 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 1210 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 1211 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 1212 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 1213 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 1214 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 1215 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 1216 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 1217 void (*hal_reo_config)(struct hal_soc *soc, 1218 uint32_t reg_val, 1219 struct hal_reo_params *reo_params); 1220 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 1221 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 1222 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 1223 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 1224 bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf); 1225 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 1226 void 1227 (*hal_rx_msdu_get_flow_params)( 1228 uint8_t *buf, 1229 bool *flow_invalid, 1230 bool *flow_timeout, 1231 uint32_t *flow_index); 1232 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 1233 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 1234 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 1235 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 1236 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 1237 void *msdu_pkt_metadata); 1238 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 1239 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 1240 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 1241 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 1242 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 1243 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 1244 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 1245 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 1246 hal_rx_mon_desc_info_t mon_desc_info); 1247 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 1248 uint32_t (*hal_rx_msdu_end_offset_get)(void); 1249 uint32_t (*hal_rx_attn_offset_get)(void); 1250 uint32_t (*hal_rx_msdu_start_offset_get)(void); 1251 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 1252 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 1253 uint32_t (*hal_rx_pkt_tlv_offset_get)(void); 1254 uint32_t (*hal_rx_msdu_end_wmask_get)(void); 1255 uint32_t (*hal_rx_mpdu_start_wmask_get)(void); 1256 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 1257 uint32_t table_offset, 1258 uint8_t *rx_flow); 1259 void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst, 1260 uint32_t hal_hash, 1261 uint8_t *tuple_info); 1262 QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst, 1263 void *fse); 1264 uint32_t (*hal_rx_fst_get_fse_size)(void); 1265 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 1266 uint32_t num_rings, 1267 uint32_t *remap1, 1268 uint32_t *remap2); 1269 void (*hal_compute_reo_remap_ix0)(uint32_t *remap0); 1270 uint32_t (*hal_rx_flow_setup_cmem_fse)( 1271 struct hal_soc *soc, uint32_t cmem_ba, 1272 uint32_t table_offset, uint8_t *rx_flow); 1273 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc, 1274 uint32_t fse_offset); 1275 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc, 1276 uint32_t fse_offset, 1277 uint32_t *fse, qdf_size_t len); 1278 1279 void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset, 1280 uint32_t value); 1281 1282 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, 1283 uint32_t *reo_destination_indication); 1284 uint8_t (*hal_tx_get_num_tcl_banks)(void); 1285 uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid); 1286 uint16_t (*hal_get_rx_max_ba_window)(int tid); 1287 1288 void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie, 1289 qdf_dma_addr_t link_desc_paddr, 1290 uint8_t bm_id); 1291 void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl, 1292 hal_ring_handle_t hal_ring_hdl); 1293 void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr); 1294 void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 1295 uint8_t ac, uint32_t *value); 1296 void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 1297 uint8_t ac, uint32_t value); 1298 uint32_t (*hal_get_reo_reg_base_offset)(void); 1299 void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size, 1300 uint16_t *rx_mon_pkt_tlv_size); 1301 uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf); 1302 uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr); 1303 void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl, 1304 uint8_t *buf, uint8_t dbg_level); 1305 int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv, 1306 struct hal_offload_info *offload_info); 1307 uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf); 1308 uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf); 1309 uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf); 1310 uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf); 1311 int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params); 1312 int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset, 1313 uint32_t *l4_hdr_offset); 1314 uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf); 1315 uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf); 1316 void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num); 1317 void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn); 1318 uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf); 1319 uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl, 1320 void *msdu_link_desc); 1321 void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 1322 void *msdu_desc_info, uint32_t dst_ind, 1323 uint32_t nbuf_len); 1324 void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 1325 void *ent_desc, 1326 void *mpdu_desc_info, 1327 uint32_t seq_no); 1328 #ifdef DP_UMAC_HW_RESET_SUPPORT 1329 void (*hal_unregister_reo_send_cmd)(struct hal_soc *hal_soc); 1330 void (*hal_register_reo_send_cmd)(struct hal_soc *hal_soc); 1331 void (*hal_reset_rx_reo_tid_q)(struct hal_soc *hal_soc, 1332 void *hw_qdesc_vaddr, uint32_t size); 1333 #endif 1334 uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf); 1335 uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf); 1336 uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf); 1337 uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf); 1338 uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf); 1339 uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf); 1340 uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf); 1341 uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf); 1342 1343 uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc); 1344 uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc); 1345 void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl, 1346 void *src_srng_desc, 1347 hal_buff_addrinfo_t buf_addr_info, 1348 uint8_t bm_action); 1349 1350 void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl, 1351 hal_buf_info_t buf_info_hdl); 1352 void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc, 1353 struct hal_buf_info *buf_info); 1354 void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry, 1355 qdf_dma_addr_t paddr, 1356 uint32_t cookie, uint8_t manager); 1357 uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl); 1358 uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc); 1359 void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr, 1360 uint32_t *ip_csum_err, 1361 uint32_t *tcp_udp_csum_err); 1362 void (*hal_rx_mpdu_desc_info_get)(void *desc_addr, 1363 void *mpdu_desc_info_hdl); 1364 uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc); 1365 uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc); 1366 bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf); 1367 uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr); 1368 uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr); 1369 void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr, 1370 struct hal_rx_pkt_capture_flags *flags); 1371 uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr); 1372 uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr); 1373 void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf, 1374 uint8_t *priv_data, 1375 uint32_t len); 1376 void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf, 1377 uint8_t *priv_data, 1378 uint32_t len); 1379 void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len); 1380 void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf, 1381 void *mpdu_desc_info_hdl); 1382 uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc); 1383 uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc, 1384 uint8_t *buf); 1385 uint8_t (*hal_rx_get_phy_ppdu_id_size)(void); 1386 void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc, 1387 uint32_t dst_ind); 1388 QDF_STATUS 1389 (*hal_rx_reo_ent_get_src_link_id)(hal_rxdma_desc_t rx_desc, 1390 uint8_t *src_link_id); 1391 1392 /* REO CMD and STATUS */ 1393 int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl, 1394 hal_ring_handle_t hal_ring_hdl, 1395 enum hal_reo_cmd_type cmd, 1396 void *params); 1397 QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl, 1398 hal_ring_desc_t reo_desc, 1399 void *st_handle, 1400 uint32_t tlv, int *num_ref); 1401 uint8_t (*hal_get_tlv_hdr_size)(void); 1402 uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id); 1403 1404 bool (*hal_txmon_is_mon_buf_addr_tlv)(void *tx_tlv_hdr); 1405 void (*hal_txmon_populate_packet_info)(void *tx_tlv_hdr, 1406 void *pkt_info); 1407 /* TX MONITOR */ 1408 #ifdef WLAN_PKT_CAPTURE_TX_2_0 1409 uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info, 1410 void *prot_ppdu_info, 1411 void *data_status_info, 1412 void *prot_status_info, 1413 void *tx_tlv_hdr, 1414 qdf_frag_t status_frag); 1415 uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr, 1416 uint8_t *num_users); 1417 void (*hal_txmon_get_word_mask)(void *wmask); 1418 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 1419 QDF_STATUS (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl, 1420 struct reo_queue_ref_table 1421 *reo_qref); 1422 void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl, 1423 int qref_reset); 1424 void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl); 1425 void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl, 1426 uint16_t peer_id, 1427 int tid, 1428 qdf_dma_addr_t hw_qdesc_paddr); 1429 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1430 uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf); 1431 #endif 1432 void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl); 1433 uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf); 1434 void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl, 1435 enum hal_tx_vdev_mismatch_notify config); 1436 void (*hal_tx_mcast_mlo_reinject_routing_set)( 1437 hal_soc_handle_t hal_soc_hdl, 1438 enum hal_tx_mcast_mlo_reinject_notify config); 1439 void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl, 1440 struct hal_hw_cc_config 1441 *cc_cfg); 1442 void (*hal_tx_populate_bank_register)(hal_soc_handle_t hal_soc_hdl, 1443 union hal_tx_bank_config *config, 1444 uint8_t bank_id); 1445 void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl, 1446 uint8_t vdev_id, 1447 uint8_t mcast_ctrl_val); 1448 void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1449 uint32_t mac_id, uint64_t *tsf, 1450 uint64_t *tsf_sync_soc_time); 1451 void (*hal_get_tsf2_scratch_reg)(hal_soc_handle_t hal_soc_hdl, 1452 uint8_t mac_id, uint64_t *value); 1453 void (*hal_get_tqm_scratch_reg)(hal_soc_handle_t hal_soc_hdl, 1454 uint64_t *value); 1455 #ifdef FEATURE_DIRECT_LINK 1456 QDF_STATUS (*hal_srng_set_msi_config)(hal_ring_handle_t ring_hdl, 1457 void *ring_params); 1458 #endif 1459 void (*hal_tx_ring_halt_set)(hal_soc_handle_t hal_soc_hdl); 1460 void (*hal_tx_ring_halt_reset)(hal_soc_handle_t hal_soc_hdl); 1461 bool (*hal_tx_ring_halt_poll)(hal_soc_handle_t hal_soc_hdl); 1462 uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)( 1463 hal_soc_handle_t hal_soc_hdl); 1464 uint32_t (*hal_tx_ring_halt_get)(hal_soc_handle_t hal_soc_hdl); 1465 bool (*hal_rx_en_mcast_fp_data_filter)(void); 1466 }; 1467 1468 /** 1469 * struct hal_soc_stats - Hal layer stats 1470 * @reg_write_fail: number of failed register writes 1471 * @wstats: delayed register write stats 1472 * @shadow_reg_write_fail: shadow reg write failure stats 1473 * @shadow_reg_write_succ: shadow reg write success stats 1474 * 1475 * This structure holds all the statistics at HAL layer. 1476 */ 1477 struct hal_soc_stats { 1478 uint32_t reg_write_fail; 1479 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1480 struct hal_reg_write_soc_stats wstats; 1481 #endif 1482 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1483 uint32_t shadow_reg_write_fail; 1484 uint32_t shadow_reg_write_succ; 1485 #endif 1486 }; 1487 1488 #ifdef ENABLE_HAL_REG_WR_HISTORY 1489 /* The history size should always be a power of 2 */ 1490 #define HAL_REG_WRITE_HIST_SIZE 8 1491 1492 /** 1493 * struct hal_reg_write_fail_entry - Record of 1494 * register write which failed. 1495 * @timestamp: timestamp of reg write failure 1496 * @reg_offset: offset of register where the write failed 1497 * @write_val: the value which was to be written 1498 * @read_val: the value read back from the register after write 1499 */ 1500 struct hal_reg_write_fail_entry { 1501 uint64_t timestamp; 1502 uint32_t reg_offset; 1503 uint32_t write_val; 1504 uint32_t read_val; 1505 }; 1506 1507 /** 1508 * struct hal_reg_write_fail_history - Hal layer history 1509 * of all the register write failures. 1510 * @index: index to add the new record 1511 * @record: array of all the records in history 1512 * 1513 * This structure holds the history of register write 1514 * failures at HAL layer. 1515 */ 1516 struct hal_reg_write_fail_history { 1517 qdf_atomic_t index; 1518 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 1519 }; 1520 #endif 1521 1522 /** 1523 * union hal_shadow_reg_cfg - Shadow register config 1524 * @addr: Place holder where shadow address is saved 1525 * @v2: shadow config v2 format 1526 * @v3: shadow config v3 format 1527 */ 1528 union hal_shadow_reg_cfg { 1529 uint32_t addr; 1530 struct pld_shadow_reg_v2_cfg v2; 1531 #ifdef CONFIG_SHADOW_V3 1532 struct pld_shadow_reg_v3_cfg v3; 1533 #endif 1534 }; 1535 1536 #ifdef HAL_RECORD_SUSPEND_WRITE 1537 #define HAL_SUSPEND_WRITE_HISTORY_MAX 256 1538 1539 struct hal_suspend_write_record { 1540 uint64_t ts; 1541 uint8_t ring_id; 1542 uit32_t value; 1543 uint32_t direct_wcount; 1544 }; 1545 1546 struct hal_suspend_write_history { 1547 qdf_atomic_t index; 1548 struct hal_suspend_write_record record[HAL_SUSPEND_WRITE_HISTORY_MAX]; 1549 1550 }; 1551 #endif 1552 1553 /** 1554 * struct hal_soc - HAL context to be used to access SRNG APIs 1555 * (currently used by data path and 1556 * transport (CE) modules) 1557 * @hif_handle: HIF handle to access HW registers 1558 * @qdf_dev: QDF device handle 1559 * @dev_base_addr: Device base address 1560 * @dev_base_addr_ce: Device base address for ce - qca5018 target 1561 * @dev_base_addr_cmem: Device base address for CMEM 1562 * @dev_base_addr_pmm: Device base address for PMM 1563 * @srng_list: HAL internal state for all SRNG rings 1564 * @shadow_rdptr_mem_vaddr: Remote pointer memory for HW/FW updates (virtual) 1565 * @shadow_rdptr_mem_paddr: Remote pointer memory for HW/FW updates (physical) 1566 * @shadow_wrptr_mem_vaddr: Shared memory for ring pointer updates from host 1567 * to FW (virtual) 1568 * @shadow_wrptr_mem_paddr: Shared memory for ring pointer updates from host 1569 * to FW (physical) 1570 * @reo_res_bitmap: REO blocking resource index 1571 * @index: 1572 * @target_type: 1573 * @version: 1574 * @shadow_config: shadow register configuration 1575 * @num_shadow_registers_configured: 1576 * @use_register_windowing: 1577 * @register_window: 1578 * @register_access_lock: 1579 * @static_window_map: Static window map configuration for multiple window write 1580 * @hw_srng_table: srng table 1581 * @hal_hw_reg_offset: 1582 * @ops: TXRX operations 1583 * @init_phase: Indicate srngs initialization 1584 * @stats: Hal level stats 1585 * @reg_wr_fail_hist: write failure history 1586 * @reg_write_queue: queue(array) to hold register writes 1587 * @reg_write_work: delayed work to be queued into workqueue 1588 * @reg_write_wq: workqueue for delayed register writes 1589 * @write_idx: write index used by caller to enqueue delayed work 1590 * @read_idx: read index used by worker thread to dequeue/write registers 1591 * @active_work_cnt: 1592 * @list_shadow_reg_config: array of generic regs mapped to 1593 * shadow regs 1594 * @num_generic_shadow_regs_configured: number of generic regs 1595 * mapped to shadow regs 1596 * @dmac_cmn_src_rxbuf_ring: flag to indicate cmn dmac rings in beryllium 1597 * @reo_qref: Reo queue ref table items 1598 */ 1599 struct hal_soc { 1600 struct hif_opaque_softc *hif_handle; 1601 qdf_device_t qdf_dev; 1602 void *dev_base_addr; 1603 void *dev_base_addr_ce; 1604 void *dev_base_addr_cmem; 1605 void *dev_base_addr_pmm; 1606 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 1607 1608 uint32_t *shadow_rdptr_mem_vaddr; 1609 qdf_dma_addr_t shadow_rdptr_mem_paddr; 1610 1611 uint32_t *shadow_wrptr_mem_vaddr; 1612 qdf_dma_addr_t shadow_wrptr_mem_paddr; 1613 1614 uint8_t reo_res_bitmap; 1615 uint8_t index; 1616 uint32_t target_type; 1617 uint32_t version; 1618 1619 union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS]; 1620 int num_shadow_registers_configured; 1621 bool use_register_windowing; 1622 uint32_t register_window; 1623 qdf_spinlock_t register_access_lock; 1624 1625 bool static_window_map; 1626 1627 struct hal_hw_srng_config *hw_srng_table; 1628 int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX]; 1629 struct hal_hw_txrx_ops *ops; 1630 1631 bool init_phase; 1632 struct hal_soc_stats stats; 1633 #ifdef ENABLE_HAL_REG_WR_HISTORY 1634 struct hal_reg_write_fail_history *reg_wr_fail_hist; 1635 #endif 1636 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1637 struct hal_reg_write_q_elem *reg_write_queue; 1638 qdf_work_t reg_write_work; 1639 qdf_workqueue_t *reg_write_wq; 1640 qdf_atomic_t write_idx; 1641 uint32_t read_idx; 1642 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */ 1643 qdf_atomic_t active_work_cnt; 1644 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1645 struct shadow_reg_config 1646 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; 1647 int num_generic_shadow_regs_configured; 1648 #endif 1649 bool dmac_cmn_src_rxbuf_ring; 1650 struct reo_queue_ref_table reo_qref; 1651 }; 1652 1653 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1654 /** 1655 * hal_delayed_reg_write() - delayed register write 1656 * @hal_soc: HAL soc handle 1657 * @srng: hal srng 1658 * @addr: iomem address 1659 * @value: value to be written 1660 * 1661 * Return: none 1662 */ 1663 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1664 struct hal_srng *srng, 1665 void __iomem *addr, 1666 uint32_t value); 1667 #endif 1668 1669 void hal_qca6750_attach(struct hal_soc *hal_soc); 1670 void hal_qca6490_attach(struct hal_soc *hal_soc); 1671 void hal_qca6390_attach(struct hal_soc *hal_soc); 1672 void hal_qca6290_attach(struct hal_soc *hal_soc); 1673 void hal_qca8074_attach(struct hal_soc *hal_soc); 1674 1675 /** 1676 * hal_kiwi_attach() - Attach kiwi target specific hal_soc ops, 1677 * offset and srng table 1678 * @hal_soc: HAL soc 1679 */ 1680 void hal_kiwi_attach(struct hal_soc *hal_soc); 1681 1682 void hal_qcn9224v2_attach(struct hal_soc *hal_soc); 1683 void hal_wcn6450_attach(struct hal_soc *hal_soc); 1684 1685 /** 1686 * hal_soc_to_hal_soc_handle() - API to convert hal_soc to opaque 1687 * hal_soc_handle_t type 1688 * @hal_soc: hal_soc type 1689 * 1690 * Return: hal_soc_handle_t type 1691 */ 1692 static inline 1693 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 1694 { 1695 return (hal_soc_handle_t)hal_soc; 1696 } 1697 1698 /** 1699 * hal_srng_to_hal_ring_handle() - API to convert hal_srng to opaque 1700 * hal_ring handle_t type 1701 * @hal_srng: hal_srng type 1702 * 1703 * Return: hal_ring_handle_t type 1704 */ 1705 static inline 1706 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 1707 { 1708 return (hal_ring_handle_t)hal_srng; 1709 } 1710 1711 /** 1712 * hal_ring_handle_to_hal_srng() - API to convert hal_ring_handle_t to hal_srng 1713 * @hal_ring: hal_ring_handle_t type 1714 * 1715 * Return: hal_srng pointer type 1716 */ 1717 static inline 1718 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 1719 { 1720 return (struct hal_srng *)hal_ring; 1721 } 1722 1723 /* Size of REO queue reference table in Host 1724 * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference) 1725 * = 278528 bytes 1726 */ 1727 #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528 1728 /* Calculated based on 512 MLO peers */ 1729 #define REO_QUEUE_REF_ML_TABLE_SIZE 69632 1730 #define HAL_ML_PEER_ID_START 0x2000 1731 #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START) 1732 1733 /* 1734 * REO2PPE destination indication 1735 */ 1736 #define REO2PPE_DST_IND 6 1737 #define REO2PPE_DST_RING 11 1738 #define REO2PPE_RULE_FAIL_FB 0x2000 1739 1740 /** 1741 * enum hal_pkt_type - Type of packet type reported by HW 1742 * @HAL_DOT11A: 802.11a PPDU type 1743 * @HAL_DOT11B: 802.11b PPDU type 1744 * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type 1745 * @HAL_DOT11AC: 802.11ac PPDU type 1746 * @HAL_DOT11AX: 802.11ax PPDU type 1747 * @HAL_DOT11BA: 802.11ba (WUR) PPDU type 1748 * @HAL_DOT11BE: 802.11be PPDU type 1749 * @HAL_DOT11AZ: 802.11az (ranging) PPDU type 1750 * @HAL_DOT11N_GF: 802.11n Green Field PPDU type 1751 * @HAL_DOT11_MAX: Maximum enumeration 1752 * 1753 * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data) 1754 * or WBM2SW ring entry's descriptor (TX data completion) 1755 */ 1756 enum hal_pkt_type { 1757 HAL_DOT11A = 0, 1758 HAL_DOT11B = 1, 1759 HAL_DOT11N_MM = 2, 1760 HAL_DOT11AC = 3, 1761 HAL_DOT11AX = 4, 1762 HAL_DOT11BA = 5, 1763 HAL_DOT11BE = 6, 1764 HAL_DOT11AZ = 7, 1765 HAL_DOT11N_GF = 8, 1766 HAL_DOT11_MAX, 1767 }; 1768 1769 #endif /* _HAL_INTERNAL_H_ */ 1770