1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_INTERNAL_H_ 21 #define _HAL_INTERNAL_H_ 22 23 #include "qdf_types.h" 24 #include "qdf_atomic.h" 25 #include "qdf_lock.h" 26 #include "qdf_mem.h" 27 #include "qdf_nbuf.h" 28 #include "pld_common.h" 29 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 30 #include "qdf_defer.h" 31 #include "qdf_timer.h" 32 #endif 33 34 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 35 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 36 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 37 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params) 38 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 39 40 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 41 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 43 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 44 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 45 46 #ifdef ENABLE_VERBOSE_DEBUG 47 extern bool is_hal_verbose_debug_enabled; 48 #define hal_verbose_debug(params...) \ 49 if (unlikely(is_hal_verbose_debug_enabled)) \ 50 do {\ 51 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 52 } while (0) 53 #define hal_verbose_hex_dump(params...) \ 54 if (unlikely(is_hal_verbose_debug_enabled)) \ 55 do {\ 56 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 57 QDF_TRACE_LEVEL_DEBUG, \ 58 params); \ 59 } while (0) 60 #else 61 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 62 #define hal_verbose_hex_dump(params...) \ 63 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 64 params) 65 #endif 66 67 /* 68 * Given the offset of a field in bytes, returns uint8_t * 69 */ 70 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 71 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 72 73 /* 74 * Given the offset of a field in bytes, returns uint32_t * 75 */ 76 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 77 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 78 79 /* 80 * Given the offset of a field in bytes, returns uint64_t * 81 */ 82 #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \ 83 (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3)) 84 85 #define _HAL_MS(_word, _mask, _shift) \ 86 (((_word) & (_mask)) >> (_shift)) 87 88 /* 89 * Get number of QWORDS possible for num. 90 * Its the caller's duty to make sure num is a multiple of QWORD (8) 91 */ 92 #define HAL_GET_NUM_QWORDS(num) ((num) >> 3) 93 94 /* 95 * Get number of DWORDS possible for num. 96 * Its the caller's duty to make sure num is a multiple of DWORD (8) 97 */ 98 #define HAL_GET_NUM_DWORDS(num) ((num) >> 2) 99 100 struct hal_hw_cc_config { 101 uint32_t lut_base_addr_31_0; 102 uint32_t cc_global_en:1, 103 page_4k_align:1, 104 cookie_offset_msb:5, 105 cookie_page_msb:5, 106 lut_base_addr_39_32:8, 107 wbm2sw6_cc_en:1, 108 wbm2sw5_cc_en:1, 109 wbm2sw4_cc_en:1, 110 wbm2sw3_cc_en:1, 111 wbm2sw2_cc_en:1, 112 wbm2sw1_cc_en:1, 113 wbm2sw0_cc_en:1, 114 wbm2fw_cc_en:1, 115 error_path_cookie_conv_en:1, 116 release_path_cookie_conv_en:1, 117 reserved:2; 118 }; 119 120 /* 121 * dp_hal_soc - opaque handle for DP HAL soc 122 */ 123 struct hal_soc_handle; 124 typedef struct hal_soc_handle *hal_soc_handle_t; 125 126 /** 127 * hal_ring_desc - opaque handle for DP ring descriptor 128 */ 129 struct hal_ring_desc; 130 typedef struct hal_ring_desc *hal_ring_desc_t; 131 132 /** 133 * hal_link_desc - opaque handle for DP link descriptor 134 */ 135 struct hal_link_desc; 136 typedef struct hal_link_desc *hal_link_desc_t; 137 138 /** 139 * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor 140 */ 141 struct hal_rxdma_desc; 142 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 143 144 /** 145 * hal_buff_addrinfo - opaque handle for DP buffer address info 146 */ 147 struct hal_buff_addrinfo; 148 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 149 150 /** 151 * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info 152 */ 153 struct hal_rx_mon_desc_info; 154 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 155 156 struct hal_buf_info; 157 typedef struct hal_buf_info *hal_buf_info_t; 158 159 struct rx_msdu_desc_info; 160 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t; 161 162 /** 163 * Opaque handler for PPE VP config. 164 */ 165 union hal_tx_ppe_vp_config; 166 union hal_tx_cmn_config_ppe; 167 union hal_tx_bank_config; 168 union hal_tx_ppe_idx_map_config; 169 170 /* TBD: This should be movded to shared HW header file */ 171 enum hal_srng_ring_id { 172 /* UMAC rings */ 173 HAL_SRNG_REO2SW0 = 0, 174 HAL_SRNG_REO2SW1 = 1, 175 HAL_SRNG_REO2SW2 = 2, 176 HAL_SRNG_REO2SW3 = 3, 177 HAL_SRNG_REO2SW4 = 4, 178 HAL_SRNG_REO2SW5 = 5, 179 HAL_SRNG_REO2SW6 = 6, 180 HAL_SRNG_REO2SW7 = 7, 181 HAL_SRNG_REO2SW8 = 8, 182 HAL_SRNG_REO2TCL = 9, 183 HAL_SRNG_REO2PPE = 10, 184 /* 11-15 unused */ 185 HAL_SRNG_SW2REO = 16, 186 HAL_SRNG_SW2REO1 = 17, 187 HAL_SRNG_SW2REO2 = 18, 188 HAL_SRNG_SW2REO3 = 19, 189 HAL_SRNG_REO_CMD = 20, 190 HAL_SRNG_REO_STATUS = 21, 191 /* 22-23 unused */ 192 HAL_SRNG_SW2TCL1 = 24, 193 HAL_SRNG_SW2TCL2 = 25, 194 HAL_SRNG_SW2TCL3 = 26, 195 HAL_SRNG_SW2TCL4 = 27, 196 HAL_SRNG_SW2TCL5 = 28, 197 HAL_SRNG_SW2TCL6 = 29, 198 HAL_SRNG_PPE2TCL1 = 30, 199 /* 31-39 unused */ 200 HAL_SRNG_SW2TCL_CMD = 40, 201 HAL_SRNG_TCL_STATUS = 41, 202 HAL_SRNG_SW2TCL_CREDIT = 42, 203 /* 43-63 unused */ 204 HAL_SRNG_CE_0_SRC = 64, 205 HAL_SRNG_CE_1_SRC = 65, 206 HAL_SRNG_CE_2_SRC = 66, 207 HAL_SRNG_CE_3_SRC = 67, 208 HAL_SRNG_CE_4_SRC = 68, 209 HAL_SRNG_CE_5_SRC = 69, 210 HAL_SRNG_CE_6_SRC = 70, 211 HAL_SRNG_CE_7_SRC = 71, 212 HAL_SRNG_CE_8_SRC = 72, 213 HAL_SRNG_CE_9_SRC = 73, 214 HAL_SRNG_CE_10_SRC = 74, 215 HAL_SRNG_CE_11_SRC = 75, 216 HAL_SRNG_CE_12_SRC = 76, 217 HAL_SRNG_CE_13_SRC = 77, 218 HAL_SRNG_CE_14_SRC = 78, 219 HAL_SRNG_CE_15_SRC = 79, 220 /* 80 */ 221 HAL_SRNG_CE_0_DST = 81, 222 HAL_SRNG_CE_1_DST = 82, 223 HAL_SRNG_CE_2_DST = 83, 224 HAL_SRNG_CE_3_DST = 84, 225 HAL_SRNG_CE_4_DST = 85, 226 HAL_SRNG_CE_5_DST = 86, 227 HAL_SRNG_CE_6_DST = 87, 228 HAL_SRNG_CE_7_DST = 89, 229 HAL_SRNG_CE_8_DST = 90, 230 HAL_SRNG_CE_9_DST = 91, 231 HAL_SRNG_CE_10_DST = 92, 232 HAL_SRNG_CE_11_DST = 93, 233 HAL_SRNG_CE_12_DST = 94, 234 HAL_SRNG_CE_13_DST = 95, 235 HAL_SRNG_CE_14_DST = 96, 236 HAL_SRNG_CE_15_DST = 97, 237 /* 98-99 unused */ 238 HAL_SRNG_CE_0_DST_STATUS = 100, 239 HAL_SRNG_CE_1_DST_STATUS = 101, 240 HAL_SRNG_CE_2_DST_STATUS = 102, 241 HAL_SRNG_CE_3_DST_STATUS = 103, 242 HAL_SRNG_CE_4_DST_STATUS = 104, 243 HAL_SRNG_CE_5_DST_STATUS = 105, 244 HAL_SRNG_CE_6_DST_STATUS = 106, 245 HAL_SRNG_CE_7_DST_STATUS = 107, 246 HAL_SRNG_CE_8_DST_STATUS = 108, 247 HAL_SRNG_CE_9_DST_STATUS = 109, 248 HAL_SRNG_CE_10_DST_STATUS = 110, 249 HAL_SRNG_CE_11_DST_STATUS = 111, 250 HAL_SRNG_CE_12_DST_STATUS = 112, 251 HAL_SRNG_CE_13_DST_STATUS = 113, 252 HAL_SRNG_CE_14_DST_STATUS = 114, 253 HAL_SRNG_CE_15_DST_STATUS = 115, 254 /* 116-119 unused */ 255 HAL_SRNG_WBM_IDLE_LINK = 120, 256 HAL_SRNG_WBM_SW_RELEASE = 121, 257 HAL_SRNG_WBM_SW1_RELEASE = 122, 258 HAL_SRNG_WBM_PPE_RELEASE = 123, 259 /* 124-127 unused */ 260 HAL_SRNG_WBM2SW0_RELEASE = 128, 261 HAL_SRNG_WBM2SW1_RELEASE = 129, 262 HAL_SRNG_WBM2SW2_RELEASE = 130, 263 HAL_SRNG_WBM2SW3_RELEASE = 131, 264 HAL_SRNG_WBM2SW4_RELEASE = 132, 265 HAL_SRNG_WBM2SW5_RELEASE = 133, 266 HAL_SRNG_WBM2SW6_RELEASE = 134, 267 HAL_SRNG_WBM_ERROR_RELEASE = 135, 268 /* 136-158 unused */ 269 HAL_SRNG_UMAC_ID_END = 159, 270 /* Common DMAC rings shared by all LMACs */ 271 HAL_SRNG_SW2RXDMA_BUF0 = 160, 272 HAL_SRNG_SW2RXDMA_BUF1 = 161, 273 HAL_SRNG_SW2RXDMA_BUF2 = 162, 274 /* 163-167 unused */ 275 HAL_SRNG_SW2RXMON_BUF0 = 168, 276 /* 169-175 unused */ 277 /* 177-183 unused */ 278 HAL_SRNG_DMAC_CMN_ID_END = 183, 279 /* LMAC rings - The following set will be replicated for each LMAC */ 280 HAL_SRNG_LMAC1_ID_START = 184, 281 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 282 #ifdef IPA_OFFLOAD 283 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1, 284 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2, 285 #ifdef IPA_WDI3_VLAN_SUPPORT 286 HAL_SRNG_WMAC1_SW2RXDMA0_BUF3, 287 #endif 288 #endif 289 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 290 #ifdef FEATURE_DIRECT_LINK 291 HAL_SRNG_WMAC1_RX_DIRECT_LINK_SW_REFILL_RING, 292 #endif 293 HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 294 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF, 295 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 296 HAL_SRNG_WMAC1_RXDMA2SW0, 297 HAL_SRNG_WMAC1_RXDMA2SW1, 298 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1, 299 HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 300 #ifdef WLAN_FEATURE_CIF_CFR 301 HAL_SRNG_WIFI_POS_SRC_DMA_RING, 302 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 303 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 304 #else 305 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 306 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 307 #endif 308 HAL_SRNG_WMAC1_TXMON2SW0, 309 HAL_SRNG_SW2TXMON_BUF0, 310 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2), 311 }; 312 313 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 314 #define HAL_MAX_LMACS 3 315 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 316 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 317 318 #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS) 319 320 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ 321 enum hal_ring_type { 322 REO_DST = 0, 323 REO_EXCEPTION = 1, 324 REO_REINJECT = 2, 325 REO_CMD = 3, 326 REO_STATUS = 4, 327 TCL_DATA = 5, 328 TCL_CMD_CREDIT = 6, 329 TCL_STATUS = 7, 330 CE_SRC = 8, 331 CE_DST = 9, 332 CE_DST_STATUS = 10, 333 WBM_IDLE_LINK = 11, 334 SW2WBM_RELEASE = 12, 335 WBM2SW_RELEASE = 13, 336 RXDMA_BUF = 14, 337 RXDMA_DST = 15, 338 RXDMA_MONITOR_BUF = 16, 339 RXDMA_MONITOR_STATUS = 17, 340 RXDMA_MONITOR_DST = 18, 341 RXDMA_MONITOR_DESC = 19, 342 DIR_BUF_RX_DMA_SRC = 20, 343 #ifdef WLAN_FEATURE_CIF_CFR 344 WIFI_POS_SRC, 345 #endif 346 REO2PPE, 347 PPE2TCL, 348 PPE_RELEASE, 349 TX_MONITOR_BUF, 350 TX_MONITOR_DST, 351 SW2RXDMA_NEW, 352 MAX_RING_TYPES 353 }; 354 355 enum SRNG_REGISTERS { 356 DST_HP = 0, 357 DST_TP, 358 DST_ID, 359 DST_MISC, 360 DST_HP_ADDR_LSB, 361 DST_HP_ADDR_MSB, 362 DST_MSI1_BASE_LSB, 363 DST_MSI1_BASE_MSB, 364 DST_MSI1_DATA, 365 #ifdef CONFIG_BERYLLIUM 366 DST_MSI2_BASE_LSB, 367 DST_MSI2_BASE_MSB, 368 DST_MSI2_DATA, 369 #endif 370 DST_BASE_LSB, 371 DST_BASE_MSB, 372 DST_PRODUCER_INT_SETUP, 373 #ifdef CONFIG_BERYLLIUM 374 DST_PRODUCER_INT2_SETUP, 375 #endif 376 377 SRC_HP, 378 SRC_TP, 379 SRC_ID, 380 SRC_MISC, 381 SRC_TP_ADDR_LSB, 382 SRC_TP_ADDR_MSB, 383 SRC_MSI1_BASE_LSB, 384 SRC_MSI1_BASE_MSB, 385 SRC_MSI1_DATA, 386 SRC_BASE_LSB, 387 SRC_BASE_MSB, 388 SRC_CONSUMER_INT_SETUP_IX0, 389 SRC_CONSUMER_INT_SETUP_IX1, 390 #ifdef DP_UMAC_HW_RESET_SUPPORT 391 SRC_CONSUMER_PREFETCH_TIMER, 392 #endif 393 SRNG_REGISTER_MAX, 394 }; 395 396 enum hal_srng_dir { 397 HAL_SRNG_SRC_RING, 398 HAL_SRNG_DST_RING 399 }; 400 401 /** 402 * enum hal_reo_remap_reg - REO remap registers 403 * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0 404 * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1 405 * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2 406 * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3 407 */ 408 enum hal_reo_remap_reg { 409 HAL_REO_REMAP_REG_IX0, 410 HAL_REO_REMAP_REG_IX1, 411 HAL_REO_REMAP_REG_IX2, 412 HAL_REO_REMAP_REG_IX3 413 }; 414 415 /* Lock wrappers for SRNG */ 416 #define hal_srng_lock_t qdf_spinlock_t 417 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 418 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 419 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock) 420 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 421 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 422 423 struct hal_soc; 424 425 /** 426 * dp_hal_ring - opaque handle for DP HAL SRNG 427 */ 428 struct hal_ring_handle; 429 typedef struct hal_ring_handle *hal_ring_handle_t; 430 431 #define MAX_SRNG_REG_GROUPS 2 432 433 /* Hal Srng bit mask 434 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 435 */ 436 #define HAL_SRNG_FLUSH_EVENT BIT(0) 437 438 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 439 440 /** 441 * struct hal_reg_write_q_elem - delayed register write queue element 442 * @srng: hal_srng queued for a delayed write 443 * @addr: iomem address of the register 444 * @enqueue_val: register value at the time of delayed write enqueue 445 * @dequeue_val: register value at the time of delayed write dequeue 446 * @valid: whether this entry is valid or not 447 * @enqueue_time: enqueue time (qdf_log_timestamp) 448 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 449 * @dequeue_time: dequeue time (qdf_log_timestamp) 450 * @cpu_id: record cpuid when schedule work 451 */ 452 struct hal_reg_write_q_elem { 453 struct hal_srng *srng; 454 void __iomem *addr; 455 uint32_t enqueue_val; 456 uint32_t dequeue_val; 457 uint8_t valid; 458 qdf_time_t enqueue_time; 459 qdf_time_t work_scheduled_time; 460 qdf_time_t dequeue_time; 461 int cpu_id; 462 }; 463 464 /** 465 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 466 * @enqueues: writes enqueued to delayed work 467 * @dequeues: writes dequeued from delayed work (not written yet) 468 * @coalesces: writes not enqueued since srng is already queued up 469 * @direct: writes not enqueued and written to register directly 470 * @dequeue_delay: dequeue operation be delayed 471 */ 472 struct hal_reg_write_srng_stats { 473 uint32_t enqueues; 474 uint32_t dequeues; 475 uint32_t coalesces; 476 uint32_t direct; 477 uint32_t dequeue_delay; 478 }; 479 480 /** 481 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 482 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 483 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 484 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 485 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 486 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 487 */ 488 enum hal_reg_sched_delay { 489 REG_WRITE_SCHED_DELAY_SUB_100us, 490 REG_WRITE_SCHED_DELAY_SUB_1000us, 491 REG_WRITE_SCHED_DELAY_SUB_5000us, 492 REG_WRITE_SCHED_DELAY_GT_5000us, 493 REG_WRITE_SCHED_DELAY_HIST_MAX, 494 }; 495 496 /** 497 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 498 * @enqueues: writes enqueued to delayed work 499 * @dequeues: writes dequeued from delayed work (not written yet) 500 * @coalesces: writes not enqueued since srng is already queued up 501 * @direct: writes not enqueud and writted to register directly 502 * @prevent_l1_fails: prevent l1 API failed 503 * @q_depth: current queue depth in delayed register write queue 504 * @max_q_depth: maximum queue for delayed register write queue 505 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 506 * @dequeue_delay: dequeue operation be delayed 507 */ 508 struct hal_reg_write_soc_stats { 509 qdf_atomic_t enqueues; 510 uint32_t dequeues; 511 qdf_atomic_t coalesces; 512 qdf_atomic_t direct; 513 uint32_t prevent_l1_fails; 514 qdf_atomic_t q_depth; 515 uint32_t max_q_depth; 516 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 517 uint32_t dequeue_delay; 518 }; 519 #endif 520 521 struct hal_offload_info { 522 uint8_t lro_eligible; 523 uint8_t tcp_proto; 524 uint8_t tcp_pure_ack; 525 uint8_t ipv6_proto; 526 uint8_t tcp_offset; 527 uint16_t tcp_csum; 528 uint16_t tcp_win; 529 uint32_t tcp_seq_num; 530 uint32_t tcp_ack_num; 531 uint32_t flow_id; 532 }; 533 534 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 535 /** 536 * enum hal_srng_high_wm_bin - BIN for SRNG high watermark 537 * @HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT: <50% SRNG entries used 538 * @HAL_SRNG_HIGH_WM_BIN_50_to_60: 50-60% SRNG entries used 539 * @HAL_SRNG_HIGH_WM_BIN_60_to_70: 60-70% SRNG entries used 540 * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used 541 * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used 542 * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used 543 */ 544 enum hal_srng_high_wm_bin { 545 HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT, 546 HAL_SRNG_HIGH_WM_BIN_50_to_60, 547 HAL_SRNG_HIGH_WM_BIN_60_to_70, 548 HAL_SRNG_HIGH_WM_BIN_70_to_80, 549 HAL_SRNG_HIGH_WM_BIN_80_to_90, 550 HAL_SRNG_HIGH_WM_BIN_90_to_100, 551 HAL_SRNG_HIGH_WM_BIN_MAX, 552 }; 553 554 /** 555 * struct hal_srng_high_wm_info - SRNG usage high watermark info 556 * @val: highest number of entries used in SRNG 557 * @timestamp: Timestamp when the max num entries were in used for a SRNG 558 * @bin_thresh: threshold for each bins 559 * @bins: Bins for srng usage 560 */ 561 struct hal_srng_high_wm_info { 562 uint32_t val; 563 uint64_t timestamp; 564 uint32_t bin_thresh[HAL_SRNG_HIGH_WM_BIN_MAX]; 565 uint32_t bins[HAL_SRNG_HIGH_WM_BIN_MAX]; 566 }; 567 #endif 568 569 #define DEFAULT_TSF_ID 1 570 571 /** 572 * enum hal_scratch_reg_enum - Enum to indicate scratch register values 573 * @PMM_QTIMER_GLOBAL_OFFSET_LO_US - QTIMER GLOBAL OFFSET LOW 574 * @PMM_QTIMER_GLOBAL_OFFSET_HI_US - QTIMER GLOBAL OFFSET HIGH 575 * @PMM_MAC0_TSF1_OFFSET_LO_US - MAC0 TSF1 OFFSET LOW 576 * @PMM_MAC0_TSF1_OFFSET_HI_US - MAC0 TSF1 OFFSET HIGH 577 * @PMM_MAC0_TSF2_OFFSET_LO_US - MAC0 TSF2 OFFSET LOW 578 * @PMM_MAC0_TSF2_OFFSET_HI_US - MAC0 TSF2 OFFSET HIGH 579 * @PMM_MAC1_TSF1_OFFSET_LO_US - MAC1 TSF1 OFFSET LOW 580 * @PMM_MAC1_TSF1_OFFSET_HI_US - MAC1 TSF1 OFFSET HIGH 581 * @PMM_MAC1_TSF2_OFFSET_LO_US - MAC1 TSF2 OFFSET LOW 582 * @PMM_MAC1_TSF2_OFFSET_HI_US - MAC1 TSF2 OFFSET HIGH 583 * @PMM_MLO_OFFSET_LO_US - MLO OFFSET LOW 584 * @PMM_MLO_OFFSET_HI_US - MLO OFFSET HIGH 585 * @PMM_TQM_CLOCK_OFFSET_LO_US - TQM CLOCK OFFSET LOW 586 * @PMM_TQM_CLOCK_OFFSET_HI_US - TQM CLOCK OFFSET HIGH 587 * @PMM_Q6_CRASH_REASON - Q6 CRASH REASON 588 * @PMM_SCRATCH_TWT_OFFSET - TWT OFFSET 589 * @PMM_PMM_REG_MAX - Max PMM REG value 590 */ 591 enum hal_scratch_reg_enum { 592 PMM_QTIMER_GLOBAL_OFFSET_LO_US, 593 PMM_QTIMER_GLOBAL_OFFSET_HI_US, 594 PMM_MAC0_TSF1_OFFSET_LO_US, 595 PMM_MAC0_TSF1_OFFSET_HI_US, 596 PMM_MAC0_TSF2_OFFSET_LO_US, 597 PMM_MAC0_TSF2_OFFSET_HI_US, 598 PMM_MAC1_TSF1_OFFSET_LO_US, 599 PMM_MAC1_TSF1_OFFSET_HI_US, 600 PMM_MAC1_TSF2_OFFSET_LO_US, 601 PMM_MAC1_TSF2_OFFSET_HI_US, 602 PMM_MLO_OFFSET_LO_US, 603 PMM_MLO_OFFSET_HI_US, 604 PMM_TQM_CLOCK_OFFSET_LO_US, 605 PMM_TQM_CLOCK_OFFSET_HI_US, 606 PMM_Q6_CRASH_REASON, 607 PMM_SCRATCH_TWT_OFFSET, 608 PMM_PMM_REG_MAX 609 }; 610 611 /** 612 * hal_get_tsf_enum(): API to get the enum corresponding to the mac and tsf id 613 * 614 * @tsf_id: tsf id 615 * @mac_id: mac id 616 * @enum_lo: Pointer to update low scratch register 617 * @enum_hi: Pointer to update hi scratch register 618 * 619 * Return: void 620 */ 621 static inline void 622 hal_get_tsf_enum(uint32_t tsf_id, uint32_t mac_id, 623 enum hal_scratch_reg_enum *tsf_enum_low, 624 enum hal_scratch_reg_enum *tsf_enum_hi) 625 { 626 if (mac_id == 0) { 627 if (tsf_id == 0) { 628 *tsf_enum_low = PMM_MAC0_TSF1_OFFSET_LO_US; 629 *tsf_enum_hi = PMM_MAC0_TSF1_OFFSET_HI_US; 630 } else if (tsf_id == 1) { 631 *tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US; 632 *tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US; 633 } 634 } else if (mac_id == 1) { 635 if (tsf_id == 0) { 636 *tsf_enum_low = PMM_MAC1_TSF1_OFFSET_LO_US; 637 *tsf_enum_hi = PMM_MAC1_TSF1_OFFSET_HI_US; 638 } else if (tsf_id == 1) { 639 *tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US; 640 *tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US; 641 } 642 } 643 } 644 645 /* Common SRNG ring structure for source and destination rings */ 646 struct hal_srng { 647 /* Unique SRNG ring ID */ 648 uint8_t ring_id; 649 650 /* Ring initialization done */ 651 uint8_t initialized; 652 653 /* Interrupt/MSI value assigned to this ring */ 654 int irq; 655 656 /* Physical base address of the ring */ 657 qdf_dma_addr_t ring_base_paddr; 658 659 /* Virtual base address of the ring */ 660 uint32_t *ring_base_vaddr; 661 662 /* virtual address end */ 663 uint32_t *ring_vaddr_end; 664 665 /* Number of entries in ring */ 666 uint32_t num_entries; 667 668 /* Ring size */ 669 uint32_t ring_size; 670 671 /* Ring size mask */ 672 uint32_t ring_size_mask; 673 674 /* Size of ring entry */ 675 uint32_t entry_size; 676 677 /* Interrupt timer threshold – in micro seconds */ 678 uint32_t intr_timer_thres_us; 679 680 /* Interrupt batch counter threshold – in number of ring entries */ 681 uint32_t intr_batch_cntr_thres_entries; 682 683 /* Applicable only for CE dest ring */ 684 uint32_t prefetch_timer; 685 686 /* MSI Address */ 687 qdf_dma_addr_t msi_addr; 688 689 /* MSI data */ 690 uint32_t msi_data; 691 692 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 693 /* MSI2 Address */ 694 qdf_dma_addr_t msi2_addr; 695 696 /* MSI2 data */ 697 uint32_t msi2_data; 698 #endif 699 700 /* Misc flags */ 701 uint32_t flags; 702 703 /* Lock for serializing ring index updates */ 704 hal_srng_lock_t lock; 705 706 /* Start offset of SRNG register groups for this ring 707 * TBD: See if this is required - register address can be derived 708 * from ring ID 709 */ 710 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 711 712 /* Ring type/name */ 713 enum hal_ring_type ring_type; 714 715 /* Source or Destination ring */ 716 enum hal_srng_dir ring_dir; 717 718 union { 719 struct { 720 /* SW tail pointer */ 721 uint32_t tp; 722 723 /* Shadow head pointer location to be updated by HW */ 724 uint32_t *hp_addr; 725 726 /* Cached head pointer */ 727 uint32_t cached_hp; 728 729 /* Tail pointer location to be updated by SW – This 730 * will be a register address and need not be 731 * accessed through SW structure */ 732 uint32_t *tp_addr; 733 734 /* Current SW loop cnt */ 735 uint32_t loop_cnt; 736 737 /* max transfer size */ 738 uint16_t max_buffer_length; 739 740 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 741 /* near full IRQ supported */ 742 uint16_t nf_irq_support; 743 744 /* High threshold for Near full IRQ */ 745 uint16_t high_thresh; 746 #endif 747 } dst_ring; 748 749 struct { 750 /* SW head pointer */ 751 uint32_t hp; 752 753 /* SW reap head pointer */ 754 uint32_t reap_hp; 755 756 /* Shadow tail pointer location to be updated by HW */ 757 uint32_t *tp_addr; 758 759 /* Cached tail pointer */ 760 uint32_t cached_tp; 761 762 /* Head pointer location to be updated by SW – This 763 * will be a register address and need not be accessed 764 * through SW structure */ 765 uint32_t *hp_addr; 766 767 /* Low threshold – in number of ring entries */ 768 uint32_t low_threshold; 769 } src_ring; 770 } u; 771 772 struct hal_soc *hal_soc; 773 774 /* Number of times hp/tp updated in runtime resume */ 775 uint32_t flush_count; 776 /* hal srng event flag*/ 777 unsigned long srng_event; 778 /* last flushed time stamp */ 779 uint64_t last_flush_ts; 780 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 781 /* last ring desc entry cleared */ 782 uint32_t last_desc_cleared; 783 #endif 784 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 785 /* flag to indicate whether srng is already queued for delayed write */ 786 uint8_t reg_write_in_progress; 787 /* last dequeue elem time stamp */ 788 qdf_time_t last_dequeue_time; 789 790 /* srng specific delayed write stats */ 791 struct hal_reg_write_srng_stats wstats; 792 #endif 793 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 794 struct hal_srng_high_wm_info high_wm; 795 #endif 796 }; 797 798 /* HW SRNG configuration table */ 799 struct hal_hw_srng_config { 800 int start_ring_id; 801 uint16_t max_rings; 802 uint16_t entry_size; 803 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 804 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 805 uint8_t lmac_ring; 806 enum hal_srng_dir ring_dir; 807 uint32_t max_size; 808 bool nf_irq_support; 809 bool dmac_cmn_ring; 810 }; 811 812 #define MAX_SHADOW_REGISTERS 40 813 #define MAX_GENERIC_SHADOW_REG 5 814 815 /** 816 * struct shadow_reg_config - Hal soc structure that contains 817 * the list of generic shadow registers 818 * @target_register: target reg offset 819 * @shadow_config_index: shadow config index in shadow config 820 * list sent to FW 821 * @va: virtual addr of shadow reg 822 * 823 * This structure holds the generic registers that are mapped to 824 * the shadow region and holds the mapping of the target 825 * register offset to shadow config index provided to FW during 826 * init 827 */ 828 struct shadow_reg_config { 829 uint32_t target_register; 830 int shadow_config_index; 831 uint64_t va; 832 }; 833 834 /* REO parameters to be passed to hal_reo_setup */ 835 struct hal_reo_params { 836 /** rx hash steering enabled or disabled */ 837 bool rx_hash_enabled; 838 /** reo remap 0 register */ 839 uint32_t remap0; 840 /** reo remap 1 register */ 841 uint32_t remap1; 842 /** reo remap 2 register */ 843 uint32_t remap2; 844 /** fragment destination ring */ 845 uint8_t frag_dst_ring; 846 /* Destination for alternate */ 847 uint8_t alt_dst_ind_0; 848 /** padding */ 849 uint8_t padding[2]; 850 }; 851 852 /** 853 * enum hal_reo_cmd_type: Enum for REO command type 854 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 855 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 856 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 857 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked 858 * earlier with a ‘REO_FLUSH_CACHE’ command 859 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 860 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 861 */ 862 enum hal_reo_cmd_type { 863 CMD_GET_QUEUE_STATS = 0, 864 CMD_FLUSH_QUEUE = 1, 865 CMD_FLUSH_CACHE = 2, 866 CMD_UNBLOCK_CACHE = 3, 867 CMD_FLUSH_TIMEOUT_LIST = 4, 868 CMD_UPDATE_RX_REO_QUEUE = 5 869 }; 870 871 /** 872 * enum hal_tx_mcast_mlo_reinject_notify 873 * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW 874 * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM 875 */ 876 enum hal_tx_mcast_mlo_reinject_notify { 877 HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0, 878 HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY, 879 }; 880 881 /** 882 * enum hal_tx_vdev_mismatch_notify 883 * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM 884 * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW 885 */ 886 enum hal_tx_vdev_mismatch_notify { 887 HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0, 888 HAL_TX_VDEV_MISMATCH_FW_NOTIFY, 889 }; 890 891 struct hal_rx_pkt_capture_flags { 892 uint8_t encrypt_type; 893 uint8_t fragment_flag; 894 uint8_t fcs_err; 895 uint32_t chan_freq; 896 uint32_t rssi_comb; 897 uint64_t tsft; 898 }; 899 900 struct hal_hw_txrx_ops { 901 /* init and setup */ 902 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 903 struct hal_srng *srng, bool idle_check, 904 uint32_t idx); 905 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 906 struct hal_srng *srng, bool idle_check, 907 uint32_t idx); 908 909 void (*hal_srng_hw_disable)(struct hal_soc *hal, 910 struct hal_srng *srng); 911 void (*hal_get_hw_hptp)(struct hal_soc *hal, 912 hal_ring_handle_t hal_ring_hdl, 913 uint32_t *headp, uint32_t *tailp, 914 uint8_t ring_type); 915 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams, 916 int qref_reset); 917 void (*hal_setup_link_idle_list)( 918 struct hal_soc *hal_soc, 919 qdf_dma_addr_t scatter_bufs_base_paddr[], 920 void *scatter_bufs_base_vaddr[], 921 uint32_t num_scatter_bufs, 922 uint32_t scatter_buf_size, 923 uint32_t last_buf_end_offset, 924 uint32_t num_entries); 925 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 926 qdf_iomem_t addr); 927 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 928 uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc); 929 void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid, 930 uint32_t ba_window_size, 931 uint32_t start_seq, void *hw_qdesc_vaddr, 932 qdf_dma_addr_t hw_qdesc_paddr, 933 int pn_type, uint8_t vdev_stats_id); 934 uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg, 935 uint8_t *ix0_map); 936 937 /* tx */ 938 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 939 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 940 uint8_t id); 941 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 942 uint8_t id, 943 uint8_t dscp); 944 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 945 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 946 uint8_t pool_id, uint32_t desc_id, 947 uint8_t type); 948 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 949 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 950 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 951 void (*hal_tx_comp_get_status)(void *desc, void *ts, 952 struct hal_soc *hal); 953 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 954 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 955 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 956 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 957 hal_ring_handle_t hal_ring_hdl); 958 uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc); 959 uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)( 960 hal_soc_handle_t hal_soc_hdl); 961 962 void (*hal_reo_config_reo2ppe_dest_info)(hal_soc_handle_t hal_soc_hdl); 963 964 void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl, 965 union hal_tx_cmn_config_ppe *cmn_cfg); 966 void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl, 967 union hal_tx_ppe_vp_config *vp_cfg, 968 int ppe_vp_idx); 969 void (*hal_ppeds_cfg_ast_override_map_reg)(hal_soc_handle_t hal_soc_hdl, 970 uint8_t idx, union hal_tx_ppe_idx_map_config *ppeds_idx_map); 971 void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 972 uint32_t val, 973 uint8_t map_no); 974 void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 975 uint8_t pri, 976 uint8_t tid); 977 void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl); 978 void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl, 979 bool value, uint8_t ppe_vp_idx); 980 void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl, 981 hal_ring_handle_t hal_ring_hdl, 982 uint8_t rbm_id); 983 984 /* rx */ 985 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 986 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 987 struct mon_rx_status *rs); 988 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 989 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 990 void *ppdu_info_handle); 991 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 992 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 993 uint8_t dbg_level); 994 uint32_t (*hal_get_link_desc_size)(void); 995 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 996 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 997 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 998 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 999 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 1000 void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b, 1001 void *h); 1002 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 1003 void *ppdu_info, 1004 hal_soc_handle_t hal_soc_hdl, 1005 qdf_nbuf_t nbuf); 1006 1007 void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc, 1008 struct hal_buf_info *buf_info); 1009 1010 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 1011 void *wbm_er_info); 1012 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 1013 uint8_t dbg_level); 1014 1015 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 1016 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 1017 uint8_t id); 1018 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 1019 1020 /* rx */ 1021 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 1022 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 1023 uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf); 1024 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 1025 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 1026 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 1027 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 1028 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 1029 void (*hal_rx_print_pn)(uint8_t *buf); 1030 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 1031 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 1032 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 1033 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 1034 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 1035 uint32_t (*hal_rx_tlv_peer_meta_data_get)(uint8_t *buf); 1036 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 1037 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 1038 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 1039 QDF_STATUS 1040 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 1041 QDF_STATUS 1042 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 1043 QDF_STATUS 1044 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 1045 QDF_STATUS 1046 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 1047 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 1048 bool (*hal_rx_is_unicast)(uint8_t *buf); 1049 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 1050 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 1051 void *rxdma_dst_ring_desc); 1052 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 1053 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 1054 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 1055 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 1056 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 1057 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 1058 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 1059 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 1060 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 1061 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 1062 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 1063 void (*hal_reo_config)(struct hal_soc *soc, 1064 uint32_t reg_val, 1065 struct hal_reo_params *reo_params); 1066 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 1067 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 1068 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 1069 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 1070 bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf); 1071 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 1072 void 1073 (*hal_rx_msdu_get_flow_params)( 1074 uint8_t *buf, 1075 bool *flow_invalid, 1076 bool *flow_timeout, 1077 uint32_t *flow_index); 1078 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 1079 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 1080 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 1081 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 1082 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 1083 void *msdu_pkt_metadata); 1084 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 1085 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 1086 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 1087 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 1088 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 1089 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 1090 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 1091 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 1092 hal_rx_mon_desc_info_t mon_desc_info); 1093 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 1094 uint32_t (*hal_rx_msdu_end_offset_get)(void); 1095 uint32_t (*hal_rx_attn_offset_get)(void); 1096 uint32_t (*hal_rx_msdu_start_offset_get)(void); 1097 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 1098 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 1099 uint32_t (*hal_rx_pkt_tlv_offset_get)(void); 1100 uint32_t (*hal_rx_msdu_end_wmask_get)(void); 1101 uint32_t (*hal_rx_mpdu_start_wmask_get)(void); 1102 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 1103 uint32_t table_offset, 1104 uint8_t *rx_flow); 1105 void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst, 1106 uint32_t hal_hash, 1107 uint8_t *tuple_info); 1108 QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst, 1109 void *fse); 1110 uint32_t (*hal_rx_fst_get_fse_size)(void); 1111 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 1112 uint32_t num_rings, 1113 uint32_t *remap1, 1114 uint32_t *remap2); 1115 void (*hal_compute_reo_remap_ix0)(uint32_t *remap0); 1116 uint32_t (*hal_rx_flow_setup_cmem_fse)( 1117 struct hal_soc *soc, uint32_t cmem_ba, 1118 uint32_t table_offset, uint8_t *rx_flow); 1119 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc, 1120 uint32_t fse_offset); 1121 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc, 1122 uint32_t fse_offset, 1123 uint32_t *fse, qdf_size_t len); 1124 1125 void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset, 1126 uint32_t value); 1127 1128 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, 1129 uint32_t *reo_destination_indication); 1130 uint8_t (*hal_tx_get_num_tcl_banks)(void); 1131 uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid); 1132 uint16_t (*hal_get_rx_max_ba_window)(int tid); 1133 1134 void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie, 1135 qdf_dma_addr_t link_desc_paddr, 1136 uint8_t bm_id); 1137 void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl, 1138 hal_ring_handle_t hal_ring_hdl); 1139 void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr); 1140 void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 1141 uint8_t ac, uint32_t *value); 1142 void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 1143 uint8_t ac, uint32_t value); 1144 uint32_t (*hal_get_reo_reg_base_offset)(void); 1145 void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size, 1146 uint16_t *rx_mon_pkt_tlv_size); 1147 uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf); 1148 uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr); 1149 void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl, 1150 uint8_t *buf, uint8_t dbg_level); 1151 int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv, 1152 struct hal_offload_info *offload_info); 1153 uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf); 1154 uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf); 1155 uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf); 1156 uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf); 1157 int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params); 1158 int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset, 1159 uint32_t *l4_hdr_offset); 1160 uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf); 1161 uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf); 1162 void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num); 1163 void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn); 1164 uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf); 1165 uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl, 1166 void *msdu_link_desc); 1167 void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 1168 void *msdu_desc_info, uint32_t dst_ind, 1169 uint32_t nbuf_len); 1170 void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 1171 void *ent_desc, 1172 void *mpdu_desc_info, 1173 uint32_t seq_no); 1174 #ifdef DP_UMAC_HW_RESET_SUPPORT 1175 void (*hal_unregister_reo_send_cmd)(struct hal_soc *hal_soc); 1176 void (*hal_register_reo_send_cmd)(struct hal_soc *hal_soc); 1177 void (*hal_reset_rx_reo_tid_q)(struct hal_soc *hal_soc, 1178 void *hw_qdesc_vaddr, uint32_t size); 1179 #endif 1180 uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf); 1181 uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf); 1182 uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf); 1183 uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf); 1184 uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf); 1185 uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf); 1186 uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf); 1187 uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf); 1188 1189 uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc); 1190 uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc); 1191 void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl, 1192 void *src_srng_desc, 1193 hal_buff_addrinfo_t buf_addr_info, 1194 uint8_t bm_action); 1195 1196 void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl, 1197 hal_buf_info_t buf_info_hdl); 1198 void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc, 1199 struct hal_buf_info *buf_info); 1200 void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry, 1201 qdf_dma_addr_t paddr, 1202 uint32_t cookie, uint8_t manager); 1203 uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl); 1204 uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc); 1205 void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr, 1206 uint32_t *ip_csum_err, 1207 uint32_t *tcp_udp_csum_err); 1208 void (*hal_rx_mpdu_desc_info_get)(void *desc_addr, 1209 void *mpdu_desc_info_hdl); 1210 uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc); 1211 uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc); 1212 bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf); 1213 uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr); 1214 uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr); 1215 void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr, 1216 struct hal_rx_pkt_capture_flags *flags); 1217 uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr); 1218 uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr); 1219 void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf, 1220 uint8_t *priv_data, 1221 uint32_t len); 1222 void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf, 1223 uint8_t *priv_data, 1224 uint32_t len); 1225 void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len); 1226 void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf, 1227 void *mpdu_desc_info_hdl); 1228 uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc); 1229 uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc, 1230 uint8_t *buf); 1231 void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc, 1232 uint32_t dst_ind); 1233 QDF_STATUS 1234 (*hal_rx_reo_ent_get_src_link_id)(hal_rxdma_desc_t rx_desc, 1235 uint8_t *src_link_id); 1236 1237 /* REO CMD and STATUS */ 1238 int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl, 1239 hal_ring_handle_t hal_ring_hdl, 1240 enum hal_reo_cmd_type cmd, 1241 void *params); 1242 QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl, 1243 hal_ring_desc_t reo_desc, 1244 void *st_handle, 1245 uint32_t tlv, int *num_ref); 1246 uint8_t (*hal_get_tlv_hdr_size)(void); 1247 uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id); 1248 1249 bool (*hal_txmon_is_mon_buf_addr_tlv)(void *tx_tlv_hdr); 1250 void (*hal_txmon_populate_packet_info)(void *tx_tlv_hdr, 1251 void *pkt_info); 1252 /* TX MONITOR */ 1253 #ifdef QCA_MONITOR_2_0_SUPPORT 1254 uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info, 1255 void *prot_ppdu_info, 1256 void *data_status_info, 1257 void *prot_status_info, 1258 void *tx_tlv_hdr, 1259 qdf_frag_t status_frag); 1260 uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr, 1261 uint8_t *num_users); 1262 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1263 QDF_STATUS (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl); 1264 void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl, 1265 int qref_reset); 1266 void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl); 1267 void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl, 1268 uint16_t peer_id, 1269 int tid, 1270 qdf_dma_addr_t hw_qdesc_paddr); 1271 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1272 uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf); 1273 #endif 1274 void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl); 1275 uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf); 1276 void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl, 1277 enum hal_tx_vdev_mismatch_notify config); 1278 void (*hal_tx_mcast_mlo_reinject_routing_set)( 1279 hal_soc_handle_t hal_soc_hdl, 1280 enum hal_tx_mcast_mlo_reinject_notify config); 1281 void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl, 1282 struct hal_hw_cc_config 1283 *cc_cfg); 1284 void (*hal_tx_populate_bank_register)(hal_soc_handle_t hal_soc_hdl, 1285 union hal_tx_bank_config *config, 1286 uint8_t bank_id); 1287 void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl, 1288 uint8_t vdev_id, 1289 uint8_t mcast_ctrl_val); 1290 void (*hal_get_tsf_time)(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1291 uint32_t mac_id, uint64_t *tsf, 1292 uint64_t *tsf_sync_soc_time); 1293 void (*hal_get_tsf2_scratch_reg)(hal_soc_handle_t hal_soc_hdl, 1294 uint8_t mac_id, uint64_t *value); 1295 void (*hal_get_tqm_scratch_reg)(hal_soc_handle_t hal_soc_hdl, 1296 uint64_t *value); 1297 #ifdef FEATURE_DIRECT_LINK 1298 QDF_STATUS (*hal_srng_set_msi_config)(hal_ring_handle_t ring_hdl, 1299 void *ring_params); 1300 #endif 1301 void (*hal_tx_ring_halt_set)(hal_soc_handle_t hal_soc_hdl); 1302 void (*hal_tx_ring_halt_reset)(hal_soc_handle_t hal_soc_hdl); 1303 bool (*hal_tx_ring_halt_poll)(hal_soc_handle_t hal_soc_hdl); 1304 uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)( 1305 hal_soc_handle_t hal_soc_hdl); 1306 }; 1307 1308 /** 1309 * struct hal_soc_stats - Hal layer stats 1310 * @reg_write_fail: number of failed register writes 1311 * @wstats: delayed register write stats 1312 * @shadow_reg_write_fail: shadow reg write failure stats 1313 * @shadow_reg_write_succ: shadow reg write success stats 1314 * 1315 * This structure holds all the statistics at HAL layer. 1316 */ 1317 struct hal_soc_stats { 1318 uint32_t reg_write_fail; 1319 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1320 struct hal_reg_write_soc_stats wstats; 1321 #endif 1322 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1323 uint32_t shadow_reg_write_fail; 1324 uint32_t shadow_reg_write_succ; 1325 #endif 1326 }; 1327 1328 #ifdef ENABLE_HAL_REG_WR_HISTORY 1329 /* The history size should always be a power of 2 */ 1330 #define HAL_REG_WRITE_HIST_SIZE 8 1331 1332 /** 1333 * struct hal_reg_write_fail_entry - Record of 1334 * register write which failed. 1335 * @timestamp: timestamp of reg write failure 1336 * @reg_offset: offset of register where the write failed 1337 * @write_val: the value which was to be written 1338 * @read_val: the value read back from the register after write 1339 */ 1340 struct hal_reg_write_fail_entry { 1341 uint64_t timestamp; 1342 uint32_t reg_offset; 1343 uint32_t write_val; 1344 uint32_t read_val; 1345 }; 1346 1347 /** 1348 * struct hal_reg_write_fail_history - Hal layer history 1349 * of all the register write failures. 1350 * @index: index to add the new record 1351 * @record: array of all the records in history 1352 * 1353 * This structure holds the history of register write 1354 * failures at HAL layer. 1355 */ 1356 struct hal_reg_write_fail_history { 1357 qdf_atomic_t index; 1358 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 1359 }; 1360 #endif 1361 1362 /** 1363 * struct reo_queue_ref_table - Reo qref LUT addr 1364 * @mlo_reo_qref_table_vaddr: MLO table vaddr 1365 * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr 1366 * @mlo_reo_qref_table_paddr: MLO table paddr 1367 * @non_mlo_reo_qref_table_paddr: Non MLO table paddr 1368 * @reo_qref_table_en: Enable flag 1369 */ 1370 struct reo_queue_ref_table { 1371 uint64_t *mlo_reo_qref_table_vaddr; 1372 uint64_t *non_mlo_reo_qref_table_vaddr; 1373 qdf_dma_addr_t mlo_reo_qref_table_paddr; 1374 qdf_dma_addr_t non_mlo_reo_qref_table_paddr; 1375 uint8_t reo_qref_table_en; 1376 }; 1377 1378 /** 1379 * union hal_shadow_reg_cfg - Shadow register config 1380 * @addr: Place holder where shadow address is saved 1381 * @v2: shadow config v2 format 1382 * @v3: shadow config v3 format 1383 */ 1384 union hal_shadow_reg_cfg { 1385 uint32_t addr; 1386 struct pld_shadow_reg_v2_cfg v2; 1387 #ifdef CONFIG_SHADOW_V3 1388 struct pld_shadow_reg_v3_cfg v3; 1389 #endif 1390 }; 1391 1392 #ifdef HAL_RECORD_SUSPEND_WRITE 1393 #define HAL_SUSPEND_WRITE_HISTORY_MAX 256 1394 1395 struct hal_suspend_write_record { 1396 uint64_t ts; 1397 uint8_t ring_id; 1398 uit32_t value; 1399 uint32_t direct_wcount; 1400 }; 1401 1402 struct hal_suspend_write_history { 1403 qdf_atomic_t index; 1404 struct hal_suspend_write_record record[HAL_SUSPEND_WRITE_HISTORY_MAX]; 1405 1406 }; 1407 #endif 1408 1409 /** 1410 * struct hal_soc - HAL context to be used to access SRNG APIs 1411 * (currently used by data path and 1412 * transport (CE) modules) 1413 * @list_shadow_reg_config: array of generic regs mapped to 1414 * shadow regs 1415 * @num_generic_shadow_regs_configured: number of generic regs 1416 * mapped to shadow regs 1417 */ 1418 struct hal_soc { 1419 /* HIF handle to access HW registers */ 1420 struct hif_opaque_softc *hif_handle; 1421 1422 /* QDF device handle */ 1423 qdf_device_t qdf_dev; 1424 1425 /* Device base address */ 1426 void *dev_base_addr; 1427 /* Device base address for ce - qca5018 target */ 1428 void *dev_base_addr_ce; 1429 1430 void *dev_base_addr_cmem; 1431 1432 void *dev_base_addr_pmm; 1433 /* HAL internal state for all SRNG rings. 1434 * TODO: See if this is required 1435 */ 1436 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 1437 1438 /* Remote pointer memory for HW/FW updates */ 1439 uint32_t *shadow_rdptr_mem_vaddr; 1440 qdf_dma_addr_t shadow_rdptr_mem_paddr; 1441 1442 /* Shared memory for ring pointer updates from host to FW */ 1443 uint32_t *shadow_wrptr_mem_vaddr; 1444 qdf_dma_addr_t shadow_wrptr_mem_paddr; 1445 1446 /* REO blocking resource index */ 1447 uint8_t reo_res_bitmap; 1448 uint8_t index; 1449 uint32_t target_type; 1450 uint32_t version; 1451 1452 /* shadow register configuration */ 1453 union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS]; 1454 int num_shadow_registers_configured; 1455 bool use_register_windowing; 1456 uint32_t register_window; 1457 qdf_spinlock_t register_access_lock; 1458 1459 /* Static window map configuration for multiple window write*/ 1460 bool static_window_map; 1461 1462 /* srng table */ 1463 struct hal_hw_srng_config *hw_srng_table; 1464 int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX]; 1465 struct hal_hw_txrx_ops *ops; 1466 1467 /* Indicate srngs initialization */ 1468 bool init_phase; 1469 /* Hal level stats */ 1470 struct hal_soc_stats stats; 1471 #ifdef ENABLE_HAL_REG_WR_HISTORY 1472 struct hal_reg_write_fail_history *reg_wr_fail_hist; 1473 #endif 1474 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1475 /* queue(array) to hold register writes */ 1476 struct hal_reg_write_q_elem *reg_write_queue; 1477 /* delayed work to be queued into workqueue */ 1478 qdf_work_t reg_write_work; 1479 /* workqueue for delayed register writes */ 1480 qdf_workqueue_t *reg_write_wq; 1481 /* write index used by caller to enqueue delayed work */ 1482 qdf_atomic_t write_idx; 1483 /* read index used by worker thread to dequeue/write registers */ 1484 uint32_t read_idx; 1485 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */ 1486 qdf_atomic_t active_work_cnt; 1487 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1488 struct shadow_reg_config 1489 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; 1490 int num_generic_shadow_regs_configured; 1491 #endif 1492 /* flag to indicate cmn dmac rings in berryllium */ 1493 bool dmac_cmn_src_rxbuf_ring; 1494 /* Reo queue ref table items */ 1495 struct reo_queue_ref_table reo_qref; 1496 }; 1497 1498 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1499 /** 1500 * hal_delayed_reg_write() - delayed register write 1501 * @hal_soc: HAL soc handle 1502 * @srng: hal srng 1503 * @addr: iomem address 1504 * @value: value to be written 1505 * 1506 * Return: none 1507 */ 1508 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1509 struct hal_srng *srng, 1510 void __iomem *addr, 1511 uint32_t value); 1512 #endif 1513 1514 void hal_qca6750_attach(struct hal_soc *hal_soc); 1515 void hal_qca6490_attach(struct hal_soc *hal_soc); 1516 void hal_qca6390_attach(struct hal_soc *hal_soc); 1517 void hal_qca6290_attach(struct hal_soc *hal_soc); 1518 void hal_qca8074_attach(struct hal_soc *hal_soc); 1519 void hal_kiwi_attach(struct hal_soc *hal_soc); 1520 void hal_qcn9224v1_attach(struct hal_soc *hal_soc); 1521 void hal_qcn9224v2_attach(struct hal_soc *hal_soc); 1522 /* 1523 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 1524 * dp_hal_soc handle type 1525 * @hal_soc - hal_soc type 1526 * 1527 * Return: hal_soc_handle_t type 1528 */ 1529 static inline 1530 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 1531 { 1532 return (hal_soc_handle_t)hal_soc; 1533 } 1534 1535 /* 1536 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 1537 * dp_hal_ring handle type 1538 * @hal_srng - hal_srng type 1539 * 1540 * Return: hal_ring_handle_t type 1541 */ 1542 static inline 1543 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 1544 { 1545 return (hal_ring_handle_t)hal_srng; 1546 } 1547 1548 /* 1549 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 1550 * @hal_ring - hal_ring_handle_t type 1551 * 1552 * Return: hal_srng pointer type 1553 */ 1554 static inline 1555 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 1556 { 1557 return (struct hal_srng *)hal_ring; 1558 } 1559 1560 /* Size of REO queue reference table in Host 1561 * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference) 1562 * = 278528 bytes 1563 */ 1564 #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528 1565 /* Calculated based on 512 MLO peers */ 1566 #define REO_QUEUE_REF_ML_TABLE_SIZE 69632 1567 #define HAL_ML_PEER_ID_START 0x2000 1568 #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START) 1569 1570 /* 1571 * REO2PPE destination indication 1572 */ 1573 #define REO2PPE_DST_IND 6 1574 #define REO2PPE_DST_RING 11 1575 #define REO2PPE_RULE_FAIL_FB 0x2000 1576 1577 /** 1578 * enum hal_pkt_type - Type of packet type reported by HW 1579 * @HAL_DOT11A: 802.11a PPDU type 1580 * @HAL_DOT11B: 802.11b PPDU type 1581 * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type 1582 * @HAL_DOT11AC: 802.11ac PPDU type 1583 * @HAL_DOT11AX: 802.11ax PPDU type 1584 * @HAL_DOT11BA: 802.11ba (WUR) PPDU type 1585 * @HAL_DOT11BE: 802.11be PPDU type 1586 * @HAL_DOT11AZ: 802.11az (ranging) PPDU type 1587 * @HAL_DOT11N_GF: 802.11n Green Field PPDU type 1588 * 1589 * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data) 1590 * or WBM2SW ring entry's descriptor (TX data completion) 1591 */ 1592 enum hal_pkt_type { 1593 HAL_DOT11A = 0, 1594 HAL_DOT11B = 1, 1595 HAL_DOT11N_MM = 2, 1596 HAL_DOT11AC = 3, 1597 HAL_DOT11AX = 4, 1598 HAL_DOT11BA = 5, 1599 HAL_DOT11BE = 6, 1600 HAL_DOT11AZ = 7, 1601 HAL_DOT11N_GF = 8, 1602 HAL_DOT11_MAX, 1603 }; 1604 1605 #endif /* _HAL_INTERNAL_H_ */ 1606