1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_atomic.h" 24 #include "qdf_lock.h" 25 #include "qdf_mem.h" 26 #include "qdf_nbuf.h" 27 #include "pld_common.h" 28 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 29 #include "qdf_defer.h" 30 #endif 31 32 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 33 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 34 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 35 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params) 36 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 37 38 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 39 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 40 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 41 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 43 44 #ifdef ENABLE_VERBOSE_DEBUG 45 extern bool is_hal_verbose_debug_enabled; 46 #define hal_verbose_debug(params...) \ 47 if (unlikely(is_hal_verbose_debug_enabled)) \ 48 do {\ 49 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 50 } while (0) 51 #define hal_verbose_hex_dump(params...) \ 52 if (unlikely(is_hal_verbose_debug_enabled)) \ 53 do {\ 54 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 55 QDF_TRACE_LEVEL_DEBUG, \ 56 params); \ 57 } while (0) 58 #else 59 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 60 #define hal_verbose_hex_dump(params...) \ 61 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 62 params) 63 #endif 64 65 /* 66 * dp_hal_soc - opaque handle for DP HAL soc 67 */ 68 struct hal_soc_handle; 69 typedef struct hal_soc_handle *hal_soc_handle_t; 70 71 /** 72 * hal_ring_desc - opaque handle for DP ring descriptor 73 */ 74 struct hal_ring_desc; 75 typedef struct hal_ring_desc *hal_ring_desc_t; 76 77 /** 78 * hal_link_desc - opaque handle for DP link descriptor 79 */ 80 struct hal_link_desc; 81 typedef struct hal_link_desc *hal_link_desc_t; 82 83 /** 84 * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor 85 */ 86 struct hal_rxdma_desc; 87 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 88 89 /** 90 * hal_buff_addrinfo - opaque handle for DP buffer address info 91 */ 92 struct hal_buff_addrinfo; 93 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 94 95 /** 96 * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info 97 */ 98 struct hal_rx_mon_desc_info; 99 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 100 101 /* TBD: This should be movded to shared HW header file */ 102 enum hal_srng_ring_id { 103 /* UMAC rings */ 104 HAL_SRNG_REO2SW1 = 0, 105 HAL_SRNG_REO2SW2 = 1, 106 HAL_SRNG_REO2SW3 = 2, 107 HAL_SRNG_REO2SW4 = 3, 108 HAL_SRNG_REO2TCL = 4, 109 HAL_SRNG_SW2REO = 5, 110 /* 6-7 unused */ 111 HAL_SRNG_REO_CMD = 8, 112 HAL_SRNG_REO_STATUS = 9, 113 /* 10-15 unused */ 114 HAL_SRNG_SW2TCL1 = 16, 115 HAL_SRNG_SW2TCL2 = 17, 116 HAL_SRNG_SW2TCL3 = 18, 117 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 118 /* 20-23 unused */ 119 HAL_SRNG_SW2TCL_CMD = 24, 120 HAL_SRNG_TCL_STATUS = 25, 121 /* 26-31 unused */ 122 HAL_SRNG_CE_0_SRC = 32, 123 HAL_SRNG_CE_1_SRC = 33, 124 HAL_SRNG_CE_2_SRC = 34, 125 HAL_SRNG_CE_3_SRC = 35, 126 HAL_SRNG_CE_4_SRC = 36, 127 HAL_SRNG_CE_5_SRC = 37, 128 HAL_SRNG_CE_6_SRC = 38, 129 HAL_SRNG_CE_7_SRC = 39, 130 HAL_SRNG_CE_8_SRC = 40, 131 HAL_SRNG_CE_9_SRC = 41, 132 HAL_SRNG_CE_10_SRC = 42, 133 HAL_SRNG_CE_11_SRC = 43, 134 /* 44-55 unused */ 135 HAL_SRNG_CE_0_DST = 56, 136 HAL_SRNG_CE_1_DST = 57, 137 HAL_SRNG_CE_2_DST = 58, 138 HAL_SRNG_CE_3_DST = 59, 139 HAL_SRNG_CE_4_DST = 60, 140 HAL_SRNG_CE_5_DST = 61, 141 HAL_SRNG_CE_6_DST = 62, 142 HAL_SRNG_CE_7_DST = 63, 143 HAL_SRNG_CE_8_DST = 64, 144 HAL_SRNG_CE_9_DST = 65, 145 HAL_SRNG_CE_10_DST = 66, 146 HAL_SRNG_CE_11_DST = 67, 147 /* 68-79 unused */ 148 HAL_SRNG_CE_0_DST_STATUS = 80, 149 HAL_SRNG_CE_1_DST_STATUS = 81, 150 HAL_SRNG_CE_2_DST_STATUS = 82, 151 HAL_SRNG_CE_3_DST_STATUS = 83, 152 HAL_SRNG_CE_4_DST_STATUS = 84, 153 HAL_SRNG_CE_5_DST_STATUS = 85, 154 HAL_SRNG_CE_6_DST_STATUS = 86, 155 HAL_SRNG_CE_7_DST_STATUS = 87, 156 HAL_SRNG_CE_8_DST_STATUS = 88, 157 HAL_SRNG_CE_9_DST_STATUS = 89, 158 HAL_SRNG_CE_10_DST_STATUS = 90, 159 HAL_SRNG_CE_11_DST_STATUS = 91, 160 /* 92-103 unused */ 161 HAL_SRNG_WBM_IDLE_LINK = 104, 162 HAL_SRNG_WBM_SW_RELEASE = 105, 163 HAL_SRNG_WBM2SW0_RELEASE = 106, 164 HAL_SRNG_WBM2SW1_RELEASE = 107, 165 HAL_SRNG_WBM2SW2_RELEASE = 108, 166 HAL_SRNG_WBM2SW3_RELEASE = 109, 167 /* 110-127 unused */ 168 HAL_SRNG_UMAC_ID_END = 127, 169 /* LMAC rings - The following set will be replicated for each LMAC */ 170 HAL_SRNG_LMAC1_ID_START = 128, 171 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 172 #ifdef IPA_OFFLOAD 173 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 174 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 175 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 176 #else 177 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 178 #endif 179 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 180 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 181 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 182 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 183 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 184 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 185 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 186 #ifdef WLAN_FEATURE_CIF_CFR 187 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 188 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 189 #else 190 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 191 #endif 192 /* -142 unused */ 193 HAL_SRNG_LMAC1_ID_END = 143 194 }; 195 196 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 197 #define HAL_MAX_LMACS 3 198 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 199 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 200 201 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 202 203 enum hal_srng_dir { 204 HAL_SRNG_SRC_RING, 205 HAL_SRNG_DST_RING 206 }; 207 208 /* Lock wrappers for SRNG */ 209 #define hal_srng_lock_t qdf_spinlock_t 210 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 211 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 212 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 213 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 214 215 struct hal_soc; 216 217 /** 218 * dp_hal_ring - opaque handle for DP HAL SRNG 219 */ 220 struct hal_ring_handle; 221 typedef struct hal_ring_handle *hal_ring_handle_t; 222 223 #define MAX_SRNG_REG_GROUPS 2 224 225 /* Hal Srng bit mask 226 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 227 */ 228 #define HAL_SRNG_FLUSH_EVENT BIT(0) 229 230 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 231 232 /** 233 * struct hal_reg_write_q_elem - delayed register write queue element 234 * @srng: hal_srng queued for a delayed write 235 * @addr: iomem address of the register 236 * @enqueue_val: register value at the time of delayed write enqueue 237 * @dequeue_val: register value at the time of delayed write dequeue 238 * @valid: whether this entry is valid or not 239 * @enqueue_time: enqueue time (qdf_log_timestamp) 240 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 241 * @dequeue_time: dequeue time (qdf_log_timestamp) 242 */ 243 struct hal_reg_write_q_elem { 244 struct hal_srng *srng; 245 void __iomem *addr; 246 uint32_t enqueue_val; 247 uint32_t dequeue_val; 248 uint8_t valid; 249 qdf_time_t enqueue_time; 250 qdf_time_t work_scheduled_time; 251 qdf_time_t dequeue_time; 252 }; 253 254 /** 255 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 256 * @enqueues: writes enqueued to delayed work 257 * @dequeues: writes dequeued from delayed work (not written yet) 258 * @coalesces: writes not enqueued since srng is already queued up 259 * @direct: writes not enqueued and written to register directly 260 */ 261 struct hal_reg_write_srng_stats { 262 uint32_t enqueues; 263 uint32_t dequeues; 264 uint32_t coalesces; 265 uint32_t direct; 266 }; 267 268 /** 269 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 270 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 271 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 272 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 273 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 274 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 275 */ 276 enum hal_reg_sched_delay { 277 REG_WRITE_SCHED_DELAY_SUB_100us, 278 REG_WRITE_SCHED_DELAY_SUB_1000us, 279 REG_WRITE_SCHED_DELAY_SUB_5000us, 280 REG_WRITE_SCHED_DELAY_GT_5000us, 281 REG_WRITE_SCHED_DELAY_HIST_MAX, 282 }; 283 284 /** 285 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 286 * @enqueues: writes enqueued to delayed work 287 * @dequeues: writes dequeued from delayed work (not written yet) 288 * @coalesces: writes not enqueued since srng is already queued up 289 * @direct: writes not enqueud and writted to register directly 290 * @prevent_l1_fails: prevent l1 API failed 291 * @q_depth: current queue depth in delayed register write queue 292 * @max_q_depth: maximum queue for delayed register write queue 293 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 294 */ 295 struct hal_reg_write_soc_stats { 296 qdf_atomic_t enqueues; 297 uint32_t dequeues; 298 qdf_atomic_t coalesces; 299 qdf_atomic_t direct; 300 uint32_t prevent_l1_fails; 301 qdf_atomic_t q_depth; 302 uint32_t max_q_depth; 303 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 304 }; 305 #endif 306 307 /* Common SRNG ring structure for source and destination rings */ 308 struct hal_srng { 309 /* Unique SRNG ring ID */ 310 uint8_t ring_id; 311 312 /* Ring initialization done */ 313 uint8_t initialized; 314 315 /* Interrupt/MSI value assigned to this ring */ 316 int irq; 317 318 /* Physical base address of the ring */ 319 qdf_dma_addr_t ring_base_paddr; 320 321 /* Virtual base address of the ring */ 322 uint32_t *ring_base_vaddr; 323 324 /* Number of entries in ring */ 325 uint32_t num_entries; 326 327 /* Ring size */ 328 uint32_t ring_size; 329 330 /* Ring size mask */ 331 uint32_t ring_size_mask; 332 333 /* Size of ring entry */ 334 uint32_t entry_size; 335 336 /* Interrupt timer threshold – in micro seconds */ 337 uint32_t intr_timer_thres_us; 338 339 /* Interrupt batch counter threshold – in number of ring entries */ 340 uint32_t intr_batch_cntr_thres_entries; 341 342 /* Applicable only for CE dest ring */ 343 uint32_t prefetch_timer; 344 345 /* MSI Address */ 346 qdf_dma_addr_t msi_addr; 347 348 /* MSI data */ 349 uint32_t msi_data; 350 351 /* Misc flags */ 352 uint32_t flags; 353 354 /* Lock for serializing ring index updates */ 355 hal_srng_lock_t lock; 356 357 /* Start offset of SRNG register groups for this ring 358 * TBD: See if this is required - register address can be derived 359 * from ring ID 360 */ 361 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 362 363 /* Source or Destination ring */ 364 enum hal_srng_dir ring_dir; 365 366 union { 367 struct { 368 /* SW tail pointer */ 369 uint32_t tp; 370 371 /* Shadow head pointer location to be updated by HW */ 372 uint32_t *hp_addr; 373 374 /* Cached head pointer */ 375 uint32_t cached_hp; 376 377 /* Tail pointer location to be updated by SW – This 378 * will be a register address and need not be 379 * accessed through SW structure */ 380 uint32_t *tp_addr; 381 382 /* Current SW loop cnt */ 383 uint32_t loop_cnt; 384 385 /* max transfer size */ 386 uint16_t max_buffer_length; 387 } dst_ring; 388 389 struct { 390 /* SW head pointer */ 391 uint32_t hp; 392 393 /* SW reap head pointer */ 394 uint32_t reap_hp; 395 396 /* Shadow tail pointer location to be updated by HW */ 397 uint32_t *tp_addr; 398 399 /* Cached tail pointer */ 400 uint32_t cached_tp; 401 402 /* Head pointer location to be updated by SW – This 403 * will be a register address and need not be accessed 404 * through SW structure */ 405 uint32_t *hp_addr; 406 407 /* Low threshold – in number of ring entries */ 408 uint32_t low_threshold; 409 } src_ring; 410 } u; 411 412 struct hal_soc *hal_soc; 413 414 /* Number of times hp/tp updated in runtime resume */ 415 uint32_t flush_count; 416 /* hal srng event flag*/ 417 unsigned long srng_event; 418 /* last flushed time stamp */ 419 uint64_t last_flush_ts; 420 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 421 /* flag to indicate whether srng is already queued for delayed write */ 422 uint8_t reg_write_in_progress; 423 424 /* srng specific delayed write stats */ 425 struct hal_reg_write_srng_stats wstats; 426 #endif 427 }; 428 429 /* HW SRNG configuration table */ 430 struct hal_hw_srng_config { 431 int start_ring_id; 432 uint16_t max_rings; 433 uint16_t entry_size; 434 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 435 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 436 uint8_t lmac_ring; 437 enum hal_srng_dir ring_dir; 438 uint32_t max_size; 439 }; 440 441 #define MAX_SHADOW_REGISTERS 36 442 443 /* REO parameters to be passed to hal_reo_setup */ 444 struct hal_reo_params { 445 /** rx hash steering enabled or disabled */ 446 bool rx_hash_enabled; 447 /** reo remap 1 register */ 448 uint32_t remap1; 449 /** reo remap 2 register */ 450 uint32_t remap2; 451 /** fragment destination ring */ 452 uint8_t frag_dst_ring; 453 /** padding */ 454 uint8_t padding[3]; 455 }; 456 457 struct hal_hw_txrx_ops { 458 459 /* init and setup */ 460 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 461 struct hal_srng *srng); 462 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 463 struct hal_srng *srng); 464 void (*hal_get_hw_hptp)(struct hal_soc *hal, 465 hal_ring_handle_t hal_ring_hdl, 466 uint32_t *headp, uint32_t *tailp, 467 uint8_t ring_type); 468 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams); 469 void (*hal_setup_link_idle_list)( 470 struct hal_soc *hal_soc, 471 qdf_dma_addr_t scatter_bufs_base_paddr[], 472 void *scatter_bufs_base_vaddr[], 473 uint32_t num_scatter_bufs, 474 uint32_t scatter_buf_size, 475 uint32_t last_buf_end_offset, 476 uint32_t num_entries); 477 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 478 qdf_iomem_t addr); 479 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 480 481 /* tx */ 482 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 483 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 484 uint8_t id); 485 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 486 uint8_t id, 487 uint8_t dscp); 488 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 489 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 490 uint8_t pool_id, uint32_t desc_id, uint8_t type); 491 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 492 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 493 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 494 void (*hal_tx_comp_get_status)(void *desc, void *ts, 495 struct hal_soc *hal); 496 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 497 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 498 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 499 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 500 hal_ring_handle_t hal_ring_hdl); 501 502 /* rx */ 503 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 504 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 505 struct mon_rx_status *rs); 506 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 507 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 508 void *ppdu_info_handle); 509 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 510 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 511 uint8_t dbg_level); 512 uint32_t (*hal_get_link_desc_size)(void); 513 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 514 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 515 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 516 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 517 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 518 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 519 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 520 void *ppdu_info, 521 hal_soc_handle_t hal_soc_hdl, 522 qdf_nbuf_t nbuf); 523 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 524 void *wbm_er_info); 525 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 526 uint8_t dbg_level); 527 528 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 529 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 530 uint8_t id); 531 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 532 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 533 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 534 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 535 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 536 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 537 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 538 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 539 void (*hal_rx_print_pn)(uint8_t *buf); 540 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 541 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 542 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 543 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 544 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 545 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 546 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 547 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 548 QDF_STATUS 549 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 550 QDF_STATUS 551 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 552 QDF_STATUS 553 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 554 QDF_STATUS 555 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 556 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 557 bool (*hal_rx_is_unicast)(uint8_t *buf); 558 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 559 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 560 void *rxdma_dst_ring_desc); 561 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 562 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 563 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 564 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 565 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 566 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 567 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 568 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 569 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 570 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 571 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 572 void (*hal_reo_config)(struct hal_soc *soc, 573 uint32_t reg_val, 574 struct hal_reo_params *reo_params); 575 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 576 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 577 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 578 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 579 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 580 void 581 (*hal_rx_msdu_get_flow_params)( 582 uint8_t *buf, 583 bool *flow_invalid, 584 bool *flow_timeout, 585 uint32_t *flow_index); 586 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 587 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 588 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 589 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 590 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 591 void *msdu_pkt_metadata); 592 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 593 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 594 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 595 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 596 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 597 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 598 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 599 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 600 hal_rx_mon_desc_info_t mon_desc_info); 601 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 602 uint32_t (*hal_rx_msdu_end_offset_get)(void); 603 uint32_t (*hal_rx_attn_offset_get)(void); 604 uint32_t (*hal_rx_msdu_start_offset_get)(void); 605 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 606 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 607 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 608 uint32_t table_offset, 609 uint8_t *rx_flow); 610 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 611 uint32_t num_rings, 612 uint32_t *remap1, 613 uint32_t *remap2); 614 }; 615 616 /** 617 * struct hal_soc_stats - Hal layer stats 618 * @reg_write_fail: number of failed register writes 619 * @wstats: delayed register write stats 620 * 621 * This structure holds all the statistics at HAL layer. 622 */ 623 struct hal_soc_stats { 624 uint32_t reg_write_fail; 625 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 626 struct hal_reg_write_soc_stats wstats; 627 #endif 628 }; 629 630 #ifdef ENABLE_HAL_REG_WR_HISTORY 631 /* The history size should always be a power of 2 */ 632 #define HAL_REG_WRITE_HIST_SIZE 8 633 634 /** 635 * struct hal_reg_write_fail_entry - Record of 636 * register write which failed. 637 * @timestamp: timestamp of reg write failure 638 * @reg_offset: offset of register where the write failed 639 * @write_val: the value which was to be written 640 * @read_val: the value read back from the register after write 641 */ 642 struct hal_reg_write_fail_entry { 643 uint64_t timestamp; 644 uint32_t reg_offset; 645 uint32_t write_val; 646 uint32_t read_val; 647 }; 648 649 /** 650 * struct hal_reg_write_fail_history - Hal layer history 651 * of all the register write failures. 652 * @index: index to add the new record 653 * @record: array of all the records in history 654 * 655 * This structure holds the history of register write 656 * failures at HAL layer. 657 */ 658 struct hal_reg_write_fail_history { 659 qdf_atomic_t index; 660 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 661 }; 662 #endif 663 664 /** 665 * HAL context to be used to access SRNG APIs (currently used by data path 666 * and transport (CE) modules) 667 */ 668 struct hal_soc { 669 /* HIF handle to access HW registers */ 670 struct hif_opaque_softc *hif_handle; 671 672 /* QDF device handle */ 673 qdf_device_t qdf_dev; 674 675 /* Device base address */ 676 void *dev_base_addr; 677 /* Device base address for ce - qca5018 target */ 678 void *dev_base_addr_ce; 679 680 /* HAL internal state for all SRNG rings. 681 * TODO: See if this is required 682 */ 683 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 684 685 /* Remote pointer memory for HW/FW updates */ 686 uint32_t *shadow_rdptr_mem_vaddr; 687 qdf_dma_addr_t shadow_rdptr_mem_paddr; 688 689 /* Shared memory for ring pointer updates from host to FW */ 690 uint32_t *shadow_wrptr_mem_vaddr; 691 qdf_dma_addr_t shadow_wrptr_mem_paddr; 692 693 /* REO blocking resource index */ 694 uint8_t reo_res_bitmap; 695 uint8_t index; 696 uint32_t target_type; 697 698 /* shadow register configuration */ 699 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 700 int num_shadow_registers_configured; 701 bool use_register_windowing; 702 uint32_t register_window; 703 qdf_spinlock_t register_access_lock; 704 705 /* Static window map configuration for multiple window write*/ 706 bool static_window_map; 707 708 /* srng table */ 709 struct hal_hw_srng_config *hw_srng_table; 710 int32_t *hal_hw_reg_offset; 711 struct hal_hw_txrx_ops *ops; 712 713 /* Indicate srngs initialization */ 714 bool init_phase; 715 /* Hal level stats */ 716 struct hal_soc_stats stats; 717 #ifdef ENABLE_HAL_REG_WR_HISTORY 718 struct hal_reg_write_fail_history *reg_wr_fail_hist; 719 #endif 720 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 721 /* queue(array) to hold register writes */ 722 struct hal_reg_write_q_elem *reg_write_queue; 723 /* delayed work to be queued into workqueue */ 724 qdf_work_t reg_write_work; 725 /* workqueue for delayed register writes */ 726 qdf_workqueue_t *reg_write_wq; 727 /* write index used by caller to enqueue delayed work */ 728 qdf_atomic_t write_idx; 729 /* read index used by worker thread to dequeue/write registers */ 730 uint32_t read_idx; 731 #endif 732 qdf_atomic_t active_work_cnt; 733 }; 734 735 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 736 /** 737 * hal_delayed_reg_write() - delayed regiter write 738 * @hal_soc: HAL soc handle 739 * @srng: hal srng 740 * @addr: iomem address 741 * @value: value to be written 742 * 743 * Return: none 744 */ 745 void hal_delayed_reg_write(struct hal_soc *hal_soc, 746 struct hal_srng *srng, 747 void __iomem *addr, 748 uint32_t value); 749 #endif 750 751 void hal_qca6750_attach(struct hal_soc *hal_soc); 752 void hal_qca6490_attach(struct hal_soc *hal_soc); 753 void hal_qca6390_attach(struct hal_soc *hal_soc); 754 void hal_qca6290_attach(struct hal_soc *hal_soc); 755 void hal_qca8074_attach(struct hal_soc *hal_soc); 756 757 /* 758 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 759 * dp_hal_soc handle type 760 * @hal_soc - hal_soc type 761 * 762 * Return: hal_soc_handle_t type 763 */ 764 static inline 765 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 766 { 767 return (hal_soc_handle_t)hal_soc; 768 } 769 770 /* 771 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 772 * dp_hal_ring handle type 773 * @hal_srng - hal_srng type 774 * 775 * Return: hal_ring_handle_t type 776 */ 777 static inline 778 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 779 { 780 return (hal_ring_handle_t)hal_srng; 781 } 782 783 /* 784 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 785 * @hal_ring - hal_ring_handle_t type 786 * 787 * Return: hal_srng pointer type 788 */ 789 static inline 790 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 791 { 792 return (struct hal_srng *)hal_ring; 793 } 794 #endif /* _HAL_INTERNAL_H_ */ 795