1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_INTERNAL_H_ 21 #define _HAL_INTERNAL_H_ 22 23 #include "qdf_types.h" 24 #include "qdf_atomic.h" 25 #include "qdf_lock.h" 26 #include "qdf_mem.h" 27 #include "qdf_nbuf.h" 28 #include "pld_common.h" 29 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 30 #include "qdf_defer.h" 31 #include "qdf_timer.h" 32 #endif 33 34 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 35 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 36 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 37 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params) 38 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 39 40 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 41 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 43 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 44 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 45 46 #ifdef ENABLE_VERBOSE_DEBUG 47 extern bool is_hal_verbose_debug_enabled; 48 #define hal_verbose_debug(params...) \ 49 if (unlikely(is_hal_verbose_debug_enabled)) \ 50 do {\ 51 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 52 } while (0) 53 #define hal_verbose_hex_dump(params...) \ 54 if (unlikely(is_hal_verbose_debug_enabled)) \ 55 do {\ 56 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 57 QDF_TRACE_LEVEL_DEBUG, \ 58 params); \ 59 } while (0) 60 #else 61 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 62 #define hal_verbose_hex_dump(params...) \ 63 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 64 params) 65 #endif 66 67 /* 68 * Given the offset of a field in bytes, returns uint8_t * 69 */ 70 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 71 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 72 73 /* 74 * Given the offset of a field in bytes, returns uint32_t * 75 */ 76 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 77 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 78 79 /* 80 * Given the offset of a field in bytes, returns uint64_t * 81 */ 82 #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \ 83 (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3)) 84 85 #define _HAL_MS(_word, _mask, _shift) \ 86 (((_word) & (_mask)) >> (_shift)) 87 88 /* 89 * Get number of QWORDS possible for num. 90 * Its the caller's duty to make sure num is a multiple of QWORD (8) 91 */ 92 #define HAL_GET_NUM_QWORDS(num) ((num) >> 3) 93 94 /* 95 * Get number of DWORDS possible for num. 96 * Its the caller's duty to make sure num is a multiple of DWORD (8) 97 */ 98 #define HAL_GET_NUM_DWORDS(num) ((num) >> 2) 99 100 /* 101 * dp_hal_soc - opaque handle for DP HAL soc 102 */ 103 struct hal_soc_handle; 104 typedef struct hal_soc_handle *hal_soc_handle_t; 105 106 /** 107 * hal_ring_desc - opaque handle for DP ring descriptor 108 */ 109 struct hal_ring_desc; 110 typedef struct hal_ring_desc *hal_ring_desc_t; 111 112 /** 113 * hal_link_desc - opaque handle for DP link descriptor 114 */ 115 struct hal_link_desc; 116 typedef struct hal_link_desc *hal_link_desc_t; 117 118 /** 119 * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor 120 */ 121 struct hal_rxdma_desc; 122 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 123 124 /** 125 * hal_buff_addrinfo - opaque handle for DP buffer address info 126 */ 127 struct hal_buff_addrinfo; 128 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 129 130 /** 131 * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info 132 */ 133 struct hal_rx_mon_desc_info; 134 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 135 136 struct hal_buf_info; 137 typedef struct hal_buf_info *hal_buf_info_t; 138 139 struct rx_msdu_desc_info; 140 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t; 141 142 /** 143 * Opaque hanlder for PPE VP config. 144 */ 145 union hal_tx_ppe_vp_config; 146 union hal_tx_cmn_config_ppe; 147 148 /* TBD: This should be movded to shared HW header file */ 149 enum hal_srng_ring_id { 150 /* UMAC rings */ 151 HAL_SRNG_REO2SW0 = 0, 152 HAL_SRNG_REO2SW1 = 1, 153 HAL_SRNG_REO2SW2 = 2, 154 HAL_SRNG_REO2SW3 = 3, 155 HAL_SRNG_REO2SW4 = 4, 156 HAL_SRNG_REO2SW5 = 5, 157 HAL_SRNG_REO2SW6 = 6, 158 HAL_SRNG_REO2SW7 = 7, 159 HAL_SRNG_REO2SW8 = 8, 160 HAL_SRNG_REO2TCL = 9, 161 HAL_SRNG_REO2PPE = 10, 162 /* 11-15 unused */ 163 HAL_SRNG_SW2REO = 16, 164 HAL_SRNG_SW2REO1 = 17, 165 HAL_SRNG_SW2REO2 = 18, 166 HAL_SRNG_SW2REO3 = 19, 167 HAL_SRNG_REO_CMD = 20, 168 HAL_SRNG_REO_STATUS = 21, 169 /* 22-23 unused */ 170 HAL_SRNG_SW2TCL1 = 24, 171 HAL_SRNG_SW2TCL2 = 25, 172 HAL_SRNG_SW2TCL3 = 26, 173 HAL_SRNG_SW2TCL4 = 27, 174 HAL_SRNG_SW2TCL5 = 28, 175 HAL_SRNG_SW2TCL6 = 29, 176 HAL_SRNG_PPE2TCL1 = 30, 177 /* 31-39 unused */ 178 HAL_SRNG_SW2TCL_CMD = 40, 179 HAL_SRNG_TCL_STATUS = 41, 180 HAL_SRNG_SW2TCL_CREDIT = 42, 181 /* 43-63 unused */ 182 HAL_SRNG_CE_0_SRC = 64, 183 HAL_SRNG_CE_1_SRC = 65, 184 HAL_SRNG_CE_2_SRC = 66, 185 HAL_SRNG_CE_3_SRC = 67, 186 HAL_SRNG_CE_4_SRC = 68, 187 HAL_SRNG_CE_5_SRC = 69, 188 HAL_SRNG_CE_6_SRC = 70, 189 HAL_SRNG_CE_7_SRC = 71, 190 HAL_SRNG_CE_8_SRC = 72, 191 HAL_SRNG_CE_9_SRC = 73, 192 HAL_SRNG_CE_10_SRC = 74, 193 HAL_SRNG_CE_11_SRC = 75, 194 HAL_SRNG_CE_12_SRC = 76, 195 HAL_SRNG_CE_13_SRC = 77, 196 HAL_SRNG_CE_14_SRC = 78, 197 HAL_SRNG_CE_15_SRC = 79, 198 /* 80 */ 199 HAL_SRNG_CE_0_DST = 81, 200 HAL_SRNG_CE_1_DST = 82, 201 HAL_SRNG_CE_2_DST = 83, 202 HAL_SRNG_CE_3_DST = 84, 203 HAL_SRNG_CE_4_DST = 85, 204 HAL_SRNG_CE_5_DST = 86, 205 HAL_SRNG_CE_6_DST = 87, 206 HAL_SRNG_CE_7_DST = 89, 207 HAL_SRNG_CE_8_DST = 90, 208 HAL_SRNG_CE_9_DST = 91, 209 HAL_SRNG_CE_10_DST = 92, 210 HAL_SRNG_CE_11_DST = 93, 211 HAL_SRNG_CE_12_DST = 94, 212 HAL_SRNG_CE_13_DST = 95, 213 HAL_SRNG_CE_14_DST = 96, 214 HAL_SRNG_CE_15_DST = 97, 215 /* 98-99 unused */ 216 HAL_SRNG_CE_0_DST_STATUS = 100, 217 HAL_SRNG_CE_1_DST_STATUS = 101, 218 HAL_SRNG_CE_2_DST_STATUS = 102, 219 HAL_SRNG_CE_3_DST_STATUS = 103, 220 HAL_SRNG_CE_4_DST_STATUS = 104, 221 HAL_SRNG_CE_5_DST_STATUS = 105, 222 HAL_SRNG_CE_6_DST_STATUS = 106, 223 HAL_SRNG_CE_7_DST_STATUS = 107, 224 HAL_SRNG_CE_8_DST_STATUS = 108, 225 HAL_SRNG_CE_9_DST_STATUS = 109, 226 HAL_SRNG_CE_10_DST_STATUS = 110, 227 HAL_SRNG_CE_11_DST_STATUS = 111, 228 HAL_SRNG_CE_12_DST_STATUS = 112, 229 HAL_SRNG_CE_13_DST_STATUS = 113, 230 HAL_SRNG_CE_14_DST_STATUS = 114, 231 HAL_SRNG_CE_15_DST_STATUS = 115, 232 /* 116-119 unused */ 233 HAL_SRNG_WBM_IDLE_LINK = 120, 234 HAL_SRNG_WBM_SW_RELEASE = 121, 235 HAL_SRNG_WBM_SW1_RELEASE = 122, 236 HAL_SRNG_WBM_PPE_RELEASE = 123, 237 /* 124-127 unused */ 238 HAL_SRNG_WBM2SW0_RELEASE = 128, 239 HAL_SRNG_WBM2SW1_RELEASE = 129, 240 HAL_SRNG_WBM2SW2_RELEASE = 130, 241 HAL_SRNG_WBM2SW3_RELEASE = 131, 242 HAL_SRNG_WBM2SW4_RELEASE = 132, 243 HAL_SRNG_WBM2SW5_RELEASE = 133, 244 HAL_SRNG_WBM2SW6_RELEASE = 134, 245 HAL_SRNG_WBM_ERROR_RELEASE = 135, 246 /* 136-158 unused */ 247 HAL_SRNG_UMAC_ID_END = 159, 248 /* Common DMAC rings shared by all LMACs */ 249 HAL_SRNG_SW2RXDMA_BUF0 = 160, 250 HAL_SRNG_SW2RXDMA_BUF1 = 161, 251 HAL_SRNG_SW2RXDMA_BUF2 = 162, 252 /* 163-167 unused */ 253 HAL_SRNG_SW2RXMON_BUF0 = 168, 254 /* 169-175 unused */ 255 /* 177-183 unused */ 256 HAL_SRNG_DMAC_CMN_ID_END = 183, 257 /* LMAC rings - The following set will be replicated for each LMAC */ 258 HAL_SRNG_LMAC1_ID_START = 184, 259 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 260 #ifdef IPA_OFFLOAD 261 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1, 262 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2, 263 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 264 #else 265 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 266 #endif 267 HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 268 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF, 269 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 270 HAL_SRNG_WMAC1_RXDMA2SW0, 271 HAL_SRNG_WMAC1_RXDMA2SW1, 272 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1, 273 HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 274 #ifdef WLAN_FEATURE_CIF_CFR 275 HAL_SRNG_WIFI_POS_SRC_DMA_RING, 276 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 277 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 278 #else 279 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 280 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING1, 281 #endif 282 HAL_SRNG_WMAC1_TXMON2SW0, 283 HAL_SRNG_SW2TXMON_BUF0, 284 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_SW2TXMON_BUF0 + 2), 285 }; 286 287 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 288 #define HAL_MAX_LMACS 3 289 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 290 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 291 292 #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS) 293 294 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ 295 enum hal_ring_type { 296 REO_DST = 0, 297 REO_EXCEPTION = 1, 298 REO_REINJECT = 2, 299 REO_CMD = 3, 300 REO_STATUS = 4, 301 TCL_DATA = 5, 302 TCL_CMD_CREDIT = 6, 303 TCL_STATUS = 7, 304 CE_SRC = 8, 305 CE_DST = 9, 306 CE_DST_STATUS = 10, 307 WBM_IDLE_LINK = 11, 308 SW2WBM_RELEASE = 12, 309 WBM2SW_RELEASE = 13, 310 RXDMA_BUF = 14, 311 RXDMA_DST = 15, 312 RXDMA_MONITOR_BUF = 16, 313 RXDMA_MONITOR_STATUS = 17, 314 RXDMA_MONITOR_DST = 18, 315 RXDMA_MONITOR_DESC = 19, 316 DIR_BUF_RX_DMA_SRC = 20, 317 #ifdef WLAN_FEATURE_CIF_CFR 318 WIFI_POS_SRC, 319 #endif 320 REO2PPE, 321 PPE2TCL, 322 PPE_RELEASE, 323 TX_MONITOR_BUF, 324 TX_MONITOR_DST, 325 SW2RXDMA_NEW, 326 MAX_RING_TYPES 327 }; 328 329 enum SRNG_REGISTERS { 330 DST_HP = 0, 331 DST_TP, 332 DST_ID, 333 DST_MISC, 334 DST_HP_ADDR_LSB, 335 DST_HP_ADDR_MSB, 336 DST_MSI1_BASE_LSB, 337 DST_MSI1_BASE_MSB, 338 DST_MSI1_DATA, 339 #ifdef CONFIG_BERYLLIUM 340 DST_MSI2_BASE_LSB, 341 DST_MSI2_BASE_MSB, 342 DST_MSI2_DATA, 343 #endif 344 DST_BASE_LSB, 345 DST_BASE_MSB, 346 DST_PRODUCER_INT_SETUP, 347 #ifdef CONFIG_BERYLLIUM 348 DST_PRODUCER_INT2_SETUP, 349 #endif 350 351 SRC_HP, 352 SRC_TP, 353 SRC_ID, 354 SRC_MISC, 355 SRC_TP_ADDR_LSB, 356 SRC_TP_ADDR_MSB, 357 SRC_MSI1_BASE_LSB, 358 SRC_MSI1_BASE_MSB, 359 SRC_MSI1_DATA, 360 SRC_BASE_LSB, 361 SRC_BASE_MSB, 362 SRC_CONSUMER_INT_SETUP_IX0, 363 SRC_CONSUMER_INT_SETUP_IX1, 364 SRNG_REGISTER_MAX, 365 }; 366 367 enum hal_srng_dir { 368 HAL_SRNG_SRC_RING, 369 HAL_SRNG_DST_RING 370 }; 371 372 /** 373 * enum hal_reo_remap_reg - REO remap registers 374 * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0 375 * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1 376 * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2 377 * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3 378 */ 379 enum hal_reo_remap_reg { 380 HAL_REO_REMAP_REG_IX0, 381 HAL_REO_REMAP_REG_IX1, 382 HAL_REO_REMAP_REG_IX2, 383 HAL_REO_REMAP_REG_IX3 384 }; 385 386 /* Lock wrappers for SRNG */ 387 #define hal_srng_lock_t qdf_spinlock_t 388 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 389 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 390 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock) 391 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 392 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 393 394 struct hal_soc; 395 396 /** 397 * dp_hal_ring - opaque handle for DP HAL SRNG 398 */ 399 struct hal_ring_handle; 400 typedef struct hal_ring_handle *hal_ring_handle_t; 401 402 #define MAX_SRNG_REG_GROUPS 2 403 404 /* Hal Srng bit mask 405 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 406 */ 407 #define HAL_SRNG_FLUSH_EVENT BIT(0) 408 409 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 410 411 /** 412 * struct hal_reg_write_q_elem - delayed register write queue element 413 * @srng: hal_srng queued for a delayed write 414 * @addr: iomem address of the register 415 * @enqueue_val: register value at the time of delayed write enqueue 416 * @dequeue_val: register value at the time of delayed write dequeue 417 * @valid: whether this entry is valid or not 418 * @enqueue_time: enqueue time (qdf_log_timestamp) 419 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 420 * @dequeue_time: dequeue time (qdf_log_timestamp) 421 * @cpu_id: record cpuid when schedule work 422 */ 423 struct hal_reg_write_q_elem { 424 struct hal_srng *srng; 425 void __iomem *addr; 426 uint32_t enqueue_val; 427 uint32_t dequeue_val; 428 uint8_t valid; 429 qdf_time_t enqueue_time; 430 qdf_time_t work_scheduled_time; 431 qdf_time_t dequeue_time; 432 int cpu_id; 433 }; 434 435 /** 436 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 437 * @enqueues: writes enqueued to delayed work 438 * @dequeues: writes dequeued from delayed work (not written yet) 439 * @coalesces: writes not enqueued since srng is already queued up 440 * @direct: writes not enqueued and written to register directly 441 * @dequeue_delay: dequeue operation be delayed 442 */ 443 struct hal_reg_write_srng_stats { 444 uint32_t enqueues; 445 uint32_t dequeues; 446 uint32_t coalesces; 447 uint32_t direct; 448 uint32_t dequeue_delay; 449 }; 450 451 /** 452 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 453 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 454 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 455 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 456 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 457 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 458 */ 459 enum hal_reg_sched_delay { 460 REG_WRITE_SCHED_DELAY_SUB_100us, 461 REG_WRITE_SCHED_DELAY_SUB_1000us, 462 REG_WRITE_SCHED_DELAY_SUB_5000us, 463 REG_WRITE_SCHED_DELAY_GT_5000us, 464 REG_WRITE_SCHED_DELAY_HIST_MAX, 465 }; 466 467 /** 468 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 469 * @enqueues: writes enqueued to delayed work 470 * @dequeues: writes dequeued from delayed work (not written yet) 471 * @coalesces: writes not enqueued since srng is already queued up 472 * @direct: writes not enqueud and writted to register directly 473 * @prevent_l1_fails: prevent l1 API failed 474 * @q_depth: current queue depth in delayed register write queue 475 * @max_q_depth: maximum queue for delayed register write queue 476 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 477 * @dequeue_delay: dequeue operation be delayed 478 */ 479 struct hal_reg_write_soc_stats { 480 qdf_atomic_t enqueues; 481 uint32_t dequeues; 482 qdf_atomic_t coalesces; 483 qdf_atomic_t direct; 484 uint32_t prevent_l1_fails; 485 qdf_atomic_t q_depth; 486 uint32_t max_q_depth; 487 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 488 uint32_t dequeue_delay; 489 }; 490 #endif 491 492 struct hal_offload_info { 493 uint8_t lro_eligible; 494 uint8_t tcp_proto; 495 uint8_t tcp_pure_ack; 496 uint8_t ipv6_proto; 497 uint8_t tcp_offset; 498 uint16_t tcp_csum; 499 uint16_t tcp_win; 500 uint32_t tcp_seq_num; 501 uint32_t tcp_ack_num; 502 uint32_t flow_id; 503 }; 504 505 /* Common SRNG ring structure for source and destination rings */ 506 struct hal_srng { 507 /* Unique SRNG ring ID */ 508 uint8_t ring_id; 509 510 /* Ring initialization done */ 511 uint8_t initialized; 512 513 /* Interrupt/MSI value assigned to this ring */ 514 int irq; 515 516 /* Physical base address of the ring */ 517 qdf_dma_addr_t ring_base_paddr; 518 519 /* Virtual base address of the ring */ 520 uint32_t *ring_base_vaddr; 521 522 /* virtual address end */ 523 uint32_t *ring_vaddr_end; 524 525 /* Number of entries in ring */ 526 uint32_t num_entries; 527 528 /* Ring size */ 529 uint32_t ring_size; 530 531 /* Ring size mask */ 532 uint32_t ring_size_mask; 533 534 /* Size of ring entry */ 535 uint32_t entry_size; 536 537 /* Interrupt timer threshold – in micro seconds */ 538 uint32_t intr_timer_thres_us; 539 540 /* Interrupt batch counter threshold – in number of ring entries */ 541 uint32_t intr_batch_cntr_thres_entries; 542 543 /* Applicable only for CE dest ring */ 544 uint32_t prefetch_timer; 545 546 /* MSI Address */ 547 qdf_dma_addr_t msi_addr; 548 549 /* MSI data */ 550 uint32_t msi_data; 551 552 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 553 /* MSI2 Address */ 554 qdf_dma_addr_t msi2_addr; 555 556 /* MSI2 data */ 557 uint32_t msi2_data; 558 #endif 559 560 /* Misc flags */ 561 uint32_t flags; 562 563 /* Lock for serializing ring index updates */ 564 hal_srng_lock_t lock; 565 566 /* Start offset of SRNG register groups for this ring 567 * TBD: See if this is required - register address can be derived 568 * from ring ID 569 */ 570 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 571 572 /* Ring type/name */ 573 enum hal_ring_type ring_type; 574 575 /* Source or Destination ring */ 576 enum hal_srng_dir ring_dir; 577 578 union { 579 struct { 580 /* SW tail pointer */ 581 uint32_t tp; 582 583 /* Shadow head pointer location to be updated by HW */ 584 uint32_t *hp_addr; 585 586 /* Cached head pointer */ 587 uint32_t cached_hp; 588 589 /* Tail pointer location to be updated by SW – This 590 * will be a register address and need not be 591 * accessed through SW structure */ 592 uint32_t *tp_addr; 593 594 /* Current SW loop cnt */ 595 uint32_t loop_cnt; 596 597 /* max transfer size */ 598 uint16_t max_buffer_length; 599 600 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 601 /* near full IRQ supported */ 602 uint16_t nf_irq_support; 603 604 /* High threshold for Near full IRQ */ 605 uint16_t high_thresh; 606 #endif 607 } dst_ring; 608 609 struct { 610 /* SW head pointer */ 611 uint32_t hp; 612 613 /* SW reap head pointer */ 614 uint32_t reap_hp; 615 616 /* Shadow tail pointer location to be updated by HW */ 617 uint32_t *tp_addr; 618 619 /* Cached tail pointer */ 620 uint32_t cached_tp; 621 622 /* Head pointer location to be updated by SW – This 623 * will be a register address and need not be accessed 624 * through SW structure */ 625 uint32_t *hp_addr; 626 627 /* Low threshold – in number of ring entries */ 628 uint32_t low_threshold; 629 } src_ring; 630 } u; 631 632 struct hal_soc *hal_soc; 633 634 /* Number of times hp/tp updated in runtime resume */ 635 uint32_t flush_count; 636 /* hal srng event flag*/ 637 unsigned long srng_event; 638 /* last flushed time stamp */ 639 uint64_t last_flush_ts; 640 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 641 /* last ring desc entry cleared */ 642 uint32_t last_desc_cleared; 643 #endif 644 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 645 /* flag to indicate whether srng is already queued for delayed write */ 646 uint8_t reg_write_in_progress; 647 /* last dequeue elem time stamp */ 648 qdf_time_t last_dequeue_time; 649 650 /* srng specific delayed write stats */ 651 struct hal_reg_write_srng_stats wstats; 652 #endif 653 }; 654 655 /* HW SRNG configuration table */ 656 struct hal_hw_srng_config { 657 int start_ring_id; 658 uint16_t max_rings; 659 uint16_t entry_size; 660 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 661 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 662 uint8_t lmac_ring; 663 enum hal_srng_dir ring_dir; 664 uint32_t max_size; 665 bool nf_irq_support; 666 }; 667 668 #define MAX_SHADOW_REGISTERS 40 669 #define MAX_GENERIC_SHADOW_REG 5 670 671 /** 672 * struct shadow_reg_config - Hal soc structure that contains 673 * the list of generic shadow registers 674 * @target_register: target reg offset 675 * @shadow_config_index: shadow config index in shadow config 676 * list sent to FW 677 * @va: virtual addr of shadow reg 678 * 679 * This structure holds the generic registers that are mapped to 680 * the shadow region and holds the mapping of the target 681 * register offset to shadow config index provided to FW during 682 * init 683 */ 684 struct shadow_reg_config { 685 uint32_t target_register; 686 int shadow_config_index; 687 uint64_t va; 688 }; 689 690 /* REO parameters to be passed to hal_reo_setup */ 691 struct hal_reo_params { 692 /** rx hash steering enabled or disabled */ 693 bool rx_hash_enabled; 694 /** reo remap 0 register */ 695 uint32_t remap0; 696 /** reo remap 1 register */ 697 uint32_t remap1; 698 /** reo remap 2 register */ 699 uint32_t remap2; 700 /** fragment destination ring */ 701 uint8_t frag_dst_ring; 702 /* Destination for alternate */ 703 uint8_t alt_dst_ind_0; 704 /** padding */ 705 uint8_t padding[2]; 706 }; 707 708 /** 709 * enum hal_reo_cmd_type: Enum for REO command type 710 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 711 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 712 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 713 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked 714 * earlier with a ‘REO_FLUSH_CACHE’ command 715 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 716 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 717 */ 718 enum hal_reo_cmd_type { 719 CMD_GET_QUEUE_STATS = 0, 720 CMD_FLUSH_QUEUE = 1, 721 CMD_FLUSH_CACHE = 2, 722 CMD_UNBLOCK_CACHE = 3, 723 CMD_FLUSH_TIMEOUT_LIST = 4, 724 CMD_UPDATE_RX_REO_QUEUE = 5 725 }; 726 727 struct hal_rx_pkt_capture_flags { 728 uint8_t encrypt_type; 729 uint8_t fragment_flag; 730 uint8_t fcs_err; 731 uint32_t chan_freq; 732 uint32_t rssi_comb; 733 uint64_t tsft; 734 }; 735 736 struct hal_hw_txrx_ops { 737 /* init and setup */ 738 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 739 struct hal_srng *srng); 740 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 741 struct hal_srng *srng); 742 void (*hal_get_hw_hptp)(struct hal_soc *hal, 743 hal_ring_handle_t hal_ring_hdl, 744 uint32_t *headp, uint32_t *tailp, 745 uint8_t ring_type); 746 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams); 747 void (*hal_setup_link_idle_list)( 748 struct hal_soc *hal_soc, 749 qdf_dma_addr_t scatter_bufs_base_paddr[], 750 void *scatter_bufs_base_vaddr[], 751 uint32_t num_scatter_bufs, 752 uint32_t scatter_buf_size, 753 uint32_t last_buf_end_offset, 754 uint32_t num_entries); 755 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 756 qdf_iomem_t addr); 757 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 758 uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc); 759 void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid, 760 uint32_t ba_window_size, 761 uint32_t start_seq, void *hw_qdesc_vaddr, 762 qdf_dma_addr_t hw_qdesc_paddr, 763 int pn_type, uint8_t vdev_stats_id); 764 uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg, 765 uint8_t *ix0_map); 766 767 /* tx */ 768 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 769 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 770 uint8_t id); 771 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 772 uint8_t id, 773 uint8_t dscp); 774 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 775 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 776 uint8_t pool_id, uint32_t desc_id, 777 uint8_t type); 778 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 779 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 780 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 781 void (*hal_tx_comp_get_status)(void *desc, void *ts, 782 struct hal_soc *hal); 783 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 784 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 785 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 786 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 787 hal_ring_handle_t hal_ring_hdl); 788 uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc); 789 uint32_t (*hal_tx_get_num_ppe_vp_tbl_entries)( 790 hal_soc_handle_t hal_soc_hdl); 791 void (*hal_tx_set_ppe_cmn_cfg)(hal_soc_handle_t hal_soc_hdl, 792 union hal_tx_cmn_config_ppe *cmn_cfg); 793 void (*hal_tx_set_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl, 794 union hal_tx_ppe_vp_config *vp_cfg, 795 int ppe_vp_idx); 796 void (*hal_tx_set_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 797 uint32_t val, 798 uint8_t map_no); 799 void (*hal_tx_update_ppe_pri2tid)(hal_soc_handle_t hal_soc_hdl, 800 uint8_t pri, 801 uint8_t tid); 802 void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl); 803 void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl, 804 bool value, uint8_t ppe_vp_idx); 805 806 /* rx */ 807 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 808 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 809 struct mon_rx_status *rs); 810 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 811 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 812 void *ppdu_info_handle); 813 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 814 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 815 uint8_t dbg_level); 816 uint32_t (*hal_get_link_desc_size)(void); 817 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 818 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 819 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 820 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 821 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 822 void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b, 823 void *h); 824 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 825 void *ppdu_info, 826 hal_soc_handle_t hal_soc_hdl, 827 qdf_nbuf_t nbuf); 828 829 void (*hal_rx_wbm_rel_buf_paddr_get)(hal_ring_desc_t rx_desc, 830 struct hal_buf_info *buf_info); 831 832 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 833 void *wbm_er_info); 834 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 835 uint8_t dbg_level); 836 837 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 838 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 839 uint8_t id); 840 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 841 842 /* rx */ 843 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 844 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 845 uint8_t (*hal_rx_msdu_end_is_tkip_mic_err)(uint8_t *buf); 846 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 847 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 848 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 849 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 850 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 851 void (*hal_rx_print_pn)(uint8_t *buf); 852 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 853 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 854 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 855 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 856 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 857 uint32_t (*hal_rx_mpdu_peer_meta_data_get)(uint8_t *buf); 858 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 859 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 860 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 861 QDF_STATUS 862 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 863 QDF_STATUS 864 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 865 QDF_STATUS 866 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 867 QDF_STATUS 868 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 869 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 870 bool (*hal_rx_is_unicast)(uint8_t *buf); 871 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 872 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 873 void *rxdma_dst_ring_desc); 874 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 875 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 876 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 877 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 878 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 879 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 880 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 881 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 882 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 883 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 884 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 885 void (*hal_reo_config)(struct hal_soc *soc, 886 uint32_t reg_val, 887 struct hal_reo_params *reo_params); 888 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 889 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 890 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 891 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 892 bool (*hal_rx_msdu_cce_match_get)(uint8_t *buf); 893 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 894 void 895 (*hal_rx_msdu_get_flow_params)( 896 uint8_t *buf, 897 bool *flow_invalid, 898 bool *flow_timeout, 899 uint32_t *flow_index); 900 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 901 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 902 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 903 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 904 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 905 void *msdu_pkt_metadata); 906 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 907 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 908 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 909 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 910 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 911 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 912 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 913 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 914 hal_rx_mon_desc_info_t mon_desc_info); 915 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 916 uint32_t (*hal_rx_msdu_end_offset_get)(void); 917 uint32_t (*hal_rx_attn_offset_get)(void); 918 uint32_t (*hal_rx_msdu_start_offset_get)(void); 919 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 920 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 921 uint32_t (*hal_rx_pkt_tlv_offset_get)(void); 922 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 923 uint32_t table_offset, 924 uint8_t *rx_flow); 925 void * (*hal_rx_flow_get_tuple_info)(uint8_t *rx_fst, 926 uint32_t hal_hash, 927 uint8_t *tuple_info); 928 QDF_STATUS (*hal_rx_flow_delete_entry)(uint8_t *fst, 929 void *fse); 930 uint32_t (*hal_rx_fst_get_fse_size)(void); 931 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 932 uint32_t num_rings, 933 uint32_t *remap1, 934 uint32_t *remap2); 935 void (*hal_compute_reo_remap_ix0)(uint32_t *remap0); 936 uint32_t (*hal_rx_flow_setup_cmem_fse)( 937 struct hal_soc *soc, uint32_t cmem_ba, 938 uint32_t table_offset, uint8_t *rx_flow); 939 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc, 940 uint32_t fse_offset); 941 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc, 942 uint32_t fse_offset, 943 uint32_t *fse, qdf_size_t len); 944 945 void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset, 946 uint32_t value); 947 948 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, 949 uint32_t *reo_destination_indication); 950 uint8_t (*hal_tx_get_num_tcl_banks)(void); 951 uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid); 952 uint16_t (*hal_get_rx_max_ba_window)(int tid); 953 954 void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie, 955 qdf_dma_addr_t link_desc_paddr, 956 uint8_t bm_id); 957 void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl, 958 hal_ring_handle_t hal_ring_hdl); 959 void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr); 960 void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 961 uint8_t ac, uint32_t *value); 962 void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 963 uint8_t ac, uint32_t value); 964 uint32_t (*hal_get_reo_reg_base_offset)(void); 965 void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size, 966 uint16_t *rx_mon_pkt_tlv_size); 967 uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf); 968 uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr); 969 void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl, 970 uint8_t *buf, uint8_t dbg_level); 971 int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv, 972 struct hal_offload_info *offload_info); 973 uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf); 974 uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf); 975 uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf); 976 uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf); 977 int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params); 978 int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset, 979 uint32_t *l4_hdr_offset); 980 uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf); 981 uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf); 982 void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num); 983 void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn); 984 uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf); 985 uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl, 986 void *msdu_link_desc); 987 void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 988 void *msdu_desc_info, uint32_t dst_ind, 989 uint32_t nbuf_len); 990 void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 991 void *mpdu_desc_info, uint32_t seq_no); 992 uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf); 993 uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf); 994 uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf); 995 uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf); 996 uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf); 997 uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf); 998 uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf); 999 uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf); 1000 1001 uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc); 1002 uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc); 1003 void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl, 1004 void *src_srng_desc, 1005 hal_buff_addrinfo_t buf_addr_info, 1006 uint8_t bm_action); 1007 1008 void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl, 1009 hal_buf_info_t buf_info_hdl); 1010 void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc, 1011 struct hal_buf_info *buf_info); 1012 void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry, 1013 qdf_dma_addr_t paddr, 1014 uint32_t cookie, uint8_t manager); 1015 uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl); 1016 uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc); 1017 void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr, 1018 uint32_t *ip_csum_err, 1019 uint32_t *tcp_udp_csum_err); 1020 void (*hal_rx_mpdu_desc_info_get)(void *desc_addr, 1021 void *mpdu_desc_info_hdl); 1022 uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc); 1023 uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc); 1024 bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf); 1025 uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr); 1026 uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr); 1027 void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr, 1028 struct hal_rx_pkt_capture_flags *flags); 1029 uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr); 1030 uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr); 1031 void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf, 1032 uint8_t *priv_data, 1033 uint32_t len); 1034 void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf, 1035 uint8_t *priv_data, 1036 uint32_t len); 1037 void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len); 1038 void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf, 1039 void *mpdu_desc_info_hdl); 1040 uint8_t *(*hal_get_reo_ent_desc_qdesc_addr)(uint8_t *desc); 1041 uint64_t (*hal_rx_get_qdesc_addr)(uint8_t *dst_ring_desc, 1042 uint8_t *buf); 1043 void (*hal_set_reo_ent_desc_reo_dest_ind)(uint8_t *desc, 1044 uint32_t dst_ind); 1045 1046 /* REO CMD and STATUS */ 1047 int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl, 1048 hal_ring_handle_t hal_ring_hdl, 1049 enum hal_reo_cmd_type cmd, 1050 void *params); 1051 QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl, 1052 hal_ring_desc_t reo_desc, 1053 void *st_handle, 1054 uint32_t tlv, int *num_ref); 1055 uint8_t (*hal_get_tlv_hdr_size)(void); 1056 uint8_t (*hal_get_idle_link_bm_id)(uint8_t chip_id); 1057 1058 /* TX MONITOR */ 1059 #ifdef QCA_MONITOR_2_0_SUPPORT 1060 uint32_t (*hal_txmon_status_parse_tlv)(void *data_ppdu_info, 1061 void *prot_ppdu_info, 1062 void *data_status_info, 1063 void *prot_status_info, 1064 void *tx_tlv_hdr, 1065 qdf_frag_t status_frag); 1066 uint32_t (*hal_txmon_status_get_num_users)(void *tx_tlv_hdr, 1067 uint8_t *num_users); 1068 QDF_STATUS (*hal_txmon_status_free_buffer)(qdf_frag_t status_frag, 1069 uint32_t end_offset); 1070 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1071 void (*hal_reo_shared_qaddr_setup)(hal_soc_handle_t hal_soc_hdl); 1072 void (*hal_reo_shared_qaddr_init)(hal_soc_handle_t hal_soc_hdl); 1073 void (*hal_reo_shared_qaddr_detach)(hal_soc_handle_t hal_soc_hdl); 1074 void (*hal_reo_shared_qaddr_write)(hal_soc_handle_t hal_soc_hdl, 1075 uint16_t peer_id, 1076 int tid, 1077 qdf_dma_addr_t hw_qdesc_paddr); 1078 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1079 uint8_t (*hal_get_first_wow_wakeup_packet)(uint8_t *buf); 1080 #endif 1081 void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl); 1082 }; 1083 1084 /** 1085 * struct hal_soc_stats - Hal layer stats 1086 * @reg_write_fail: number of failed register writes 1087 * @wstats: delayed register write stats 1088 * @shadow_reg_write_fail: shadow reg write failure stats 1089 * @shadow_reg_write_succ: shadow reg write success stats 1090 * 1091 * This structure holds all the statistics at HAL layer. 1092 */ 1093 struct hal_soc_stats { 1094 uint32_t reg_write_fail; 1095 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1096 struct hal_reg_write_soc_stats wstats; 1097 #endif 1098 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1099 uint32_t shadow_reg_write_fail; 1100 uint32_t shadow_reg_write_succ; 1101 #endif 1102 }; 1103 1104 #ifdef ENABLE_HAL_REG_WR_HISTORY 1105 /* The history size should always be a power of 2 */ 1106 #define HAL_REG_WRITE_HIST_SIZE 8 1107 1108 /** 1109 * struct hal_reg_write_fail_entry - Record of 1110 * register write which failed. 1111 * @timestamp: timestamp of reg write failure 1112 * @reg_offset: offset of register where the write failed 1113 * @write_val: the value which was to be written 1114 * @read_val: the value read back from the register after write 1115 */ 1116 struct hal_reg_write_fail_entry { 1117 uint64_t timestamp; 1118 uint32_t reg_offset; 1119 uint32_t write_val; 1120 uint32_t read_val; 1121 }; 1122 1123 /** 1124 * struct hal_reg_write_fail_history - Hal layer history 1125 * of all the register write failures. 1126 * @index: index to add the new record 1127 * @record: array of all the records in history 1128 * 1129 * This structure holds the history of register write 1130 * failures at HAL layer. 1131 */ 1132 struct hal_reg_write_fail_history { 1133 qdf_atomic_t index; 1134 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 1135 }; 1136 #endif 1137 1138 /** 1139 * struct reo_queue_ref_table - Reo qref LUT addr 1140 * @mlo_reo_qref_table_vaddr: MLO table vaddr 1141 * @non_mlo_reo_qref_table_vaddr: Non MLO table vaddr 1142 * @mlo_reo_qref_table_paddr: MLO table paddr 1143 * @non_mlo_reo_qref_table_paddr: Non MLO table paddr 1144 * @reo_qref_table_en: Enable flag 1145 */ 1146 struct reo_queue_ref_table { 1147 uint64_t *mlo_reo_qref_table_vaddr; 1148 uint64_t *non_mlo_reo_qref_table_vaddr; 1149 qdf_dma_addr_t mlo_reo_qref_table_paddr; 1150 qdf_dma_addr_t non_mlo_reo_qref_table_paddr; 1151 uint8_t reo_qref_table_en; 1152 }; 1153 1154 /** 1155 * union hal_shadow_reg_cfg - Shadow register config 1156 * @addr: Place holder where shadow address is saved 1157 * @v2: shadow config v2 format 1158 * @v3: shadow config v3 format 1159 */ 1160 union hal_shadow_reg_cfg { 1161 uint32_t addr; 1162 struct pld_shadow_reg_v2_cfg v2; 1163 #ifdef CONFIG_SHADOW_V3 1164 struct pld_shadow_reg_v3_cfg v3; 1165 #endif 1166 }; 1167 1168 /** 1169 * struct hal_soc - HAL context to be used to access SRNG APIs 1170 * (currently used by data path and 1171 * transport (CE) modules) 1172 * @list_shadow_reg_config: array of generic regs mapped to 1173 * shadow regs 1174 * @num_generic_shadow_regs_configured: number of generic regs 1175 * mapped to shadow regs 1176 */ 1177 struct hal_soc { 1178 /* HIF handle to access HW registers */ 1179 struct hif_opaque_softc *hif_handle; 1180 1181 /* QDF device handle */ 1182 qdf_device_t qdf_dev; 1183 1184 /* Device base address */ 1185 void *dev_base_addr; 1186 /* Device base address for ce - qca5018 target */ 1187 void *dev_base_addr_ce; 1188 1189 /* HAL internal state for all SRNG rings. 1190 * TODO: See if this is required 1191 */ 1192 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 1193 1194 /* Remote pointer memory for HW/FW updates */ 1195 uint32_t *shadow_rdptr_mem_vaddr; 1196 qdf_dma_addr_t shadow_rdptr_mem_paddr; 1197 1198 /* Shared memory for ring pointer updates from host to FW */ 1199 uint32_t *shadow_wrptr_mem_vaddr; 1200 qdf_dma_addr_t shadow_wrptr_mem_paddr; 1201 1202 /* REO blocking resource index */ 1203 uint8_t reo_res_bitmap; 1204 uint8_t index; 1205 uint32_t target_type; 1206 1207 /* shadow register configuration */ 1208 union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS]; 1209 int num_shadow_registers_configured; 1210 bool use_register_windowing; 1211 uint32_t register_window; 1212 qdf_spinlock_t register_access_lock; 1213 1214 /* Static window map configuration for multiple window write*/ 1215 bool static_window_map; 1216 1217 /* srng table */ 1218 struct hal_hw_srng_config *hw_srng_table; 1219 int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX]; 1220 struct hal_hw_txrx_ops *ops; 1221 1222 /* Indicate srngs initialization */ 1223 bool init_phase; 1224 /* Hal level stats */ 1225 struct hal_soc_stats stats; 1226 #ifdef ENABLE_HAL_REG_WR_HISTORY 1227 struct hal_reg_write_fail_history *reg_wr_fail_hist; 1228 #endif 1229 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1230 /* queue(array) to hold register writes */ 1231 struct hal_reg_write_q_elem *reg_write_queue; 1232 /* delayed work to be queued into workqueue */ 1233 qdf_work_t reg_write_work; 1234 /* workqueue for delayed register writes */ 1235 qdf_workqueue_t *reg_write_wq; 1236 /* write index used by caller to enqueue delayed work */ 1237 qdf_atomic_t write_idx; 1238 /* read index used by worker thread to dequeue/write registers */ 1239 uint32_t read_idx; 1240 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */ 1241 qdf_atomic_t active_work_cnt; 1242 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1243 struct shadow_reg_config 1244 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; 1245 int num_generic_shadow_regs_configured; 1246 #endif 1247 /* flag to indicate cmn dmac rings in berryllium */ 1248 bool dmac_cmn_src_rxbuf_ring; 1249 /* Reo queue ref table items */ 1250 struct reo_queue_ref_table reo_qref; 1251 }; 1252 1253 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 1254 /** 1255 * hal_delayed_reg_write() - delayed regiter write 1256 * @hal_soc: HAL soc handle 1257 * @srng: hal srng 1258 * @addr: iomem address 1259 * @value: value to be written 1260 * 1261 * Return: none 1262 */ 1263 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1264 struct hal_srng *srng, 1265 void __iomem *addr, 1266 uint32_t value); 1267 #endif 1268 1269 void hal_qca6750_attach(struct hal_soc *hal_soc); 1270 void hal_qca6490_attach(struct hal_soc *hal_soc); 1271 void hal_qca6390_attach(struct hal_soc *hal_soc); 1272 void hal_qca6290_attach(struct hal_soc *hal_soc); 1273 void hal_qca8074_attach(struct hal_soc *hal_soc); 1274 void hal_kiwi_attach(struct hal_soc *hal_soc); 1275 void hal_qcn9224_attach(struct hal_soc *hal_soc); 1276 /* 1277 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 1278 * dp_hal_soc handle type 1279 * @hal_soc - hal_soc type 1280 * 1281 * Return: hal_soc_handle_t type 1282 */ 1283 static inline 1284 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 1285 { 1286 return (hal_soc_handle_t)hal_soc; 1287 } 1288 1289 /* 1290 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 1291 * dp_hal_ring handle type 1292 * @hal_srng - hal_srng type 1293 * 1294 * Return: hal_ring_handle_t type 1295 */ 1296 static inline 1297 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 1298 { 1299 return (hal_ring_handle_t)hal_srng; 1300 } 1301 1302 /* 1303 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 1304 * @hal_ring - hal_ring_handle_t type 1305 * 1306 * Return: hal_srng pointer type 1307 */ 1308 static inline 1309 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 1310 { 1311 return (struct hal_srng *)hal_ring; 1312 } 1313 1314 /* Size of REO queue reference table in Host 1315 * 2k peers * 17 tids * 8bytes(rx_reo_queue_reference) 1316 * = 278528 bytes 1317 */ 1318 #define REO_QUEUE_REF_NON_ML_TABLE_SIZE 278528 1319 /* Calculated based on 512 MLO peers */ 1320 #define REO_QUEUE_REF_ML_TABLE_SIZE 69632 1321 #define HAL_ML_PEER_ID_START 0x2000 1322 #define HAL_PEER_ID_IS_MLO(peer_id) ((peer_id) & HAL_ML_PEER_ID_START) 1323 1324 /* 1325 * REO2PPE destination indication 1326 */ 1327 #define REO2PPE_DST_IND 11 1328 1329 /** 1330 * enum hal_pkt_type - Type of packet type reported by HW 1331 * @HAL_DOT11A: 802.11a PPDU type 1332 * @HAL_DOT11B: 802.11b PPDU type 1333 * @HAL_DOT11N_MM: 802.11n Mixed Mode PPDU type 1334 * @HAL_DOT11AC: 802.11ac PPDU type 1335 * @HAL_DOT11AX: 802.11ax PPDU type 1336 * @HAL_DOT11BA: 802.11ba (WUR) PPDU type 1337 * @HAL_DOT11BE: 802.11be PPDU type 1338 * @HAL_DOT11AZ: 802.11az (ranging) PPDU type 1339 * @HAL_DOT11N_GF: 802.11n Green Field PPDU type 1340 * 1341 * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data) 1342 * or WBM2SW ring entry's descriptor (TX data completion) 1343 */ 1344 enum hal_pkt_type { 1345 HAL_DOT11A = 0, 1346 HAL_DOT11B = 1, 1347 HAL_DOT11N_MM = 2, 1348 HAL_DOT11AC = 3, 1349 HAL_DOT11AX = 4, 1350 HAL_DOT11BA = 5, 1351 HAL_DOT11BE = 6, 1352 HAL_DOT11AZ = 7, 1353 HAL_DOT11N_GF = 8, 1354 HAL_DOT11_MAX, 1355 }; 1356 1357 #endif /* _HAL_INTERNAL_H_ */ 1358