1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_atomic.h" 24 #include "qdf_lock.h" 25 #include "qdf_mem.h" 26 #include "qdf_nbuf.h" 27 #include "pld_common.h" 28 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 29 defined(FEATURE_HAL_DELAYED_REG_WRITE_V2) 30 #include "qdf_defer.h" 31 #include "qdf_timer.h" 32 #endif 33 34 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params) 35 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_HAL, params) 36 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_HAL, params) 37 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HAL, params) 38 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 39 40 #define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params) 41 #define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params) 42 #define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params) 43 #define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params) 44 #define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params) 45 46 #ifdef ENABLE_VERBOSE_DEBUG 47 extern bool is_hal_verbose_debug_enabled; 48 #define hal_verbose_debug(params...) \ 49 if (unlikely(is_hal_verbose_debug_enabled)) \ 50 do {\ 51 QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params); \ 52 } while (0) 53 #define hal_verbose_hex_dump(params...) \ 54 if (unlikely(is_hal_verbose_debug_enabled)) \ 55 do {\ 56 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, \ 57 QDF_TRACE_LEVEL_DEBUG, \ 58 params); \ 59 } while (0) 60 #else 61 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HAL, params) 62 #define hal_verbose_hex_dump(params...) \ 63 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, \ 64 params) 65 #endif 66 67 /* 68 * Given the offset of a field in bytes, returns uint8_t * 69 */ 70 #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ 71 (((uint8_t *)(_ptr)) + (_off_in_bytes)) 72 73 /* 74 * Given the offset of a field in bytes, returns uint32_t * 75 */ 76 #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ 77 (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) 78 79 /* 80 * Given the offset of a field in bytes, returns uint64_t * 81 */ 82 #define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \ 83 (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3)) 84 85 #define _HAL_MS(_word, _mask, _shift) \ 86 (((_word) & (_mask)) >> (_shift)) 87 88 /* 89 * Get number of QWORDS possible for num. 90 * Its the caller's duty to make sure num is a multiple of QWORD (8) 91 */ 92 #define HAL_GET_NUM_QWORDS(num) ((num) >> 3) 93 94 /* 95 * Get number of DWORDS possible for num. 96 * Its the caller's duty to make sure num is a multiple of DWORD (8) 97 */ 98 #define HAL_GET_NUM_DWORDS(num) ((num) >> 2) 99 100 /* 101 * dp_hal_soc - opaque handle for DP HAL soc 102 */ 103 struct hal_soc_handle; 104 typedef struct hal_soc_handle *hal_soc_handle_t; 105 106 /** 107 * hal_ring_desc - opaque handle for DP ring descriptor 108 */ 109 struct hal_ring_desc; 110 typedef struct hal_ring_desc *hal_ring_desc_t; 111 112 /** 113 * hal_link_desc - opaque handle for DP link descriptor 114 */ 115 struct hal_link_desc; 116 typedef struct hal_link_desc *hal_link_desc_t; 117 118 /** 119 * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor 120 */ 121 struct hal_rxdma_desc; 122 typedef struct hal_rxdma_desc *hal_rxdma_desc_t; 123 124 /** 125 * hal_buff_addrinfo - opaque handle for DP buffer address info 126 */ 127 struct hal_buff_addrinfo; 128 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; 129 130 /** 131 * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info 132 */ 133 struct hal_rx_mon_desc_info; 134 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; 135 136 struct hal_buf_info; 137 typedef struct hal_buf_info *hal_buf_info_t; 138 139 struct rx_msdu_desc_info; 140 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t; 141 142 /* TBD: This should be movded to shared HW header file */ 143 enum hal_srng_ring_id { 144 /* UMAC rings */ 145 HAL_SRNG_REO2SW0 = 0, 146 HAL_SRNG_REO2SW1 = 1, 147 HAL_SRNG_REO2SW2 = 2, 148 HAL_SRNG_REO2SW3 = 3, 149 HAL_SRNG_REO2SW4 = 4, 150 HAL_SRNG_REO2SW5 = 5, 151 HAL_SRNG_REO2SW6 = 6, 152 HAL_SRNG_REO2SW7 = 7, 153 HAL_SRNG_REO2SW8 = 8, 154 HAL_SRNG_REO2TCL = 9, 155 HAL_SRNG_REO2PPE = 10, 156 /* 11-15 unused */ 157 HAL_SRNG_SW2REO = 16, 158 HAL_SRNG_SW2REO1 = 17, 159 HAL_SRNG_SW2REO2 = 18, 160 HAL_SRNG_SW2REO3 = 19, 161 HAL_SRNG_REO_CMD = 20, 162 HAL_SRNG_REO_STATUS = 21, 163 /* 22-23 unused */ 164 HAL_SRNG_SW2TCL1 = 24, 165 HAL_SRNG_SW2TCL2 = 25, 166 HAL_SRNG_SW2TCL3 = 26, 167 HAL_SRNG_SW2TCL4 = 27, 168 HAL_SRNG_SW2TCL5 = 28, 169 HAL_SRNG_SW2TCL6 = 29, 170 HAL_SRNG_PPE2TCL1 = 30, 171 /* 31-39 unused */ 172 HAL_SRNG_SW2TCL_CMD = 40, 173 HAL_SRNG_TCL_STATUS = 41, 174 HAL_SRNG_SW2TCL_CREDIT = 42, 175 /* 43-63 unused */ 176 HAL_SRNG_CE_0_SRC = 64, 177 HAL_SRNG_CE_1_SRC = 65, 178 HAL_SRNG_CE_2_SRC = 66, 179 HAL_SRNG_CE_3_SRC = 67, 180 HAL_SRNG_CE_4_SRC = 68, 181 HAL_SRNG_CE_5_SRC = 69, 182 HAL_SRNG_CE_6_SRC = 70, 183 HAL_SRNG_CE_7_SRC = 71, 184 HAL_SRNG_CE_8_SRC = 72, 185 HAL_SRNG_CE_9_SRC = 73, 186 HAL_SRNG_CE_10_SRC = 74, 187 HAL_SRNG_CE_11_SRC = 75, 188 HAL_SRNG_CE_12_SRC = 76, 189 HAL_SRNG_CE_13_SRC = 77, 190 HAL_SRNG_CE_14_SRC = 78, 191 HAL_SRNG_CE_15_SRC = 79, 192 /* 80 */ 193 HAL_SRNG_CE_0_DST = 81, 194 HAL_SRNG_CE_1_DST = 82, 195 HAL_SRNG_CE_2_DST = 83, 196 HAL_SRNG_CE_3_DST = 84, 197 HAL_SRNG_CE_4_DST = 85, 198 HAL_SRNG_CE_5_DST = 86, 199 HAL_SRNG_CE_6_DST = 87, 200 HAL_SRNG_CE_7_DST = 89, 201 HAL_SRNG_CE_8_DST = 90, 202 HAL_SRNG_CE_9_DST = 91, 203 HAL_SRNG_CE_10_DST = 92, 204 HAL_SRNG_CE_11_DST = 93, 205 HAL_SRNG_CE_12_DST = 94, 206 HAL_SRNG_CE_13_DST = 95, 207 HAL_SRNG_CE_14_DST = 96, 208 HAL_SRNG_CE_15_DST = 97, 209 /* 98-99 unused */ 210 HAL_SRNG_CE_0_DST_STATUS = 100, 211 HAL_SRNG_CE_1_DST_STATUS = 101, 212 HAL_SRNG_CE_2_DST_STATUS = 102, 213 HAL_SRNG_CE_3_DST_STATUS = 103, 214 HAL_SRNG_CE_4_DST_STATUS = 104, 215 HAL_SRNG_CE_5_DST_STATUS = 105, 216 HAL_SRNG_CE_6_DST_STATUS = 106, 217 HAL_SRNG_CE_7_DST_STATUS = 107, 218 HAL_SRNG_CE_8_DST_STATUS = 108, 219 HAL_SRNG_CE_9_DST_STATUS = 109, 220 HAL_SRNG_CE_10_DST_STATUS = 110, 221 HAL_SRNG_CE_11_DST_STATUS = 111, 222 HAL_SRNG_CE_12_DST_STATUS = 112, 223 HAL_SRNG_CE_13_DST_STATUS = 113, 224 HAL_SRNG_CE_14_DST_STATUS = 114, 225 HAL_SRNG_CE_15_DST_STATUS = 115, 226 /* 116-119 unused */ 227 HAL_SRNG_WBM_IDLE_LINK = 120, 228 HAL_SRNG_WBM_SW_RELEASE = 121, 229 HAL_SRNG_WBM_SW1_RELEASE = 122, 230 HAL_SRNG_WBM_PPE_RELEASE = 123, 231 /* 124-127 unused */ 232 HAL_SRNG_WBM2SW0_RELEASE = 128, 233 HAL_SRNG_WBM2SW1_RELEASE = 129, 234 HAL_SRNG_WBM2SW2_RELEASE = 130, 235 HAL_SRNG_WBM2SW3_RELEASE = 131, 236 HAL_SRNG_WBM2SW4_RELEASE = 132, 237 HAL_SRNG_WBM2SW5_RELEASE = 133, 238 HAL_SRNG_WBM2SW6_RELEASE = 134, 239 HAL_SRNG_WBM_ERROR_RELEASE = 135, 240 /* 136-158 unused */ 241 HAL_SRNG_UMAC_ID_END = 159, 242 /* Common DMAC rings shared by all LMACs */ 243 HAL_SRNG_SW2RXDMA_BUF0 = 160, 244 HAL_SRNG_SW2RXDMA_BUF1 = 161, 245 HAL_SRNG_SW2RXDMA_BUF2 = 162, 246 /* 163-167 unused */ 247 HAL_SRNG_SW2RXMON_BUF0 = 168, 248 /* 169-175 unused */ 249 HAL_SRNG_SW2TXMON_BUF0 = 176, 250 /* 177-183 unused */ 251 HAL_SRNG_DMAC_CMN_ID_END = 183, 252 /* LMAC rings - The following set will be replicated for each LMAC */ 253 HAL_SRNG_LMAC1_ID_START = 184, 254 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 255 #ifdef IPA_OFFLOAD 256 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1, 257 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2, 258 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 259 #else 260 HAL_SRNG_WMAC1_SW2RXDMA1_BUF, 261 #endif 262 HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 263 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF, 264 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 265 HAL_SRNG_WMAC1_RXDMA2SW0, 266 HAL_SRNG_WMAC1_RXDMA2SW1, 267 HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1, 268 HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 269 #ifdef WLAN_FEATURE_CIF_CFR 270 HAL_SRNG_WIFI_POS_SRC_DMA_RING, 271 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 272 #else 273 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 274 #endif 275 HAL_SRNG_WMAC1_TXMON2SW0, 276 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_WMAC1_TXMON2SW0 + 3), 277 }; 278 279 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 280 #define HAL_MAX_LMACS 3 281 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 282 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 283 284 #define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS) 285 286 /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ 287 enum hal_ring_type { 288 REO_DST = 0, 289 REO_EXCEPTION = 1, 290 REO_REINJECT = 2, 291 REO_CMD = 3, 292 REO_STATUS = 4, 293 TCL_DATA = 5, 294 TCL_CMD_CREDIT = 6, 295 TCL_STATUS = 7, 296 CE_SRC = 8, 297 CE_DST = 9, 298 CE_DST_STATUS = 10, 299 WBM_IDLE_LINK = 11, 300 SW2WBM_RELEASE = 12, 301 WBM2SW_RELEASE = 13, 302 RXDMA_BUF = 14, 303 RXDMA_DST = 15, 304 RXDMA_MONITOR_BUF = 16, 305 RXDMA_MONITOR_STATUS = 17, 306 RXDMA_MONITOR_DST = 18, 307 RXDMA_MONITOR_DESC = 19, 308 DIR_BUF_RX_DMA_SRC = 20, 309 #ifdef WLAN_FEATURE_CIF_CFR 310 WIFI_POS_SRC, 311 #endif 312 REO2PPE, 313 PPE2TCL, 314 PPE_RELEASE, 315 TX_MONITOR_BUF, 316 TX_MONITOR_DST, 317 SW2RXDMA_NEW, 318 MAX_RING_TYPES 319 }; 320 321 enum SRNG_REGISTERS { 322 DST_HP = 0, 323 DST_TP, 324 DST_ID, 325 DST_MISC, 326 DST_HP_ADDR_LSB, 327 DST_HP_ADDR_MSB, 328 DST_MSI1_BASE_LSB, 329 DST_MSI1_BASE_MSB, 330 DST_MSI1_DATA, 331 #ifdef CONFIG_BERYLLIUM 332 DST_MSI2_BASE_LSB, 333 DST_MSI2_BASE_MSB, 334 DST_MSI2_DATA, 335 #endif 336 DST_BASE_LSB, 337 DST_BASE_MSB, 338 DST_PRODUCER_INT_SETUP, 339 #ifdef CONFIG_BERYLLIUM 340 DST_PRODUCER_INT2_SETUP, 341 #endif 342 343 SRC_HP, 344 SRC_TP, 345 SRC_ID, 346 SRC_MISC, 347 SRC_TP_ADDR_LSB, 348 SRC_TP_ADDR_MSB, 349 SRC_MSI1_BASE_LSB, 350 SRC_MSI1_BASE_MSB, 351 SRC_MSI1_DATA, 352 SRC_BASE_LSB, 353 SRC_BASE_MSB, 354 SRC_CONSUMER_INT_SETUP_IX0, 355 SRC_CONSUMER_INT_SETUP_IX1, 356 SRNG_REGISTER_MAX, 357 }; 358 359 enum hal_srng_dir { 360 HAL_SRNG_SRC_RING, 361 HAL_SRNG_DST_RING 362 }; 363 364 /** 365 * enum hal_reo_remap_reg - REO remap registers 366 * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0 367 * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1 368 * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2 369 * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3 370 */ 371 enum hal_reo_remap_reg { 372 HAL_REO_REMAP_REG_IX0, 373 HAL_REO_REMAP_REG_IX1, 374 HAL_REO_REMAP_REG_IX2, 375 HAL_REO_REMAP_REG_IX3 376 }; 377 378 /* Lock wrappers for SRNG */ 379 #define hal_srng_lock_t qdf_spinlock_t 380 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 381 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 382 #define SRNG_TRY_LOCK(_lock) qdf_spin_trylock_bh(_lock) 383 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 384 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 385 386 struct hal_soc; 387 388 /** 389 * dp_hal_ring - opaque handle for DP HAL SRNG 390 */ 391 struct hal_ring_handle; 392 typedef struct hal_ring_handle *hal_ring_handle_t; 393 394 #define MAX_SRNG_REG_GROUPS 2 395 396 /* Hal Srng bit mask 397 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 398 */ 399 #define HAL_SRNG_FLUSH_EVENT BIT(0) 400 401 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 402 defined(FEATURE_HAL_DELAYED_REG_WRITE_V2) 403 404 /** 405 * struct hal_reg_write_q_elem - delayed register write queue element 406 * @srng: hal_srng queued for a delayed write 407 * @addr: iomem address of the register 408 * @enqueue_val: register value at the time of delayed write enqueue 409 * @dequeue_val: register value at the time of delayed write dequeue 410 * @valid: whether this entry is valid or not 411 * @enqueue_time: enqueue time (qdf_log_timestamp) 412 * @work_scheduled_time: work scheduled time (qdf_log_timestamp) 413 * @dequeue_time: dequeue time (qdf_log_timestamp) 414 */ 415 struct hal_reg_write_q_elem { 416 struct hal_srng *srng; 417 void __iomem *addr; 418 uint32_t enqueue_val; 419 uint32_t dequeue_val; 420 uint8_t valid; 421 qdf_time_t enqueue_time; 422 qdf_time_t work_scheduled_time; 423 qdf_time_t dequeue_time; 424 }; 425 426 /** 427 * struct hal_reg_write_srng_stats - srng stats to keep track of register writes 428 * @enqueues: writes enqueued to delayed work 429 * @dequeues: writes dequeued from delayed work (not written yet) 430 * @coalesces: writes not enqueued since srng is already queued up 431 * @direct: writes not enqueued and written to register directly 432 * @dequeue_delay: dequeue operation be delayed 433 */ 434 struct hal_reg_write_srng_stats { 435 uint32_t enqueues; 436 uint32_t dequeues; 437 uint32_t coalesces; 438 uint32_t direct; 439 uint32_t dequeue_delay; 440 }; 441 442 /** 443 * enum hal_reg_sched_delay - ENUM for write sched delay histogram 444 * @REG_WRITE_SCHED_DELAY_SUB_100us: index for delay < 100us 445 * @REG_WRITE_SCHED_DELAY_SUB_1000us: index for delay < 1000us 446 * @REG_WRITE_SCHED_DELAY_SUB_5000us: index for delay < 5000us 447 * @REG_WRITE_SCHED_DELAY_GT_5000us: index for delay >= 5000us 448 * @REG_WRITE_SCHED_DELAY_HIST_MAX: Max value (nnsize of histogram array) 449 */ 450 enum hal_reg_sched_delay { 451 REG_WRITE_SCHED_DELAY_SUB_100us, 452 REG_WRITE_SCHED_DELAY_SUB_1000us, 453 REG_WRITE_SCHED_DELAY_SUB_5000us, 454 REG_WRITE_SCHED_DELAY_GT_5000us, 455 REG_WRITE_SCHED_DELAY_HIST_MAX, 456 }; 457 458 /** 459 * struct hal_reg_write_soc_stats - soc stats to keep track of register writes 460 * @enqueues: writes enqueued to delayed work 461 * @dequeues: writes dequeued from delayed work (not written yet) 462 * @coalesces: writes not enqueued since srng is already queued up 463 * @direct: writes not enqueud and writted to register directly 464 * @prevent_l1_fails: prevent l1 API failed 465 * @q_depth: current queue depth in delayed register write queue 466 * @max_q_depth: maximum queue for delayed register write queue 467 * @sched_delay: = kernel work sched delay + bus wakeup delay, histogram 468 * @dequeue_delay: dequeue operation be delayed 469 */ 470 struct hal_reg_write_soc_stats { 471 qdf_atomic_t enqueues; 472 uint32_t dequeues; 473 qdf_atomic_t coalesces; 474 qdf_atomic_t direct; 475 uint32_t prevent_l1_fails; 476 qdf_atomic_t q_depth; 477 uint32_t max_q_depth; 478 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 479 uint32_t dequeue_delay; 480 }; 481 482 #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2 483 struct hal_reg_write_tcl_stats { 484 uint32_t wq_delayed; 485 uint32_t wq_direct; 486 uint32_t timer_enq; 487 uint32_t timer_direct; 488 uint32_t enq_timer_set; 489 uint32_t direct_timer_set; 490 uint32_t timer_reset; 491 qdf_time_t enq_time; 492 qdf_time_t deq_time; 493 uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX]; 494 }; 495 #endif 496 #endif 497 498 struct hal_offload_info { 499 uint8_t lro_eligible; 500 uint8_t tcp_proto; 501 uint8_t tcp_pure_ack; 502 uint8_t ipv6_proto; 503 uint8_t tcp_offset; 504 uint16_t tcp_csum; 505 uint16_t tcp_win; 506 uint32_t tcp_seq_num; 507 uint32_t tcp_ack_num; 508 uint32_t flow_id; 509 }; 510 511 /* Common SRNG ring structure for source and destination rings */ 512 struct hal_srng { 513 /* Unique SRNG ring ID */ 514 uint8_t ring_id; 515 516 /* Ring initialization done */ 517 uint8_t initialized; 518 519 /* Interrupt/MSI value assigned to this ring */ 520 int irq; 521 522 /* Physical base address of the ring */ 523 qdf_dma_addr_t ring_base_paddr; 524 525 /* Virtual base address of the ring */ 526 uint32_t *ring_base_vaddr; 527 528 /* Number of entries in ring */ 529 uint32_t num_entries; 530 531 /* Ring size */ 532 uint32_t ring_size; 533 534 /* Ring size mask */ 535 uint32_t ring_size_mask; 536 537 /* Size of ring entry */ 538 uint32_t entry_size; 539 540 /* Interrupt timer threshold – in micro seconds */ 541 uint32_t intr_timer_thres_us; 542 543 /* Interrupt batch counter threshold – in number of ring entries */ 544 uint32_t intr_batch_cntr_thres_entries; 545 546 /* Applicable only for CE dest ring */ 547 uint32_t prefetch_timer; 548 549 /* MSI Address */ 550 qdf_dma_addr_t msi_addr; 551 552 /* MSI data */ 553 uint32_t msi_data; 554 555 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 556 /* MSI2 Address */ 557 qdf_dma_addr_t msi2_addr; 558 559 /* MSI2 data */ 560 uint32_t msi2_data; 561 #endif 562 563 /* Misc flags */ 564 uint32_t flags; 565 566 /* Lock for serializing ring index updates */ 567 hal_srng_lock_t lock; 568 569 /* Start offset of SRNG register groups for this ring 570 * TBD: See if this is required - register address can be derived 571 * from ring ID 572 */ 573 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 574 575 /* Ring type/name */ 576 enum hal_ring_type ring_type; 577 578 /* Source or Destination ring */ 579 enum hal_srng_dir ring_dir; 580 581 union { 582 struct { 583 /* SW tail pointer */ 584 uint32_t tp; 585 586 /* Shadow head pointer location to be updated by HW */ 587 uint32_t *hp_addr; 588 589 /* Cached head pointer */ 590 uint32_t cached_hp; 591 592 /* Tail pointer location to be updated by SW – This 593 * will be a register address and need not be 594 * accessed through SW structure */ 595 uint32_t *tp_addr; 596 597 /* Current SW loop cnt */ 598 uint32_t loop_cnt; 599 600 /* max transfer size */ 601 uint16_t max_buffer_length; 602 603 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 604 /* near full IRQ supported */ 605 uint16_t nf_irq_support; 606 607 /* High threshold for Near full IRQ */ 608 uint16_t high_thresh; 609 #endif 610 } dst_ring; 611 612 struct { 613 /* SW head pointer */ 614 uint32_t hp; 615 616 /* SW reap head pointer */ 617 uint32_t reap_hp; 618 619 /* Shadow tail pointer location to be updated by HW */ 620 uint32_t *tp_addr; 621 622 /* Cached tail pointer */ 623 uint32_t cached_tp; 624 625 /* Head pointer location to be updated by SW – This 626 * will be a register address and need not be accessed 627 * through SW structure */ 628 uint32_t *hp_addr; 629 630 /* Low threshold – in number of ring entries */ 631 uint32_t low_threshold; 632 } src_ring; 633 } u; 634 635 struct hal_soc *hal_soc; 636 637 /* Number of times hp/tp updated in runtime resume */ 638 uint32_t flush_count; 639 /* hal srng event flag*/ 640 unsigned long srng_event; 641 /* last flushed time stamp */ 642 uint64_t last_flush_ts; 643 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 644 /* last ring desc entry cleared */ 645 uint32_t last_desc_cleared; 646 #endif 647 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 648 defined(FEATURE_HAL_DELAYED_REG_WRITE_V2) 649 /* Previous hp/tp (based on ring dir) value written to the reg */ 650 uint32_t last_reg_wr_val; 651 /* flag to indicate whether srng is already queued for delayed write */ 652 uint8_t reg_write_in_progress; 653 /* last dequeue elem time stamp */ 654 qdf_time_t last_dequeue_time; 655 656 /* srng specific delayed write stats */ 657 struct hal_reg_write_srng_stats wstats; 658 #endif 659 }; 660 661 /* HW SRNG configuration table */ 662 struct hal_hw_srng_config { 663 int start_ring_id; 664 uint16_t max_rings; 665 uint16_t entry_size; 666 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 667 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 668 uint8_t lmac_ring; 669 enum hal_srng_dir ring_dir; 670 uint32_t max_size; 671 bool nf_irq_support; 672 }; 673 674 #define MAX_SHADOW_REGISTERS 40 675 #define MAX_GENERIC_SHADOW_REG 5 676 677 /** 678 * struct shadow_reg_config - Hal soc structure that contains 679 * the list of generic shadow registers 680 * @target_register: target reg offset 681 * @shadow_config_index: shadow config index in shadow config 682 * list sent to FW 683 * @va: virtual addr of shadow reg 684 * 685 * This structure holds the generic registers that are mapped to 686 * the shadow region and holds the mapping of the target 687 * register offset to shadow config index provided to FW during 688 * init 689 */ 690 struct shadow_reg_config { 691 uint32_t target_register; 692 int shadow_config_index; 693 uint64_t va; 694 }; 695 696 /* REO parameters to be passed to hal_reo_setup */ 697 struct hal_reo_params { 698 /** rx hash steering enabled or disabled */ 699 bool rx_hash_enabled; 700 /** reo remap 1 register */ 701 uint32_t remap1; 702 /** reo remap 2 register */ 703 uint32_t remap2; 704 /** fragment destination ring */ 705 uint8_t frag_dst_ring; 706 /* Destination for alternate */ 707 uint8_t alt_dst_ind_0; 708 /** padding */ 709 uint8_t padding[2]; 710 }; 711 712 /** 713 * enum hal_reo_cmd_type: Enum for REO command type 714 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 715 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 716 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 717 * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked 718 * earlier with a ‘REO_FLUSH_CACHE’ command 719 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 720 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 721 */ 722 enum hal_reo_cmd_type { 723 CMD_GET_QUEUE_STATS = 0, 724 CMD_FLUSH_QUEUE = 1, 725 CMD_FLUSH_CACHE = 2, 726 CMD_UNBLOCK_CACHE = 3, 727 CMD_FLUSH_TIMEOUT_LIST = 4, 728 CMD_UPDATE_RX_REO_QUEUE = 5 729 }; 730 731 struct hal_rx_pkt_capture_flags { 732 uint8_t encrypt_type; 733 uint8_t fragment_flag; 734 uint8_t fcs_err; 735 uint32_t chan_freq; 736 uint32_t rssi_comb; 737 uint64_t tsft; 738 }; 739 740 struct hal_hw_txrx_ops { 741 /* init and setup */ 742 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 743 struct hal_srng *srng); 744 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 745 struct hal_srng *srng); 746 void (*hal_get_hw_hptp)(struct hal_soc *hal, 747 hal_ring_handle_t hal_ring_hdl, 748 uint32_t *headp, uint32_t *tailp, 749 uint8_t ring_type); 750 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams); 751 void (*hal_setup_link_idle_list)( 752 struct hal_soc *hal_soc, 753 qdf_dma_addr_t scatter_bufs_base_paddr[], 754 void *scatter_bufs_base_vaddr[], 755 uint32_t num_scatter_bufs, 756 uint32_t scatter_buf_size, 757 uint32_t last_buf_end_offset, 758 uint32_t num_entries); 759 qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, 760 qdf_iomem_t addr); 761 void (*hal_reo_set_err_dst_remap)(void *hal_soc); 762 uint8_t (*hal_reo_enable_pn_in_dest)(void *hal_soc); 763 void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid, 764 uint32_t ba_window_size, 765 uint32_t start_seq, void *hw_qdesc_vaddr, 766 qdf_dma_addr_t hw_qdesc_paddr, 767 int pn_type); 768 uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg, 769 uint8_t *ix0_map); 770 771 /* tx */ 772 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 773 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 774 uint8_t id); 775 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 776 uint8_t id, 777 uint8_t dscp); 778 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 779 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 780 uint8_t pool_id, uint32_t desc_id, 781 uint8_t type); 782 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 783 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 784 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 785 void (*hal_tx_comp_get_status)(void *desc, void *ts, 786 struct hal_soc *hal); 787 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 788 uint8_t (*hal_get_wbm_internal_error)(void *hal_desc); 789 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 790 void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, 791 hal_ring_handle_t hal_ring_hdl); 792 uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc); 793 794 /* rx */ 795 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 796 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 797 struct mon_rx_status *rs); 798 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 799 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 800 void *ppdu_info_handle); 801 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 802 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 803 uint8_t dbg_level); 804 uint32_t (*hal_get_link_desc_size)(void); 805 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 806 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 807 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 808 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 809 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 810 void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b, 811 void *h); 812 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 813 void *ppdu_info, 814 hal_soc_handle_t hal_soc_hdl, 815 qdf_nbuf_t nbuf); 816 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 817 void *wbm_er_info); 818 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 819 uint8_t dbg_level); 820 821 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 822 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 823 uint8_t id); 824 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 825 826 /* rx */ 827 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 828 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 829 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 830 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 831 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 832 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 833 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 834 void (*hal_rx_print_pn)(uint8_t *buf); 835 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 836 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 837 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 838 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 839 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 840 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 841 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 842 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 843 QDF_STATUS 844 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 845 QDF_STATUS 846 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 847 QDF_STATUS 848 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 849 QDF_STATUS 850 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 851 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 852 bool (*hal_rx_is_unicast)(uint8_t *buf); 853 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 854 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr, 855 void *rxdma_dst_ring_desc); 856 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 857 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 858 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 859 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 860 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 861 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 862 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 863 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 864 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 865 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 866 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 867 void (*hal_reo_config)(struct hal_soc *soc, 868 uint32_t reg_val, 869 struct hal_reo_params *reo_params); 870 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 871 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 872 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 873 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 874 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 875 void 876 (*hal_rx_msdu_get_flow_params)( 877 uint8_t *buf, 878 bool *flow_invalid, 879 bool *flow_timeout, 880 uint32_t *flow_index); 881 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 882 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 883 void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle); 884 void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle); 885 void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf, 886 void *msdu_pkt_metadata); 887 uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf); 888 uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf); 889 bool (*hal_rx_get_udp_proto)(uint8_t *buf); 890 bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf); 891 uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf); 892 bool (*hal_rx_get_fisa_timeout)(uint8_t *buf); 893 uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr); 894 void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc, 895 hal_rx_mon_desc_info_t mon_desc_info); 896 uint8_t (*hal_rx_wbm_err_msdu_continuation_get)(void *ring_desc); 897 uint32_t (*hal_rx_msdu_end_offset_get)(void); 898 uint32_t (*hal_rx_attn_offset_get)(void); 899 uint32_t (*hal_rx_msdu_start_offset_get)(void); 900 uint32_t (*hal_rx_mpdu_start_offset_get)(void); 901 uint32_t (*hal_rx_mpdu_end_offset_get)(void); 902 uint32_t (*hal_rx_pkt_tlv_offset_get)(void); 903 void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, 904 uint32_t table_offset, 905 uint8_t *rx_flow); 906 void (*hal_compute_reo_remap_ix2_ix3)(uint32_t *ring, 907 uint32_t num_rings, 908 uint32_t *remap1, 909 uint32_t *remap2); 910 uint32_t (*hal_rx_flow_setup_cmem_fse)( 911 struct hal_soc *soc, uint32_t cmem_ba, 912 uint32_t table_offset, uint8_t *rx_flow); 913 uint32_t (*hal_rx_flow_get_cmem_fse_ts)(struct hal_soc *soc, 914 uint32_t fse_offset); 915 void (*hal_rx_flow_get_cmem_fse)(struct hal_soc *soc, 916 uint32_t fse_offset, 917 uint32_t *fse, qdf_size_t len); 918 919 void (*hal_cmem_write)(hal_soc_handle_t hal_soc_hdl, uint32_t offset, 920 uint32_t value); 921 922 void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, 923 uint32_t *reo_destination_indication); 924 uint8_t (*hal_tx_get_num_tcl_banks)(void); 925 uint32_t (*hal_get_reo_qdesc_size)(uint32_t ba_window_size, int tid); 926 927 void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie, 928 qdf_dma_addr_t link_desc_paddr); 929 void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl, 930 hal_ring_handle_t hal_ring_hdl); 931 void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr); 932 void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 933 uint8_t ac, uint32_t *value); 934 void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, 935 uint8_t ac, uint32_t value); 936 uint32_t (*hal_get_reo_reg_base_offset)(void); 937 void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size, 938 uint16_t *rx_mon_pkt_tlv_size); 939 uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf); 940 uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr); 941 void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl, 942 uint8_t *buf, uint8_t dbg_level); 943 int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv, 944 struct hal_offload_info *offload_info); 945 uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf); 946 uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf); 947 uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf); 948 uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf); 949 int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params); 950 int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset, 951 uint32_t *l4_hdr_offset); 952 uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf); 953 uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf); 954 void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num); 955 void (*hal_rx_reo_prev_pn_get)(void *ring_desc, uint64_t *prev_pn); 956 uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf); 957 uint32_t (*hal_rx_msdu_reo_dst_ind_get)(hal_soc_handle_t hal_soc_hdl, 958 void *msdu_link_desc); 959 void (*hal_msdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 960 void *msdu_desc_info, uint32_t dst_ind, 961 uint32_t nbuf_len); 962 void (*hal_mpdu_desc_info_set)(hal_soc_handle_t hal_soc_hdl, 963 void *mpdu_desc_info, uint32_t seq_no); 964 uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf); 965 uint32_t (*hal_rx_tlv_get_freq)(uint8_t *buf); 966 uint8_t (*hal_rx_msdu_get_keyid)(uint8_t *buf); 967 uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf); 968 uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf); 969 uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf); 970 uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf); 971 uint32_t (*hal_rx_tlv_get_is_decrypted)(uint8_t *buf); 972 973 uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc); 974 uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc); 975 void (*hal_rx_msdu_link_desc_set)(hal_soc_handle_t hal_soc_hdl, 976 void *src_srng_desc, 977 hal_buff_addrinfo_t buf_addr_info, 978 uint8_t bm_action); 979 980 void (*hal_rx_buf_cookie_rbm_get)(uint32_t *buf_addr_info_hdl, 981 hal_buf_info_t buf_info_hdl); 982 void (*hal_rx_reo_buf_paddr_get)(hal_ring_desc_t rx_desc, 983 struct hal_buf_info *buf_info); 984 void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry, 985 qdf_dma_addr_t paddr, 986 uint32_t cookie, uint8_t manager); 987 uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl); 988 uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc); 989 void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr, 990 uint32_t *ip_csum_err, 991 uint32_t *tcp_udp_csum_err); 992 void (*hal_rx_mpdu_desc_info_get)(void *desc_addr, 993 void *mpdu_desc_info_hdl); 994 uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc); 995 uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc); 996 bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf); 997 uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr); 998 uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr); 999 void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr, 1000 struct hal_rx_pkt_capture_flags *flags); 1001 uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr); 1002 uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr); 1003 void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf, 1004 uint8_t *priv_data, 1005 uint32_t len); 1006 void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf, 1007 uint8_t *priv_data, 1008 uint32_t len); 1009 void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len); 1010 void (*hal_rx_tlv_populate_mpdu_desc_info)(uint8_t *buf, 1011 void *mpdu_desc_info_hdl); 1012 1013 /* REO CMD and STATUS */ 1014 int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl, 1015 hal_ring_handle_t hal_ring_hdl, 1016 enum hal_reo_cmd_type cmd, 1017 void *params); 1018 QDF_STATUS (*hal_reo_status_update)(hal_soc_handle_t hal_soc_hdl, 1019 hal_ring_desc_t reo_desc, 1020 void *st_handle, 1021 uint32_t tlv, int *num_ref); 1022 uint8_t (*hal_get_tlv_hdr_size)(void); 1023 }; 1024 1025 /** 1026 * struct hal_soc_stats - Hal layer stats 1027 * @reg_write_fail: number of failed register writes 1028 * @wstats: delayed register write stats 1029 * @shadow_reg_write_fail: shadow reg write failure stats 1030 * @shadow_reg_write_succ: shadow reg write success stats 1031 * 1032 * This structure holds all the statistics at HAL layer. 1033 */ 1034 struct hal_soc_stats { 1035 uint32_t reg_write_fail; 1036 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 1037 defined(FEATURE_HAL_DELAYED_REG_WRITE_V2) 1038 struct hal_reg_write_soc_stats wstats; 1039 #endif 1040 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1041 uint32_t shadow_reg_write_fail; 1042 uint32_t shadow_reg_write_succ; 1043 #endif 1044 }; 1045 1046 #ifdef ENABLE_HAL_REG_WR_HISTORY 1047 /* The history size should always be a power of 2 */ 1048 #define HAL_REG_WRITE_HIST_SIZE 8 1049 1050 /** 1051 * struct hal_reg_write_fail_entry - Record of 1052 * register write which failed. 1053 * @timestamp: timestamp of reg write failure 1054 * @reg_offset: offset of register where the write failed 1055 * @write_val: the value which was to be written 1056 * @read_val: the value read back from the register after write 1057 */ 1058 struct hal_reg_write_fail_entry { 1059 uint64_t timestamp; 1060 uint32_t reg_offset; 1061 uint32_t write_val; 1062 uint32_t read_val; 1063 }; 1064 1065 /** 1066 * struct hal_reg_write_fail_history - Hal layer history 1067 * of all the register write failures. 1068 * @index: index to add the new record 1069 * @record: array of all the records in history 1070 * 1071 * This structure holds the history of register write 1072 * failures at HAL layer. 1073 */ 1074 struct hal_reg_write_fail_history { 1075 qdf_atomic_t index; 1076 struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE]; 1077 }; 1078 #endif 1079 1080 /** 1081 * struct hal_soc - HAL context to be used to access SRNG APIs 1082 * (currently used by data path and 1083 * transport (CE) modules) 1084 * @list_shadow_reg_config: array of generic regs mapped to 1085 * shadow regs 1086 * @num_generic_shadow_regs_configured: number of generic regs 1087 * mapped to shadow regs 1088 */ 1089 struct hal_soc { 1090 /* HIF handle to access HW registers */ 1091 struct hif_opaque_softc *hif_handle; 1092 1093 /* QDF device handle */ 1094 qdf_device_t qdf_dev; 1095 1096 /* Device base address */ 1097 void *dev_base_addr; 1098 /* Device base address for ce - qca5018 target */ 1099 void *dev_base_addr_ce; 1100 1101 /* HAL internal state for all SRNG rings. 1102 * TODO: See if this is required 1103 */ 1104 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 1105 1106 /* Remote pointer memory for HW/FW updates */ 1107 uint32_t *shadow_rdptr_mem_vaddr; 1108 qdf_dma_addr_t shadow_rdptr_mem_paddr; 1109 1110 /* Shared memory for ring pointer updates from host to FW */ 1111 uint32_t *shadow_wrptr_mem_vaddr; 1112 qdf_dma_addr_t shadow_wrptr_mem_paddr; 1113 1114 /* REO blocking resource index */ 1115 uint8_t reo_res_bitmap; 1116 uint8_t index; 1117 uint32_t target_type; 1118 1119 /* shadow register configuration */ 1120 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 1121 int num_shadow_registers_configured; 1122 bool use_register_windowing; 1123 uint32_t register_window; 1124 qdf_spinlock_t register_access_lock; 1125 1126 /* Static window map configuration for multiple window write*/ 1127 bool static_window_map; 1128 1129 /* srng table */ 1130 struct hal_hw_srng_config *hw_srng_table; 1131 int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX]; 1132 struct hal_hw_txrx_ops *ops; 1133 1134 /* Indicate srngs initialization */ 1135 bool init_phase; 1136 /* Hal level stats */ 1137 struct hal_soc_stats stats; 1138 #ifdef ENABLE_HAL_REG_WR_HISTORY 1139 struct hal_reg_write_fail_history *reg_wr_fail_hist; 1140 #endif 1141 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1142 /* queue(array) to hold register writes */ 1143 struct hal_reg_write_q_elem *reg_write_queue; 1144 /* delayed work to be queued into workqueue */ 1145 qdf_work_t reg_write_work; 1146 /* workqueue for delayed register writes */ 1147 qdf_workqueue_t *reg_write_wq; 1148 /* write index used by caller to enqueue delayed work */ 1149 qdf_atomic_t write_idx; 1150 /* read index used by worker thread to dequeue/write registers */ 1151 uint32_t read_idx; 1152 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */ 1153 #ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2 1154 /* delayed work for TCL reg write to be queued into workqueue */ 1155 qdf_work_t tcl_reg_write_work; 1156 /* workqueue for TCL delayed register writes */ 1157 qdf_workqueue_t *tcl_reg_write_wq; 1158 /* flag denotes whether TCL delayed write work is active */ 1159 qdf_atomic_t tcl_work_active; 1160 /* flag indiactes TCL write happening from direct context */ 1161 bool tcl_direct; 1162 /* timer to handle the pending TCL reg writes */ 1163 qdf_timer_t tcl_reg_write_timer; 1164 /* stats related to TCL reg write */ 1165 struct hal_reg_write_tcl_stats tcl_stats; 1166 #endif /* FEATURE_HAL_DELAYED_REG_WRITE_V2 */ 1167 qdf_atomic_t active_work_cnt; 1168 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 1169 struct shadow_reg_config 1170 list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; 1171 int num_generic_shadow_regs_configured; 1172 #endif 1173 /* flag to indicate cmn dmac rings in berryllium */ 1174 bool dmac_cmn_src_rxbuf_ring; 1175 }; 1176 1177 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ 1178 defined(FEATURE_HAL_DELAYED_REG_WRITE_V2) 1179 /** 1180 * hal_delayed_reg_write() - delayed regiter write 1181 * @hal_soc: HAL soc handle 1182 * @srng: hal srng 1183 * @addr: iomem address 1184 * @value: value to be written 1185 * 1186 * Return: none 1187 */ 1188 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1189 struct hal_srng *srng, 1190 void __iomem *addr, 1191 uint32_t value); 1192 #endif 1193 1194 void hal_qca6750_attach(struct hal_soc *hal_soc); 1195 void hal_qca6490_attach(struct hal_soc *hal_soc); 1196 void hal_qca6390_attach(struct hal_soc *hal_soc); 1197 void hal_qca6290_attach(struct hal_soc *hal_soc); 1198 void hal_qca8074_attach(struct hal_soc *hal_soc); 1199 void hal_wcn7850_attach(struct hal_soc *hal_soc); 1200 void hal_qcn9224_attach(struct hal_soc *hal_soc); 1201 /* 1202 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 1203 * dp_hal_soc handle type 1204 * @hal_soc - hal_soc type 1205 * 1206 * Return: hal_soc_handle_t type 1207 */ 1208 static inline 1209 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 1210 { 1211 return (hal_soc_handle_t)hal_soc; 1212 } 1213 1214 /* 1215 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 1216 * dp_hal_ring handle type 1217 * @hal_srng - hal_srng type 1218 * 1219 * Return: hal_ring_handle_t type 1220 */ 1221 static inline 1222 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 1223 { 1224 return (hal_ring_handle_t)hal_srng; 1225 } 1226 1227 /* 1228 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 1229 * @hal_ring - hal_ring_handle_t type 1230 * 1231 * Return: hal_srng pointer type 1232 */ 1233 static inline 1234 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 1235 { 1236 return (struct hal_srng *)hal_ring; 1237 } 1238 #endif /* _HAL_INTERNAL_H_ */ 1239