1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer in the documentation and/or other materials provided 12 * with the distribution. 13 * * Neither the name of The Linux Foundation nor the names of its 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _HAL_INTERNAL_H_ 31 #define _HAL_INTERNAL_H_ 32 33 #include "qdf_types.h" 34 #include "qdf_lock.h" 35 #include "qdf_mem.h" 36 #include "qdf_nbuf.h" 37 #include "pld_common.h" 38 39 40 /* TBD: This should be movded to shared HW header file */ 41 enum hal_srng_ring_id { 42 /* UMAC rings */ 43 HAL_SRNG_REO2SW1 = 0, 44 HAL_SRNG_REO2SW2 = 1, 45 HAL_SRNG_REO2SW3 = 2, 46 HAL_SRNG_REO2SW4 = 3, 47 HAL_SRNG_REO2TCL = 4, 48 HAL_SRNG_SW2REO = 5, 49 /* 6-7 unused */ 50 HAL_SRNG_REO_CMD = 8, 51 HAL_SRNG_REO_STATUS = 9, 52 /* 10-15 unused */ 53 HAL_SRNG_SW2TCL1 = 16, 54 HAL_SRNG_SW2TCL2 = 17, 55 HAL_SRNG_SW2TCL3 = 18, 56 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 57 /* 20-23 unused */ 58 HAL_SRNG_SW2TCL_CMD = 24, 59 HAL_SRNG_TCL_STATUS = 25, 60 /* 26-31 unused */ 61 HAL_SRNG_CE_0_SRC = 32, 62 HAL_SRNG_CE_1_SRC = 33, 63 HAL_SRNG_CE_2_SRC = 34, 64 HAL_SRNG_CE_3_SRC = 35, 65 HAL_SRNG_CE_4_SRC = 36, 66 HAL_SRNG_CE_5_SRC = 37, 67 HAL_SRNG_CE_6_SRC = 38, 68 HAL_SRNG_CE_7_SRC = 39, 69 HAL_SRNG_CE_8_SRC = 40, 70 HAL_SRNG_CE_9_SRC = 41, 71 HAL_SRNG_CE_10_SRC = 42, 72 HAL_SRNG_CE_11_SRC = 43, 73 /* 44-55 unused */ 74 HAL_SRNG_CE_0_DST = 56, 75 HAL_SRNG_CE_1_DST = 57, 76 HAL_SRNG_CE_2_DST = 58, 77 HAL_SRNG_CE_3_DST = 59, 78 HAL_SRNG_CE_4_DST = 60, 79 HAL_SRNG_CE_5_DST = 61, 80 HAL_SRNG_CE_6_DST = 62, 81 HAL_SRNG_CE_7_DST = 63, 82 HAL_SRNG_CE_8_DST = 64, 83 HAL_SRNG_CE_9_DST = 65, 84 HAL_SRNG_CE_10_DST = 66, 85 HAL_SRNG_CE_11_DST = 67, 86 /* 68-79 unused */ 87 HAL_SRNG_CE_0_DST_STATUS = 80, 88 HAL_SRNG_CE_1_DST_STATUS = 81, 89 HAL_SRNG_CE_2_DST_STATUS = 82, 90 HAL_SRNG_CE_3_DST_STATUS = 83, 91 HAL_SRNG_CE_4_DST_STATUS = 84, 92 HAL_SRNG_CE_5_DST_STATUS = 85, 93 HAL_SRNG_CE_6_DST_STATUS = 86, 94 HAL_SRNG_CE_7_DST_STATUS = 87, 95 HAL_SRNG_CE_8_DST_STATUS = 88, 96 HAL_SRNG_CE_9_DST_STATUS = 89, 97 HAL_SRNG_CE_10_DST_STATUS = 90, 98 HAL_SRNG_CE_11_DST_STATUS = 91, 99 /* 92-103 unused */ 100 HAL_SRNG_WBM_IDLE_LINK = 104, 101 HAL_SRNG_WBM_SW_RELEASE = 105, 102 HAL_SRNG_WBM2SW0_RELEASE = 106, 103 HAL_SRNG_WBM2SW1_RELEASE = 107, 104 HAL_SRNG_WBM2SW2_RELEASE = 108, 105 HAL_SRNG_WBM2SW3_RELEASE = 109, 106 /* 110-127 unused */ 107 HAL_SRNG_UMAC_ID_END = 127, 108 /* LMAC rings - The following set will be replicated for each LMAC */ 109 HAL_SRNG_LMAC1_ID_START = 128, 110 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 111 #ifdef IPA_OFFLOAD 112 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 113 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 114 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 115 #else 116 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 117 #endif 118 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 119 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 120 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 121 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 122 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 123 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 124 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 125 #ifdef WLAN_FEATURE_CIF_CFR 126 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 127 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 128 #else 129 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 130 #endif 131 /* -142 unused */ 132 HAL_SRNG_LMAC1_ID_END = 143 133 }; 134 135 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 136 #define HAL_MAX_LMACS 3 137 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 138 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 139 140 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 141 142 enum hal_srng_dir { 143 HAL_SRNG_SRC_RING, 144 HAL_SRNG_DST_RING 145 }; 146 147 /* Lock wrappers for SRNG */ 148 #define hal_srng_lock_t qdf_spinlock_t 149 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 150 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 151 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 152 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 153 154 struct hal_soc; 155 #define MAX_SRNG_REG_GROUPS 2 156 157 /* Common SRNG ring structure for source and destination rings */ 158 struct hal_srng { 159 /* Unique SRNG ring ID */ 160 uint8_t ring_id; 161 162 /* Ring initialization done */ 163 uint8_t initialized; 164 165 /* Interrupt/MSI value assigned to this ring */ 166 int irq; 167 168 /* Physical base address of the ring */ 169 qdf_dma_addr_t ring_base_paddr; 170 171 /* Virtual base address of the ring */ 172 uint32_t *ring_base_vaddr; 173 174 /* Number of entries in ring */ 175 uint32_t num_entries; 176 177 /* Ring size */ 178 uint32_t ring_size; 179 180 /* Ring size mask */ 181 uint32_t ring_size_mask; 182 183 /* Size of ring entry */ 184 uint32_t entry_size; 185 186 /* Interrupt timer threshold – in micro seconds */ 187 uint32_t intr_timer_thres_us; 188 189 /* Interrupt batch counter threshold – in number of ring entries */ 190 uint32_t intr_batch_cntr_thres_entries; 191 192 /* MSI Address */ 193 qdf_dma_addr_t msi_addr; 194 195 /* MSI data */ 196 uint32_t msi_data; 197 198 /* Misc flags */ 199 uint32_t flags; 200 201 /* Lock for serializing ring index updates */ 202 hal_srng_lock_t lock; 203 204 /* Start offset of SRNG register groups for this ring 205 * TBD: See if this is required - register address can be derived 206 * from ring ID 207 */ 208 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 209 210 /* Source or Destination ring */ 211 enum hal_srng_dir ring_dir; 212 213 union { 214 struct { 215 /* SW tail pointer */ 216 uint32_t tp; 217 218 /* Shadow head pointer location to be updated by HW */ 219 uint32_t *hp_addr; 220 221 /* Cached head pointer */ 222 uint32_t cached_hp; 223 224 /* Tail pointer location to be updated by SW – This 225 * will be a register address and need not be 226 * accessed through SW structure */ 227 uint32_t *tp_addr; 228 229 /* Current SW loop cnt */ 230 uint32_t loop_cnt; 231 232 /* max transfer size */ 233 uint16_t max_buffer_length; 234 } dst_ring; 235 236 struct { 237 /* SW head pointer */ 238 uint32_t hp; 239 240 /* SW reap head pointer */ 241 uint32_t reap_hp; 242 243 /* Shadow tail pointer location to be updated by HW */ 244 uint32_t *tp_addr; 245 246 /* Cached tail pointer */ 247 uint32_t cached_tp; 248 249 /* Head pointer location to be updated by SW – This 250 * will be a register address and need not be accessed 251 * through SW structure */ 252 uint32_t *hp_addr; 253 254 /* Low threshold – in number of ring entries */ 255 uint32_t low_threshold; 256 } src_ring; 257 } u; 258 259 struct hal_soc *hal_soc; 260 }; 261 262 /* HW SRNG configuration table */ 263 struct hal_hw_srng_config { 264 int start_ring_id; 265 uint16_t max_rings; 266 uint16_t entry_size; 267 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 268 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 269 uint8_t lmac_ring; 270 enum hal_srng_dir ring_dir; 271 uint32_t max_size; 272 }; 273 274 #define MAX_SHADOW_REGISTERS 36 275 276 struct hal_hw_txrx_ops { 277 /* tx */ 278 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 279 void (*hal_tx_set_dscp_tid_map)(void *hal_soc, uint8_t *map, 280 uint8_t id); 281 void (*hal_tx_update_dscp_tid)(void *hal_soc, uint8_t tid, uint8_t id, 282 uint8_t dscp); 283 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 284 285 /* rx */ 286 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 287 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 288 struct mon_rx_status *rs); 289 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 290 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 291 void *ppdu_info_handle); 292 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 293 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 294 uint8_t dbg_level); 295 uint32_t (*hal_get_link_desc_size)(void); 296 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 297 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 298 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 299 }; 300 301 /** 302 * HAL context to be used to access SRNG APIs (currently used by data path 303 * and transport (CE) modules) 304 */ 305 struct hal_soc { 306 /* HIF handle to access HW registers */ 307 void *hif_handle; 308 309 /* QDF device handle */ 310 qdf_device_t qdf_dev; 311 312 /* Device base address */ 313 void *dev_base_addr; 314 315 /* HAL internal state for all SRNG rings. 316 * TODO: See if this is required 317 */ 318 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 319 320 /* Remote pointer memory for HW/FW updates */ 321 uint32_t *shadow_rdptr_mem_vaddr; 322 qdf_dma_addr_t shadow_rdptr_mem_paddr; 323 324 /* Shared memory for ring pointer updates from host to FW */ 325 uint32_t *shadow_wrptr_mem_vaddr; 326 qdf_dma_addr_t shadow_wrptr_mem_paddr; 327 328 /* REO blocking resource index */ 329 uint8_t reo_res_bitmap; 330 uint8_t index; 331 uint32_t target_type; 332 333 /* shadow register configuration */ 334 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 335 int num_shadow_registers_configured; 336 bool use_register_windowing; 337 uint32_t register_window; 338 qdf_spinlock_t register_access_lock; 339 340 /* srng table */ 341 struct hal_hw_srng_config *hw_srng_table; 342 int32_t *hal_hw_reg_offset; 343 struct hal_hw_txrx_ops *ops; 344 }; 345 346 void hal_qca6390_attach(struct hal_soc *hal_soc); 347 void hal_qca6290_attach(struct hal_soc *hal_soc); 348 void hal_qca8074_attach(struct hal_soc *hal_soc); 349 #endif /* _HAL_INTERNAL_H_ */ 350