1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "pld_common.h" 27 28 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_TXRX, params) 29 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_TXRX, params) 30 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_TXRX, params) 31 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_TXRX, params) 32 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 33 34 35 /* TBD: This should be movded to shared HW header file */ 36 enum hal_srng_ring_id { 37 /* UMAC rings */ 38 HAL_SRNG_REO2SW1 = 0, 39 HAL_SRNG_REO2SW2 = 1, 40 HAL_SRNG_REO2SW3 = 2, 41 HAL_SRNG_REO2SW4 = 3, 42 HAL_SRNG_REO2TCL = 4, 43 HAL_SRNG_SW2REO = 5, 44 /* 6-7 unused */ 45 HAL_SRNG_REO_CMD = 8, 46 HAL_SRNG_REO_STATUS = 9, 47 /* 10-15 unused */ 48 HAL_SRNG_SW2TCL1 = 16, 49 HAL_SRNG_SW2TCL2 = 17, 50 HAL_SRNG_SW2TCL3 = 18, 51 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 52 /* 20-23 unused */ 53 HAL_SRNG_SW2TCL_CMD = 24, 54 HAL_SRNG_TCL_STATUS = 25, 55 /* 26-31 unused */ 56 HAL_SRNG_CE_0_SRC = 32, 57 HAL_SRNG_CE_1_SRC = 33, 58 HAL_SRNG_CE_2_SRC = 34, 59 HAL_SRNG_CE_3_SRC = 35, 60 HAL_SRNG_CE_4_SRC = 36, 61 HAL_SRNG_CE_5_SRC = 37, 62 HAL_SRNG_CE_6_SRC = 38, 63 HAL_SRNG_CE_7_SRC = 39, 64 HAL_SRNG_CE_8_SRC = 40, 65 HAL_SRNG_CE_9_SRC = 41, 66 HAL_SRNG_CE_10_SRC = 42, 67 HAL_SRNG_CE_11_SRC = 43, 68 /* 44-55 unused */ 69 HAL_SRNG_CE_0_DST = 56, 70 HAL_SRNG_CE_1_DST = 57, 71 HAL_SRNG_CE_2_DST = 58, 72 HAL_SRNG_CE_3_DST = 59, 73 HAL_SRNG_CE_4_DST = 60, 74 HAL_SRNG_CE_5_DST = 61, 75 HAL_SRNG_CE_6_DST = 62, 76 HAL_SRNG_CE_7_DST = 63, 77 HAL_SRNG_CE_8_DST = 64, 78 HAL_SRNG_CE_9_DST = 65, 79 HAL_SRNG_CE_10_DST = 66, 80 HAL_SRNG_CE_11_DST = 67, 81 /* 68-79 unused */ 82 HAL_SRNG_CE_0_DST_STATUS = 80, 83 HAL_SRNG_CE_1_DST_STATUS = 81, 84 HAL_SRNG_CE_2_DST_STATUS = 82, 85 HAL_SRNG_CE_3_DST_STATUS = 83, 86 HAL_SRNG_CE_4_DST_STATUS = 84, 87 HAL_SRNG_CE_5_DST_STATUS = 85, 88 HAL_SRNG_CE_6_DST_STATUS = 86, 89 HAL_SRNG_CE_7_DST_STATUS = 87, 90 HAL_SRNG_CE_8_DST_STATUS = 88, 91 HAL_SRNG_CE_9_DST_STATUS = 89, 92 HAL_SRNG_CE_10_DST_STATUS = 90, 93 HAL_SRNG_CE_11_DST_STATUS = 91, 94 /* 92-103 unused */ 95 HAL_SRNG_WBM_IDLE_LINK = 104, 96 HAL_SRNG_WBM_SW_RELEASE = 105, 97 HAL_SRNG_WBM2SW0_RELEASE = 106, 98 HAL_SRNG_WBM2SW1_RELEASE = 107, 99 HAL_SRNG_WBM2SW2_RELEASE = 108, 100 HAL_SRNG_WBM2SW3_RELEASE = 109, 101 /* 110-127 unused */ 102 HAL_SRNG_UMAC_ID_END = 127, 103 /* LMAC rings - The following set will be replicated for each LMAC */ 104 HAL_SRNG_LMAC1_ID_START = 128, 105 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 106 #ifdef IPA_OFFLOAD 107 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 108 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 109 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 110 #else 111 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 112 #endif 113 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 114 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 115 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 116 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 117 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 118 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 119 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 120 #ifdef WLAN_FEATURE_CIF_CFR 121 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 122 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 123 #else 124 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 125 #endif 126 /* -142 unused */ 127 HAL_SRNG_LMAC1_ID_END = 143 128 }; 129 130 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 131 #define HAL_MAX_LMACS 3 132 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 133 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 134 135 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 136 137 enum hal_srng_dir { 138 HAL_SRNG_SRC_RING, 139 HAL_SRNG_DST_RING 140 }; 141 142 /* Lock wrappers for SRNG */ 143 #define hal_srng_lock_t qdf_spinlock_t 144 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 145 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 146 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 147 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 148 149 struct hal_soc; 150 #define MAX_SRNG_REG_GROUPS 2 151 152 /* Common SRNG ring structure for source and destination rings */ 153 struct hal_srng { 154 /* Unique SRNG ring ID */ 155 uint8_t ring_id; 156 157 /* Ring initialization done */ 158 uint8_t initialized; 159 160 /* Interrupt/MSI value assigned to this ring */ 161 int irq; 162 163 /* Physical base address of the ring */ 164 qdf_dma_addr_t ring_base_paddr; 165 166 /* Virtual base address of the ring */ 167 uint32_t *ring_base_vaddr; 168 169 /* Number of entries in ring */ 170 uint32_t num_entries; 171 172 /* Ring size */ 173 uint32_t ring_size; 174 175 /* Ring size mask */ 176 uint32_t ring_size_mask; 177 178 /* Size of ring entry */ 179 uint32_t entry_size; 180 181 /* Interrupt timer threshold – in micro seconds */ 182 uint32_t intr_timer_thres_us; 183 184 /* Interrupt batch counter threshold – in number of ring entries */ 185 uint32_t intr_batch_cntr_thres_entries; 186 187 /* MSI Address */ 188 qdf_dma_addr_t msi_addr; 189 190 /* MSI data */ 191 uint32_t msi_data; 192 193 /* Misc flags */ 194 uint32_t flags; 195 196 /* Lock for serializing ring index updates */ 197 hal_srng_lock_t lock; 198 199 /* Start offset of SRNG register groups for this ring 200 * TBD: See if this is required - register address can be derived 201 * from ring ID 202 */ 203 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 204 205 /* Source or Destination ring */ 206 enum hal_srng_dir ring_dir; 207 208 union { 209 struct { 210 /* SW tail pointer */ 211 uint32_t tp; 212 213 /* Shadow head pointer location to be updated by HW */ 214 uint32_t *hp_addr; 215 216 /* Cached head pointer */ 217 uint32_t cached_hp; 218 219 /* Tail pointer location to be updated by SW – This 220 * will be a register address and need not be 221 * accessed through SW structure */ 222 uint32_t *tp_addr; 223 224 /* Current SW loop cnt */ 225 uint32_t loop_cnt; 226 227 /* max transfer size */ 228 uint16_t max_buffer_length; 229 } dst_ring; 230 231 struct { 232 /* SW head pointer */ 233 uint32_t hp; 234 235 /* SW reap head pointer */ 236 uint32_t reap_hp; 237 238 /* Shadow tail pointer location to be updated by HW */ 239 uint32_t *tp_addr; 240 241 /* Cached tail pointer */ 242 uint32_t cached_tp; 243 244 /* Head pointer location to be updated by SW – This 245 * will be a register address and need not be accessed 246 * through SW structure */ 247 uint32_t *hp_addr; 248 249 /* Low threshold – in number of ring entries */ 250 uint32_t low_threshold; 251 } src_ring; 252 } u; 253 254 struct hal_soc *hal_soc; 255 }; 256 257 /* HW SRNG configuration table */ 258 struct hal_hw_srng_config { 259 int start_ring_id; 260 uint16_t max_rings; 261 uint16_t entry_size; 262 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 263 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 264 uint8_t lmac_ring; 265 enum hal_srng_dir ring_dir; 266 uint32_t max_size; 267 }; 268 269 #define MAX_SHADOW_REGISTERS 36 270 271 struct hal_hw_txrx_ops { 272 273 /* init and setup */ 274 void (*hal_srng_dst_hw_init)(void *hal, 275 struct hal_srng *srng); 276 void (*hal_srng_src_hw_init)(void *hal, 277 struct hal_srng *srng); 278 void (*hal_get_hw_hptp)(struct hal_soc *hal, void *hal_ring, 279 uint32_t *headp, uint32_t *tailp, 280 uint8_t ring_type); 281 void (*hal_reo_setup)(void *hal_soc, void *reoparams); 282 void (*hal_setup_link_idle_list)(void *hal_soc, 283 qdf_dma_addr_t scatter_bufs_base_paddr[], 284 void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs, 285 uint32_t scatter_buf_size, uint32_t last_buf_end_offset, 286 uint32_t num_entries); 287 288 /* tx */ 289 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 290 void (*hal_tx_set_dscp_tid_map)(void *hal_soc, uint8_t *map, 291 uint8_t id); 292 void (*hal_tx_update_dscp_tid)(void *hal_soc, uint8_t tid, uint8_t id, 293 uint8_t dscp); 294 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 295 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 296 uint8_t pool_id, uint32_t desc_id, uint8_t type); 297 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 298 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 299 void (*hal_tx_comp_get_status)(void *desc, void *ts, void *hal); 300 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 301 302 /* rx */ 303 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 304 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 305 struct mon_rx_status *rs); 306 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 307 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 308 void *ppdu_info_handle); 309 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 310 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 311 uint8_t dbg_level); 312 uint32_t (*hal_get_link_desc_size)(void); 313 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 314 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 315 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 316 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 317 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 318 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 319 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 320 void *ppdu_info, 321 void *hal); 322 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 323 void *wbm_er_info); 324 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 325 uint8_t dbg_level); 326 }; 327 328 /** 329 * HAL context to be used to access SRNG APIs (currently used by data path 330 * and transport (CE) modules) 331 */ 332 struct hal_soc { 333 /* HIF handle to access HW registers */ 334 void *hif_handle; 335 336 /* QDF device handle */ 337 qdf_device_t qdf_dev; 338 339 /* Device base address */ 340 void *dev_base_addr; 341 342 /* HAL internal state for all SRNG rings. 343 * TODO: See if this is required 344 */ 345 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 346 347 /* Remote pointer memory for HW/FW updates */ 348 uint32_t *shadow_rdptr_mem_vaddr; 349 qdf_dma_addr_t shadow_rdptr_mem_paddr; 350 351 /* Shared memory for ring pointer updates from host to FW */ 352 uint32_t *shadow_wrptr_mem_vaddr; 353 qdf_dma_addr_t shadow_wrptr_mem_paddr; 354 355 /* REO blocking resource index */ 356 uint8_t reo_res_bitmap; 357 uint8_t index; 358 uint32_t target_type; 359 360 /* shadow register configuration */ 361 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 362 int num_shadow_registers_configured; 363 bool use_register_windowing; 364 uint32_t register_window; 365 qdf_spinlock_t register_access_lock; 366 367 /* srng table */ 368 struct hal_hw_srng_config *hw_srng_table; 369 int32_t *hal_hw_reg_offset; 370 struct hal_hw_txrx_ops *ops; 371 }; 372 373 void hal_qca6390_attach(struct hal_soc *hal_soc); 374 void hal_qca6290_attach(struct hal_soc *hal_soc); 375 void hal_qca8074_attach(struct hal_soc *hal_soc); 376 #endif /* _HAL_INTERNAL_H_ */ 377