1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "pld_common.h" 27 28 #define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_TXRX, params) 29 #define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_TXRX, params) 30 #define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_TXRX, params) 31 #define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_TXRX, params) 32 #define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 33 #ifdef ENABLE_VERBOSE_DEBUG 34 extern bool is_hal_verbose_debug_enabled; 35 #define hal_verbose_debug(params...) \ 36 if (unlikely(is_hal_verbose_debug_enabled)) \ 37 do {\ 38 QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params); \ 39 } while (0) 40 #define hal_verbose_hex_dump(params...) \ 41 if (unlikely(is_hal_verbose_debug_enabled)) \ 42 do {\ 43 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, \ 44 QDF_TRACE_LEVEL_DEBUG, \ 45 params); \ 46 } while (0) 47 #else 48 #define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params) 49 #define hal_verbose_hex_dump(params...) \ 50 QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, \ 51 params) 52 #endif 53 54 /* 55 * dp_hal_soc - opaque handle for DP HAL soc 56 */ 57 struct hal_soc_handle; 58 typedef struct hal_soc_handle *hal_soc_handle_t; 59 60 /* TBD: This should be movded to shared HW header file */ 61 enum hal_srng_ring_id { 62 /* UMAC rings */ 63 HAL_SRNG_REO2SW1 = 0, 64 HAL_SRNG_REO2SW2 = 1, 65 HAL_SRNG_REO2SW3 = 2, 66 HAL_SRNG_REO2SW4 = 3, 67 HAL_SRNG_REO2TCL = 4, 68 HAL_SRNG_SW2REO = 5, 69 /* 6-7 unused */ 70 HAL_SRNG_REO_CMD = 8, 71 HAL_SRNG_REO_STATUS = 9, 72 /* 10-15 unused */ 73 HAL_SRNG_SW2TCL1 = 16, 74 HAL_SRNG_SW2TCL2 = 17, 75 HAL_SRNG_SW2TCL3 = 18, 76 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 77 /* 20-23 unused */ 78 HAL_SRNG_SW2TCL_CMD = 24, 79 HAL_SRNG_TCL_STATUS = 25, 80 /* 26-31 unused */ 81 HAL_SRNG_CE_0_SRC = 32, 82 HAL_SRNG_CE_1_SRC = 33, 83 HAL_SRNG_CE_2_SRC = 34, 84 HAL_SRNG_CE_3_SRC = 35, 85 HAL_SRNG_CE_4_SRC = 36, 86 HAL_SRNG_CE_5_SRC = 37, 87 HAL_SRNG_CE_6_SRC = 38, 88 HAL_SRNG_CE_7_SRC = 39, 89 HAL_SRNG_CE_8_SRC = 40, 90 HAL_SRNG_CE_9_SRC = 41, 91 HAL_SRNG_CE_10_SRC = 42, 92 HAL_SRNG_CE_11_SRC = 43, 93 /* 44-55 unused */ 94 HAL_SRNG_CE_0_DST = 56, 95 HAL_SRNG_CE_1_DST = 57, 96 HAL_SRNG_CE_2_DST = 58, 97 HAL_SRNG_CE_3_DST = 59, 98 HAL_SRNG_CE_4_DST = 60, 99 HAL_SRNG_CE_5_DST = 61, 100 HAL_SRNG_CE_6_DST = 62, 101 HAL_SRNG_CE_7_DST = 63, 102 HAL_SRNG_CE_8_DST = 64, 103 HAL_SRNG_CE_9_DST = 65, 104 HAL_SRNG_CE_10_DST = 66, 105 HAL_SRNG_CE_11_DST = 67, 106 /* 68-79 unused */ 107 HAL_SRNG_CE_0_DST_STATUS = 80, 108 HAL_SRNG_CE_1_DST_STATUS = 81, 109 HAL_SRNG_CE_2_DST_STATUS = 82, 110 HAL_SRNG_CE_3_DST_STATUS = 83, 111 HAL_SRNG_CE_4_DST_STATUS = 84, 112 HAL_SRNG_CE_5_DST_STATUS = 85, 113 HAL_SRNG_CE_6_DST_STATUS = 86, 114 HAL_SRNG_CE_7_DST_STATUS = 87, 115 HAL_SRNG_CE_8_DST_STATUS = 88, 116 HAL_SRNG_CE_9_DST_STATUS = 89, 117 HAL_SRNG_CE_10_DST_STATUS = 90, 118 HAL_SRNG_CE_11_DST_STATUS = 91, 119 /* 92-103 unused */ 120 HAL_SRNG_WBM_IDLE_LINK = 104, 121 HAL_SRNG_WBM_SW_RELEASE = 105, 122 HAL_SRNG_WBM2SW0_RELEASE = 106, 123 HAL_SRNG_WBM2SW1_RELEASE = 107, 124 HAL_SRNG_WBM2SW2_RELEASE = 108, 125 HAL_SRNG_WBM2SW3_RELEASE = 109, 126 /* 110-127 unused */ 127 HAL_SRNG_UMAC_ID_END = 127, 128 /* LMAC rings - The following set will be replicated for each LMAC */ 129 HAL_SRNG_LMAC1_ID_START = 128, 130 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 131 #ifdef IPA_OFFLOAD 132 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 133 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 134 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 135 #else 136 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 137 #endif 138 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 139 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 140 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 141 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 142 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 143 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 144 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 145 #ifdef WLAN_FEATURE_CIF_CFR 146 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 147 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 148 #else 149 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 150 #endif 151 /* -142 unused */ 152 HAL_SRNG_LMAC1_ID_END = 143 153 }; 154 155 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 156 #define HAL_MAX_LMACS 3 157 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 158 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 159 160 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 161 162 enum hal_srng_dir { 163 HAL_SRNG_SRC_RING, 164 HAL_SRNG_DST_RING 165 }; 166 167 /* Lock wrappers for SRNG */ 168 #define hal_srng_lock_t qdf_spinlock_t 169 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 170 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 171 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 172 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 173 174 struct hal_soc; 175 176 /** 177 * dp_hal_ring - opaque handle for DP HAL SRNG 178 */ 179 struct hal_ring_handle; 180 typedef struct hal_ring_handle *hal_ring_handle_t; 181 182 #define MAX_SRNG_REG_GROUPS 2 183 184 /* Hal Srng bit mask 185 * HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down 186 */ 187 #define HAL_SRNG_FLUSH_EVENT BIT(0) 188 189 /* Common SRNG ring structure for source and destination rings */ 190 struct hal_srng { 191 /* Unique SRNG ring ID */ 192 uint8_t ring_id; 193 194 /* Ring initialization done */ 195 uint8_t initialized; 196 197 /* Interrupt/MSI value assigned to this ring */ 198 int irq; 199 200 /* Physical base address of the ring */ 201 qdf_dma_addr_t ring_base_paddr; 202 203 /* Virtual base address of the ring */ 204 uint32_t *ring_base_vaddr; 205 206 /* Number of entries in ring */ 207 uint32_t num_entries; 208 209 /* Ring size */ 210 uint32_t ring_size; 211 212 /* Ring size mask */ 213 uint32_t ring_size_mask; 214 215 /* Size of ring entry */ 216 uint32_t entry_size; 217 218 /* Interrupt timer threshold – in micro seconds */ 219 uint32_t intr_timer_thres_us; 220 221 /* Interrupt batch counter threshold – in number of ring entries */ 222 uint32_t intr_batch_cntr_thres_entries; 223 224 /* MSI Address */ 225 qdf_dma_addr_t msi_addr; 226 227 /* MSI data */ 228 uint32_t msi_data; 229 230 /* Misc flags */ 231 uint32_t flags; 232 233 /* Lock for serializing ring index updates */ 234 hal_srng_lock_t lock; 235 236 /* Start offset of SRNG register groups for this ring 237 * TBD: See if this is required - register address can be derived 238 * from ring ID 239 */ 240 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 241 242 /* Source or Destination ring */ 243 enum hal_srng_dir ring_dir; 244 245 union { 246 struct { 247 /* SW tail pointer */ 248 uint32_t tp; 249 250 /* Shadow head pointer location to be updated by HW */ 251 uint32_t *hp_addr; 252 253 /* Cached head pointer */ 254 uint32_t cached_hp; 255 256 /* Tail pointer location to be updated by SW – This 257 * will be a register address and need not be 258 * accessed through SW structure */ 259 uint32_t *tp_addr; 260 261 /* Current SW loop cnt */ 262 uint32_t loop_cnt; 263 264 /* max transfer size */ 265 uint16_t max_buffer_length; 266 } dst_ring; 267 268 struct { 269 /* SW head pointer */ 270 uint32_t hp; 271 272 /* SW reap head pointer */ 273 uint32_t reap_hp; 274 275 /* Shadow tail pointer location to be updated by HW */ 276 uint32_t *tp_addr; 277 278 /* Cached tail pointer */ 279 uint32_t cached_tp; 280 281 /* Head pointer location to be updated by SW – This 282 * will be a register address and need not be accessed 283 * through SW structure */ 284 uint32_t *hp_addr; 285 286 /* Low threshold – in number of ring entries */ 287 uint32_t low_threshold; 288 } src_ring; 289 } u; 290 291 struct hal_soc *hal_soc; 292 293 /* Number of times hp/tp updated in runtime resume */ 294 uint32_t flush_count; 295 /* hal srng event flag*/ 296 unsigned long srng_event; 297 /* last flushed time stamp */ 298 uint64_t last_flush_ts; 299 }; 300 301 /* HW SRNG configuration table */ 302 struct hal_hw_srng_config { 303 int start_ring_id; 304 uint16_t max_rings; 305 uint16_t entry_size; 306 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 307 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 308 uint8_t lmac_ring; 309 enum hal_srng_dir ring_dir; 310 uint32_t max_size; 311 }; 312 313 #define MAX_SHADOW_REGISTERS 36 314 315 /* REO parameters to be passed to hal_reo_setup */ 316 struct hal_reo_params { 317 /** rx hash steering enabled or disabled */ 318 bool rx_hash_enabled; 319 /** reo remap 1 register */ 320 uint32_t remap1; 321 /** reo remap 2 register */ 322 uint32_t remap2; 323 /** fragment destination ring */ 324 uint8_t frag_dst_ring; 325 /** padding */ 326 uint8_t padding[3]; 327 }; 328 329 struct hal_hw_txrx_ops { 330 331 /* init and setup */ 332 void (*hal_srng_dst_hw_init)(struct hal_soc *hal, 333 struct hal_srng *srng); 334 void (*hal_srng_src_hw_init)(struct hal_soc *hal, 335 struct hal_srng *srng); 336 void (*hal_get_hw_hptp)(struct hal_soc *hal, 337 hal_ring_handle_t hal_ring_hdl, 338 uint32_t *headp, uint32_t *tailp, 339 uint8_t ring_type); 340 void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams); 341 void (*hal_setup_link_idle_list)( 342 struct hal_soc *hal_soc, 343 qdf_dma_addr_t scatter_bufs_base_paddr[], 344 void *scatter_bufs_base_vaddr[], 345 uint32_t num_scatter_bufs, 346 uint32_t scatter_buf_size, 347 uint32_t last_buf_end_offset, 348 uint32_t num_entries); 349 350 /* tx */ 351 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 352 void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map, 353 uint8_t id); 354 void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid, 355 uint8_t id, 356 uint8_t dscp); 357 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 358 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 359 uint8_t pool_id, uint32_t desc_id, uint8_t type); 360 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 361 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 362 void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); 363 void (*hal_tx_comp_get_status)(void *desc, void *ts, 364 struct hal_soc *hal); 365 uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc); 366 void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); 367 368 /* rx */ 369 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 370 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 371 struct mon_rx_status *rs); 372 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 373 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 374 void *ppdu_info_handle); 375 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 376 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 377 uint8_t dbg_level); 378 uint32_t (*hal_get_link_desc_size)(void); 379 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 380 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 381 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 382 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 383 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 384 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 385 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 386 void *ppdu_info, 387 hal_soc_handle_t hal_soc_hdl, 388 qdf_nbuf_t nbuf); 389 void (*hal_rx_wbm_err_info_get)(void *wbm_desc, 390 void *wbm_er_info); 391 void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart, 392 uint8_t dbg_level); 393 394 void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map); 395 void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, 396 uint8_t id); 397 void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); 398 uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); 399 uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); 400 uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); 401 uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf); 402 uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr); 403 uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf); 404 uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf); 405 void (*hal_rx_print_pn)(uint8_t *buf); 406 uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf); 407 uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf); 408 uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf); 409 bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf); 410 uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf); 411 uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf); 412 uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf); 413 uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf); 414 QDF_STATUS 415 (*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr); 416 QDF_STATUS 417 (*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr); 418 QDF_STATUS 419 (*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr); 420 QDF_STATUS 421 (*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr); 422 uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf); 423 bool (*hal_rx_is_unicast)(uint8_t *buf); 424 uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf); 425 uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *hw_desc_addr); 426 uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf); 427 uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf); 428 void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr); 429 void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0); 430 void * (*hal_ent_mpdu_desc_info)(void *hw_addr); 431 void * (*hal_dst_mpdu_desc_info)(void *hw_addr); 432 uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf); 433 uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf); 434 uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf); 435 uint8_t (*hal_rx_get_filter_category)(uint8_t *buf); 436 uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf); 437 void (*hal_reo_config)(struct hal_soc *soc, 438 uint32_t reg_val, 439 struct hal_reo_params *reo_params); 440 uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf); 441 bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf); 442 bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf); 443 uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf); 444 uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf); 445 void 446 (*hal_rx_msdu_get_flow_params)( 447 uint8_t *buf, 448 bool *flow_invalid, 449 bool *flow_timeout, 450 uint32_t *flow_index); 451 uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); 452 uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf); 453 }; 454 455 /** 456 * HAL context to be used to access SRNG APIs (currently used by data path 457 * and transport (CE) modules) 458 */ 459 struct hal_soc { 460 /* HIF handle to access HW registers */ 461 struct hif_opaque_softc *hif_handle; 462 463 /* QDF device handle */ 464 qdf_device_t qdf_dev; 465 466 /* Device base address */ 467 void *dev_base_addr; 468 469 /* HAL internal state for all SRNG rings. 470 * TODO: See if this is required 471 */ 472 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 473 474 /* Remote pointer memory for HW/FW updates */ 475 uint32_t *shadow_rdptr_mem_vaddr; 476 qdf_dma_addr_t shadow_rdptr_mem_paddr; 477 478 /* Shared memory for ring pointer updates from host to FW */ 479 uint32_t *shadow_wrptr_mem_vaddr; 480 qdf_dma_addr_t shadow_wrptr_mem_paddr; 481 482 /* REO blocking resource index */ 483 uint8_t reo_res_bitmap; 484 uint8_t index; 485 uint32_t target_type; 486 487 /* shadow register configuration */ 488 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 489 int num_shadow_registers_configured; 490 bool use_register_windowing; 491 uint32_t register_window; 492 qdf_spinlock_t register_access_lock; 493 494 /* srng table */ 495 struct hal_hw_srng_config *hw_srng_table; 496 int32_t *hal_hw_reg_offset; 497 struct hal_hw_txrx_ops *ops; 498 }; 499 500 void hal_qca6490_attach(struct hal_soc *hal_soc); 501 void hal_qca6390_attach(struct hal_soc *hal_soc); 502 void hal_qca6290_attach(struct hal_soc *hal_soc); 503 void hal_qca8074_attach(struct hal_soc *hal_soc); 504 505 /* 506 * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque 507 * dp_hal_soc handle type 508 * @hal_soc - hal_soc type 509 * 510 * Return: hal_soc_handle_t type 511 */ 512 static inline 513 hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc) 514 { 515 return (hal_soc_handle_t)hal_soc; 516 } 517 518 /* 519 * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque 520 * dp_hal_ring handle type 521 * @hal_srng - hal_srng type 522 * 523 * Return: hal_ring_handle_t type 524 */ 525 static inline 526 hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng) 527 { 528 return (hal_ring_handle_t)hal_srng; 529 } 530 531 /* 532 * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle 533 * @hal_ring - hal_ring_handle_t type 534 * 535 * Return: hal_srng pointer type 536 */ 537 static inline 538 struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring) 539 { 540 return (struct hal_srng *)hal_ring; 541 } 542 #endif /* _HAL_INTERNAL_H_ */ 543