1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_INTERNAL_H_ 20 #define _HAL_INTERNAL_H_ 21 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "pld_common.h" 27 28 29 /* TBD: This should be movded to shared HW header file */ 30 enum hal_srng_ring_id { 31 /* UMAC rings */ 32 HAL_SRNG_REO2SW1 = 0, 33 HAL_SRNG_REO2SW2 = 1, 34 HAL_SRNG_REO2SW3 = 2, 35 HAL_SRNG_REO2SW4 = 3, 36 HAL_SRNG_REO2TCL = 4, 37 HAL_SRNG_SW2REO = 5, 38 /* 6-7 unused */ 39 HAL_SRNG_REO_CMD = 8, 40 HAL_SRNG_REO_STATUS = 9, 41 /* 10-15 unused */ 42 HAL_SRNG_SW2TCL1 = 16, 43 HAL_SRNG_SW2TCL2 = 17, 44 HAL_SRNG_SW2TCL3 = 18, 45 HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ 46 /* 20-23 unused */ 47 HAL_SRNG_SW2TCL_CMD = 24, 48 HAL_SRNG_TCL_STATUS = 25, 49 /* 26-31 unused */ 50 HAL_SRNG_CE_0_SRC = 32, 51 HAL_SRNG_CE_1_SRC = 33, 52 HAL_SRNG_CE_2_SRC = 34, 53 HAL_SRNG_CE_3_SRC = 35, 54 HAL_SRNG_CE_4_SRC = 36, 55 HAL_SRNG_CE_5_SRC = 37, 56 HAL_SRNG_CE_6_SRC = 38, 57 HAL_SRNG_CE_7_SRC = 39, 58 HAL_SRNG_CE_8_SRC = 40, 59 HAL_SRNG_CE_9_SRC = 41, 60 HAL_SRNG_CE_10_SRC = 42, 61 HAL_SRNG_CE_11_SRC = 43, 62 /* 44-55 unused */ 63 HAL_SRNG_CE_0_DST = 56, 64 HAL_SRNG_CE_1_DST = 57, 65 HAL_SRNG_CE_2_DST = 58, 66 HAL_SRNG_CE_3_DST = 59, 67 HAL_SRNG_CE_4_DST = 60, 68 HAL_SRNG_CE_5_DST = 61, 69 HAL_SRNG_CE_6_DST = 62, 70 HAL_SRNG_CE_7_DST = 63, 71 HAL_SRNG_CE_8_DST = 64, 72 HAL_SRNG_CE_9_DST = 65, 73 HAL_SRNG_CE_10_DST = 66, 74 HAL_SRNG_CE_11_DST = 67, 75 /* 68-79 unused */ 76 HAL_SRNG_CE_0_DST_STATUS = 80, 77 HAL_SRNG_CE_1_DST_STATUS = 81, 78 HAL_SRNG_CE_2_DST_STATUS = 82, 79 HAL_SRNG_CE_3_DST_STATUS = 83, 80 HAL_SRNG_CE_4_DST_STATUS = 84, 81 HAL_SRNG_CE_5_DST_STATUS = 85, 82 HAL_SRNG_CE_6_DST_STATUS = 86, 83 HAL_SRNG_CE_7_DST_STATUS = 87, 84 HAL_SRNG_CE_8_DST_STATUS = 88, 85 HAL_SRNG_CE_9_DST_STATUS = 89, 86 HAL_SRNG_CE_10_DST_STATUS = 90, 87 HAL_SRNG_CE_11_DST_STATUS = 91, 88 /* 92-103 unused */ 89 HAL_SRNG_WBM_IDLE_LINK = 104, 90 HAL_SRNG_WBM_SW_RELEASE = 105, 91 HAL_SRNG_WBM2SW0_RELEASE = 106, 92 HAL_SRNG_WBM2SW1_RELEASE = 107, 93 HAL_SRNG_WBM2SW2_RELEASE = 108, 94 HAL_SRNG_WBM2SW3_RELEASE = 109, 95 /* 110-127 unused */ 96 HAL_SRNG_UMAC_ID_END = 127, 97 /* LMAC rings - The following set will be replicated for each LMAC */ 98 HAL_SRNG_LMAC1_ID_START = 128, 99 HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, 100 #ifdef IPA_OFFLOAD 101 HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), 102 HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), 103 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), 104 #else 105 HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), 106 #endif 107 HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), 108 HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), 109 HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = 110 (HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), 111 HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), 112 HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), 113 HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), 114 #ifdef WLAN_FEATURE_CIF_CFR 115 HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 116 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), 117 #else 118 HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), 119 #endif 120 /* -142 unused */ 121 HAL_SRNG_LMAC1_ID_END = 143 122 }; 123 124 #define HAL_RXDMA_MAX_RING_SIZE 0xFFFF 125 #define HAL_MAX_LMACS 3 126 #define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START) 127 #define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC) 128 129 #define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS) 130 131 enum hal_srng_dir { 132 HAL_SRNG_SRC_RING, 133 HAL_SRNG_DST_RING 134 }; 135 136 /* Lock wrappers for SRNG */ 137 #define hal_srng_lock_t qdf_spinlock_t 138 #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) 139 #define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock) 140 #define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock) 141 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock) 142 143 struct hal_soc; 144 #define MAX_SRNG_REG_GROUPS 2 145 146 /* Common SRNG ring structure for source and destination rings */ 147 struct hal_srng { 148 /* Unique SRNG ring ID */ 149 uint8_t ring_id; 150 151 /* Ring initialization done */ 152 uint8_t initialized; 153 154 /* Interrupt/MSI value assigned to this ring */ 155 int irq; 156 157 /* Physical base address of the ring */ 158 qdf_dma_addr_t ring_base_paddr; 159 160 /* Virtual base address of the ring */ 161 uint32_t *ring_base_vaddr; 162 163 /* Number of entries in ring */ 164 uint32_t num_entries; 165 166 /* Ring size */ 167 uint32_t ring_size; 168 169 /* Ring size mask */ 170 uint32_t ring_size_mask; 171 172 /* Size of ring entry */ 173 uint32_t entry_size; 174 175 /* Interrupt timer threshold – in micro seconds */ 176 uint32_t intr_timer_thres_us; 177 178 /* Interrupt batch counter threshold – in number of ring entries */ 179 uint32_t intr_batch_cntr_thres_entries; 180 181 /* MSI Address */ 182 qdf_dma_addr_t msi_addr; 183 184 /* MSI data */ 185 uint32_t msi_data; 186 187 /* Misc flags */ 188 uint32_t flags; 189 190 /* Lock for serializing ring index updates */ 191 hal_srng_lock_t lock; 192 193 /* Start offset of SRNG register groups for this ring 194 * TBD: See if this is required - register address can be derived 195 * from ring ID 196 */ 197 void *hwreg_base[MAX_SRNG_REG_GROUPS]; 198 199 /* Source or Destination ring */ 200 enum hal_srng_dir ring_dir; 201 202 union { 203 struct { 204 /* SW tail pointer */ 205 uint32_t tp; 206 207 /* Shadow head pointer location to be updated by HW */ 208 uint32_t *hp_addr; 209 210 /* Cached head pointer */ 211 uint32_t cached_hp; 212 213 /* Tail pointer location to be updated by SW – This 214 * will be a register address and need not be 215 * accessed through SW structure */ 216 uint32_t *tp_addr; 217 218 /* Current SW loop cnt */ 219 uint32_t loop_cnt; 220 221 /* max transfer size */ 222 uint16_t max_buffer_length; 223 } dst_ring; 224 225 struct { 226 /* SW head pointer */ 227 uint32_t hp; 228 229 /* SW reap head pointer */ 230 uint32_t reap_hp; 231 232 /* Shadow tail pointer location to be updated by HW */ 233 uint32_t *tp_addr; 234 235 /* Cached tail pointer */ 236 uint32_t cached_tp; 237 238 /* Head pointer location to be updated by SW – This 239 * will be a register address and need not be accessed 240 * through SW structure */ 241 uint32_t *hp_addr; 242 243 /* Low threshold – in number of ring entries */ 244 uint32_t low_threshold; 245 } src_ring; 246 } u; 247 248 struct hal_soc *hal_soc; 249 }; 250 251 /* HW SRNG configuration table */ 252 struct hal_hw_srng_config { 253 int start_ring_id; 254 uint16_t max_rings; 255 uint16_t entry_size; 256 uint32_t reg_start[MAX_SRNG_REG_GROUPS]; 257 uint16_t reg_size[MAX_SRNG_REG_GROUPS]; 258 uint8_t lmac_ring; 259 enum hal_srng_dir ring_dir; 260 uint32_t max_size; 261 }; 262 263 #define MAX_SHADOW_REGISTERS 36 264 265 struct hal_hw_txrx_ops { 266 267 /* init and setup */ 268 void (*hal_srng_dst_hw_init)(void *hal, 269 struct hal_srng *srng); 270 void (*hal_srng_src_hw_init)(void *hal, 271 struct hal_srng *srng); 272 void (*hal_reo_setup)(void *hal_soc, void *reoparams); 273 void (*hal_setup_link_idle_list)(void *hal_soc, 274 qdf_dma_addr_t scatter_bufs_base_paddr[], 275 void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs, 276 uint32_t scatter_buf_size, uint32_t last_buf_end_offset, 277 uint32_t num_entries); 278 279 /* tx */ 280 void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); 281 void (*hal_tx_set_dscp_tid_map)(void *hal_soc, uint8_t *map, 282 uint8_t id); 283 void (*hal_tx_update_dscp_tid)(void *hal_soc, uint8_t tid, uint8_t id, 284 uint8_t dscp); 285 void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); 286 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, 287 uint8_t pool_id, uint32_t desc_id, uint8_t type); 288 void (*hal_tx_comp_get_status)(void *desc, void *ts); 289 290 /* rx */ 291 uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); 292 void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr, 293 struct mon_rx_status *rs); 294 uint8_t (*hal_rx_get_tlv)(void *rx_tlv); 295 void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr, 296 void *ppdu_info_handle); 297 void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level); 298 void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end, 299 uint8_t dbg_level); 300 uint32_t (*hal_get_link_desc_size)(void); 301 uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf); 302 uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf); 303 uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); 304 void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); 305 void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); 306 void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); 307 uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, 308 void *ppdu_info, 309 void *hal); 310 void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); 311 void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); 312 }; 313 314 /** 315 * HAL context to be used to access SRNG APIs (currently used by data path 316 * and transport (CE) modules) 317 */ 318 struct hal_soc { 319 /* HIF handle to access HW registers */ 320 void *hif_handle; 321 322 /* QDF device handle */ 323 qdf_device_t qdf_dev; 324 325 /* Device base address */ 326 void *dev_base_addr; 327 328 /* HAL internal state for all SRNG rings. 329 * TODO: See if this is required 330 */ 331 struct hal_srng srng_list[HAL_SRNG_ID_MAX]; 332 333 /* Remote pointer memory for HW/FW updates */ 334 uint32_t *shadow_rdptr_mem_vaddr; 335 qdf_dma_addr_t shadow_rdptr_mem_paddr; 336 337 /* Shared memory for ring pointer updates from host to FW */ 338 uint32_t *shadow_wrptr_mem_vaddr; 339 qdf_dma_addr_t shadow_wrptr_mem_paddr; 340 341 /* REO blocking resource index */ 342 uint8_t reo_res_bitmap; 343 uint8_t index; 344 uint32_t target_type; 345 346 /* shadow register configuration */ 347 struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS]; 348 int num_shadow_registers_configured; 349 bool use_register_windowing; 350 uint32_t register_window; 351 qdf_spinlock_t register_access_lock; 352 353 /* srng table */ 354 struct hal_hw_srng_config *hw_srng_table; 355 int32_t *hal_hw_reg_offset; 356 struct hal_hw_txrx_ops *ops; 357 }; 358 359 void hal_qca6390_attach(struct hal_soc *hal_soc); 360 void hal_qca6290_attach(struct hal_soc *hal_soc); 361 void hal_qca8074_attach(struct hal_soc *hal_soc); 362 #endif /* _HAL_INTERNAL_H_ */ 363