1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_HW_INTERNAL_H_ 20 #define _HAL_HW_INTERNAL_H_ 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "rx_msdu_link.h" 25 #include "rx_reo_queue.h" 26 #include "rx_reo_queue_ext.h" 27 #include "wcss_seq_hwiobase.h" 28 #include "tlv_hdr.h" 29 #include "tlv_tag_def.h" 30 #include "reo_destination_ring.h" 31 #include "reo_reg_seq_hwioreg.h" 32 #include "reo_entrance_ring.h" 33 #include "reo_get_queue_stats.h" 34 #include "reo_get_queue_stats_status.h" 35 #include "tcl_data_cmd.h" 36 #include "tcl_gse_cmd.h" 37 #include "tcl_status_ring.h" 38 #include "mac_tcl_reg_seq_hwioreg.h" 39 #include "ce_src_desc.h" 40 #include "ce_stat_desc.h" 41 #ifdef QCA_WIFI_QCA6490 42 #include "wfss_ce_channel_dst_reg_seq_hwioreg.h" 43 #include "wfss_ce_channel_src_reg_seq_hwioreg.h" 44 #else 45 #include "wfss_ce_reg_seq_hwioreg.h" 46 #endif /* QCA_WIFI_QCA6490 */ 47 #include "wbm_link_descriptor_ring.h" 48 #include "wbm_reg_seq_hwioreg.h" 49 #include "wbm_buffer_ring.h" 50 #include "wbm_release_ring.h" 51 #include "rx_msdu_desc_info.h" 52 #include "rx_mpdu_start.h" 53 #include "rx_mpdu_end.h" 54 #include "rx_msdu_start.h" 55 #include "rx_msdu_end.h" 56 #include "rx_attention.h" 57 #include "rx_ppdu_start.h" 58 #include "rx_ppdu_start_user_info.h" 59 #include "rx_ppdu_end_user_stats.h" 60 #include "rx_ppdu_end_user_stats_ext.h" 61 #include "rx_mpdu_desc_info.h" 62 #include "rxpcu_ppdu_end_info.h" 63 #include "phyrx_he_sig_a_su.h" 64 #include "phyrx_he_sig_a_mu_dl.h" 65 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 66 #include "phyrx_he_sig_a_mu_ul.h" 67 #endif 68 #include "phyrx_he_sig_b1_mu.h" 69 #include "phyrx_he_sig_b2_mu.h" 70 #include "phyrx_he_sig_b2_ofdma.h" 71 #include "phyrx_l_sig_a.h" 72 #include "phyrx_l_sig_b.h" 73 #include "phyrx_vht_sig_a.h" 74 #include "phyrx_ht_sig.h" 75 #include "tx_msdu_extension.h" 76 #include "receive_rssi_info.h" 77 #include "phyrx_pkt_end.h" 78 #include "phyrx_rssi_legacy.h" 79 #include "wcss_version.h" 80 #include "rx_msdu_link.h" 81 #include "hal_internal.h" 82 83 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 84 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 85 #define HAL_NON_QOS_TID 16 86 87 /* TODO: Check if the following can be provided directly by HW headers */ 88 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 89 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 90 91 /* HAL Macro to get the buffer info size */ 92 #define HAL_RX_BUFFINFO_NUM_DWORDS NUM_OF_DWORDS_BUFFER_ADDR_INFO 93 94 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS 100 /* milliseconds */ 95 #define HAL_DEFAULT_VO_REO_TIMEOUT_MS 40 /* milliseconds */ 96 97 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ 98 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ 99 ~(_word ## _ ## _fld ## _MASK); \ 100 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ 101 ((_value) << _word ## _ ## _fld ## _LSB); \ 102 } while (0) 103 104 #define HAL_SM(_reg, _fld, _val) \ 105 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ 106 (_reg ## _ ## _fld ## _BMSK)) 107 108 #define HAL_MS(_reg, _fld, _val) \ 109 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ 110 (_reg ## _ ## _fld ## _SHFT)) 111 112 #define HAL_REG_WRITE(_soc, _reg, _value) \ 113 hal_write32_mb(_soc, (_reg), (_value)) 114 115 /* Check register writing result */ 116 #define HAL_REG_WRITE_CONFIRM(_soc, _reg, _value) \ 117 hal_write32_mb_confirm(_soc, (_reg), (_value)) 118 119 #define HAL_REG_READ(_soc, _offset) \ 120 hal_read32_mb(_soc, (_offset)) 121 122 #define WBM_IDLE_DESC_LIST 1 123 124 /** 125 * Common SRNG register access macros: 126 * The SRNG registers are distributed across various UMAC and LMAC HW blocks, 127 * but the register group and format is exactly same for all rings, with some 128 * difference between producer rings (these are 'producer rings' with respect 129 * to HW and referred as 'destination rings' in SW) and consumer rings (these 130 * are 'consumer rings' with respect to HW and 131 * referred as 'source rings' in SW). 132 * The following macros provide uniform access to all SRNG rings. 133 */ 134 135 /* SRNG registers are split among two groups R0 and R2 and following 136 * definitions identify the group to which each register belongs to 137 */ 138 #define R0_INDEX 0 139 #define R2_INDEX 1 140 141 #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX 142 143 /* Registers in R0 group */ 144 #define BASE_LSB_GROUP R0 145 #define BASE_MSB_GROUP R0 146 #define ID_GROUP R0 147 #define STATUS_GROUP R0 148 #define MISC_GROUP R0 149 #define HP_ADDR_LSB_GROUP R0 150 #define HP_ADDR_MSB_GROUP R0 151 #define PRODUCER_INT_SETUP_GROUP R0 152 #define PRODUCER_INT_STATUS_GROUP R0 153 #define PRODUCER_FULL_COUNTER_GROUP R0 154 #define MSI1_BASE_LSB_GROUP R0 155 #define MSI1_BASE_MSB_GROUP R0 156 #define MSI1_DATA_GROUP R0 157 #define HP_TP_SW_OFFSET_GROUP R0 158 #define TP_ADDR_LSB_GROUP R0 159 #define TP_ADDR_MSB_GROUP R0 160 #define CONSUMER_INT_SETUP_IX0_GROUP R0 161 #define CONSUMER_INT_SETUP_IX1_GROUP R0 162 #define CONSUMER_INT_STATUS_GROUP R0 163 #define CONSUMER_EMPTY_COUNTER_GROUP R0 164 #define CONSUMER_PREFETCH_TIMER_GROUP R0 165 #define CONSUMER_PREFETCH_STATUS_GROUP R0 166 167 /* Registers in R2 group */ 168 #define HP_GROUP R2 169 #define TP_GROUP R2 170 171 /** 172 * Register definitions for all SRNG based rings are same, except few 173 * differences between source (HW consumer) and destination (HW producer) 174 * registers. Following macros definitions provide generic access to all 175 * SRNG based rings. 176 * For source rings, we will use the register/field definitions of SW2TCL1 177 * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup 178 * individual fields, SRNG_SM macros should be used with fields specified 179 * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done 180 * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>). 181 * Similarly for destination rings we will use definitions of REO2SW1 ring 182 * defined in the register reo_destination_ring.h. To setup individual 183 * fields SRNG_SM macros should be used with fields specified using 184 * SRNG_DST_FLD(<register>, <field>). Register writes should be done using 185 * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>). 186 */ 187 188 #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \ 189 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0) 190 191 #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \ 192 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0) 193 194 #define _SRNG_DST_FLD(_reg_group, _reg_fld) \ 195 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld 196 #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \ 197 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld 198 199 #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \ 200 _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld) 201 202 #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST) 203 #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC) 204 205 #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0) 206 #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0) 207 208 #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2) 209 #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2) 210 211 #define SRNG_SRC_START_OFFSET(_reg_group) \ 212 SRNG_SRC_ ## _reg_group ## _START_OFFSET 213 #define SRNG_DST_START_OFFSET(_reg_group) \ 214 SRNG_DST_ ## _reg_group ## _START_OFFSET 215 #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \ 216 ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \ 217 ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg])) 218 219 #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \ 220 (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \ 221 SRNG_ ## _dir ## _START_OFFSET(_reg_group)) 222 223 #define REG_OFFSET(_dir, _reg) \ 224 CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP) 225 226 #define SRNG_DST_ADDR(_srng, _reg) \ 227 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST) 228 229 #define SRNG_SRC_ADDR(_srng, _reg) \ 230 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC) 231 232 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \ 233 hal_write_address_32_mb(_srng->hal_soc,\ 234 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), false) 235 236 #define SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, _dir) \ 237 hal_write_address_32_mb(_srng->hal_soc,\ 238 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), true) 239 240 #define SRNG_REG_READ(_srng, _reg, _dir) \ 241 hal_read_address_32_mb(_srng->hal_soc, \ 242 SRNG_ ## _dir ## _ADDR(_srng, _reg)) 243 244 #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \ 245 SRNG_REG_WRITE(_srng, _reg, _value, SRC) 246 247 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \ 248 SRNG_REG_WRITE(_srng, _reg, _value, DST) 249 250 #define SRNG_DST_REG_WRITE_CONFIRM(_srng, _reg, _value) \ 251 SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, DST) 252 253 #define SRNG_SRC_REG_READ(_srng, _reg) \ 254 SRNG_REG_READ(_srng, _reg, SRC) 255 256 #define SRNG_DST_REG_READ(_srng, _reg) \ 257 SRNG_REG_READ(_srng, _reg, DST) 258 259 #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK 260 #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT 261 262 #define SRNG_SM(_reg_fld, _val) \ 263 (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld)) 264 265 #define SRNG_MS(_reg_fld, _val) \ 266 (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld)) 267 268 #define SRNG_MAX_SIZE_DWORDS \ 269 (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff)) 270 271 /** 272 * HW ring configuration table to identify hardware ring attributes like 273 * register addresses, number of rings, ring entry size etc., for each type 274 * of SRNG ring. 275 * 276 * Currently there is just one HW ring table, but there could be multiple 277 * configurations in future based on HW variants from the same wifi3.0 family 278 * and hence need to be attached with hal_soc based on HW type 279 */ 280 #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \ 281 (&_hal_soc->hw_srng_table[_ring_type]) 282 283 enum SRNG_REGISTERS { 284 DST_HP = 0, 285 DST_TP, 286 DST_ID, 287 DST_MISC, 288 DST_HP_ADDR_LSB, 289 DST_HP_ADDR_MSB, 290 DST_MSI1_BASE_LSB, 291 DST_MSI1_BASE_MSB, 292 DST_MSI1_DATA, 293 DST_BASE_LSB, 294 DST_BASE_MSB, 295 DST_PRODUCER_INT_SETUP, 296 297 SRC_HP, 298 SRC_TP, 299 SRC_ID, 300 SRC_MISC, 301 SRC_TP_ADDR_LSB, 302 SRC_TP_ADDR_MSB, 303 SRC_MSI1_BASE_LSB, 304 SRC_MSI1_BASE_MSB, 305 SRC_MSI1_DATA, 306 SRC_BASE_LSB, 307 SRC_BASE_MSB, 308 SRC_CONSUMER_INT_SETUP_IX0, 309 SRC_CONSUMER_INT_SETUP_IX1, 310 }; 311 312 /** 313 * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info 314 * HW structure 315 * 316 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 317 * @cookie: SW cookie for the buffer/descriptor 318 * @link_desc_paddr: Physical address of link descriptor entry 319 * 320 */ 321 static inline void hal_set_link_desc_addr(void *desc, uint32_t cookie, 322 qdf_dma_addr_t link_desc_paddr) 323 { 324 uint32_t *buf_addr = (uint32_t *)desc; 325 326 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 327 link_desc_paddr & 0xffffffff); 328 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 329 (uint64_t)link_desc_paddr >> 32); 330 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 331 WBM_IDLE_DESC_LIST); 332 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 333 cookie); 334 } 335 336 /** 337 * hal_get_reo_qdesc_size - Get size of reo queue descriptor 338 * 339 * @hal_soc: Opaque HAL SOC handle 340 * @ba_window_size: BlockAck window size 341 * @tid: TID number 342 * 343 */ 344 static inline 345 uint32_t hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl, 346 uint32_t ba_window_size, int tid) 347 { 348 /* Return descriptor size corresponding to window size of 2 since 349 * we set ba_window_size to 2 while setting up REO descriptors as 350 * a WAR to get 2k jump exception aggregates are received without 351 * a BA session. 352 */ 353 if (ba_window_size <= 1) { 354 if (tid != HAL_NON_QOS_TID) 355 return sizeof(struct rx_reo_queue) + 356 sizeof(struct rx_reo_queue_ext); 357 else 358 return sizeof(struct rx_reo_queue); 359 } 360 361 if (ba_window_size <= 105) 362 return sizeof(struct rx_reo_queue) + 363 sizeof(struct rx_reo_queue_ext); 364 365 if (ba_window_size <= 210) 366 return sizeof(struct rx_reo_queue) + 367 (2 * sizeof(struct rx_reo_queue_ext)); 368 369 return sizeof(struct rx_reo_queue) + 370 (3 * sizeof(struct rx_reo_queue_ext)); 371 } 372 373 #endif /* _HAL_HW_INTERNAL_H_ */ 374