1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_HW_INTERNAL_H_ 20 #define _HAL_HW_INTERNAL_H_ 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "rx_msdu_link.h" 25 #include "rx_reo_queue.h" 26 #include "rx_reo_queue_ext.h" 27 #include "wcss_seq_hwiobase.h" 28 #include "tlv_hdr.h" 29 #include "tlv_tag_def.h" 30 #include "reo_destination_ring.h" 31 #include "reo_reg_seq_hwioreg.h" 32 #include "reo_entrance_ring.h" 33 #include "reo_get_queue_stats.h" 34 #include "reo_get_queue_stats_status.h" 35 #include "tcl_data_cmd.h" 36 #include "tcl_gse_cmd.h" 37 #include "tcl_status_ring.h" 38 #include "mac_tcl_reg_seq_hwioreg.h" 39 #include "ce_src_desc.h" 40 #include "ce_stat_desc.h" 41 #ifdef QCA_WIFI_QCA6490 42 #include "wfss_ce_channel_dst_reg_seq_hwioreg.h" 43 #include "wfss_ce_channel_src_reg_seq_hwioreg.h" 44 #else 45 #include "wfss_ce_reg_seq_hwioreg.h" 46 #endif /* QCA_WIFI_QCA6490 */ 47 #include "wbm_link_descriptor_ring.h" 48 #include "wbm_reg_seq_hwioreg.h" 49 #include "wbm_buffer_ring.h" 50 #include "wbm_release_ring.h" 51 #include "rx_msdu_desc_info.h" 52 #include "rx_mpdu_start.h" 53 #include "rx_mpdu_end.h" 54 #include "rx_msdu_start.h" 55 #include "rx_msdu_end.h" 56 #include "rx_attention.h" 57 #include "rx_ppdu_start.h" 58 #include "rx_ppdu_start_user_info.h" 59 #include "rx_ppdu_end_user_stats.h" 60 #include "rx_ppdu_end_user_stats_ext.h" 61 #include "rx_mpdu_desc_info.h" 62 #include "rxpcu_ppdu_end_info.h" 63 #include "phyrx_he_sig_a_su.h" 64 #include "phyrx_he_sig_a_mu_dl.h" 65 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 66 #include "phyrx_he_sig_a_mu_ul.h" 67 #endif 68 #include "phyrx_he_sig_b1_mu.h" 69 #include "phyrx_he_sig_b2_mu.h" 70 #include "phyrx_he_sig_b2_ofdma.h" 71 #include "phyrx_l_sig_a.h" 72 #include "phyrx_l_sig_b.h" 73 #include "phyrx_vht_sig_a.h" 74 #include "phyrx_ht_sig.h" 75 #include "tx_msdu_extension.h" 76 #include "receive_rssi_info.h" 77 #include "phyrx_pkt_end.h" 78 #include "phyrx_rssi_legacy.h" 79 #include "wcss_version.h" 80 #include "rx_msdu_link.h" 81 #include "hal_internal.h" 82 83 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 84 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 85 #define HAL_NON_QOS_TID 16 86 87 /* TODO: Check if the following can be provided directly by HW headers */ 88 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 89 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 90 91 /* HAL Macro to get the buffer info size */ 92 #define HAL_RX_BUFFINFO_NUM_DWORDS NUM_OF_DWORDS_BUFFER_ADDR_INFO 93 94 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS 100 /* milliseconds */ 95 #define HAL_DEFAULT_VO_REO_TIMEOUT_MS 40 /* milliseconds */ 96 97 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ 98 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ 99 ~(_word ## _ ## _fld ## _MASK); \ 100 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ 101 ((_value) << _word ## _ ## _fld ## _LSB); \ 102 } while (0) 103 104 #define HAL_SM(_reg, _fld, _val) \ 105 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ 106 (_reg ## _ ## _fld ## _BMSK)) 107 108 #define HAL_MS(_reg, _fld, _val) \ 109 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ 110 (_reg ## _ ## _fld ## _SHFT)) 111 112 #define HAL_REG_WRITE(_soc, _reg, _value) \ 113 hal_write32_mb(_soc, (_reg), (_value)) 114 115 /* Check register writing result */ 116 #define HAL_REG_WRITE_CONFIRM(_soc, _reg, _value) \ 117 hal_write32_mb_confirm(_soc, (_reg), (_value)) 118 119 #define HAL_REG_WRITE_CONFIRM_RETRY(_soc, _reg, _value, _recovery) \ 120 hal_write32_mb_confirm_retry(_soc, (_reg), (_value), (_recovery)) 121 122 #define HAL_REG_READ(_soc, _offset) \ 123 hal_read32_mb(_soc, (_offset)) 124 125 #define HAL_CMEM_WRITE(_soc, _reg, _value) \ 126 hal_write32_mb_cmem(_soc, (_reg), (_value)) 127 128 #define HAL_CMEM_READ(_soc, _offset) \ 129 hal_read32_mb_cmem(_soc, (_offset)) 130 131 #define WBM_IDLE_DESC_LIST 1 132 133 /** 134 * Common SRNG register access macros: 135 * The SRNG registers are distributed across various UMAC and LMAC HW blocks, 136 * but the register group and format is exactly same for all rings, with some 137 * difference between producer rings (these are 'producer rings' with respect 138 * to HW and referred as 'destination rings' in SW) and consumer rings (these 139 * are 'consumer rings' with respect to HW and 140 * referred as 'source rings' in SW). 141 * The following macros provide uniform access to all SRNG rings. 142 */ 143 144 /* SRNG registers are split among two groups R0 and R2 and following 145 * definitions identify the group to which each register belongs to 146 */ 147 #define R0_INDEX 0 148 #define R2_INDEX 1 149 150 #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX 151 152 /* Registers in R0 group */ 153 #define BASE_LSB_GROUP R0 154 #define BASE_MSB_GROUP R0 155 #define ID_GROUP R0 156 #define STATUS_GROUP R0 157 #define MISC_GROUP R0 158 #define HP_ADDR_LSB_GROUP R0 159 #define HP_ADDR_MSB_GROUP R0 160 #define PRODUCER_INT_SETUP_GROUP R0 161 #define PRODUCER_INT_STATUS_GROUP R0 162 #define PRODUCER_FULL_COUNTER_GROUP R0 163 #define MSI1_BASE_LSB_GROUP R0 164 #define MSI1_BASE_MSB_GROUP R0 165 #define MSI1_DATA_GROUP R0 166 #define HP_TP_SW_OFFSET_GROUP R0 167 #define TP_ADDR_LSB_GROUP R0 168 #define TP_ADDR_MSB_GROUP R0 169 #define CONSUMER_INT_SETUP_IX0_GROUP R0 170 #define CONSUMER_INT_SETUP_IX1_GROUP R0 171 #define CONSUMER_INT_STATUS_GROUP R0 172 #define CONSUMER_EMPTY_COUNTER_GROUP R0 173 #define CONSUMER_PREFETCH_TIMER_GROUP R0 174 #define CONSUMER_PREFETCH_STATUS_GROUP R0 175 176 /* Registers in R2 group */ 177 #define HP_GROUP R2 178 #define TP_GROUP R2 179 180 /** 181 * Register definitions for all SRNG based rings are same, except few 182 * differences between source (HW consumer) and destination (HW producer) 183 * registers. Following macros definitions provide generic access to all 184 * SRNG based rings. 185 * For source rings, we will use the register/field definitions of SW2TCL1 186 * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup 187 * individual fields, SRNG_SM macros should be used with fields specified 188 * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done 189 * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>). 190 * Similarly for destination rings we will use definitions of REO2SW1 ring 191 * defined in the register reo_destination_ring.h. To setup individual 192 * fields SRNG_SM macros should be used with fields specified using 193 * SRNG_DST_FLD(<register>, <field>). Register writes should be done using 194 * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>). 195 */ 196 197 #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \ 198 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0) 199 200 #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \ 201 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0) 202 203 #define _SRNG_DST_FLD(_reg_group, _reg_fld) \ 204 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld 205 #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \ 206 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld 207 208 #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \ 209 _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld) 210 211 #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST) 212 #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC) 213 214 #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0) 215 #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0) 216 217 #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2) 218 #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2) 219 220 #define SRNG_SRC_START_OFFSET(_reg_group) \ 221 SRNG_SRC_ ## _reg_group ## _START_OFFSET 222 #define SRNG_DST_START_OFFSET(_reg_group) \ 223 SRNG_DST_ ## _reg_group ## _START_OFFSET 224 #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \ 225 ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \ 226 ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg])) 227 228 #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \ 229 (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \ 230 SRNG_ ## _dir ## _START_OFFSET(_reg_group)) 231 232 #define REG_OFFSET(_dir, _reg) \ 233 CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP) 234 235 #define SRNG_DST_ADDR(_srng, _reg) \ 236 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST) 237 238 #define SRNG_SRC_ADDR(_srng, _reg) \ 239 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC) 240 241 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \ 242 hal_write_address_32_mb(_srng->hal_soc,\ 243 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), false) 244 245 #define SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, _dir) \ 246 hal_write_address_32_mb(_srng->hal_soc,\ 247 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), true) 248 249 #define SRNG_REG_READ(_srng, _reg, _dir) \ 250 hal_read_address_32_mb(_srng->hal_soc, \ 251 SRNG_ ## _dir ## _ADDR(_srng, _reg)) 252 253 #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \ 254 SRNG_REG_WRITE(_srng, _reg, _value, SRC) 255 256 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \ 257 SRNG_REG_WRITE(_srng, _reg, _value, DST) 258 259 #define SRNG_DST_REG_WRITE_CONFIRM(_srng, _reg, _value) \ 260 SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, DST) 261 262 #define SRNG_SRC_REG_READ(_srng, _reg) \ 263 SRNG_REG_READ(_srng, _reg, SRC) 264 265 #define SRNG_DST_REG_READ(_srng, _reg) \ 266 SRNG_REG_READ(_srng, _reg, DST) 267 268 #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK 269 #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT 270 271 #define SRNG_SM(_reg_fld, _val) \ 272 (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld)) 273 274 #define SRNG_MS(_reg_fld, _val) \ 275 (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld)) 276 277 #define SRNG_MAX_SIZE_DWORDS \ 278 (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff)) 279 280 /** 281 * HW ring configuration table to identify hardware ring attributes like 282 * register addresses, number of rings, ring entry size etc., for each type 283 * of SRNG ring. 284 * 285 * Currently there is just one HW ring table, but there could be multiple 286 * configurations in future based on HW variants from the same wifi3.0 family 287 * and hence need to be attached with hal_soc based on HW type 288 */ 289 #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \ 290 (&_hal_soc->hw_srng_table[_ring_type]) 291 292 enum SRNG_REGISTERS { 293 DST_HP = 0, 294 DST_TP, 295 DST_ID, 296 DST_MISC, 297 DST_HP_ADDR_LSB, 298 DST_HP_ADDR_MSB, 299 DST_MSI1_BASE_LSB, 300 DST_MSI1_BASE_MSB, 301 DST_MSI1_DATA, 302 DST_BASE_LSB, 303 DST_BASE_MSB, 304 DST_PRODUCER_INT_SETUP, 305 306 SRC_HP, 307 SRC_TP, 308 SRC_ID, 309 SRC_MISC, 310 SRC_TP_ADDR_LSB, 311 SRC_TP_ADDR_MSB, 312 SRC_MSI1_BASE_LSB, 313 SRC_MSI1_BASE_MSB, 314 SRC_MSI1_DATA, 315 SRC_BASE_LSB, 316 SRC_BASE_MSB, 317 SRC_CONSUMER_INT_SETUP_IX0, 318 SRC_CONSUMER_INT_SETUP_IX1, 319 }; 320 321 /** 322 * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info 323 * HW structure 324 * 325 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 326 * @cookie: SW cookie for the buffer/descriptor 327 * @link_desc_paddr: Physical address of link descriptor entry 328 * 329 */ 330 static inline void hal_set_link_desc_addr(void *desc, uint32_t cookie, 331 qdf_dma_addr_t link_desc_paddr) 332 { 333 uint32_t *buf_addr = (uint32_t *)desc; 334 335 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 336 link_desc_paddr & 0xffffffff); 337 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 338 (uint64_t)link_desc_paddr >> 32); 339 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 340 WBM_IDLE_DESC_LIST); 341 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 342 cookie); 343 } 344 345 /** 346 * hal_get_reo_qdesc_size - Get size of reo queue descriptor 347 * 348 * @hal_soc: Opaque HAL SOC handle 349 * @ba_window_size: BlockAck window size 350 * @tid: TID number 351 * 352 */ 353 static inline 354 uint32_t hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl, 355 uint32_t ba_window_size, int tid) 356 { 357 /* Return descriptor size corresponding to window size of 2 since 358 * we set ba_window_size to 2 while setting up REO descriptors as 359 * a WAR to get 2k jump exception aggregates are received without 360 * a BA session. 361 */ 362 if (ba_window_size <= 1) { 363 if (tid != HAL_NON_QOS_TID) 364 return sizeof(struct rx_reo_queue) + 365 sizeof(struct rx_reo_queue_ext); 366 else 367 return sizeof(struct rx_reo_queue); 368 } 369 370 if (ba_window_size <= 105) 371 return sizeof(struct rx_reo_queue) + 372 sizeof(struct rx_reo_queue_ext); 373 374 if (ba_window_size <= 210) 375 return sizeof(struct rx_reo_queue) + 376 (2 * sizeof(struct rx_reo_queue_ext)); 377 378 return sizeof(struct rx_reo_queue) + 379 (3 * sizeof(struct rx_reo_queue_ext)); 380 } 381 382 #endif /* _HAL_HW_INTERNAL_H_ */ 383