1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_HW_INTERNAL_H_ 20 #define _HAL_HW_INTERNAL_H_ 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "rx_msdu_link.h" 25 #include "rx_reo_queue.h" 26 #include "rx_reo_queue_ext.h" 27 #include "wcss_seq_hwiobase.h" 28 #include "tlv_hdr.h" 29 #include "tlv_tag_def.h" 30 #include "reo_destination_ring.h" 31 #include "reo_reg_seq_hwioreg.h" 32 #include "reo_entrance_ring.h" 33 #include "reo_get_queue_stats.h" 34 #include "reo_get_queue_stats_status.h" 35 #include "tcl_data_cmd.h" 36 #include "tcl_gse_cmd.h" 37 #include "tcl_status_ring.h" 38 #include "mac_tcl_reg_seq_hwioreg.h" 39 #include "ce_src_desc.h" 40 #include "ce_stat_desc.h" 41 #include "wfss_ce_reg_seq_hwioreg.h" 42 #include "wbm_link_descriptor_ring.h" 43 #include "wbm_reg_seq_hwioreg.h" 44 #include "wbm_buffer_ring.h" 45 #include "wbm_release_ring.h" 46 #include "rx_msdu_desc_info.h" 47 #include "rx_mpdu_start.h" 48 #include "rx_mpdu_end.h" 49 #include "rx_msdu_start.h" 50 #include "rx_msdu_end.h" 51 #include "rx_attention.h" 52 #include "rx_ppdu_start.h" 53 #include "rx_ppdu_start_user_info.h" 54 #include "rx_ppdu_end_user_stats.h" 55 #include "rx_ppdu_end_user_stats_ext.h" 56 #include "rx_mpdu_desc_info.h" 57 #include "rxpcu_ppdu_end_info.h" 58 #include "phyrx_he_sig_a_su.h" 59 #include "phyrx_he_sig_a_mu_dl.h" 60 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 61 #include "phyrx_he_sig_a_mu_ul.h" 62 #endif 63 #include "phyrx_he_sig_b1_mu.h" 64 #include "phyrx_he_sig_b2_mu.h" 65 #include "phyrx_he_sig_b2_ofdma.h" 66 #include "phyrx_l_sig_a.h" 67 #include "phyrx_l_sig_b.h" 68 #include "phyrx_vht_sig_a.h" 69 #include "phyrx_ht_sig.h" 70 #include "tx_msdu_extension.h" 71 #include "receive_rssi_info.h" 72 #include "phyrx_pkt_end.h" 73 #include "phyrx_rssi_legacy.h" 74 #include "wcss_version.h" 75 #include "rx_msdu_link.h" 76 77 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 78 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 79 80 /* calculate the register address offset from bar0 of shadow register x */ 81 #define SHADOW_REGISTER(x) (0x00003024 + (4 * (x))) 82 83 /* TODO: Check if the following can be provided directly by HW headers */ 84 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 85 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 86 87 #define HAL_DEFAULT_REO_TIMEOUT_MS 40 /* milliseconds */ 88 89 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ 90 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ 91 ~(_word ## _ ## _fld ## _MASK); \ 92 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ 93 ((_value) << _word ## _ ## _fld ## _LSB); \ 94 } while (0) 95 96 #define HAL_SM(_reg, _fld, _val) \ 97 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ 98 (_reg ## _ ## _fld ## _BMSK)) 99 100 #define HAL_MS(_reg, _fld, _val) \ 101 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ 102 (_reg ## _ ## _fld ## _SHFT)) 103 104 #define HAL_REG_WRITE(_soc, _reg, _value) \ 105 hal_write32_mb(_soc, (_reg), (_value)) 106 107 #define HAL_REG_READ(_soc, _offset) \ 108 hal_read32_mb(_soc, (_offset)) 109 110 #define WBM_IDLE_DESC_LIST 1 111 112 /** 113 * Common SRNG register access macros: 114 * The SRNG registers are distributed across various UMAC and LMAC HW blocks, 115 * but the register group and format is exactly same for all rings, with some 116 * difference between producer rings (these are 'producer rings' with respect 117 * to HW and referred as 'destination rings' in SW) and consumer rings (these 118 * are 'consumer rings' with respect to HW and 119 * referred as 'source rings' in SW). 120 * The following macros provide uniform access to all SRNG rings. 121 */ 122 123 /* SRNG registers are split among two groups R0 and R2 and following 124 * definitions identify the group to which each register belongs to 125 */ 126 #define R0_INDEX 0 127 #define R2_INDEX 1 128 129 #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX 130 131 /* Registers in R0 group */ 132 #define BASE_LSB_GROUP R0 133 #define BASE_MSB_GROUP R0 134 #define ID_GROUP R0 135 #define STATUS_GROUP R0 136 #define MISC_GROUP R0 137 #define HP_ADDR_LSB_GROUP R0 138 #define HP_ADDR_MSB_GROUP R0 139 #define PRODUCER_INT_SETUP_GROUP R0 140 #define PRODUCER_INT_STATUS_GROUP R0 141 #define PRODUCER_FULL_COUNTER_GROUP R0 142 #define MSI1_BASE_LSB_GROUP R0 143 #define MSI1_BASE_MSB_GROUP R0 144 #define MSI1_DATA_GROUP R0 145 #define HP_TP_SW_OFFSET_GROUP R0 146 #define TP_ADDR_LSB_GROUP R0 147 #define TP_ADDR_MSB_GROUP R0 148 #define CONSUMER_INT_SETUP_IX0_GROUP R0 149 #define CONSUMER_INT_SETUP_IX1_GROUP R0 150 #define CONSUMER_INT_STATUS_GROUP R0 151 #define CONSUMER_EMPTY_COUNTER_GROUP R0 152 #define CONSUMER_PREFETCH_TIMER_GROUP R0 153 #define CONSUMER_PREFETCH_STATUS_GROUP R0 154 155 /* Registers in R2 group */ 156 #define HP_GROUP R2 157 #define TP_GROUP R2 158 159 /** 160 * Register definitions for all SRNG based rings are same, except few 161 * differences between source (HW consumer) and destination (HW producer) 162 * registers. Following macros definitions provide generic access to all 163 * SRNG based rings. 164 * For source rings, we will use the register/field definitions of SW2TCL1 165 * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup 166 * individual fields, SRNG_SM macros should be used with fields specified 167 * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done 168 * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>). 169 * Similarly for destination rings we will use definitions of REO2SW1 ring 170 * defined in the register reo_destination_ring.h. To setup individual 171 * fields SRNG_SM macros should be used with fields specified using 172 * SRNG_DST_FLD(<register>, <field>). Register writes should be done using 173 * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>). 174 */ 175 176 #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \ 177 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0) 178 179 #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \ 180 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0) 181 182 #define _SRNG_DST_FLD(_reg_group, _reg_fld) \ 183 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld 184 #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \ 185 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld 186 187 #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \ 188 _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld) 189 190 #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST) 191 #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC) 192 193 #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0) 194 #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0) 195 196 #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2) 197 #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2) 198 199 #define SRNG_SRC_START_OFFSET(_reg_group) \ 200 SRNG_SRC_ ## _reg_group ## _START_OFFSET 201 #define SRNG_DST_START_OFFSET(_reg_group) \ 202 SRNG_DST_ ## _reg_group ## _START_OFFSET 203 #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \ 204 ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \ 205 ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg])) 206 207 #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \ 208 (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \ 209 SRNG_ ## _dir ## _START_OFFSET(_reg_group)) 210 211 #define REG_OFFSET(_dir, _reg) \ 212 CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP) 213 214 #define SRNG_DST_ADDR(_srng, _reg) \ 215 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST) 216 217 #define SRNG_SRC_ADDR(_srng, _reg) \ 218 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC) 219 220 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \ 221 hal_write_address_32_mb(_srng->hal_soc, \ 222 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value)) 223 224 #define SRNG_REG_READ(_srng, _reg, _dir) \ 225 hal_read_address_32_mb(_srng->hal_soc, \ 226 SRNG_ ## _dir ## _ADDR(_srng, _reg)) 227 228 #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \ 229 SRNG_REG_WRITE(_srng, _reg, _value, SRC) 230 231 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \ 232 SRNG_REG_WRITE(_srng, _reg, _value, DST) 233 234 #define SRNG_SRC_REG_READ(_srng, _reg) \ 235 SRNG_REG_READ(_srng, _reg, SRC) 236 237 #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK 238 #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT 239 240 #define SRNG_SM(_reg_fld, _val) \ 241 (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld)) 242 243 #define SRNG_MS(_reg_fld, _val) \ 244 (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld)) 245 246 #define SRNG_MAX_SIZE_DWORDS \ 247 (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff)) 248 249 /** 250 * HW ring configuration table to identify hardware ring attributes like 251 * register addresses, number of rings, ring entry size etc., for each type 252 * of SRNG ring. 253 * 254 * Currently there is just one HW ring table, but there could be multiple 255 * configurations in future based on HW variants from the same wifi3.0 family 256 * and hence need to be attached with hal_soc based on HW type 257 */ 258 #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \ 259 (&_hal_soc->hw_srng_table[_ring_type]) 260 261 enum SRNG_REGISTERS { 262 DST_HP = 0, 263 DST_TP, 264 DST_ID, 265 DST_MISC, 266 DST_HP_ADDR_LSB, 267 DST_HP_ADDR_MSB, 268 DST_MSI1_BASE_LSB, 269 DST_MSI1_BASE_MSB, 270 DST_MSI1_DATA, 271 DST_BASE_LSB, 272 DST_BASE_MSB, 273 DST_PRODUCER_INT_SETUP, 274 275 SRC_HP, 276 SRC_TP, 277 SRC_ID, 278 SRC_MISC, 279 SRC_TP_ADDR_LSB, 280 SRC_TP_ADDR_MSB, 281 SRC_MSI1_BASE_LSB, 282 SRC_MSI1_BASE_MSB, 283 SRC_MSI1_DATA, 284 SRC_BASE_LSB, 285 SRC_BASE_MSB, 286 SRC_CONSUMER_INT_SETUP_IX0, 287 SRC_CONSUMER_INT_SETUP_IX1, 288 }; 289 290 /** 291 * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info 292 * HW structure 293 * 294 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 295 * @cookie: SW cookie for the buffer/descriptor 296 * @link_desc_paddr: Physical address of link descriptor entry 297 * 298 */ 299 static inline void hal_set_link_desc_addr(void *desc, uint32_t cookie, 300 qdf_dma_addr_t link_desc_paddr) 301 { 302 uint32_t *buf_addr = (uint32_t *)desc; 303 304 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 305 link_desc_paddr & 0xffffffff); 306 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 307 (uint64_t)link_desc_paddr >> 32); 308 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 309 WBM_IDLE_DESC_LIST); 310 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 311 cookie); 312 } 313 314 /** 315 * hal_get_reo_qdesc_size - Get size of reo queue descriptor 316 * 317 * @hal_soc: Opaque HAL SOC handle 318 * @ba_window_size: BlockAck window size 319 * 320 */ 321 static inline uint32_t hal_get_reo_qdesc_size(void *hal_soc, 322 uint32_t ba_window_size) 323 { 324 if (ba_window_size <= 1) 325 return sizeof(struct rx_reo_queue); 326 327 if (ba_window_size <= 105) 328 return sizeof(struct rx_reo_queue) + 329 sizeof(struct rx_reo_queue_ext); 330 331 if (ba_window_size <= 210) 332 return sizeof(struct rx_reo_queue) + 333 (2 * sizeof(struct rx_reo_queue_ext)); 334 335 return sizeof(struct rx_reo_queue) + 336 (3 * sizeof(struct rx_reo_queue_ext)); 337 } 338 339 #endif /* _HAL_HW_INTERNAL_H_ */ 340