1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_HW_INTERNAL_H_ 20 #define _HAL_HW_INTERNAL_H_ 21 #include "qdf_types.h" 22 #include "qdf_lock.h" 23 #include "qdf_mem.h" 24 #include "qdf_trace.h" 25 #include "rx_msdu_link.h" 26 #include "rx_reo_queue.h" 27 #include "rx_reo_queue_ext.h" 28 #include "wcss_seq_hwiobase.h" 29 #include "tlv_hdr.h" 30 #include "tlv_tag_def.h" 31 #include "reo_destination_ring.h" 32 #include "reo_entrance_ring.h" 33 #include "reo_get_queue_stats.h" 34 #include "reo_get_queue_stats_status.h" 35 #include "tcl_data_cmd.h" 36 #include "tcl_gse_cmd.h" 37 #include "tcl_status_ring.h" 38 #include "ce_src_desc.h" 39 #include "ce_stat_desc.h" 40 #include "wbm_link_descriptor_ring.h" 41 #include "wbm_buffer_ring.h" 42 #include "wbm_release_ring.h" 43 #include "rx_msdu_desc_info.h" 44 #include "rx_mpdu_start.h" 45 #include "rx_mpdu_end.h" 46 #include "rx_msdu_start.h" 47 #include "rx_msdu_end.h" 48 #include "rx_attention.h" 49 #include "rx_ppdu_start.h" 50 #include "rx_ppdu_start_user_info.h" 51 #include "rx_ppdu_end_user_stats.h" 52 #include "rx_ppdu_end_user_stats_ext.h" 53 #include "rx_mpdu_desc_info.h" 54 #include "rxpcu_ppdu_end_info.h" 55 #include "phyrx_he_sig_a_su.h" 56 #include "phyrx_he_sig_a_mu_dl.h" 57 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 58 #include "phyrx_he_sig_a_mu_ul.h" 59 #endif 60 #include "phyrx_he_sig_b1_mu.h" 61 #include "phyrx_he_sig_b2_mu.h" 62 #include "phyrx_he_sig_b2_ofdma.h" 63 #include "phyrx_l_sig_a.h" 64 #include "phyrx_l_sig_b.h" 65 #include "phyrx_vht_sig_a.h" 66 #include "phyrx_ht_sig.h" 67 #include "tx_msdu_extension.h" 68 #include "receive_rssi_info.h" 69 #include "phyrx_pkt_end.h" 70 #include "phyrx_rssi_legacy.h" 71 #include "wcss_version.h" 72 #include "rx_msdu_link.h" 73 #include "hal_internal.h" 74 75 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 76 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 77 #define HAL_NON_QOS_TID 16 78 79 /* TODO: Check if the following can be provided directly by HW headers */ 80 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 81 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 82 83 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 84 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff 85 86 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 87 #define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 88 89 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_SHFT 0x0 90 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff 91 92 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 0x8 93 #define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 94 95 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 96 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff 97 98 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 99 #define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 100 101 #define HAL_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 102 #define HAL_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 103 104 #define HAL_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 105 #define HAL_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0xff 106 107 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 108 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 109 110 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 111 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 112 113 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 114 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 115 116 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 117 #define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff 118 119 #define HAL_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 120 #define HAL_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 121 122 #define HAL_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 123 #define HAL_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 124 125 #define HAL_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 126 #define HAL_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 127 128 /* HAL Macro to get the buffer info size */ 129 #define HAL_RX_BUFFINFO_NUM_DWORDS NUM_OF_DWORDS_BUFFER_ADDR_INFO 130 131 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS 100 /* milliseconds */ 132 #define HAL_DEFAULT_VO_REO_TIMEOUT_MS 40 /* milliseconds */ 133 134 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ 135 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ 136 ~(_word ## _ ## _fld ## _MASK); \ 137 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ 138 ((_value) << _word ## _ ## _fld ## _LSB); \ 139 } while (0) 140 141 #define HAL_SM(_reg, _fld, _val) \ 142 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ 143 (_reg ## _ ## _fld ## _BMSK)) 144 145 #define HAL_MS(_reg, _fld, _val) \ 146 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ 147 (_reg ## _ ## _fld ## _SHFT)) 148 149 #define HAL_REG_WRITE(_soc, _reg, _value) \ 150 hal_write32_mb(_soc, (_reg), (_value)) 151 152 /* Check register writing result */ 153 #define HAL_REG_WRITE_CONFIRM(_soc, _reg, _value) \ 154 hal_write32_mb_confirm(_soc, (_reg), (_value)) 155 156 #define HAL_REG_WRITE_CONFIRM_RETRY(_soc, _reg, _value, _recovery) \ 157 hal_write32_mb_confirm_retry(_soc, (_reg), (_value), (_recovery)) 158 159 #define HAL_REG_READ(_soc, _offset) \ 160 hal_read32_mb(_soc, (_offset)) 161 162 #define HAL_CMEM_WRITE(_soc, _reg, _value) \ 163 hal_write32_mb_cmem(_soc, (_reg), (_value)) 164 165 #define HAL_CMEM_READ(_soc, _offset) \ 166 hal_read32_mb_cmem(_soc, (_offset)) 167 168 #define WBM_IDLE_DESC_LIST 1 169 170 /** 171 * Common SRNG register access macros: 172 * The SRNG registers are distributed across various UMAC and LMAC HW blocks, 173 * but the register group and format is exactly same for all rings, with some 174 * difference between producer rings (these are 'producer rings' with respect 175 * to HW and referred as 'destination rings' in SW) and consumer rings (these 176 * are 'consumer rings' with respect to HW and 177 * referred as 'source rings' in SW). 178 * The following macros provide uniform access to all SRNG rings. 179 */ 180 181 /* SRNG registers are split among two groups R0 and R2 and following 182 * definitions identify the group to which each register belongs to 183 */ 184 #define R0_INDEX 0 185 #define R2_INDEX 1 186 187 #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX 188 189 /* Registers in R0 group */ 190 #define BASE_LSB_GROUP R0 191 #define BASE_MSB_GROUP R0 192 #define ID_GROUP R0 193 #define STATUS_GROUP R0 194 #define MISC_GROUP R0 195 #define HP_ADDR_LSB_GROUP R0 196 #define HP_ADDR_MSB_GROUP R0 197 #define PRODUCER_INT_SETUP_GROUP R0 198 #define PRODUCER_INT2_SETUP_GROUP R0 199 #define PRODUCER_INT_STATUS_GROUP R0 200 #define PRODUCER_FULL_COUNTER_GROUP R0 201 #define MSI1_BASE_LSB_GROUP R0 202 #define MSI1_BASE_MSB_GROUP R0 203 #define MSI1_DATA_GROUP R0 204 #define MSI2_BASE_LSB_GROUP R0 205 #define MSI2_BASE_MSB_GROUP R0 206 #define MSI2_DATA_GROUP R0 207 #define HP_TP_SW_OFFSET_GROUP R0 208 #define TP_ADDR_LSB_GROUP R0 209 #define TP_ADDR_MSB_GROUP R0 210 #define CONSUMER_INT_SETUP_IX0_GROUP R0 211 #define CONSUMER_INT_SETUP_IX1_GROUP R0 212 #define CONSUMER_INT_STATUS_GROUP R0 213 #define CONSUMER_EMPTY_COUNTER_GROUP R0 214 #define CONSUMER_PREFETCH_TIMER_GROUP R0 215 #define CONSUMER_PREFETCH_STATUS_GROUP R0 216 217 /* Registers in R2 group */ 218 #define HP_GROUP R2 219 #define TP_GROUP R2 220 221 /** 222 * Register definitions for all SRNG based rings are same, except few 223 * differences between source (HW consumer) and destination (HW producer) 224 * registers. Following macros definitions provide generic access to all 225 * SRNG based rings. 226 * For source rings, we will use the register/field definitions of SW2TCL1 227 * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup 228 * individual fields, SRNG_SM macros should be used with fields specified 229 * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done 230 * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>). 231 * Similarly for destination rings we will use definitions of REO2SW1 ring 232 * defined in the register reo_destination_ring.h. To setup individual 233 * fields SRNG_SM macros should be used with fields specified using 234 * SRNG_DST_FLD(<register>, <field>). Register writes should be done using 235 * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>). 236 */ 237 238 #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \ 239 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0) 240 241 #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \ 242 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0) 243 244 #define _SRNG_DST_FLD(_reg_group, _reg_fld) \ 245 HAL_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld 246 #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \ 247 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld 248 249 #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \ 250 _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld) 251 252 #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST) 253 #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC) 254 255 #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0) 256 #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0) 257 258 #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2) 259 #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2) 260 261 #define SRNG_SRC_START_OFFSET(_reg_group) \ 262 SRNG_SRC_ ## _reg_group ## _START_OFFSET 263 #define SRNG_DST_START_OFFSET(_reg_group) \ 264 SRNG_DST_ ## _reg_group ## _START_OFFSET 265 #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \ 266 ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \ 267 ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg])) 268 269 #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \ 270 (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \ 271 SRNG_ ## _dir ## _START_OFFSET(_reg_group)) 272 273 #define REG_OFFSET(_dir, _reg) \ 274 CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP) 275 276 #define SRNG_DST_ADDR(_srng, _reg) \ 277 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST) 278 279 #define SRNG_SRC_ADDR(_srng, _reg) \ 280 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC) 281 282 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \ 283 hal_write_address_32_mb(_srng->hal_soc,\ 284 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), false) 285 286 #define SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, _dir) \ 287 hal_write_address_32_mb(_srng->hal_soc,\ 288 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), true) 289 290 #define SRNG_REG_READ(_srng, _reg, _dir) \ 291 hal_read_address_32_mb(_srng->hal_soc, \ 292 SRNG_ ## _dir ## _ADDR(_srng, _reg)) 293 294 #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \ 295 SRNG_REG_WRITE(_srng, _reg, _value, SRC) 296 297 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \ 298 SRNG_REG_WRITE(_srng, _reg, _value, DST) 299 300 #define SRNG_DST_REG_WRITE_CONFIRM(_srng, _reg, _value) \ 301 SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, DST) 302 303 #define SRNG_SRC_REG_READ(_srng, _reg) \ 304 SRNG_REG_READ(_srng, _reg, SRC) 305 306 #define SRNG_DST_REG_READ(_srng, _reg) \ 307 SRNG_REG_READ(_srng, _reg, DST) 308 309 #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK 310 #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT 311 312 #define SRNG_SM(_reg_fld, _val) \ 313 (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld)) 314 315 #define SRNG_MS(_reg_fld, _val) \ 316 (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld)) 317 318 #define SRNG_MAX_SIZE_DWORDS \ 319 (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff)) 320 321 /** 322 * HW ring configuration table to identify hardware ring attributes like 323 * register addresses, number of rings, ring entry size etc., for each type 324 * of SRNG ring. 325 * 326 * Currently there is just one HW ring table, but there could be multiple 327 * configurations in future based on HW variants from the same wifi3.0 family 328 * and hence need to be attached with hal_soc based on HW type 329 */ 330 #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \ 331 (&_hal_soc->hw_srng_table[_ring_type]) 332 333 /** 334 * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info 335 * HW structure 336 * 337 * @hal_soc_hdl: HAL soc handle 338 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 339 * @cookie: SW cookie for the buffer/descriptor 340 * @link_desc_paddr: Physical address of link descriptor entry 341 * 342 */ 343 static inline void hal_set_link_desc_addr(hal_soc_handle_t hal_soc_hdl, 344 void *desc, uint32_t cookie, 345 qdf_dma_addr_t link_desc_paddr) 346 { 347 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 348 349 if ((!hal_soc) || (!hal_soc->ops)) { 350 hal_err("hal handle is NULL"); 351 return; 352 } 353 354 if (hal_soc->ops->hal_set_link_desc_addr) 355 hal_soc->ops->hal_set_link_desc_addr(desc, cookie, 356 link_desc_paddr); 357 } 358 359 /** 360 * hal_get_reo_qdesc_size - Get size of reo queue descriptor 361 * 362 * @hal_soc: Opaque HAL SOC handle 363 * @ba_window_size: BlockAck window size 364 * @tid: TID number 365 * 366 */ 367 static inline 368 uint32_t hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl, 369 uint32_t ba_window_size, int tid) 370 { 371 /* Return descriptor size corresponding to window size of 2 since 372 * we set ba_window_size to 2 while setting up REO descriptors as 373 * a WAR to get 2k jump exception aggregates are received without 374 * a BA session. 375 */ 376 if (ba_window_size <= 1) { 377 if (tid != HAL_NON_QOS_TID) 378 return sizeof(struct rx_reo_queue) + 379 sizeof(struct rx_reo_queue_ext); 380 else 381 return sizeof(struct rx_reo_queue); 382 } 383 384 if (ba_window_size <= 105) 385 return sizeof(struct rx_reo_queue) + 386 sizeof(struct rx_reo_queue_ext); 387 388 if (ba_window_size <= 210) 389 return sizeof(struct rx_reo_queue) + 390 (2 * sizeof(struct rx_reo_queue_ext)); 391 392 return sizeof(struct rx_reo_queue) + 393 (3 * sizeof(struct rx_reo_queue_ext)); 394 } 395 396 #endif /* _HAL_HW_INTERNAL_H_ */ 397