1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer in the documentation and/or other materials provided 12 * with the distribution. 13 * * Neither the name of The Linux Foundation nor the names of its 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _HAL_HW_INTERNAL_H_ 31 #define _HAL_HW_INTERNAL_H_ 32 #include "qdf_types.h" 33 #include "qdf_lock.h" 34 #include "qdf_mem.h" 35 #include "rx_msdu_link.h" 36 #include "rx_reo_queue.h" 37 #include "rx_reo_queue_ext.h" 38 #include "wcss_seq_hwiobase.h" 39 #include "tlv_hdr.h" 40 #include "tlv_tag_def.h" 41 #include "reo_destination_ring.h" 42 #include "reo_reg_seq_hwioreg.h" 43 #include "reo_entrance_ring.h" 44 #include "reo_get_queue_stats.h" 45 #include "reo_get_queue_stats_status.h" 46 #include "tcl_data_cmd.h" 47 #include "tcl_gse_cmd.h" 48 #include "tcl_status_ring.h" 49 #include "mac_tcl_reg_seq_hwioreg.h" 50 #include "ce_src_desc.h" 51 #include "ce_stat_desc.h" 52 #include "wfss_ce_reg_seq_hwioreg.h" 53 #include "wbm_link_descriptor_ring.h" 54 #include "wbm_reg_seq_hwioreg.h" 55 #include "wbm_buffer_ring.h" 56 #include "wbm_release_ring.h" 57 #include "rx_msdu_desc_info.h" 58 #include "rx_mpdu_start.h" 59 #include "rx_mpdu_end.h" 60 #include "rx_msdu_start.h" 61 #include "rx_msdu_end.h" 62 #include "rx_attention.h" 63 #include "rx_ppdu_start.h" 64 #include "rx_ppdu_start_user_info.h" 65 #include "rx_ppdu_end_user_stats.h" 66 #include "rx_ppdu_end_user_stats_ext.h" 67 #include "rx_mpdu_desc_info.h" 68 #include "rxpcu_ppdu_end_info.h" 69 #include "phyrx_he_sig_a_su.h" 70 #include "phyrx_he_sig_a_mu_dl.h" 71 #include "phyrx_he_sig_b1_mu.h" 72 #include "phyrx_he_sig_b2_mu.h" 73 #include "phyrx_he_sig_b2_ofdma.h" 74 #include "phyrx_l_sig_a.h" 75 #include "phyrx_l_sig_b.h" 76 #include "phyrx_vht_sig_a.h" 77 #include "phyrx_ht_sig.h" 78 #include "tx_msdu_extension.h" 79 #include "receive_rssi_info.h" 80 #include "phyrx_pkt_end.h" 81 #include "phyrx_rssi_legacy.h" 82 #include "wcss_version.h" 83 #include "rx_msdu_link.h" 84 85 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 86 #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 87 88 /* calculate the register address offset from bar0 of shadow register x */ 89 #define SHADOW_REGISTER(x) (0x00003024 + (4 * (x))) 90 91 /* TODO: Check if the following can be provided directly by HW headers */ 92 #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 93 #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 94 95 #define HAL_DEFAULT_REO_TIMEOUT_MS 40 /* milliseconds */ 96 97 #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ 98 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ 99 ~(_word ## _ ## _fld ## _MASK); \ 100 ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ 101 ((_value) << _word ## _ ## _fld ## _LSB); \ 102 } while (0) 103 104 #define HAL_SM(_reg, _fld, _val) \ 105 (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ 106 (_reg ## _ ## _fld ## _BMSK)) 107 108 #define HAL_MS(_reg, _fld, _val) \ 109 (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ 110 (_reg ## _ ## _fld ## _SHFT)) 111 112 #define HAL_REG_WRITE(_soc, _reg, _value) \ 113 hal_write32_mb(_soc, (_reg), (_value)) 114 115 #define HAL_REG_READ(_soc, _offset) \ 116 hal_read32_mb(_soc, (_offset)) 117 118 #define WBM_IDLE_DESC_LIST 1 119 120 /** 121 * Common SRNG register access macros: 122 * The SRNG registers are distributed across various UMAC and LMAC HW blocks, 123 * but the register group and format is exactly same for all rings, with some 124 * difference between producer rings (these are 'producer rings' with respect 125 * to HW and referred as 'destination rings' in SW) and consumer rings (these 126 * are 'consumer rings' with respect to HW and 127 * referred as 'source rings' in SW). 128 * The following macros provide uniform access to all SRNG rings. 129 */ 130 131 /* SRNG registers are split among two groups R0 and R2 and following 132 * definitions identify the group to which each register belongs to 133 */ 134 #define R0_INDEX 0 135 #define R2_INDEX 1 136 137 #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX 138 139 /* Registers in R0 group */ 140 #define BASE_LSB_GROUP R0 141 #define BASE_MSB_GROUP R0 142 #define ID_GROUP R0 143 #define STATUS_GROUP R0 144 #define MISC_GROUP R0 145 #define HP_ADDR_LSB_GROUP R0 146 #define HP_ADDR_MSB_GROUP R0 147 #define PRODUCER_INT_SETUP_GROUP R0 148 #define PRODUCER_INT_STATUS_GROUP R0 149 #define PRODUCER_FULL_COUNTER_GROUP R0 150 #define MSI1_BASE_LSB_GROUP R0 151 #define MSI1_BASE_MSB_GROUP R0 152 #define MSI1_DATA_GROUP R0 153 #define HP_TP_SW_OFFSET_GROUP R0 154 #define TP_ADDR_LSB_GROUP R0 155 #define TP_ADDR_MSB_GROUP R0 156 #define CONSUMER_INT_SETUP_IX0_GROUP R0 157 #define CONSUMER_INT_SETUP_IX1_GROUP R0 158 #define CONSUMER_INT_STATUS_GROUP R0 159 #define CONSUMER_EMPTY_COUNTER_GROUP R0 160 #define CONSUMER_PREFETCH_TIMER_GROUP R0 161 #define CONSUMER_PREFETCH_STATUS_GROUP R0 162 163 /* Registers in R2 group */ 164 #define HP_GROUP R2 165 #define TP_GROUP R2 166 167 /** 168 * Register definitions for all SRNG based rings are same, except few 169 * differences between source (HW consumer) and destination (HW producer) 170 * registers. Following macros definitions provide generic access to all 171 * SRNG based rings. 172 * For source rings, we will use the register/field definitions of SW2TCL1 173 * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup 174 * individual fields, SRNG_SM macros should be used with fields specified 175 * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done 176 * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>). 177 * Similarly for destination rings we will use definitions of REO2SW1 ring 178 * defined in the register reo_destination_ring.h. To setup individual 179 * fields SRNG_SM macros should be used with fields specified using 180 * SRNG_DST_FLD(<register>, <field>). Register writes should be done using 181 * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>). 182 */ 183 184 #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \ 185 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0) 186 187 #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \ 188 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0) 189 190 #define _SRNG_DST_FLD(_reg_group, _reg_fld) \ 191 HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld 192 #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \ 193 HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld 194 195 #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \ 196 _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld) 197 198 #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST) 199 #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC) 200 201 #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0) 202 #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0) 203 204 #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2) 205 #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2) 206 207 #define SRNG_SRC_START_OFFSET(_reg_group) \ 208 SRNG_SRC_ ## _reg_group ## _START_OFFSET 209 #define SRNG_DST_START_OFFSET(_reg_group) \ 210 SRNG_DST_ ## _reg_group ## _START_OFFSET 211 #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \ 212 ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \ 213 ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg])) 214 215 #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \ 216 (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \ 217 SRNG_ ## _dir ## _START_OFFSET(_reg_group)) 218 219 #define REG_OFFSET(_dir, _reg) \ 220 CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP) 221 222 #define SRNG_DST_ADDR(_srng, _reg) \ 223 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST) 224 225 #define SRNG_SRC_ADDR(_srng, _reg) \ 226 SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC) 227 228 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \ 229 hal_write_address_32_mb(_srng->hal_soc, \ 230 SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value)) 231 232 #define SRNG_REG_READ(_srng, _reg, _dir) \ 233 hal_read_address_32_mb(_srng->hal_soc, \ 234 SRNG_ ## _dir ## _ADDR(_srng, _reg)) 235 236 #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \ 237 SRNG_REG_WRITE(_srng, _reg, _value, SRC) 238 239 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \ 240 SRNG_REG_WRITE(_srng, _reg, _value, DST) 241 242 #define SRNG_SRC_REG_READ(_srng, _reg) \ 243 SRNG_REG_READ(_srng, _reg, SRC) 244 245 #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK 246 #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT 247 248 #define SRNG_SM(_reg_fld, _val) \ 249 (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld)) 250 251 #define SRNG_MS(_reg_fld, _val) \ 252 (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld)) 253 254 #define SRNG_MAX_SIZE_DWORDS \ 255 (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff)) 256 257 /** 258 * HW ring configuration table to identify hardware ring attributes like 259 * register addresses, number of rings, ring entry size etc., for each type 260 * of SRNG ring. 261 * 262 * Currently there is just one HW ring table, but there could be multiple 263 * configurations in future based on HW variants from the same wifi3.0 family 264 * and hence need to be attached with hal_soc based on HW type 265 */ 266 #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \ 267 (&_hal_soc->hw_srng_table[_ring_type]) 268 269 enum SRNG_REGISTERS { 270 DST_HP = 0, 271 DST_TP, 272 DST_ID, 273 DST_MISC, 274 DST_HP_ADDR_LSB, 275 DST_HP_ADDR_MSB, 276 DST_MSI1_BASE_LSB, 277 DST_MSI1_BASE_MSB, 278 DST_MSI1_DATA, 279 DST_BASE_LSB, 280 DST_BASE_MSB, 281 DST_PRODUCER_INT_SETUP, 282 283 SRC_HP, 284 SRC_TP, 285 SRC_ID, 286 SRC_MISC, 287 SRC_TP_ADDR_LSB, 288 SRC_TP_ADDR_MSB, 289 SRC_MSI1_BASE_LSB, 290 SRC_MSI1_BASE_MSB, 291 SRC_MSI1_DATA, 292 SRC_BASE_LSB, 293 SRC_BASE_MSB, 294 SRC_CONSUMER_INT_SETUP_IX0, 295 SRC_CONSUMER_INT_SETUP_IX1, 296 }; 297 298 /** 299 * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info 300 * HW structure 301 * 302 * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 303 * @cookie: SW cookie for the buffer/descriptor 304 * @link_desc_paddr: Physical address of link descriptor entry 305 * 306 */ 307 static inline void hal_set_link_desc_addr(void *desc, uint32_t cookie, 308 qdf_dma_addr_t link_desc_paddr) 309 { 310 uint32_t *buf_addr = (uint32_t *)desc; 311 312 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 313 link_desc_paddr & 0xffffffff); 314 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 315 (uint64_t)link_desc_paddr >> 32); 316 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 317 WBM_IDLE_DESC_LIST); 318 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 319 cookie); 320 } 321 322 /** 323 * hal_get_reo_qdesc_size - Get size of reo queue descriptor 324 * 325 * @hal_soc: Opaque HAL SOC handle 326 * @ba_window_size: BlockAck window size 327 * 328 */ 329 static inline uint32_t hal_get_reo_qdesc_size(void *hal_soc, 330 uint32_t ba_window_size) 331 { 332 if (ba_window_size <= 1) 333 return sizeof(struct rx_reo_queue); 334 335 if (ba_window_size <= 105) 336 return sizeof(struct rx_reo_queue) + 337 sizeof(struct rx_reo_queue_ext); 338 339 if (ba_window_size <= 210) 340 return sizeof(struct rx_reo_queue) + 341 (2 * sizeof(struct rx_reo_queue_ext)); 342 343 return sizeof(struct rx_reo_queue) + 344 (3 * sizeof(struct rx_reo_queue_ext)); 345 } 346 347 #endif /* _HAL_HW_INTERNAL_H_ */ 348