1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 23 /** 24 * hal_tx_comp_get_status() - TQM Release reason 25 * @hal_desc: completion ring Tx status 26 * 27 * This function will parse the WBM completion descriptor and populate in 28 * HAL structure 29 * 30 * Return: none 31 */ 32 static inline 33 void hal_tx_comp_get_status_generic(void *desc, 34 void *ts1, 35 struct hal_soc *hal) 36 { 37 uint8_t rate_stats_valid = 0; 38 uint32_t rate_stats = 0; 39 struct hal_tx_completion_status *ts = 40 (struct hal_tx_completion_status *)ts1; 41 42 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 43 TQM_STATUS_NUMBER); 44 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 45 ACK_FRAME_RSSI); 46 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 47 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 48 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 49 MSDU_PART_OF_AMSDU); 50 51 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 52 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 53 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 54 TRANSMIT_COUNT); 55 56 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 57 TX_RATE_STATS); 58 59 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 60 TX_RATE_STATS_INFO_VALID, rate_stats); 61 62 ts->valid = rate_stats_valid; 63 64 if (rate_stats_valid) { 65 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 66 rate_stats); 67 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 68 TRANSMIT_PKT_TYPE, rate_stats); 69 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 70 TRANSMIT_STBC, rate_stats); 71 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 72 rate_stats); 73 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 74 rate_stats); 75 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 76 rate_stats); 77 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 78 rate_stats); 79 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 80 rate_stats); 81 } 82 83 ts->release_src = hal_tx_comp_get_buffer_source(desc); 84 ts->status = hal_tx_comp_get_release_reason( 85 desc, 86 hal_soc_to_hal_soc_handle(hal)); 87 88 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 89 TX_RATE_STATS_INFO_TX_RATE_STATS); 90 } 91 92 /** 93 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 94 * @desc: Handle to Tx Descriptor 95 * @paddr: Physical Address 96 * @pool_id: Return Buffer Manager ID 97 * @desc_id: Descriptor ID 98 * @type: 0 - Address points to a MSDU buffer 99 * 1 - Address points to MSDU extension descriptor 100 * 101 * Return: void 102 */ 103 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 104 dma_addr_t paddr, uint8_t pool_id, 105 uint32_t desc_id, uint8_t type) 106 { 107 /* Set buffer_addr_info.buffer_addr_31_0 */ 108 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 109 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 110 111 /* Set buffer_addr_info.buffer_addr_39_32 */ 112 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 113 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 114 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 115 (((uint64_t) paddr) >> 32)); 116 117 /* Set buffer_addr_info.return_buffer_manager = pool id */ 118 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 119 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 120 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 121 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 122 123 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 124 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 125 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 126 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 127 128 /* Set Buffer or Ext Descriptor Type */ 129 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 130 BUF_OR_EXT_DESC_TYPE) |= 131 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 132 } 133 134 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 135 /** 136 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 137 * tlv_tag: Taf of the TLVs 138 * rx_tlv: the pointer to the TLVs 139 * @ppdu_info: pointer to ppdu_info 140 * 141 * Return: true if the tlv is handled, false if not 142 */ 143 static inline bool 144 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 145 struct hal_rx_ppdu_info *ppdu_info) 146 { 147 uint32_t value; 148 149 switch (tlv_tag) { 150 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 151 { 152 uint8_t *he_sig_a_mu_ul_info = 153 (uint8_t *)rx_tlv + 154 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 155 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 156 ppdu_info->rx_status.he_flags = 1; 157 158 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 159 FORMAT_INDICATION); 160 if (value == 0) { 161 ppdu_info->rx_status.he_data1 = 162 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 163 } else { 164 ppdu_info->rx_status.he_data1 = 165 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 166 } 167 168 /* data1 */ 169 ppdu_info->rx_status.he_data1 |= 170 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 171 QDF_MON_STATUS_HE_DL_UL_KNOWN | 172 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 173 174 /* data2 */ 175 ppdu_info->rx_status.he_data2 |= 176 QDF_MON_STATUS_TXOP_KNOWN; 177 178 /*data3*/ 179 value = HAL_RX_GET(he_sig_a_mu_ul_info, 180 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 181 ppdu_info->rx_status.he_data3 = value; 182 /* 1 for UL and 0 for DL */ 183 value = 1; 184 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 185 ppdu_info->rx_status.he_data3 |= value; 186 187 /*data4*/ 188 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 189 SPATIAL_REUSE); 190 ppdu_info->rx_status.he_data4 = value; 191 192 /*data5*/ 193 value = HAL_RX_GET(he_sig_a_mu_ul_info, 194 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 195 ppdu_info->rx_status.he_data5 = value; 196 ppdu_info->rx_status.bw = value; 197 198 /*data6*/ 199 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 200 TXOP_DURATION); 201 value = value << QDF_MON_STATUS_TXOP_SHIFT; 202 ppdu_info->rx_status.he_data6 |= value; 203 return true; 204 } 205 default: 206 return false; 207 } 208 } 209 #else 210 static inline bool 211 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 212 struct hal_rx_ppdu_info *ppdu_info) 213 { 214 return false; 215 } 216 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 217 218 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 219 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 220 221 static inline void 222 hal_rx_handle_mu_ul_info( 223 void *rx_tlv, 224 struct mon_rx_user_status *mon_rx_user_status) 225 { 226 mon_rx_user_status->mu_ul_user_v0_word0 = 227 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 228 SW_RESPONSE_REFERENCE_PTR); 229 230 mon_rx_user_status->mu_ul_user_v0_word1 = 231 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 232 SW_RESPONSE_REFERENCE_PTR_EXT); 233 } 234 235 static inline void 236 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 237 struct mon_rx_user_status *mon_rx_user_status) 238 { 239 uint32_t mpdu_ok_byte_count; 240 uint32_t mpdu_err_byte_count; 241 242 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 243 RX_PPDU_END_USER_STATS_17, 244 MPDU_OK_BYTE_COUNT); 245 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 246 RX_PPDU_END_USER_STATS_19, 247 MPDU_ERR_BYTE_COUNT); 248 249 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 250 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 251 } 252 #else 253 static inline void 254 hal_rx_handle_mu_ul_info(void *rx_tlv, 255 struct mon_rx_user_status *mon_rx_user_status) 256 { 257 } 258 259 static inline void 260 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 261 struct mon_rx_user_status *mon_rx_user_status) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = 264 (struct hal_rx_ppdu_info *)ppduinfo; 265 266 /* HKV1: doesn't support mpdu byte count */ 267 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 268 mon_rx_user_status->mpdu_err_byte_count = 0; 269 } 270 #endif 271 272 static inline void 273 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, 274 struct mon_rx_user_status *mon_rx_user_status) 275 { 276 struct hal_rx_ppdu_info *ppdu_info = 277 (struct hal_rx_ppdu_info *)ppduinfo; 278 279 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 280 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 281 mon_rx_user_status->tcp_msdu_count = 282 ppdu_info->rx_status.tcp_msdu_count; 283 mon_rx_user_status->udp_msdu_count = 284 ppdu_info->rx_status.udp_msdu_count; 285 mon_rx_user_status->other_msdu_count = 286 ppdu_info->rx_status.other_msdu_count; 287 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 288 mon_rx_user_status->frame_control_info_valid = 289 ppdu_info->rx_status.frame_control_info_valid; 290 mon_rx_user_status->data_sequence_control_info_valid = 291 ppdu_info->rx_status.data_sequence_control_info_valid; 292 mon_rx_user_status->first_data_seq_ctrl = 293 ppdu_info->rx_status.first_data_seq_ctrl; 294 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 295 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 296 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 297 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 298 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 299 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 300 301 mon_rx_user_status->mpdu_cnt_fcs_ok = 302 ppdu_info->com_info.mpdu_cnt_fcs_ok; 303 mon_rx_user_status->mpdu_cnt_fcs_err = 304 ppdu_info->com_info.mpdu_cnt_fcs_err; 305 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 306 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 307 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 308 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 309 310 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 311 } 312 313 #ifdef WLAN_TX_PKT_CAPTURE_ENH 314 static inline void 315 hal_rx_populate_tx_capture_user_info(void *ppduinfo, 316 uint32_t user_id) 317 { 318 struct hal_rx_ppdu_info *ppdu_info; 319 struct mon_rx_info *mon_rx_info; 320 struct mon_rx_user_info *mon_rx_user_info; 321 322 ppdu_info = (struct hal_rx_ppdu_info *)ppduinfo; 323 mon_rx_info = &ppdu_info->rx_info; 324 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 325 mon_rx_user_info->qos_control_info_valid = 326 mon_rx_info->qos_control_info_valid; 327 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 328 } 329 #else 330 static inline void 331 hal_rx_populate_tx_capture_user_info(void *ppduinfo, 332 uint32_t user_id) 333 { 334 } 335 #endif 336 337 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 338 ppdu_info, rssi_info_tlv) \ 339 { \ 340 ppdu_info->rx_status.rssi_chain[chain][0] = \ 341 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 342 RSSI_PRI20_CHAIN##chain); \ 343 ppdu_info->rx_status.rssi_chain[chain][1] = \ 344 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 345 RSSI_EXT20_CHAIN##chain); \ 346 ppdu_info->rx_status.rssi_chain[chain][2] = \ 347 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 348 RSSI_EXT40_LOW20_CHAIN##chain); \ 349 ppdu_info->rx_status.rssi_chain[chain][3] = \ 350 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 351 RSSI_EXT40_HIGH20_CHAIN##chain); \ 352 ppdu_info->rx_status.rssi_chain[chain][4] = \ 353 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 354 RSSI_EXT80_LOW20_CHAIN##chain); \ 355 ppdu_info->rx_status.rssi_chain[chain][5] = \ 356 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 357 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 358 ppdu_info->rx_status.rssi_chain[chain][6] = \ 359 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 360 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 361 ppdu_info->rx_status.rssi_chain[chain][7] = \ 362 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 363 RSSI_EXT80_HIGH20_CHAIN##chain); \ 364 } \ 365 366 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 367 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 368 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 369 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 370 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 371 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 372 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 373 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 374 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 375 376 static inline uint32_t 377 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 378 uint8_t *rssi_info_tlv) 379 { 380 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 381 return 0; 382 } 383 384 #ifdef WLAN_TX_PKT_CAPTURE_ENH 385 static inline void 386 hal_get_qos_control(void *rx_tlv, 387 struct hal_rx_ppdu_info *ppdu_info) 388 { 389 ppdu_info->rx_info.qos_control_info_valid = 390 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 391 QOS_CONTROL_INFO_VALID); 392 393 if (ppdu_info->rx_info.qos_control_info_valid) 394 ppdu_info->rx_info.qos_control = 395 HAL_RX_GET(rx_tlv, 396 RX_PPDU_END_USER_STATS_5, 397 QOS_CONTROL_FIELD); 398 } 399 400 static inline void 401 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 402 struct hal_rx_ppdu_info *ppdu_info) 403 { 404 if (ppdu_info->sw_frame_group_id 405 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) { 406 ppdu_info->rx_info.mac_addr1_valid = 407 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 408 409 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 410 HAL_RX_GET(rx_mpdu_start, 411 RX_MPDU_INFO_15, 412 MAC_ADDR_AD1_31_0); 413 } 414 } 415 #else 416 static inline void 417 hal_get_qos_control(void *rx_tlv, 418 struct hal_rx_ppdu_info *ppdu_info) 419 { 420 } 421 422 static inline void 423 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 424 struct hal_rx_ppdu_info *ppdu_info) 425 { 426 } 427 #endif 428 /** 429 * hal_rx_status_get_tlv_info() - process receive info TLV 430 * @rx_tlv_hdr: pointer to TLV header 431 * @ppdu_info: pointer to ppdu_info 432 * 433 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 434 */ 435 static inline uint32_t 436 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 437 hal_soc_handle_t hal_soc_hdl, 438 qdf_nbuf_t nbuf) 439 { 440 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 441 uint32_t tlv_tag, user_id, tlv_len, value; 442 uint8_t group_id = 0; 443 uint8_t he_dcm = 0; 444 uint8_t he_stbc = 0; 445 uint16_t he_gi = 0; 446 uint16_t he_ltf = 0; 447 void *rx_tlv; 448 bool unhandled = false; 449 struct mon_rx_user_status *mon_rx_user_status; 450 struct hal_rx_ppdu_info *ppdu_info = 451 (struct hal_rx_ppdu_info *)ppduinfo; 452 453 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 454 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 455 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 456 457 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 458 459 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 460 rx_tlv, tlv_len); 461 462 switch (tlv_tag) { 463 464 case WIFIRX_PPDU_START_E: 465 { 466 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 467 468 ppdu_info->com_info.ppdu_id = 469 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 470 PHY_PPDU_ID); 471 /* channel number is set in PHY meta data */ 472 ppdu_info->rx_status.chan_num = 473 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 474 SW_PHY_META_DATA) & 0x0000FFFF); 475 ppdu_info->rx_status.chan_freq = 476 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 477 SW_PHY_META_DATA) & 0xFFFF0000)>>16; 478 ppdu_info->com_info.ppdu_timestamp = 479 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 480 PPDU_START_TIMESTAMP); 481 ppdu_info->rx_status.ppdu_timestamp = 482 ppdu_info->com_info.ppdu_timestamp; 483 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 484 485 /* If last ppdu_id doesn't match new ppdu_id, 486 * 1. reset mpdu_cnt 487 * 2. update last_ppdu_id with new 488 * 3. reset mpdu fcs bitmap 489 */ 490 if (com_info->ppdu_id != com_info->last_ppdu_id) { 491 com_info->mpdu_cnt = 0; 492 com_info->last_ppdu_id = 493 com_info->ppdu_id; 494 com_info->num_users = 0; 495 qdf_mem_zero(&com_info->mpdu_fcs_ok_bitmap, 496 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 497 sizeof(com_info->mpdu_fcs_ok_bitmap[0])); 498 } 499 break; 500 } 501 502 case WIFIRX_PPDU_START_USER_INFO_E: 503 break; 504 505 case WIFIRX_PPDU_END_E: 506 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 507 "[%s][%d] ppdu_end_e len=%d", 508 __func__, __LINE__, tlv_len); 509 /* This is followed by sub-TLVs of PPDU_END */ 510 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 511 break; 512 513 case WIFIPHYRX_PKT_END_E: 514 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 515 break; 516 517 case WIFIRXPCU_PPDU_END_INFO_E: 518 ppdu_info->rx_status.rx_antenna = 519 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 520 ppdu_info->rx_status.tsft = 521 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 522 WB_TIMESTAMP_UPPER_32); 523 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 524 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 525 WB_TIMESTAMP_LOWER_32); 526 ppdu_info->rx_status.duration = 527 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 528 RX_PPDU_DURATION); 529 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 530 break; 531 532 /* 533 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 534 * for MU, based on num users we see this tlv that many times. 535 */ 536 case WIFIRX_PPDU_END_USER_STATS_E: 537 { 538 unsigned long tid = 0; 539 uint16_t seq = 0; 540 541 ppdu_info->rx_status.ast_index = 542 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 543 AST_INDEX); 544 545 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 546 RECEIVED_QOS_DATA_TID_BITMAP); 547 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 548 549 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 550 ppdu_info->rx_status.tid = HAL_TID_INVALID; 551 552 ppdu_info->rx_status.tcp_msdu_count = 553 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 554 TCP_MSDU_COUNT) + 555 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 556 TCP_ACK_MSDU_COUNT); 557 ppdu_info->rx_status.udp_msdu_count = 558 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 559 UDP_MSDU_COUNT); 560 ppdu_info->rx_status.other_msdu_count = 561 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 562 OTHER_MSDU_COUNT); 563 564 if (ppdu_info->sw_frame_group_id 565 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 566 ppdu_info->rx_status.frame_control_info_valid = 567 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 568 FRAME_CONTROL_INFO_VALID); 569 570 if (ppdu_info->rx_status.frame_control_info_valid) 571 ppdu_info->rx_status.frame_control = 572 HAL_RX_GET(rx_tlv, 573 RX_PPDU_END_USER_STATS_4, 574 FRAME_CONTROL_FIELD); 575 576 hal_get_qos_control(rx_tlv, ppdu_info); 577 } 578 579 ppdu_info->rx_status.data_sequence_control_info_valid = 580 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 581 DATA_SEQUENCE_CONTROL_INFO_VALID); 582 583 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 584 FIRST_DATA_SEQ_CTRL); 585 if (ppdu_info->rx_status.data_sequence_control_info_valid) 586 ppdu_info->rx_status.first_data_seq_ctrl = seq; 587 588 ppdu_info->rx_status.preamble_type = 589 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 590 HT_CONTROL_FIELD_PKT_TYPE); 591 switch (ppdu_info->rx_status.preamble_type) { 592 case HAL_RX_PKT_TYPE_11N: 593 ppdu_info->rx_status.ht_flags = 1; 594 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 595 break; 596 case HAL_RX_PKT_TYPE_11AC: 597 ppdu_info->rx_status.vht_flags = 1; 598 break; 599 case HAL_RX_PKT_TYPE_11AX: 600 ppdu_info->rx_status.he_flags = 1; 601 break; 602 default: 603 break; 604 } 605 606 ppdu_info->com_info.mpdu_cnt_fcs_ok = 607 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 608 MPDU_CNT_FCS_OK); 609 ppdu_info->com_info.mpdu_cnt_fcs_err = 610 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 611 MPDU_CNT_FCS_ERR); 612 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 613 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 614 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 615 else 616 ppdu_info->rx_status.rs_flags &= 617 (~IEEE80211_AMPDU_FLAG); 618 619 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 620 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 621 FCS_OK_BITMAP_31_0); 622 623 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 624 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 625 FCS_OK_BITMAP_63_32); 626 627 if (user_id < HAL_MAX_UL_MU_USERS) { 628 mon_rx_user_status = 629 &ppdu_info->rx_user_status[user_id]; 630 631 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 632 633 ppdu_info->com_info.num_users++; 634 635 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 636 mon_rx_user_status); 637 638 hal_rx_populate_tx_capture_user_info(ppdu_info, 639 user_id); 640 641 } 642 break; 643 } 644 645 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 646 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 647 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 648 FCS_OK_BITMAP_95_64); 649 650 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 651 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 652 FCS_OK_BITMAP_127_96); 653 654 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 655 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 656 FCS_OK_BITMAP_159_128); 657 658 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 659 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 660 FCS_OK_BITMAP_191_160); 661 662 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 663 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 664 FCS_OK_BITMAP_223_192); 665 666 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 667 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 668 FCS_OK_BITMAP_255_224); 669 break; 670 671 case WIFIRX_PPDU_END_STATUS_DONE_E: 672 return HAL_TLV_STATUS_PPDU_DONE; 673 674 case WIFIDUMMY_E: 675 return HAL_TLV_STATUS_BUF_DONE; 676 677 case WIFIPHYRX_HT_SIG_E: 678 { 679 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 680 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 681 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 682 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 683 FEC_CODING); 684 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 685 1 : 0; 686 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 687 HT_SIG_INFO_0, MCS); 688 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 689 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 690 HT_SIG_INFO_0, CBW); 691 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 692 HT_SIG_INFO_1, SHORT_GI); 693 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 694 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 695 HT_SIG_SU_NSS_SHIFT) + 1; 696 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 697 break; 698 } 699 700 case WIFIPHYRX_L_SIG_B_E: 701 { 702 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 703 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 704 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 705 706 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 707 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 708 switch (value) { 709 case 1: 710 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 711 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 712 break; 713 case 2: 714 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 715 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 716 break; 717 case 3: 718 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 719 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 720 break; 721 case 4: 722 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 723 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 724 break; 725 case 5: 726 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 727 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 728 break; 729 case 6: 730 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 731 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 732 break; 733 case 7: 734 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 735 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 736 break; 737 default: 738 break; 739 } 740 ppdu_info->rx_status.cck_flag = 1; 741 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 742 break; 743 } 744 745 case WIFIPHYRX_L_SIG_A_E: 746 { 747 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 748 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 749 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 750 751 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 752 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 753 switch (value) { 754 case 8: 755 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 756 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 757 break; 758 case 9: 759 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 760 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 761 break; 762 case 10: 763 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 764 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 765 break; 766 case 11: 767 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 768 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 769 break; 770 case 12: 771 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 772 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 773 break; 774 case 13: 775 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 776 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 777 break; 778 case 14: 779 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 780 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 781 break; 782 case 15: 783 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 784 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 785 break; 786 default: 787 break; 788 } 789 ppdu_info->rx_status.ofdm_flag = 1; 790 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 791 break; 792 } 793 794 case WIFIPHYRX_VHT_SIG_A_E: 795 { 796 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 797 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 798 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 799 800 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 801 SU_MU_CODING); 802 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 803 1 : 0; 804 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 805 ppdu_info->rx_status.vht_flag_values5 = group_id; 806 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 807 VHT_SIG_A_INFO_1, MCS); 808 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 809 VHT_SIG_A_INFO_1, GI_SETTING); 810 811 switch (hal->target_type) { 812 case TARGET_TYPE_QCA8074: 813 case TARGET_TYPE_QCA8074V2: 814 case TARGET_TYPE_QCA6018: 815 case TARGET_TYPE_QCN9000: 816 #ifdef QCA_WIFI_QCA6390 817 case TARGET_TYPE_QCA6390: 818 #endif 819 ppdu_info->rx_status.is_stbc = 820 HAL_RX_GET(vht_sig_a_info, 821 VHT_SIG_A_INFO_0, STBC); 822 value = HAL_RX_GET(vht_sig_a_info, 823 VHT_SIG_A_INFO_0, N_STS); 824 value = value & VHT_SIG_SU_NSS_MASK; 825 if (ppdu_info->rx_status.is_stbc && (value > 0)) 826 value = ((value + 1) >> 1) - 1; 827 ppdu_info->rx_status.nss = 828 ((value & VHT_SIG_SU_NSS_MASK) + 1); 829 830 break; 831 case TARGET_TYPE_QCA6290: 832 #if !defined(QCA_WIFI_QCA6290_11AX) 833 ppdu_info->rx_status.is_stbc = 834 HAL_RX_GET(vht_sig_a_info, 835 VHT_SIG_A_INFO_0, STBC); 836 value = HAL_RX_GET(vht_sig_a_info, 837 VHT_SIG_A_INFO_0, N_STS); 838 value = value & VHT_SIG_SU_NSS_MASK; 839 if (ppdu_info->rx_status.is_stbc && (value > 0)) 840 value = ((value + 1) >> 1) - 1; 841 ppdu_info->rx_status.nss = 842 ((value & VHT_SIG_SU_NSS_MASK) + 1); 843 #else 844 ppdu_info->rx_status.nss = 0; 845 #endif 846 break; 847 case TARGET_TYPE_QCA6490: 848 case TARGET_TYPE_QCA6750: 849 ppdu_info->rx_status.nss = 0; 850 break; 851 default: 852 break; 853 } 854 ppdu_info->rx_status.vht_flag_values3[0] = 855 (((ppdu_info->rx_status.mcs) << 4) 856 | ppdu_info->rx_status.nss); 857 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 858 VHT_SIG_A_INFO_0, BANDWIDTH); 859 ppdu_info->rx_status.vht_flag_values2 = 860 ppdu_info->rx_status.bw; 861 ppdu_info->rx_status.vht_flag_values4 = 862 HAL_RX_GET(vht_sig_a_info, 863 VHT_SIG_A_INFO_1, SU_MU_CODING); 864 865 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 866 VHT_SIG_A_INFO_1, BEAMFORMED); 867 if (group_id == 0 || group_id == 63) 868 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 869 else 870 ppdu_info->rx_status.reception_type = 871 HAL_RX_TYPE_MU_MIMO; 872 873 break; 874 } 875 case WIFIPHYRX_HE_SIG_A_SU_E: 876 { 877 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 878 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 879 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 880 ppdu_info->rx_status.he_flags = 1; 881 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 882 FORMAT_INDICATION); 883 if (value == 0) { 884 ppdu_info->rx_status.he_data1 = 885 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 886 } else { 887 ppdu_info->rx_status.he_data1 = 888 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 889 } 890 891 /* data1 */ 892 ppdu_info->rx_status.he_data1 |= 893 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 894 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 895 QDF_MON_STATUS_HE_DL_UL_KNOWN | 896 QDF_MON_STATUS_HE_MCS_KNOWN | 897 QDF_MON_STATUS_HE_DCM_KNOWN | 898 QDF_MON_STATUS_HE_CODING_KNOWN | 899 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 900 QDF_MON_STATUS_HE_STBC_KNOWN | 901 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 902 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 903 904 /* data2 */ 905 ppdu_info->rx_status.he_data2 = 906 QDF_MON_STATUS_HE_GI_KNOWN; 907 ppdu_info->rx_status.he_data2 |= 908 QDF_MON_STATUS_TXBF_KNOWN | 909 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 910 QDF_MON_STATUS_TXOP_KNOWN | 911 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 912 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 913 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 914 915 /* data3 */ 916 value = HAL_RX_GET(he_sig_a_su_info, 917 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 918 ppdu_info->rx_status.he_data3 = value; 919 value = HAL_RX_GET(he_sig_a_su_info, 920 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 921 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 922 ppdu_info->rx_status.he_data3 |= value; 923 value = HAL_RX_GET(he_sig_a_su_info, 924 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 925 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 926 ppdu_info->rx_status.he_data3 |= value; 927 928 value = HAL_RX_GET(he_sig_a_su_info, 929 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 930 ppdu_info->rx_status.mcs = value; 931 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 932 ppdu_info->rx_status.he_data3 |= value; 933 934 value = HAL_RX_GET(he_sig_a_su_info, 935 HE_SIG_A_SU_INFO_0, DCM); 936 he_dcm = value; 937 value = value << QDF_MON_STATUS_DCM_SHIFT; 938 ppdu_info->rx_status.he_data3 |= value; 939 value = HAL_RX_GET(he_sig_a_su_info, 940 HE_SIG_A_SU_INFO_1, CODING); 941 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 942 1 : 0; 943 value = value << QDF_MON_STATUS_CODING_SHIFT; 944 ppdu_info->rx_status.he_data3 |= value; 945 value = HAL_RX_GET(he_sig_a_su_info, 946 HE_SIG_A_SU_INFO_1, 947 LDPC_EXTRA_SYMBOL); 948 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 949 ppdu_info->rx_status.he_data3 |= value; 950 value = HAL_RX_GET(he_sig_a_su_info, 951 HE_SIG_A_SU_INFO_1, STBC); 952 he_stbc = value; 953 value = value << QDF_MON_STATUS_STBC_SHIFT; 954 ppdu_info->rx_status.he_data3 |= value; 955 956 /* data4 */ 957 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 958 SPATIAL_REUSE); 959 ppdu_info->rx_status.he_data4 = value; 960 961 /* data5 */ 962 value = HAL_RX_GET(he_sig_a_su_info, 963 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 964 ppdu_info->rx_status.he_data5 = value; 965 ppdu_info->rx_status.bw = value; 966 value = HAL_RX_GET(he_sig_a_su_info, 967 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 968 switch (value) { 969 case 0: 970 he_gi = HE_GI_0_8; 971 he_ltf = HE_LTF_1_X; 972 break; 973 case 1: 974 he_gi = HE_GI_0_8; 975 he_ltf = HE_LTF_2_X; 976 break; 977 case 2: 978 he_gi = HE_GI_1_6; 979 he_ltf = HE_LTF_2_X; 980 break; 981 case 3: 982 if (he_dcm && he_stbc) { 983 he_gi = HE_GI_0_8; 984 he_ltf = HE_LTF_4_X; 985 } else { 986 he_gi = HE_GI_3_2; 987 he_ltf = HE_LTF_4_X; 988 } 989 break; 990 } 991 ppdu_info->rx_status.sgi = he_gi; 992 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 993 ppdu_info->rx_status.he_data5 |= value; 994 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 995 ppdu_info->rx_status.ltf_size = he_ltf; 996 ppdu_info->rx_status.he_data5 |= value; 997 998 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 999 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1000 ppdu_info->rx_status.he_data5 |= value; 1001 1002 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1003 PACKET_EXTENSION_A_FACTOR); 1004 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1005 ppdu_info->rx_status.he_data5 |= value; 1006 1007 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1008 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1009 ppdu_info->rx_status.he_data5 |= value; 1010 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1011 PACKET_EXTENSION_PE_DISAMBIGUITY); 1012 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1013 ppdu_info->rx_status.he_data5 |= value; 1014 1015 /* data6 */ 1016 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1017 value++; 1018 ppdu_info->rx_status.nss = value; 1019 ppdu_info->rx_status.he_data6 = value; 1020 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1021 DOPPLER_INDICATION); 1022 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1023 ppdu_info->rx_status.he_data6 |= value; 1024 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1025 TXOP_DURATION); 1026 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1027 ppdu_info->rx_status.he_data6 |= value; 1028 1029 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1030 HE_SIG_A_SU_INFO_1, TXBF); 1031 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1032 break; 1033 } 1034 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1035 { 1036 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1037 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1038 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1039 1040 ppdu_info->rx_status.he_mu_flags = 1; 1041 1042 /* HE Flags */ 1043 /*data1*/ 1044 ppdu_info->rx_status.he_data1 = 1045 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1046 ppdu_info->rx_status.he_data1 |= 1047 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1048 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1049 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1050 QDF_MON_STATUS_HE_STBC_KNOWN | 1051 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1052 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1053 1054 /* data2 */ 1055 ppdu_info->rx_status.he_data2 = 1056 QDF_MON_STATUS_HE_GI_KNOWN; 1057 ppdu_info->rx_status.he_data2 |= 1058 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1059 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1060 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1061 QDF_MON_STATUS_TXOP_KNOWN | 1062 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1063 1064 /*data3*/ 1065 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1066 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1067 ppdu_info->rx_status.he_data3 = value; 1068 1069 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1070 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1071 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1072 ppdu_info->rx_status.he_data3 |= value; 1073 1074 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1075 HE_SIG_A_MU_DL_INFO_1, 1076 LDPC_EXTRA_SYMBOL); 1077 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1078 ppdu_info->rx_status.he_data3 |= value; 1079 1080 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1081 HE_SIG_A_MU_DL_INFO_1, STBC); 1082 he_stbc = value; 1083 value = value << QDF_MON_STATUS_STBC_SHIFT; 1084 ppdu_info->rx_status.he_data3 |= value; 1085 1086 /*data4*/ 1087 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1088 SPATIAL_REUSE); 1089 ppdu_info->rx_status.he_data4 = value; 1090 1091 /*data5*/ 1092 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1093 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1094 ppdu_info->rx_status.he_data5 = value; 1095 ppdu_info->rx_status.bw = value; 1096 1097 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1098 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1099 switch (value) { 1100 case 0: 1101 he_gi = HE_GI_0_8; 1102 he_ltf = HE_LTF_4_X; 1103 break; 1104 case 1: 1105 he_gi = HE_GI_0_8; 1106 he_ltf = HE_LTF_2_X; 1107 break; 1108 case 2: 1109 he_gi = HE_GI_1_6; 1110 he_ltf = HE_LTF_2_X; 1111 break; 1112 case 3: 1113 he_gi = HE_GI_3_2; 1114 he_ltf = HE_LTF_4_X; 1115 break; 1116 } 1117 ppdu_info->rx_status.sgi = he_gi; 1118 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1119 ppdu_info->rx_status.he_data5 |= value; 1120 1121 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1122 ppdu_info->rx_status.he_data5 |= value; 1123 1124 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1125 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1126 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1127 ppdu_info->rx_status.he_data5 |= value; 1128 1129 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1130 PACKET_EXTENSION_A_FACTOR); 1131 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1132 ppdu_info->rx_status.he_data5 |= value; 1133 1134 1135 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1136 PACKET_EXTENSION_PE_DISAMBIGUITY); 1137 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1138 ppdu_info->rx_status.he_data5 |= value; 1139 1140 /*data6*/ 1141 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1142 DOPPLER_INDICATION); 1143 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1144 ppdu_info->rx_status.he_data6 |= value; 1145 1146 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1147 TXOP_DURATION); 1148 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1149 ppdu_info->rx_status.he_data6 |= value; 1150 1151 /* HE-MU Flags */ 1152 /* HE-MU-flags1 */ 1153 ppdu_info->rx_status.he_flags1 = 1154 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1155 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1156 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1157 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1158 QDF_MON_STATUS_RU_0_KNOWN; 1159 1160 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1161 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1162 ppdu_info->rx_status.he_flags1 |= value; 1163 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1164 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1165 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1166 ppdu_info->rx_status.he_flags1 |= value; 1167 1168 /* HE-MU-flags2 */ 1169 ppdu_info->rx_status.he_flags2 = 1170 QDF_MON_STATUS_BW_KNOWN; 1171 1172 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1173 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1174 ppdu_info->rx_status.he_flags2 |= value; 1175 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1176 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1177 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1178 ppdu_info->rx_status.he_flags2 |= value; 1179 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1180 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1181 value = value - 1; 1182 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1183 ppdu_info->rx_status.he_flags2 |= value; 1184 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1185 break; 1186 } 1187 case WIFIPHYRX_HE_SIG_B1_MU_E: 1188 { 1189 1190 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1191 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1192 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1193 1194 ppdu_info->rx_status.he_sig_b_common_known |= 1195 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1196 /* TODO: Check on the availability of other fields in 1197 * sig_b_common 1198 */ 1199 1200 value = HAL_RX_GET(he_sig_b1_mu_info, 1201 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1202 ppdu_info->rx_status.he_RU[0] = value; 1203 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1204 break; 1205 } 1206 case WIFIPHYRX_HE_SIG_B2_MU_E: 1207 { 1208 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1209 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1210 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1211 /* 1212 * Not all "HE" fields can be updated from 1213 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1214 * to populate rest of the "HE" fields for MU scenarios. 1215 */ 1216 1217 /* HE-data1 */ 1218 ppdu_info->rx_status.he_data1 |= 1219 QDF_MON_STATUS_HE_MCS_KNOWN | 1220 QDF_MON_STATUS_HE_CODING_KNOWN; 1221 1222 /* HE-data2 */ 1223 1224 /* HE-data3 */ 1225 value = HAL_RX_GET(he_sig_b2_mu_info, 1226 HE_SIG_B2_MU_INFO_0, STA_MCS); 1227 ppdu_info->rx_status.mcs = value; 1228 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1229 ppdu_info->rx_status.he_data3 |= value; 1230 1231 1232 value = HAL_RX_GET(he_sig_b2_mu_info, 1233 HE_SIG_B2_MU_INFO_0, STA_CODING); 1234 value = value << QDF_MON_STATUS_CODING_SHIFT; 1235 ppdu_info->rx_status.he_data3 |= value; 1236 1237 /* HE-data4 */ 1238 value = HAL_RX_GET(he_sig_b2_mu_info, 1239 HE_SIG_B2_MU_INFO_0, STA_ID); 1240 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1241 ppdu_info->rx_status.he_data4 |= value; 1242 1243 /* HE-data5 */ 1244 1245 /* HE-data6 */ 1246 value = HAL_RX_GET(he_sig_b2_mu_info, 1247 HE_SIG_B2_MU_INFO_0, NSTS); 1248 /* value n indicates n+1 spatial streams */ 1249 value++; 1250 ppdu_info->rx_status.nss = value; 1251 ppdu_info->rx_status.he_data6 |= value; 1252 1253 break; 1254 1255 } 1256 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1257 { 1258 uint8_t *he_sig_b2_ofdma_info = 1259 (uint8_t *)rx_tlv + 1260 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1261 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1262 1263 /* 1264 * Not all "HE" fields can be updated from 1265 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1266 * to populate rest of "HE" fields for MU OFDMA scenarios. 1267 */ 1268 1269 /* HE-data1 */ 1270 ppdu_info->rx_status.he_data1 |= 1271 QDF_MON_STATUS_HE_MCS_KNOWN | 1272 QDF_MON_STATUS_HE_DCM_KNOWN | 1273 QDF_MON_STATUS_HE_CODING_KNOWN; 1274 1275 /* HE-data2 */ 1276 ppdu_info->rx_status.he_data2 |= 1277 QDF_MON_STATUS_TXBF_KNOWN; 1278 1279 /* HE-data3 */ 1280 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1281 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1282 ppdu_info->rx_status.mcs = value; 1283 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1284 ppdu_info->rx_status.he_data3 |= value; 1285 1286 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1287 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1288 he_dcm = value; 1289 value = value << QDF_MON_STATUS_DCM_SHIFT; 1290 ppdu_info->rx_status.he_data3 |= value; 1291 1292 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1293 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1294 value = value << QDF_MON_STATUS_CODING_SHIFT; 1295 ppdu_info->rx_status.he_data3 |= value; 1296 1297 /* HE-data4 */ 1298 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1299 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1300 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1301 ppdu_info->rx_status.he_data4 |= value; 1302 1303 /* HE-data5 */ 1304 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1305 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1306 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1307 ppdu_info->rx_status.he_data5 |= value; 1308 1309 /* HE-data6 */ 1310 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1311 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1312 /* value n indicates n+1 spatial streams */ 1313 value++; 1314 ppdu_info->rx_status.nss = value; 1315 ppdu_info->rx_status.he_data6 |= value; 1316 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1317 break; 1318 } 1319 case WIFIPHYRX_RSSI_LEGACY_E: 1320 { 1321 uint8_t reception_type; 1322 int8_t rssi_value; 1323 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1324 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1325 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1326 1327 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1328 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1329 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1330 ppdu_info->rx_status.he_re = 0; 1331 1332 reception_type = HAL_RX_GET(rx_tlv, 1333 PHYRX_RSSI_LEGACY_0, 1334 RECEPTION_TYPE); 1335 switch (reception_type) { 1336 case QDF_RECEPTION_TYPE_ULOFMDA: 1337 ppdu_info->rx_status.reception_type = 1338 HAL_RX_TYPE_MU_OFDMA; 1339 ppdu_info->rx_status.ulofdma_flag = 1; 1340 ppdu_info->rx_status.he_data1 = 1341 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1342 break; 1343 case QDF_RECEPTION_TYPE_ULMIMO: 1344 ppdu_info->rx_status.reception_type = 1345 HAL_RX_TYPE_MU_MIMO; 1346 ppdu_info->rx_status.he_data1 = 1347 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1348 break; 1349 default: 1350 ppdu_info->rx_status.reception_type = 1351 HAL_RX_TYPE_SU; 1352 break; 1353 } 1354 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1355 rssi_value = HAL_RX_GET(rssi_info_tlv, 1356 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1357 ppdu_info->rx_status.rssi[0] = rssi_value; 1358 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1359 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1360 1361 rssi_value = HAL_RX_GET(rssi_info_tlv, 1362 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1363 ppdu_info->rx_status.rssi[1] = rssi_value; 1364 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1365 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1366 1367 rssi_value = HAL_RX_GET(rssi_info_tlv, 1368 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1369 ppdu_info->rx_status.rssi[2] = rssi_value; 1370 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1371 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1372 1373 rssi_value = HAL_RX_GET(rssi_info_tlv, 1374 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1375 ppdu_info->rx_status.rssi[3] = rssi_value; 1376 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1377 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1378 1379 rssi_value = HAL_RX_GET(rssi_info_tlv, 1380 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1381 ppdu_info->rx_status.rssi[4] = rssi_value; 1382 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1383 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1384 1385 rssi_value = HAL_RX_GET(rssi_info_tlv, 1386 RECEIVE_RSSI_INFO_10, 1387 RSSI_PRI20_CHAIN5); 1388 ppdu_info->rx_status.rssi[5] = rssi_value; 1389 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1390 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1391 1392 rssi_value = HAL_RX_GET(rssi_info_tlv, 1393 RECEIVE_RSSI_INFO_12, 1394 RSSI_PRI20_CHAIN6); 1395 ppdu_info->rx_status.rssi[6] = rssi_value; 1396 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1397 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1398 1399 rssi_value = HAL_RX_GET(rssi_info_tlv, 1400 RECEIVE_RSSI_INFO_14, 1401 RSSI_PRI20_CHAIN7); 1402 ppdu_info->rx_status.rssi[7] = rssi_value; 1403 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1404 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1405 break; 1406 } 1407 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1408 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1409 ppdu_info); 1410 break; 1411 case WIFIRX_HEADER_E: 1412 { 1413 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1414 uint16_t mpdu_cnt = com_info->mpdu_cnt; 1415 1416 if (mpdu_cnt >= HAL_RX_MAX_MPDU) { 1417 hal_alert("Number of MPDUs per PPDU exceeded"); 1418 break; 1419 } 1420 /* Update first_msdu_payload for every mpdu and increment 1421 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1422 */ 1423 ppdu_info->ppdu_msdu_info[mpdu_cnt].first_msdu_payload = 1424 rx_tlv; 1425 ppdu_info->ppdu_msdu_info[mpdu_cnt].payload_len = tlv_len; 1426 ppdu_info->ppdu_msdu_info[mpdu_cnt].nbuf = nbuf; 1427 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1428 ppdu_info->msdu_info.payload_len = tlv_len; 1429 ppdu_info->user_id = user_id; 1430 ppdu_info->hdr_len = tlv_len; 1431 ppdu_info->data = rx_tlv; 1432 ppdu_info->data += 4; 1433 1434 /* for every RX_HEADER TLV increment mpdu_cnt */ 1435 com_info->mpdu_cnt++; 1436 return HAL_TLV_STATUS_HEADER; 1437 } 1438 case WIFIRX_MPDU_START_E: 1439 { 1440 uint8_t *rx_mpdu_start = 1441 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1442 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1443 uint32_t ppdu_id = 1444 HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1445 uint8_t filter_category = 0; 1446 1447 ppdu_info->nac_info.fc_valid = 1448 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1449 1450 ppdu_info->nac_info.to_ds_flag = 1451 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1452 1453 ppdu_info->nac_info.frame_control = 1454 HAL_RX_GET(rx_mpdu_start, 1455 RX_MPDU_INFO_14, 1456 MPDU_FRAME_CONTROL_FIELD); 1457 1458 ppdu_info->sw_frame_group_id = 1459 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1460 1461 if (ppdu_info->sw_frame_group_id == 1462 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1463 ppdu_info->rx_status.frame_control_info_valid = 1464 ppdu_info->nac_info.fc_valid; 1465 ppdu_info->rx_status.frame_control = 1466 ppdu_info->nac_info.frame_control; 1467 } 1468 1469 hal_get_mac_addr1(rx_mpdu_start, 1470 ppdu_info); 1471 1472 ppdu_info->nac_info.mac_addr2_valid = 1473 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1474 1475 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1476 HAL_RX_GET(rx_mpdu_start, 1477 RX_MPDU_INFO_16, 1478 MAC_ADDR_AD2_15_0); 1479 1480 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1481 HAL_RX_GET(rx_mpdu_start, 1482 RX_MPDU_INFO_17, 1483 MAC_ADDR_AD2_47_16); 1484 1485 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1486 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1487 ppdu_info->rx_status.ppdu_len = 1488 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1489 MPDU_LENGTH); 1490 } else { 1491 ppdu_info->rx_status.ppdu_len += 1492 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1493 MPDU_LENGTH); 1494 } 1495 1496 filter_category = 1497 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1498 1499 if (filter_category == 0) 1500 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1501 else if (filter_category == 1) 1502 ppdu_info->rx_status.monitor_direct_used = 1; 1503 1504 ppdu_info->nac_info.mcast_bcast = 1505 HAL_RX_GET(rx_mpdu_start, 1506 RX_MPDU_INFO_13, 1507 MCAST_BCAST); 1508 break; 1509 } 1510 case WIFIRX_MPDU_END_E: 1511 ppdu_info->user_id = user_id; 1512 ppdu_info->fcs_err = 1513 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1514 FCS_ERR); 1515 return HAL_TLV_STATUS_MPDU_END; 1516 case WIFIRX_MSDU_END_E: 1517 if (user_id < HAL_MAX_UL_MU_USERS) { 1518 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1519 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1520 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1521 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1522 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1523 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1524 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1525 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1526 ppdu_info->rx_msdu_info[user_id].flow_idx = 1527 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1528 } 1529 return HAL_TLV_STATUS_MSDU_END; 1530 case 0: 1531 return HAL_TLV_STATUS_PPDU_DONE; 1532 1533 default: 1534 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1535 unhandled = false; 1536 else 1537 unhandled = true; 1538 break; 1539 } 1540 1541 if (!unhandled) 1542 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1543 "%s TLV type: %d, TLV len:%d %s", 1544 __func__, tlv_tag, tlv_len, 1545 unhandled == true ? "unhandled" : ""); 1546 1547 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1548 rx_tlv, tlv_len); 1549 1550 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1551 } 1552 1553 /** 1554 * hal_reo_setup - Initialize HW REO block 1555 * 1556 * @hal_soc: Opaque HAL SOC handle 1557 * @reo_params: parameters needed by HAL for REO config 1558 */ 1559 static void hal_reo_setup_generic(struct hal_soc *soc, 1560 void *reoparams) 1561 { 1562 uint32_t reg_val; 1563 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1564 1565 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1566 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1567 1568 hal_reo_config(soc, reg_val, reo_params); 1569 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1570 1571 /* TODO: Setup destination ring mapping if enabled */ 1572 1573 /* TODO: Error destination ring setting is left to default. 1574 * Default setting is to send all errors to release ring. 1575 */ 1576 1577 HAL_REG_WRITE(soc, 1578 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1579 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1580 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1581 1582 HAL_REG_WRITE(soc, 1583 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1584 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1585 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1586 1587 HAL_REG_WRITE(soc, 1588 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1589 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1590 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1591 1592 HAL_REG_WRITE(soc, 1593 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1594 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1595 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1596 1597 /* 1598 * When hash based routing is enabled, routing of the rx packet 1599 * is done based on the following value: 1 _ _ _ _ The last 4 1600 * bits are based on hash[3:0]. This means the possible values 1601 * are 0x10 to 0x1f. This value is used to look-up the 1602 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1603 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1604 * registers need to be configured to set-up the 16 entries to 1605 * map the hash values to a ring number. There are 3 bits per 1606 * hash entry – which are mapped as follows: 1607 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1608 * 7: NOT_USED. 1609 */ 1610 if (reo_params->rx_hash_enabled) { 1611 HAL_REG_WRITE(soc, 1612 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1613 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1614 reo_params->remap1); 1615 1616 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1617 HAL_REG_READ(soc, 1618 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1619 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1620 1621 HAL_REG_WRITE(soc, 1622 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1623 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1624 reo_params->remap2); 1625 1626 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1627 HAL_REG_READ(soc, 1628 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1629 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1630 } 1631 1632 1633 /* TODO: Check if the following registers shoould be setup by host: 1634 * AGING_CONTROL 1635 * HIGH_MEMORY_THRESHOLD 1636 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1637 * GLOBAL_LINK_DESC_COUNT_CTRL 1638 */ 1639 } 1640 1641 /** 1642 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1643 * @hal_soc: Opaque HAL SOC handle 1644 * @hal_ring: Source ring pointer 1645 * @headp: Head Pointer 1646 * @tailp: Tail Pointer 1647 * @ring: Ring type 1648 * 1649 * Return: Update tail pointer and head pointer in arguments. 1650 */ 1651 static inline 1652 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 1653 hal_ring_handle_t hal_ring_hdl, 1654 uint32_t *headp, uint32_t *tailp, 1655 uint8_t ring) 1656 { 1657 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1658 struct hal_hw_srng_config *ring_config; 1659 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1660 1661 if (!hal_soc || !srng) { 1662 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1663 "%s: Context is Null", __func__); 1664 return; 1665 } 1666 1667 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 1668 if (!ring_config->lmac_ring) { 1669 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1670 *headp = SRNG_SRC_REG_READ(srng, HP); 1671 *tailp = SRNG_SRC_REG_READ(srng, TP); 1672 } else { 1673 *headp = SRNG_DST_REG_READ(srng, HP); 1674 *tailp = SRNG_DST_REG_READ(srng, TP); 1675 } 1676 } 1677 } 1678 1679 /** 1680 * hal_srng_src_hw_init - Private function to initialize SRNG 1681 * source ring HW 1682 * @hal_soc: HAL SOC handle 1683 * @srng: SRNG ring pointer 1684 */ 1685 static inline 1686 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 1687 struct hal_srng *srng) 1688 { 1689 uint32_t reg_val = 0; 1690 uint64_t tp_addr = 0; 1691 1692 hal_debug("hw_init srng %d", srng->ring_id); 1693 1694 if (srng->flags & HAL_SRNG_MSI_INTR) { 1695 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1696 srng->msi_addr & 0xffffffff); 1697 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1698 (uint64_t)(srng->msi_addr) >> 32) | 1699 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1700 MSI1_ENABLE), 1); 1701 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1702 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1703 } 1704 1705 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1706 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1707 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1708 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1709 srng->entry_size * srng->num_entries); 1710 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1711 1712 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1713 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1714 1715 /** 1716 * Interrupt setup: 1717 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1718 * if level mode is required 1719 */ 1720 reg_val = 0; 1721 1722 /* 1723 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1724 * programmed in terms of 1us resolution instead of 8us resolution as 1725 * given in MLD. 1726 */ 1727 if (srng->intr_timer_thres_us) { 1728 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1729 INTERRUPT_TIMER_THRESHOLD), 1730 srng->intr_timer_thres_us); 1731 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1732 } 1733 1734 if (srng->intr_batch_cntr_thres_entries) { 1735 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1736 BATCH_COUNTER_THRESHOLD), 1737 srng->intr_batch_cntr_thres_entries * 1738 srng->entry_size); 1739 } 1740 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1741 1742 reg_val = 0; 1743 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1744 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1745 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1746 } 1747 1748 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1749 1750 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1751 * remain 0 to avoid some WBM stability issues. Remote head/tail 1752 * pointers are not required since this ring is completely managed 1753 * by WBM HW 1754 */ 1755 reg_val = 0; 1756 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1757 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1758 ((unsigned long)(srng->u.src_ring.tp_addr) - 1759 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1760 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1761 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1762 } else { 1763 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1764 } 1765 1766 /* Initilaize head and tail pointers to indicate ring is empty */ 1767 SRNG_SRC_REG_WRITE(srng, HP, 0); 1768 SRNG_SRC_REG_WRITE(srng, TP, 0); 1769 *(srng->u.src_ring.tp_addr) = 0; 1770 1771 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1772 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1773 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1774 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1775 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1776 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1777 1778 /* Loop count is not used for SRC rings */ 1779 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1780 1781 /* 1782 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1783 * todo: update fw_api and replace with above line 1784 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1785 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1786 */ 1787 reg_val |= 0x40; 1788 1789 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1790 } 1791 1792 /** 1793 * hal_srng_dst_hw_init - Private function to initialize SRNG 1794 * destination ring HW 1795 * @hal_soc: HAL SOC handle 1796 * @srng: SRNG ring pointer 1797 */ 1798 static inline 1799 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 1800 struct hal_srng *srng) 1801 { 1802 uint32_t reg_val = 0; 1803 uint64_t hp_addr = 0; 1804 1805 hal_debug("hw_init srng %d", srng->ring_id); 1806 1807 if (srng->flags & HAL_SRNG_MSI_INTR) { 1808 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1809 srng->msi_addr & 0xffffffff); 1810 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1811 (uint64_t)(srng->msi_addr) >> 32) | 1812 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1813 MSI1_ENABLE), 1); 1814 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1815 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1816 } 1817 1818 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1819 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1820 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1821 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1822 srng->entry_size * srng->num_entries); 1823 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1824 1825 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1826 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1827 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1828 1829 1830 /** 1831 * Interrupt setup: 1832 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1833 * if level mode is required 1834 */ 1835 reg_val = 0; 1836 if (srng->intr_timer_thres_us) { 1837 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1838 INTERRUPT_TIMER_THRESHOLD), 1839 srng->intr_timer_thres_us >> 3); 1840 } 1841 1842 if (srng->intr_batch_cntr_thres_entries) { 1843 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1844 BATCH_COUNTER_THRESHOLD), 1845 srng->intr_batch_cntr_thres_entries * 1846 srng->entry_size); 1847 } 1848 1849 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1850 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1851 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1852 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1853 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1854 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1855 1856 /* Initilaize head and tail pointers to indicate ring is empty */ 1857 SRNG_DST_REG_WRITE(srng, HP, 0); 1858 SRNG_DST_REG_WRITE(srng, TP, 0); 1859 *(srng->u.dst_ring.hp_addr) = 0; 1860 1861 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1862 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1863 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1864 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1865 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1866 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1867 1868 /* 1869 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1870 * todo: update fw_api and replace with above line 1871 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1872 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1873 */ 1874 reg_val |= 0x40; 1875 1876 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1877 1878 } 1879 1880 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1881 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1882 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1883 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1884 1885 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1886 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1887 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1888 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1889 1890 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1891 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1892 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1893 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1894 1895 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1896 (((*(((uint32_t *) wbm_desc) + \ 1897 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1898 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1899 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1900 1901 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1902 (((*(((uint32_t *) wbm_desc) + \ 1903 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1904 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1905 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1906 1907 /** 1908 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1909 * save it to hal_wbm_err_desc_info structure passed by caller 1910 * @wbm_desc: wbm ring descriptor 1911 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1912 * Return: void 1913 */ 1914 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1915 void *wbm_er_info1) 1916 { 1917 struct hal_wbm_err_desc_info *wbm_er_info = 1918 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1919 1920 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1921 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1922 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1923 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1924 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1925 } 1926 1927 /** 1928 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1929 * @hal_desc: completion ring descriptor pointer 1930 * 1931 * This function will return the type of pointer - buffer or descriptor 1932 * 1933 * Return: buffer type 1934 */ 1935 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1936 { 1937 uint32_t comp_desc = 1938 *(uint32_t *) (((uint8_t *) hal_desc) + 1939 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1940 1941 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1942 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1943 } 1944 1945 /** 1946 * hal_get_wbm_internal_error_generic() - is WBM internal error 1947 * @hal_desc: completion ring descriptor pointer 1948 * 1949 * This function will return 0 or 1 - is it WBM internal error or not 1950 * 1951 * Return: uint8_t 1952 */ 1953 static inline uint8_t hal_get_wbm_internal_error_generic(void *hal_desc) 1954 { 1955 uint32_t comp_desc = 1956 *(uint32_t *)(((uint8_t *)hal_desc) + 1957 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET); 1958 1959 return (comp_desc & WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK) >> 1960 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB; 1961 } 1962 1963 /** 1964 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1965 * human readable format. 1966 * @mpdu_start: pointer the rx_attention TLV in pkt. 1967 * @dbg_level: log level. 1968 * 1969 * Return: void 1970 */ 1971 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1972 uint8_t dbg_level) 1973 { 1974 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1975 struct rx_mpdu_info *mpdu_info = 1976 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1977 1978 hal_verbose_debug( 1979 "rx_mpdu_start tlv (1/5) - " 1980 "rxpcu_mpdu_filter_in_category: %x " 1981 "sw_frame_group_id: %x " 1982 "ndp_frame: %x " 1983 "phy_err: %x " 1984 "phy_err_during_mpdu_header: %x " 1985 "protocol_version_err: %x " 1986 "ast_based_lookup_valid: %x " 1987 "phy_ppdu_id: %x " 1988 "ast_index: %x " 1989 "sw_peer_id: %x " 1990 "mpdu_frame_control_valid: %x " 1991 "mpdu_duration_valid: %x " 1992 "mac_addr_ad1_valid: %x " 1993 "mac_addr_ad2_valid: %x " 1994 "mac_addr_ad3_valid: %x " 1995 "mac_addr_ad4_valid: %x " 1996 "mpdu_sequence_control_valid: %x " 1997 "mpdu_qos_control_valid: %x " 1998 "mpdu_ht_control_valid: %x " 1999 "frame_encryption_info_valid: %x ", 2000 mpdu_info->rxpcu_mpdu_filter_in_category, 2001 mpdu_info->sw_frame_group_id, 2002 mpdu_info->ndp_frame, 2003 mpdu_info->phy_err, 2004 mpdu_info->phy_err_during_mpdu_header, 2005 mpdu_info->protocol_version_err, 2006 mpdu_info->ast_based_lookup_valid, 2007 mpdu_info->phy_ppdu_id, 2008 mpdu_info->ast_index, 2009 mpdu_info->sw_peer_id, 2010 mpdu_info->mpdu_frame_control_valid, 2011 mpdu_info->mpdu_duration_valid, 2012 mpdu_info->mac_addr_ad1_valid, 2013 mpdu_info->mac_addr_ad2_valid, 2014 mpdu_info->mac_addr_ad3_valid, 2015 mpdu_info->mac_addr_ad4_valid, 2016 mpdu_info->mpdu_sequence_control_valid, 2017 mpdu_info->mpdu_qos_control_valid, 2018 mpdu_info->mpdu_ht_control_valid, 2019 mpdu_info->frame_encryption_info_valid); 2020 2021 hal_verbose_debug( 2022 "rx_mpdu_start tlv (2/5) - " 2023 "fr_ds: %x " 2024 "to_ds: %x " 2025 "encrypted: %x " 2026 "mpdu_retry: %x " 2027 "mpdu_sequence_number: %x " 2028 "epd_en: %x " 2029 "all_frames_shall_be_encrypted: %x " 2030 "encrypt_type: %x " 2031 "mesh_sta: %x " 2032 "bssid_hit: %x " 2033 "bssid_number: %x " 2034 "tid: %x " 2035 "pn_31_0: %x " 2036 "pn_63_32: %x " 2037 "pn_95_64: %x " 2038 "pn_127_96: %x " 2039 "peer_meta_data: %x " 2040 "rxpt_classify_info.reo_destination_indication: %x " 2041 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 2042 "rx_reo_queue_desc_addr_31_0: %x ", 2043 mpdu_info->fr_ds, 2044 mpdu_info->to_ds, 2045 mpdu_info->encrypted, 2046 mpdu_info->mpdu_retry, 2047 mpdu_info->mpdu_sequence_number, 2048 mpdu_info->epd_en, 2049 mpdu_info->all_frames_shall_be_encrypted, 2050 mpdu_info->encrypt_type, 2051 mpdu_info->mesh_sta, 2052 mpdu_info->bssid_hit, 2053 mpdu_info->bssid_number, 2054 mpdu_info->tid, 2055 mpdu_info->pn_31_0, 2056 mpdu_info->pn_63_32, 2057 mpdu_info->pn_95_64, 2058 mpdu_info->pn_127_96, 2059 mpdu_info->peer_meta_data, 2060 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 2061 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 2062 mpdu_info->rx_reo_queue_desc_addr_31_0); 2063 2064 hal_verbose_debug( 2065 "rx_mpdu_start tlv (3/5) - " 2066 "rx_reo_queue_desc_addr_39_32: %x " 2067 "receive_queue_number: %x " 2068 "pre_delim_err_warning: %x " 2069 "first_delim_err: %x " 2070 "key_id_octet: %x " 2071 "new_peer_entry: %x " 2072 "decrypt_needed: %x " 2073 "decap_type: %x " 2074 "rx_insert_vlan_c_tag_padding: %x " 2075 "rx_insert_vlan_s_tag_padding: %x " 2076 "strip_vlan_c_tag_decap: %x " 2077 "strip_vlan_s_tag_decap: %x " 2078 "pre_delim_count: %x " 2079 "ampdu_flag: %x " 2080 "bar_frame: %x " 2081 "mpdu_length: %x " 2082 "first_mpdu: %x " 2083 "mcast_bcast: %x " 2084 "ast_index_not_found: %x " 2085 "ast_index_timeout: %x ", 2086 mpdu_info->rx_reo_queue_desc_addr_39_32, 2087 mpdu_info->receive_queue_number, 2088 mpdu_info->pre_delim_err_warning, 2089 mpdu_info->first_delim_err, 2090 mpdu_info->key_id_octet, 2091 mpdu_info->new_peer_entry, 2092 mpdu_info->decrypt_needed, 2093 mpdu_info->decap_type, 2094 mpdu_info->rx_insert_vlan_c_tag_padding, 2095 mpdu_info->rx_insert_vlan_s_tag_padding, 2096 mpdu_info->strip_vlan_c_tag_decap, 2097 mpdu_info->strip_vlan_s_tag_decap, 2098 mpdu_info->pre_delim_count, 2099 mpdu_info->ampdu_flag, 2100 mpdu_info->bar_frame, 2101 mpdu_info->mpdu_length, 2102 mpdu_info->first_mpdu, 2103 mpdu_info->mcast_bcast, 2104 mpdu_info->ast_index_not_found, 2105 mpdu_info->ast_index_timeout); 2106 2107 hal_verbose_debug( 2108 "rx_mpdu_start tlv (4/5) - " 2109 "power_mgmt: %x " 2110 "non_qos: %x " 2111 "null_data: %x " 2112 "mgmt_type: %x " 2113 "ctrl_type: %x " 2114 "more_data: %x " 2115 "eosp: %x " 2116 "fragment_flag: %x " 2117 "order: %x " 2118 "u_apsd_trigger: %x " 2119 "encrypt_required: %x " 2120 "directed: %x " 2121 "mpdu_frame_control_field: %x " 2122 "mpdu_duration_field: %x " 2123 "mac_addr_ad1_31_0: %x " 2124 "mac_addr_ad1_47_32: %x " 2125 "mac_addr_ad2_15_0: %x " 2126 "mac_addr_ad2_47_16: %x " 2127 "mac_addr_ad3_31_0: %x " 2128 "mac_addr_ad3_47_32: %x ", 2129 mpdu_info->power_mgmt, 2130 mpdu_info->non_qos, 2131 mpdu_info->null_data, 2132 mpdu_info->mgmt_type, 2133 mpdu_info->ctrl_type, 2134 mpdu_info->more_data, 2135 mpdu_info->eosp, 2136 mpdu_info->fragment_flag, 2137 mpdu_info->order, 2138 mpdu_info->u_apsd_trigger, 2139 mpdu_info->encrypt_required, 2140 mpdu_info->directed, 2141 mpdu_info->mpdu_frame_control_field, 2142 mpdu_info->mpdu_duration_field, 2143 mpdu_info->mac_addr_ad1_31_0, 2144 mpdu_info->mac_addr_ad1_47_32, 2145 mpdu_info->mac_addr_ad2_15_0, 2146 mpdu_info->mac_addr_ad2_47_16, 2147 mpdu_info->mac_addr_ad3_31_0, 2148 mpdu_info->mac_addr_ad3_47_32); 2149 2150 hal_verbose_debug( 2151 "rx_mpdu_start tlv (5/5) - " 2152 "mpdu_sequence_control_field: %x " 2153 "mac_addr_ad4_31_0: %x " 2154 "mac_addr_ad4_47_32: %x " 2155 "mpdu_qos_control_field: %x " 2156 "mpdu_ht_control_field: %x ", 2157 mpdu_info->mpdu_sequence_control_field, 2158 mpdu_info->mac_addr_ad4_31_0, 2159 mpdu_info->mac_addr_ad4_47_32, 2160 mpdu_info->mpdu_qos_control_field, 2161 mpdu_info->mpdu_ht_control_field); 2162 } 2163 2164 /** 2165 * hal_tx_desc_set_search_type - Set the search type value 2166 * @desc: Handle to Tx Descriptor 2167 * @search_type: search type 2168 * 0 – Normal search 2169 * 1 – Index based address search 2170 * 2 – Index based flow search 2171 * 2172 * Return: void 2173 */ 2174 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2175 static void hal_tx_desc_set_search_type_generic(void *desc, 2176 uint8_t search_type) 2177 { 2178 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2179 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2180 } 2181 #else 2182 static void hal_tx_desc_set_search_type_generic(void *desc, 2183 uint8_t search_type) 2184 { 2185 } 2186 2187 #endif 2188 2189 /** 2190 * hal_tx_desc_set_search_index - Set the search index value 2191 * @desc: Handle to Tx Descriptor 2192 * @search_index: The index that will be used for index based address or 2193 * flow search. The field is valid when 'search_type' is 2194 * 1 0r 2 2195 * 2196 * Return: void 2197 */ 2198 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2199 static void hal_tx_desc_set_search_index_generic(void *desc, 2200 uint32_t search_index) 2201 { 2202 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2203 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2204 } 2205 #else 2206 static void hal_tx_desc_set_search_index_generic(void *desc, 2207 uint32_t search_index) 2208 { 2209 } 2210 #endif 2211 2212 /** 2213 * hal_tx_desc_set_cache_set_num_generic - Set the cache-set-num value 2214 * @desc: Handle to Tx Descriptor 2215 * @cache_num: Cache set number that should be used to cache the index 2216 * based search results, for address and flow search. 2217 * This value should be equal to LSB four bits of the hash value 2218 * of match data, in case of search index points to an entry 2219 * which may be used in content based search also. The value can 2220 * be anything when the entry pointed by search index will not be 2221 * used for content based search. 2222 * 2223 * Return: void 2224 */ 2225 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2226 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2227 uint8_t cache_num) 2228 { 2229 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2230 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2231 } 2232 #else 2233 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2234 uint8_t cache_num) 2235 { 2236 } 2237 #endif 2238 2239 /** 2240 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2241 * @soc: HAL SoC context 2242 * @map: PCP-TID mapping table 2243 * 2244 * PCP are mapped to 8 TID values using TID values programmed 2245 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2246 * The mapping register has TID mapping for 8 PCP values 2247 * 2248 * Return: none 2249 */ 2250 static void hal_tx_set_pcp_tid_map_generic(struct hal_soc *soc, uint8_t *map) 2251 { 2252 uint32_t addr, value; 2253 2254 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2255 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2256 2257 value = (map[0] | 2258 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2259 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2260 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2261 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2262 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2263 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2264 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2265 2266 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2267 } 2268 2269 /** 2270 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2271 * value received from user-space 2272 * @soc: HAL SoC context 2273 * @pcp: pcp value 2274 * @tid : tid value 2275 * 2276 * Return: void 2277 */ 2278 static 2279 void hal_tx_update_pcp_tid_generic(struct hal_soc *soc, 2280 uint8_t pcp, uint8_t tid) 2281 { 2282 uint32_t addr, value, regval; 2283 2284 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2285 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2286 2287 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2288 2289 /* Read back previous PCP TID config and update 2290 * with new config. 2291 */ 2292 regval = HAL_REG_READ(soc, addr); 2293 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2294 regval |= value; 2295 2296 HAL_REG_WRITE(soc, addr, 2297 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2298 } 2299 2300 /** 2301 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2302 * @soc: HAL SoC context 2303 * @val: priority value 2304 * 2305 * Return: void 2306 */ 2307 static 2308 void hal_tx_update_tidmap_prty_generic(struct hal_soc *soc, uint8_t value) 2309 { 2310 uint32_t addr; 2311 2312 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2313 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2314 2315 HAL_REG_WRITE(soc, addr, 2316 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2317 } 2318 2319 /** 2320 * hal_rx_msdu_packet_metadata_get(): API to get the 2321 * msdu information from rx_msdu_end TLV 2322 * 2323 * @ buf: pointer to the start of RX PKT TLV headers 2324 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2325 */ 2326 static void 2327 hal_rx_msdu_packet_metadata_get_generic(uint8_t *buf, 2328 void *pkt_msdu_metadata) 2329 { 2330 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2331 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2332 struct hal_rx_msdu_metadata *msdu_metadata = 2333 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2334 2335 msdu_metadata->l3_hdr_pad = 2336 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2337 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2338 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2339 msdu_metadata->sa_sw_peer_id = 2340 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2341 } 2342 #endif /* _HAL_GENERIC_API_H_ */ 2343