1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 22 ((struct rx_msdu_desc_info *) \ 23 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 24 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 25 /** 26 * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr 27 * @msdu_details_ptr - Pointer to msdu_details_ptr 28 * Return - Pointer to rx_msdu_desc_info structure. 29 * 30 */ 31 static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) 32 { 33 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 34 } 35 36 37 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 38 ((struct rx_msdu_details *) \ 39 _OFFSET_TO_BYTE_PTR((link_desc),\ 40 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 41 /** 42 * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details 43 * @link_desc - Pointer to link desc 44 * Return - Pointer to rx_msdu_details structure 45 * 46 */ 47 48 static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) 49 { 50 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 51 } 52 53 /** 54 * hal_tx_comp_get_status() - TQM Release reason 55 * @hal_desc: completion ring Tx status 56 * 57 * This function will parse the WBM completion descriptor and populate in 58 * HAL structure 59 * 60 * Return: none 61 */ 62 static inline void hal_tx_comp_get_status_generic(void *desc, 63 void *ts1, void *hal) 64 { 65 uint8_t rate_stats_valid = 0; 66 uint32_t rate_stats = 0; 67 struct hal_tx_completion_status *ts = 68 (struct hal_tx_completion_status *)ts1; 69 70 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 71 TQM_STATUS_NUMBER); 72 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 73 ACK_FRAME_RSSI); 74 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 75 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 76 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 77 MSDU_PART_OF_AMSDU); 78 79 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 80 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 81 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 82 TRANSMIT_COUNT); 83 84 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 85 TX_RATE_STATS); 86 87 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 88 TX_RATE_STATS_INFO_VALID, rate_stats); 89 90 ts->valid = rate_stats_valid; 91 92 if (rate_stats_valid) { 93 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 94 rate_stats); 95 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 96 TRANSMIT_PKT_TYPE, rate_stats); 97 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 98 TRANSMIT_STBC, rate_stats); 99 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 100 rate_stats); 101 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 102 rate_stats); 103 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 104 rate_stats); 105 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 106 rate_stats); 107 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 108 rate_stats); 109 } 110 111 ts->release_src = hal_tx_comp_get_buffer_source(desc); 112 ts->status = hal_tx_comp_get_release_reason(desc, hal); 113 114 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 115 TX_RATE_STATS_INFO_TX_RATE_STATS); 116 } 117 118 /** 119 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 120 * @desc: Handle to Tx Descriptor 121 * @paddr: Physical Address 122 * @pool_id: Return Buffer Manager ID 123 * @desc_id: Descriptor ID 124 * @type: 0 - Address points to a MSDU buffer 125 * 1 - Address points to MSDU extension descriptor 126 * 127 * Return: void 128 */ 129 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 130 dma_addr_t paddr, uint8_t pool_id, 131 uint32_t desc_id, uint8_t type) 132 { 133 /* Set buffer_addr_info.buffer_addr_31_0 */ 134 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 135 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 136 137 /* Set buffer_addr_info.buffer_addr_39_32 */ 138 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 139 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 140 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 141 (((uint64_t) paddr) >> 32)); 142 143 /* Set buffer_addr_info.return_buffer_manager = pool id */ 144 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 145 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 146 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 147 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 148 149 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 150 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 151 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 152 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 153 154 /* Set Buffer or Ext Descriptor Type */ 155 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 156 BUF_OR_EXT_DESC_TYPE) |= 157 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 158 } 159 160 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 161 /** 162 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 163 * tlv_tag: Taf of the TLVs 164 * rx_tlv: the pointer to the TLVs 165 * @ppdu_info: pointer to ppdu_info 166 * 167 * Return: true if the tlv is handled, false if not 168 */ 169 static inline bool 170 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 171 struct hal_rx_ppdu_info *ppdu_info) 172 { 173 uint32_t value; 174 175 switch (tlv_tag) { 176 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 177 { 178 uint8_t *he_sig_a_mu_ul_info = 179 (uint8_t *)rx_tlv + 180 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 181 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 182 ppdu_info->rx_status.he_flags = 1; 183 184 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 185 FORMAT_INDICATION); 186 if (value == 0) { 187 ppdu_info->rx_status.he_data1 = 188 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 189 } else { 190 ppdu_info->rx_status.he_data1 = 191 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 192 } 193 194 /* data1 */ 195 ppdu_info->rx_status.he_data1 |= 196 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 197 QDF_MON_STATUS_HE_DL_UL_KNOWN | 198 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 199 200 /* data2 */ 201 ppdu_info->rx_status.he_data2 |= 202 QDF_MON_STATUS_TXOP_KNOWN; 203 204 /*data3*/ 205 value = HAL_RX_GET(he_sig_a_mu_ul_info, 206 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 207 ppdu_info->rx_status.he_data3 = value; 208 /* 1 for UL and 0 for DL */ 209 value = 1; 210 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 211 ppdu_info->rx_status.he_data3 |= value; 212 213 /*data4*/ 214 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 215 SPATIAL_REUSE); 216 ppdu_info->rx_status.he_data4 = value; 217 218 /*data5*/ 219 value = HAL_RX_GET(he_sig_a_mu_ul_info, 220 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 221 ppdu_info->rx_status.he_data5 = value; 222 ppdu_info->rx_status.bw = value; 223 224 /*data6*/ 225 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 226 TXOP_DURATION); 227 value = value << QDF_MON_STATUS_TXOP_SHIFT; 228 ppdu_info->rx_status.he_data6 |= value; 229 return true; 230 } 231 default: 232 return false; 233 } 234 } 235 #else 236 static inline bool 237 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 238 struct hal_rx_ppdu_info *ppdu_info) 239 { 240 return false; 241 } 242 #endif /* CONFIG_MCL && QCA_WIFI_QCA6290_11AX */ 243 244 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) 245 static inline void 246 hal_rx_handle_ofdma_info( 247 void *rx_tlv, 248 struct mon_rx_user_status *mon_rx_user_status) 249 { 250 mon_rx_user_status->ofdma_info_valid = 251 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, 252 OFDMA_INFO_VALID); 253 mon_rx_user_status->dl_ofdma_ru_start_index = 254 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, 255 DL_OFDMA_RU_START_INDEX); 256 mon_rx_user_status->dl_ofdma_ru_width = 257 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 258 DL_OFDMA_RU_WIDTH); 259 } 260 #else 261 static inline void 262 hal_rx_handle_ofdma_info(void *rx_tlv, 263 struct mon_rx_user_status *mon_rx_user_status) 264 { 265 } 266 #endif 267 268 /** 269 * hal_rx_status_get_tlv_info() - process receive info TLV 270 * @rx_tlv_hdr: pointer to TLV header 271 * @ppdu_info: pointer to ppdu_info 272 * 273 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 274 */ 275 static inline uint32_t 276 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 277 void *halsoc) 278 { 279 struct hal_soc *hal = (struct hal_soc *)halsoc; 280 uint32_t tlv_tag, user_id, tlv_len, value; 281 uint8_t group_id = 0; 282 uint8_t he_dcm = 0; 283 uint8_t he_stbc = 0; 284 uint16_t he_gi = 0; 285 uint16_t he_ltf = 0; 286 void *rx_tlv; 287 bool unhandled = false; 288 struct mon_rx_user_status *mon_rx_user_status; 289 struct hal_rx_ppdu_info *ppdu_info = 290 (struct hal_rx_ppdu_info *)ppduinfo; 291 292 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 293 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 294 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 295 296 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 297 298 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 299 rx_tlv, tlv_len); 300 301 switch (tlv_tag) { 302 303 case WIFIRX_PPDU_START_E: 304 ppdu_info->com_info.ppdu_id = 305 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 306 PHY_PPDU_ID); 307 /* channel number is set in PHY meta data */ 308 ppdu_info->rx_status.chan_num = 309 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 310 SW_PHY_META_DATA); 311 ppdu_info->com_info.ppdu_timestamp = 312 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 313 PPDU_START_TIMESTAMP); 314 ppdu_info->rx_status.ppdu_timestamp = 315 ppdu_info->com_info.ppdu_timestamp; 316 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 317 break; 318 319 case WIFIRX_PPDU_START_USER_INFO_E: 320 break; 321 322 case WIFIRX_PPDU_END_E: 323 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 324 "[%s][%d] ppdu_end_e len=%d", 325 __func__, __LINE__, tlv_len); 326 /* This is followed by sub-TLVs of PPDU_END */ 327 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 328 break; 329 330 case WIFIRXPCU_PPDU_END_INFO_E: 331 ppdu_info->rx_status.tsft = 332 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 333 WB_TIMESTAMP_UPPER_32); 334 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 335 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 336 WB_TIMESTAMP_LOWER_32); 337 ppdu_info->rx_status.duration = 338 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 339 RX_PPDU_DURATION); 340 break; 341 342 case WIFIRX_PPDU_END_USER_STATS_E: 343 { 344 unsigned long tid = 0; 345 uint16_t seq = 0; 346 347 ppdu_info->rx_status.ast_index = 348 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 349 AST_INDEX); 350 351 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 352 RECEIVED_QOS_DATA_TID_BITMAP); 353 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 354 355 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 356 ppdu_info->rx_status.tid = HAL_TID_INVALID; 357 358 ppdu_info->rx_status.tcp_msdu_count = 359 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 360 TCP_MSDU_COUNT) + 361 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 362 TCP_ACK_MSDU_COUNT); 363 ppdu_info->rx_status.udp_msdu_count = 364 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 365 UDP_MSDU_COUNT); 366 ppdu_info->rx_status.other_msdu_count = 367 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 368 OTHER_MSDU_COUNT); 369 370 ppdu_info->rx_status.frame_control_info_valid = 371 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 372 FRAME_CONTROL_INFO_VALID); 373 374 if (ppdu_info->rx_status.frame_control_info_valid) 375 ppdu_info->rx_status.frame_control = 376 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 377 FRAME_CONTROL_FIELD); 378 379 ppdu_info->rx_status.data_sequence_control_info_valid = 380 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 381 DATA_SEQUENCE_CONTROL_INFO_VALID); 382 383 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 384 FIRST_DATA_SEQ_CTRL); 385 if (ppdu_info->rx_status.data_sequence_control_info_valid) 386 ppdu_info->rx_status.first_data_seq_ctrl = seq; 387 388 ppdu_info->rx_status.preamble_type = 389 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 390 HT_CONTROL_FIELD_PKT_TYPE); 391 switch (ppdu_info->rx_status.preamble_type) { 392 case HAL_RX_PKT_TYPE_11N: 393 ppdu_info->rx_status.ht_flags = 1; 394 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 395 break; 396 case HAL_RX_PKT_TYPE_11AC: 397 ppdu_info->rx_status.vht_flags = 1; 398 break; 399 case HAL_RX_PKT_TYPE_11AX: 400 ppdu_info->rx_status.he_flags = 1; 401 break; 402 default: 403 break; 404 } 405 406 mon_rx_user_status = &ppdu_info->rx_user_status[user_id]; 407 408 mon_rx_user_status->mcs = 409 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, 410 MCS); 411 mon_rx_user_status->nss = 412 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, 413 NSS); 414 415 hal_rx_handle_ofdma_info(rx_tlv, mon_rx_user_status); 416 417 ppdu_info->com_info.mpdu_cnt_fcs_ok = 418 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 419 MPDU_CNT_FCS_OK); 420 ppdu_info->com_info.mpdu_cnt_fcs_err = 421 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 422 MPDU_CNT_FCS_ERR); 423 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 424 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 425 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 426 else 427 ppdu_info->rx_status.rs_flags &= 428 (~IEEE80211_AMPDU_FLAG); 429 break; 430 } 431 432 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 433 break; 434 435 case WIFIRX_PPDU_END_STATUS_DONE_E: 436 return HAL_TLV_STATUS_PPDU_DONE; 437 438 case WIFIDUMMY_E: 439 return HAL_TLV_STATUS_BUF_DONE; 440 441 case WIFIPHYRX_HT_SIG_E: 442 { 443 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 444 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 445 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 446 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 447 FEC_CODING); 448 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 449 1 : 0; 450 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 451 HT_SIG_INFO_0, MCS); 452 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 453 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 454 HT_SIG_INFO_0, CBW); 455 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 456 HT_SIG_INFO_1, SHORT_GI); 457 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 458 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 459 HT_SIG_SU_NSS_SHIFT) + 1; 460 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 461 break; 462 } 463 464 case WIFIPHYRX_L_SIG_B_E: 465 { 466 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 467 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 468 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 469 470 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 471 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 472 switch (value) { 473 case 1: 474 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 475 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 476 break; 477 case 2: 478 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 479 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 480 break; 481 case 3: 482 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 483 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 484 break; 485 case 4: 486 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 487 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 488 break; 489 case 5: 490 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 491 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 492 break; 493 case 6: 494 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 495 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 496 break; 497 case 7: 498 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 499 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 500 break; 501 default: 502 break; 503 } 504 ppdu_info->rx_status.cck_flag = 1; 505 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 506 break; 507 } 508 509 case WIFIPHYRX_L_SIG_A_E: 510 { 511 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 512 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 513 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 514 515 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 516 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 517 switch (value) { 518 case 8: 519 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 520 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 521 break; 522 case 9: 523 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 524 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 525 break; 526 case 10: 527 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 528 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 529 break; 530 case 11: 531 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 532 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 533 break; 534 case 12: 535 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 536 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 537 break; 538 case 13: 539 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 540 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 541 break; 542 case 14: 543 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 544 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 545 break; 546 case 15: 547 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 548 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 549 break; 550 default: 551 break; 552 } 553 ppdu_info->rx_status.ofdm_flag = 1; 554 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 555 break; 556 } 557 558 case WIFIPHYRX_VHT_SIG_A_E: 559 { 560 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 561 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 562 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 563 564 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 565 SU_MU_CODING); 566 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 567 1 : 0; 568 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 569 ppdu_info->rx_status.vht_flag_values5 = group_id; 570 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 571 VHT_SIG_A_INFO_1, MCS); 572 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 573 VHT_SIG_A_INFO_1, GI_SETTING); 574 575 switch (hal->target_type) { 576 case TARGET_TYPE_QCA8074: 577 case TARGET_TYPE_QCA8074V2: 578 case TARGET_TYPE_QCA6018: 579 ppdu_info->rx_status.is_stbc = 580 HAL_RX_GET(vht_sig_a_info, 581 VHT_SIG_A_INFO_0, STBC); 582 value = HAL_RX_GET(vht_sig_a_info, 583 VHT_SIG_A_INFO_0, N_STS); 584 if (ppdu_info->rx_status.is_stbc && (value > 0)) 585 value = ((value + 1) >> 1) - 1; 586 ppdu_info->rx_status.nss = 587 ((value & VHT_SIG_SU_NSS_MASK) + 1); 588 589 break; 590 case TARGET_TYPE_QCA6290: 591 #if !defined(QCA_WIFI_QCA6290_11AX) 592 ppdu_info->rx_status.is_stbc = 593 HAL_RX_GET(vht_sig_a_info, 594 VHT_SIG_A_INFO_0, STBC); 595 value = HAL_RX_GET(vht_sig_a_info, 596 VHT_SIG_A_INFO_0, N_STS); 597 if (ppdu_info->rx_status.is_stbc && (value > 0)) 598 value = ((value + 1) >> 1) - 1; 599 ppdu_info->rx_status.nss = 600 ((value & VHT_SIG_SU_NSS_MASK) + 1); 601 #else 602 ppdu_info->rx_status.nss = 0; 603 #endif 604 break; 605 #ifdef QCA_WIFI_QCA6390 606 case TARGET_TYPE_QCA6390: 607 ppdu_info->rx_status.nss = 0; 608 break; 609 #endif 610 default: 611 break; 612 } 613 ppdu_info->rx_status.vht_flag_values3[0] = 614 (((ppdu_info->rx_status.mcs) << 4) 615 | ppdu_info->rx_status.nss); 616 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 617 VHT_SIG_A_INFO_0, BANDWIDTH); 618 ppdu_info->rx_status.vht_flag_values2 = 619 ppdu_info->rx_status.bw; 620 ppdu_info->rx_status.vht_flag_values4 = 621 HAL_RX_GET(vht_sig_a_info, 622 VHT_SIG_A_INFO_1, SU_MU_CODING); 623 624 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 625 VHT_SIG_A_INFO_1, BEAMFORMED); 626 if (group_id == 0 || group_id == 63) 627 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 628 else 629 ppdu_info->rx_status.reception_type = 630 HAL_RX_TYPE_MU_MIMO; 631 632 break; 633 } 634 case WIFIPHYRX_HE_SIG_A_SU_E: 635 { 636 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 637 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 638 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 639 ppdu_info->rx_status.he_flags = 1; 640 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 641 FORMAT_INDICATION); 642 if (value == 0) { 643 ppdu_info->rx_status.he_data1 = 644 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 645 } else { 646 ppdu_info->rx_status.he_data1 = 647 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 648 } 649 650 /* data1 */ 651 ppdu_info->rx_status.he_data1 |= 652 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 653 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 654 QDF_MON_STATUS_HE_DL_UL_KNOWN | 655 QDF_MON_STATUS_HE_MCS_KNOWN | 656 QDF_MON_STATUS_HE_DCM_KNOWN | 657 QDF_MON_STATUS_HE_CODING_KNOWN | 658 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 659 QDF_MON_STATUS_HE_STBC_KNOWN | 660 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 661 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 662 663 /* data2 */ 664 ppdu_info->rx_status.he_data2 = 665 QDF_MON_STATUS_HE_GI_KNOWN; 666 ppdu_info->rx_status.he_data2 |= 667 QDF_MON_STATUS_TXBF_KNOWN | 668 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 669 QDF_MON_STATUS_TXOP_KNOWN | 670 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 671 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 672 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 673 674 /* data3 */ 675 value = HAL_RX_GET(he_sig_a_su_info, 676 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 677 ppdu_info->rx_status.he_data3 = value; 678 value = HAL_RX_GET(he_sig_a_su_info, 679 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 680 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 681 ppdu_info->rx_status.he_data3 |= value; 682 value = HAL_RX_GET(he_sig_a_su_info, 683 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 684 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 685 ppdu_info->rx_status.he_data3 |= value; 686 687 value = HAL_RX_GET(he_sig_a_su_info, 688 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 689 ppdu_info->rx_status.mcs = value; 690 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 691 ppdu_info->rx_status.he_data3 |= value; 692 693 value = HAL_RX_GET(he_sig_a_su_info, 694 HE_SIG_A_SU_INFO_0, DCM); 695 he_dcm = value; 696 value = value << QDF_MON_STATUS_DCM_SHIFT; 697 ppdu_info->rx_status.he_data3 |= value; 698 value = HAL_RX_GET(he_sig_a_su_info, 699 HE_SIG_A_SU_INFO_1, CODING); 700 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 701 1 : 0; 702 value = value << QDF_MON_STATUS_CODING_SHIFT; 703 ppdu_info->rx_status.he_data3 |= value; 704 value = HAL_RX_GET(he_sig_a_su_info, 705 HE_SIG_A_SU_INFO_1, 706 LDPC_EXTRA_SYMBOL); 707 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 708 ppdu_info->rx_status.he_data3 |= value; 709 value = HAL_RX_GET(he_sig_a_su_info, 710 HE_SIG_A_SU_INFO_1, STBC); 711 he_stbc = value; 712 value = value << QDF_MON_STATUS_STBC_SHIFT; 713 ppdu_info->rx_status.he_data3 |= value; 714 715 /* data4 */ 716 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 717 SPATIAL_REUSE); 718 ppdu_info->rx_status.he_data4 = value; 719 720 /* data5 */ 721 value = HAL_RX_GET(he_sig_a_su_info, 722 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 723 ppdu_info->rx_status.he_data5 = value; 724 ppdu_info->rx_status.bw = value; 725 value = HAL_RX_GET(he_sig_a_su_info, 726 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 727 switch (value) { 728 case 0: 729 he_gi = HE_GI_0_8; 730 he_ltf = HE_LTF_1_X; 731 break; 732 case 1: 733 he_gi = HE_GI_0_8; 734 he_ltf = HE_LTF_2_X; 735 break; 736 case 2: 737 he_gi = HE_GI_1_6; 738 he_ltf = HE_LTF_2_X; 739 break; 740 case 3: 741 if (he_dcm && he_stbc) { 742 he_gi = HE_GI_0_8; 743 he_ltf = HE_LTF_4_X; 744 } else { 745 he_gi = HE_GI_3_2; 746 he_ltf = HE_LTF_4_X; 747 } 748 break; 749 } 750 ppdu_info->rx_status.sgi = he_gi; 751 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 752 ppdu_info->rx_status.he_data5 |= value; 753 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 754 ppdu_info->rx_status.ltf_size = he_ltf; 755 ppdu_info->rx_status.he_data5 |= value; 756 757 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 758 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 759 ppdu_info->rx_status.he_data5 |= value; 760 761 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 762 PACKET_EXTENSION_A_FACTOR); 763 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 764 ppdu_info->rx_status.he_data5 |= value; 765 766 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 767 value = value << QDF_MON_STATUS_TXBF_SHIFT; 768 ppdu_info->rx_status.he_data5 |= value; 769 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 770 PACKET_EXTENSION_PE_DISAMBIGUITY); 771 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 772 ppdu_info->rx_status.he_data5 |= value; 773 774 /* data6 */ 775 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 776 value++; 777 ppdu_info->rx_status.nss = value; 778 ppdu_info->rx_status.he_data6 = value; 779 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 780 DOPPLER_INDICATION); 781 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 782 ppdu_info->rx_status.he_data6 |= value; 783 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 784 TXOP_DURATION); 785 value = value << QDF_MON_STATUS_TXOP_SHIFT; 786 ppdu_info->rx_status.he_data6 |= value; 787 788 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 789 HE_SIG_A_SU_INFO_1, TXBF); 790 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 791 break; 792 } 793 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 794 { 795 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 796 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 797 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 798 799 ppdu_info->rx_status.he_mu_flags = 1; 800 801 /* HE Flags */ 802 /*data1*/ 803 ppdu_info->rx_status.he_data1 = 804 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 805 ppdu_info->rx_status.he_data1 |= 806 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 807 QDF_MON_STATUS_HE_DL_UL_KNOWN | 808 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 809 QDF_MON_STATUS_HE_STBC_KNOWN | 810 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 811 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 812 813 /* data2 */ 814 ppdu_info->rx_status.he_data2 = 815 QDF_MON_STATUS_HE_GI_KNOWN; 816 ppdu_info->rx_status.he_data2 |= 817 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 818 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 819 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 820 QDF_MON_STATUS_TXOP_KNOWN | 821 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 822 823 /*data3*/ 824 value = HAL_RX_GET(he_sig_a_mu_dl_info, 825 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 826 ppdu_info->rx_status.he_data3 = value; 827 828 value = HAL_RX_GET(he_sig_a_mu_dl_info, 829 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 830 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 831 ppdu_info->rx_status.he_data3 |= value; 832 833 value = HAL_RX_GET(he_sig_a_mu_dl_info, 834 HE_SIG_A_MU_DL_INFO_1, 835 LDPC_EXTRA_SYMBOL); 836 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 837 ppdu_info->rx_status.he_data3 |= value; 838 839 value = HAL_RX_GET(he_sig_a_mu_dl_info, 840 HE_SIG_A_MU_DL_INFO_1, STBC); 841 he_stbc = value; 842 value = value << QDF_MON_STATUS_STBC_SHIFT; 843 ppdu_info->rx_status.he_data3 |= value; 844 845 /*data4*/ 846 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 847 SPATIAL_REUSE); 848 ppdu_info->rx_status.he_data4 = value; 849 850 /*data5*/ 851 value = HAL_RX_GET(he_sig_a_mu_dl_info, 852 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 853 ppdu_info->rx_status.he_data5 = value; 854 ppdu_info->rx_status.bw = value; 855 856 value = HAL_RX_GET(he_sig_a_mu_dl_info, 857 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 858 switch (value) { 859 case 0: 860 he_gi = HE_GI_0_8; 861 he_ltf = HE_LTF_4_X; 862 break; 863 case 1: 864 he_gi = HE_GI_0_8; 865 he_ltf = HE_LTF_2_X; 866 break; 867 case 2: 868 he_gi = HE_GI_1_6; 869 he_ltf = HE_LTF_2_X; 870 break; 871 case 3: 872 he_gi = HE_GI_3_2; 873 he_ltf = HE_LTF_4_X; 874 break; 875 } 876 ppdu_info->rx_status.sgi = he_gi; 877 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 878 ppdu_info->rx_status.he_data5 |= value; 879 880 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 881 ppdu_info->rx_status.he_data5 |= value; 882 883 value = HAL_RX_GET(he_sig_a_mu_dl_info, 884 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 885 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 886 ppdu_info->rx_status.he_data5 |= value; 887 888 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 889 PACKET_EXTENSION_A_FACTOR); 890 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 891 ppdu_info->rx_status.he_data5 |= value; 892 893 894 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 895 PACKET_EXTENSION_PE_DISAMBIGUITY); 896 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 897 ppdu_info->rx_status.he_data5 |= value; 898 899 /*data6*/ 900 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 901 DOPPLER_INDICATION); 902 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 903 ppdu_info->rx_status.he_data6 |= value; 904 905 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 906 TXOP_DURATION); 907 value = value << QDF_MON_STATUS_TXOP_SHIFT; 908 ppdu_info->rx_status.he_data6 |= value; 909 910 /* HE-MU Flags */ 911 /* HE-MU-flags1 */ 912 ppdu_info->rx_status.he_flags1 = 913 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 914 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 915 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 916 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 917 QDF_MON_STATUS_RU_0_KNOWN; 918 919 value = HAL_RX_GET(he_sig_a_mu_dl_info, 920 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 921 ppdu_info->rx_status.he_flags1 |= value; 922 value = HAL_RX_GET(he_sig_a_mu_dl_info, 923 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 924 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 925 ppdu_info->rx_status.he_flags1 |= value; 926 927 /* HE-MU-flags2 */ 928 ppdu_info->rx_status.he_flags2 = 929 QDF_MON_STATUS_BW_KNOWN; 930 931 value = HAL_RX_GET(he_sig_a_mu_dl_info, 932 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 933 ppdu_info->rx_status.he_flags2 |= value; 934 value = HAL_RX_GET(he_sig_a_mu_dl_info, 935 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 936 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 937 ppdu_info->rx_status.he_flags2 |= value; 938 value = HAL_RX_GET(he_sig_a_mu_dl_info, 939 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 940 value = value - 1; 941 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 942 ppdu_info->rx_status.he_flags2 |= value; 943 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 944 break; 945 } 946 case WIFIPHYRX_HE_SIG_B1_MU_E: 947 { 948 949 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 950 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 951 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 952 953 ppdu_info->rx_status.he_sig_b_common_known |= 954 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 955 /* TODO: Check on the availability of other fields in 956 * sig_b_common 957 */ 958 959 value = HAL_RX_GET(he_sig_b1_mu_info, 960 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 961 ppdu_info->rx_status.he_RU[0] = value; 962 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 963 break; 964 } 965 case WIFIPHYRX_HE_SIG_B2_MU_E: 966 { 967 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 968 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 969 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 970 /* 971 * Not all "HE" fields can be updated from 972 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 973 * to populate rest of the "HE" fields for MU scenarios. 974 */ 975 976 /* HE-data1 */ 977 ppdu_info->rx_status.he_data1 |= 978 QDF_MON_STATUS_HE_MCS_KNOWN | 979 QDF_MON_STATUS_HE_CODING_KNOWN; 980 981 /* HE-data2 */ 982 983 /* HE-data3 */ 984 value = HAL_RX_GET(he_sig_b2_mu_info, 985 HE_SIG_B2_MU_INFO_0, STA_MCS); 986 ppdu_info->rx_status.mcs = value; 987 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 988 ppdu_info->rx_status.he_data3 |= value; 989 990 991 value = HAL_RX_GET(he_sig_b2_mu_info, 992 HE_SIG_B2_MU_INFO_0, STA_CODING); 993 value = value << QDF_MON_STATUS_CODING_SHIFT; 994 ppdu_info->rx_status.he_data3 |= value; 995 996 /* HE-data4 */ 997 value = HAL_RX_GET(he_sig_b2_mu_info, 998 HE_SIG_B2_MU_INFO_0, STA_ID); 999 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1000 ppdu_info->rx_status.he_data4 |= value; 1001 1002 /* HE-data5 */ 1003 1004 /* HE-data6 */ 1005 value = HAL_RX_GET(he_sig_b2_mu_info, 1006 HE_SIG_B2_MU_INFO_0, NSTS); 1007 /* value n indicates n+1 spatial streams */ 1008 value++; 1009 ppdu_info->rx_status.nss = value; 1010 ppdu_info->rx_status.he_data6 |= value; 1011 1012 break; 1013 1014 } 1015 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1016 { 1017 uint8_t *he_sig_b2_ofdma_info = 1018 (uint8_t *)rx_tlv + 1019 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1020 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1021 1022 /* 1023 * Not all "HE" fields can be updated from 1024 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1025 * to populate rest of "HE" fields for MU OFDMA scenarios. 1026 */ 1027 1028 /* HE-data1 */ 1029 ppdu_info->rx_status.he_data1 |= 1030 QDF_MON_STATUS_HE_MCS_KNOWN | 1031 QDF_MON_STATUS_HE_DCM_KNOWN | 1032 QDF_MON_STATUS_HE_CODING_KNOWN; 1033 1034 /* HE-data2 */ 1035 ppdu_info->rx_status.he_data2 |= 1036 QDF_MON_STATUS_TXBF_KNOWN; 1037 1038 /* HE-data3 */ 1039 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1040 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1041 ppdu_info->rx_status.mcs = value; 1042 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1043 ppdu_info->rx_status.he_data3 |= value; 1044 1045 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1046 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1047 he_dcm = value; 1048 value = value << QDF_MON_STATUS_DCM_SHIFT; 1049 ppdu_info->rx_status.he_data3 |= value; 1050 1051 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1052 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1053 value = value << QDF_MON_STATUS_CODING_SHIFT; 1054 ppdu_info->rx_status.he_data3 |= value; 1055 1056 /* HE-data4 */ 1057 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1058 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1059 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1060 ppdu_info->rx_status.he_data4 |= value; 1061 1062 /* HE-data5 */ 1063 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1064 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1065 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1066 ppdu_info->rx_status.he_data5 |= value; 1067 1068 /* HE-data6 */ 1069 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1070 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1071 /* value n indicates n+1 spatial streams */ 1072 value++; 1073 ppdu_info->rx_status.nss = value; 1074 ppdu_info->rx_status.he_data6 |= value; 1075 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1076 break; 1077 } 1078 case WIFIPHYRX_RSSI_LEGACY_E: 1079 { 1080 uint8_t reception_type; 1081 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1082 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1083 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1084 1085 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1086 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1087 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1088 ppdu_info->rx_status.he_re = 0; 1089 1090 reception_type = HAL_RX_GET(rx_tlv, 1091 PHYRX_RSSI_LEGACY_0, 1092 RECEPTION_TYPE); 1093 switch (reception_type) { 1094 case QDF_RECEPTION_TYPE_ULOFMDA: 1095 ppdu_info->rx_status.ulofdma_flag = 1; 1096 ppdu_info->rx_status.he_data1 = 1097 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1098 break; 1099 case QDF_RECEPTION_TYPE_ULMIMO: 1100 ppdu_info->rx_status.he_data1 = 1101 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1102 break; 1103 default: 1104 break; 1105 } 1106 value = HAL_RX_GET(rssi_info_tlv, 1107 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1108 ppdu_info->rx_status.rssi[0] = value; 1109 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1110 "RSSI_PRI20_CHAIN0: %d\n", value); 1111 1112 value = HAL_RX_GET(rssi_info_tlv, 1113 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1114 ppdu_info->rx_status.rssi[1] = value; 1115 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1116 "RSSI_PRI20_CHAIN1: %d\n", value); 1117 1118 value = HAL_RX_GET(rssi_info_tlv, 1119 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1120 ppdu_info->rx_status.rssi[2] = value; 1121 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1122 "RSSI_PRI20_CHAIN2: %d\n", value); 1123 1124 value = HAL_RX_GET(rssi_info_tlv, 1125 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1126 ppdu_info->rx_status.rssi[3] = value; 1127 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1128 "RSSI_PRI20_CHAIN3: %d\n", value); 1129 1130 value = HAL_RX_GET(rssi_info_tlv, 1131 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1132 ppdu_info->rx_status.rssi[4] = value; 1133 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1134 "RSSI_PRI20_CHAIN4: %d\n", value); 1135 1136 value = HAL_RX_GET(rssi_info_tlv, 1137 RECEIVE_RSSI_INFO_10, RSSI_PRI20_CHAIN5); 1138 ppdu_info->rx_status.rssi[5] = value; 1139 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1140 "RSSI_PRI20_CHAIN5: %d\n", value); 1141 1142 value = HAL_RX_GET(rssi_info_tlv, 1143 RECEIVE_RSSI_INFO_12, RSSI_PRI20_CHAIN6); 1144 ppdu_info->rx_status.rssi[6] = value; 1145 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1146 "RSSI_PRI20_CHAIN1: %d\n", value); 1147 1148 value = HAL_RX_GET(rssi_info_tlv, 1149 RECEIVE_RSSI_INFO_14, RSSI_PRI20_CHAIN7); 1150 ppdu_info->rx_status.rssi[7] = value; 1151 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1152 "RSSI_PRI20_CHAIN7: %d\n", value); 1153 break; 1154 } 1155 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1156 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1157 ppdu_info); 1158 break; 1159 case WIFIRX_HEADER_E: 1160 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1161 ppdu_info->msdu_info.payload_len = tlv_len; 1162 ppdu_info->user_id = user_id; 1163 ppdu_info->hdr_len = tlv_len; 1164 ppdu_info->data = rx_tlv; 1165 ppdu_info->data += 4; 1166 return HAL_TLV_STATUS_HEADER; 1167 case WIFIRX_MPDU_START_E: 1168 { 1169 uint8_t *rx_mpdu_start = 1170 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1171 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1172 uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1173 PHY_PPDU_ID); 1174 uint8_t filter_category = 0; 1175 1176 ppdu_info->nac_info.fc_valid = 1177 HAL_RX_GET(rx_mpdu_start, 1178 RX_MPDU_INFO_2, 1179 MPDU_FRAME_CONTROL_VALID); 1180 1181 ppdu_info->nac_info.to_ds_flag = 1182 HAL_RX_GET(rx_mpdu_start, 1183 RX_MPDU_INFO_2, 1184 TO_DS); 1185 1186 ppdu_info->nac_info.mac_addr2_valid = 1187 HAL_RX_GET(rx_mpdu_start, 1188 RX_MPDU_INFO_2, 1189 MAC_ADDR_AD2_VALID); 1190 1191 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1192 HAL_RX_GET(rx_mpdu_start, 1193 RX_MPDU_INFO_16, 1194 MAC_ADDR_AD2_15_0); 1195 1196 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1197 HAL_RX_GET(rx_mpdu_start, 1198 RX_MPDU_INFO_17, 1199 MAC_ADDR_AD2_47_16); 1200 1201 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1202 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1203 ppdu_info->rx_status.ppdu_len = 1204 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1205 MPDU_LENGTH); 1206 } else { 1207 ppdu_info->rx_status.ppdu_len += 1208 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1209 MPDU_LENGTH); 1210 } 1211 1212 filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1213 RXPCU_MPDU_FILTER_IN_CATEGORY); 1214 1215 if (filter_category == 0) 1216 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1217 else if (filter_category == 1) 1218 ppdu_info->rx_status.monitor_direct_used = 1; 1219 1220 break; 1221 } 1222 case WIFIRX_MPDU_END_E: 1223 ppdu_info->user_id = user_id; 1224 ppdu_info->fcs_err = 1225 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1226 FCS_ERR); 1227 return HAL_TLV_STATUS_MPDU_END; 1228 case 0: 1229 return HAL_TLV_STATUS_PPDU_DONE; 1230 1231 default: 1232 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1233 unhandled = false; 1234 else 1235 unhandled = true; 1236 break; 1237 } 1238 1239 if (!unhandled) 1240 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1241 "%s TLV type: %d, TLV len:%d %s", 1242 __func__, tlv_tag, tlv_len, 1243 unhandled == true ? "unhandled" : ""); 1244 1245 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1246 rx_tlv, tlv_len); 1247 1248 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1249 } 1250 /** 1251 * hal_reo_status_get_header_generic - Process reo desc info 1252 * @d - Pointer to reo descriptior 1253 * @b - tlv type info 1254 * @h1 - Pointer to hal_reo_status_header where info to be stored 1255 * 1256 * Return - none. 1257 * 1258 */ 1259 static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) 1260 { 1261 1262 uint32_t val1 = 0; 1263 struct hal_reo_status_header *h = 1264 (struct hal_reo_status_header *)h1; 1265 1266 switch (b) { 1267 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1268 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1269 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1270 break; 1271 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1272 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1273 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1274 break; 1275 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1276 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1277 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1278 break; 1279 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1280 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1281 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1282 break; 1283 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1284 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1285 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1286 break; 1287 case HAL_REO_DESC_THRES_STATUS_TLV: 1288 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1289 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1290 break; 1291 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1292 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1293 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1294 break; 1295 default: 1296 pr_err("ERROR: Unknown tlv\n"); 1297 break; 1298 } 1299 h->cmd_num = 1300 HAL_GET_FIELD( 1301 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1302 val1); 1303 h->exec_time = 1304 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1305 CMD_EXECUTION_TIME, val1); 1306 h->status = 1307 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1308 REO_CMD_EXECUTION_STATUS, val1); 1309 switch (b) { 1310 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1311 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1312 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1313 break; 1314 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1315 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1316 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1317 break; 1318 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1319 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1320 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1321 break; 1322 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1323 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1324 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1325 break; 1326 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1327 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1328 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1329 break; 1330 case HAL_REO_DESC_THRES_STATUS_TLV: 1331 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1332 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1333 break; 1334 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1335 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1336 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1337 break; 1338 default: 1339 pr_err("ERROR: Unknown tlv\n"); 1340 break; 1341 } 1342 h->tstamp = 1343 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1344 } 1345 1346 /** 1347 * hal_reo_setup - Initialize HW REO block 1348 * 1349 * @hal_soc: Opaque HAL SOC handle 1350 * @reo_params: parameters needed by HAL for REO config 1351 */ 1352 static void hal_reo_setup_generic(void *hal_soc, 1353 void *reoparams) 1354 { 1355 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1356 uint32_t reg_val; 1357 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1358 1359 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1360 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1361 1362 reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | 1363 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | 1364 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); 1365 1366 reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, 1367 FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | 1368 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | 1369 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); 1370 1371 HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1372 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1373 1374 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1375 1376 /* TODO: Setup destination ring mapping if enabled */ 1377 1378 /* TODO: Error destination ring setting is left to default. 1379 * Default setting is to send all errors to release ring. 1380 */ 1381 1382 HAL_REG_WRITE(soc, 1383 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1384 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1385 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1386 1387 HAL_REG_WRITE(soc, 1388 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1389 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1390 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1391 1392 HAL_REG_WRITE(soc, 1393 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1394 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1395 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1396 1397 HAL_REG_WRITE(soc, 1398 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1399 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1400 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1401 1402 /* 1403 * When hash based routing is enabled, routing of the rx packet 1404 * is done based on the following value: 1 _ _ _ _ The last 4 1405 * bits are based on hash[3:0]. This means the possible values 1406 * are 0x10 to 0x1f. This value is used to look-up the 1407 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1408 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1409 * registers need to be configured to set-up the 16 entries to 1410 * map the hash values to a ring number. There are 3 bits per 1411 * hash entry – which are mapped as follows: 1412 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1413 * 7: NOT_USED. 1414 */ 1415 if (reo_params->rx_hash_enabled) { 1416 HAL_REG_WRITE(soc, 1417 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1418 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1419 reo_params->remap1); 1420 1421 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1422 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), 1423 HAL_REG_READ(soc, 1424 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1425 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1426 1427 HAL_REG_WRITE(soc, 1428 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1429 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1430 reo_params->remap2); 1431 1432 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1433 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), 1434 HAL_REG_READ(soc, 1435 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1436 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1437 } 1438 1439 1440 /* TODO: Check if the following registers shoould be setup by host: 1441 * AGING_CONTROL 1442 * HIGH_MEMORY_THRESHOLD 1443 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1444 * GLOBAL_LINK_DESC_COUNT_CTRL 1445 */ 1446 } 1447 1448 /** 1449 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1450 * @hal_soc: Opaque HAL SOC handle 1451 * @hal_ring: Source ring pointer 1452 * @headp: Head Pointer 1453 * @tailp: Tail Pointer 1454 * @ring: Ring type 1455 * 1456 * Return: Update tail pointer and head pointer in arguments. 1457 */ 1458 static inline 1459 void hal_get_hw_hptp_generic(struct hal_soc *soc, void *hal_ring, 1460 uint32_t *headp, uint32_t *tailp, 1461 uint8_t ring) 1462 { 1463 struct hal_srng *srng = (struct hal_srng *)hal_ring; 1464 struct hal_hw_srng_config *ring_config; 1465 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1466 1467 if (!soc || !srng) { 1468 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1469 "%s: Context is Null", __func__); 1470 return; 1471 } 1472 1473 ring_config = HAL_SRNG_CONFIG(soc, ring_type); 1474 if (!ring_config->lmac_ring) { 1475 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1476 *headp = 1477 (SRNG_SRC_REG_READ(srng, HP)) / srng->entry_size; 1478 *tailp = 1479 (SRNG_SRC_REG_READ(srng, TP)) / srng->entry_size; 1480 } else { 1481 *headp = 1482 (SRNG_DST_REG_READ(srng, HP)) / srng->entry_size; 1483 *tailp = 1484 (SRNG_DST_REG_READ(srng, TP)) / srng->entry_size; 1485 } 1486 } 1487 } 1488 1489 /** 1490 * hal_srng_src_hw_init - Private function to initialize SRNG 1491 * source ring HW 1492 * @hal_soc: HAL SOC handle 1493 * @srng: SRNG ring pointer 1494 */ 1495 static inline void hal_srng_src_hw_init_generic(void *halsoc, 1496 struct hal_srng *srng) 1497 { 1498 struct hal_soc *hal = (struct hal_soc *)halsoc; 1499 uint32_t reg_val = 0; 1500 uint64_t tp_addr = 0; 1501 1502 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1503 1504 if (srng->flags & HAL_SRNG_MSI_INTR) { 1505 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1506 srng->msi_addr & 0xffffffff); 1507 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1508 (uint64_t)(srng->msi_addr) >> 32) | 1509 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1510 MSI1_ENABLE), 1); 1511 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1512 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1513 } 1514 1515 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1516 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1517 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1518 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1519 srng->entry_size * srng->num_entries); 1520 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1521 1522 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1523 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1524 1525 /** 1526 * Interrupt setup: 1527 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1528 * if level mode is required 1529 */ 1530 reg_val = 0; 1531 1532 /* 1533 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1534 * programmed in terms of 1us resolution instead of 8us resolution as 1535 * given in MLD. 1536 */ 1537 if (srng->intr_timer_thres_us) { 1538 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1539 INTERRUPT_TIMER_THRESHOLD), 1540 srng->intr_timer_thres_us); 1541 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1542 } 1543 1544 if (srng->intr_batch_cntr_thres_entries) { 1545 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1546 BATCH_COUNTER_THRESHOLD), 1547 srng->intr_batch_cntr_thres_entries * 1548 srng->entry_size); 1549 } 1550 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1551 1552 reg_val = 0; 1553 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1554 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1555 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1556 } 1557 1558 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1559 1560 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1561 * remain 0 to avoid some WBM stability issues. Remote head/tail 1562 * pointers are not required since this ring is completely managed 1563 * by WBM HW 1564 */ 1565 reg_val = 0; 1566 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1567 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1568 ((unsigned long)(srng->u.src_ring.tp_addr) - 1569 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1570 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1571 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1572 } else { 1573 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1574 } 1575 1576 /* Initilaize head and tail pointers to indicate ring is empty */ 1577 SRNG_SRC_REG_WRITE(srng, HP, 0); 1578 SRNG_SRC_REG_WRITE(srng, TP, 0); 1579 *(srng->u.src_ring.tp_addr) = 0; 1580 1581 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1582 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1583 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1584 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1585 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1586 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1587 1588 /* Loop count is not used for SRC rings */ 1589 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1590 1591 /* 1592 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1593 * todo: update fw_api and replace with above line 1594 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1595 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1596 */ 1597 reg_val |= 0x40; 1598 1599 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1600 } 1601 1602 /** 1603 * hal_srng_dst_hw_init - Private function to initialize SRNG 1604 * destination ring HW 1605 * @hal_soc: HAL SOC handle 1606 * @srng: SRNG ring pointer 1607 */ 1608 static inline void hal_srng_dst_hw_init_generic(void *halsoc, 1609 struct hal_srng *srng) 1610 { 1611 struct hal_soc *hal = (struct hal_soc *)halsoc; 1612 uint32_t reg_val = 0; 1613 uint64_t hp_addr = 0; 1614 1615 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1616 1617 if (srng->flags & HAL_SRNG_MSI_INTR) { 1618 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1619 srng->msi_addr & 0xffffffff); 1620 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1621 (uint64_t)(srng->msi_addr) >> 32) | 1622 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1623 MSI1_ENABLE), 1); 1624 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1625 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1626 } 1627 1628 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1629 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1630 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1631 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1632 srng->entry_size * srng->num_entries); 1633 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1634 1635 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1636 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1637 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1638 1639 1640 /** 1641 * Interrupt setup: 1642 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1643 * if level mode is required 1644 */ 1645 reg_val = 0; 1646 if (srng->intr_timer_thres_us) { 1647 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1648 INTERRUPT_TIMER_THRESHOLD), 1649 srng->intr_timer_thres_us >> 3); 1650 } 1651 1652 if (srng->intr_batch_cntr_thres_entries) { 1653 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1654 BATCH_COUNTER_THRESHOLD), 1655 srng->intr_batch_cntr_thres_entries * 1656 srng->entry_size); 1657 } 1658 1659 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1660 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1661 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1662 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1663 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1664 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1665 1666 /* Initilaize head and tail pointers to indicate ring is empty */ 1667 SRNG_DST_REG_WRITE(srng, HP, 0); 1668 SRNG_DST_REG_WRITE(srng, TP, 0); 1669 *(srng->u.dst_ring.hp_addr) = 0; 1670 1671 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1672 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1673 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1674 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1675 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1676 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1677 1678 /* 1679 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1680 * todo: update fw_api and replace with above line 1681 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1682 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1683 */ 1684 reg_val |= 0x40; 1685 1686 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1687 1688 } 1689 1690 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1691 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1692 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1693 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1694 1695 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1696 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1697 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1698 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1699 1700 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1701 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1702 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1703 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1704 1705 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1706 (((*(((uint32_t *) wbm_desc) + \ 1707 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1708 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1709 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1710 1711 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1712 (((*(((uint32_t *) wbm_desc) + \ 1713 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1714 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1715 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1716 1717 /** 1718 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1719 * save it to hal_wbm_err_desc_info structure passed by caller 1720 * @wbm_desc: wbm ring descriptor 1721 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1722 * Return: void 1723 */ 1724 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1725 void *wbm_er_info1) 1726 { 1727 struct hal_wbm_err_desc_info *wbm_er_info = 1728 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1729 1730 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1731 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1732 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1733 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1734 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1735 } 1736 1737 /** 1738 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1739 * @hal_desc: completion ring descriptor pointer 1740 * 1741 * This function will return the type of pointer - buffer or descriptor 1742 * 1743 * Return: buffer type 1744 */ 1745 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1746 { 1747 uint32_t comp_desc = 1748 *(uint32_t *) (((uint8_t *) hal_desc) + 1749 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1750 1751 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1752 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1753 } 1754 1755 /** 1756 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1757 * human readable format. 1758 * @mpdu_start: pointer the rx_attention TLV in pkt. 1759 * @dbg_level: log level. 1760 * 1761 * Return: void 1762 */ 1763 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1764 uint8_t dbg_level) 1765 { 1766 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1767 struct rx_mpdu_info *mpdu_info = 1768 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1769 1770 hal_verbose_debug( 1771 "rx_mpdu_start tlv (1/5) - " 1772 "rxpcu_mpdu_filter_in_category: %x " 1773 "sw_frame_group_id: %x " 1774 "ndp_frame: %x " 1775 "phy_err: %x " 1776 "phy_err_during_mpdu_header: %x " 1777 "protocol_version_err: %x " 1778 "ast_based_lookup_valid: %x " 1779 "phy_ppdu_id: %x " 1780 "ast_index: %x " 1781 "sw_peer_id: %x " 1782 "mpdu_frame_control_valid: %x " 1783 "mpdu_duration_valid: %x " 1784 "mac_addr_ad1_valid: %x " 1785 "mac_addr_ad2_valid: %x " 1786 "mac_addr_ad3_valid: %x " 1787 "mac_addr_ad4_valid: %x " 1788 "mpdu_sequence_control_valid: %x " 1789 "mpdu_qos_control_valid: %x " 1790 "mpdu_ht_control_valid: %x " 1791 "frame_encryption_info_valid: %x ", 1792 mpdu_info->rxpcu_mpdu_filter_in_category, 1793 mpdu_info->sw_frame_group_id, 1794 mpdu_info->ndp_frame, 1795 mpdu_info->phy_err, 1796 mpdu_info->phy_err_during_mpdu_header, 1797 mpdu_info->protocol_version_err, 1798 mpdu_info->ast_based_lookup_valid, 1799 mpdu_info->phy_ppdu_id, 1800 mpdu_info->ast_index, 1801 mpdu_info->sw_peer_id, 1802 mpdu_info->mpdu_frame_control_valid, 1803 mpdu_info->mpdu_duration_valid, 1804 mpdu_info->mac_addr_ad1_valid, 1805 mpdu_info->mac_addr_ad2_valid, 1806 mpdu_info->mac_addr_ad3_valid, 1807 mpdu_info->mac_addr_ad4_valid, 1808 mpdu_info->mpdu_sequence_control_valid, 1809 mpdu_info->mpdu_qos_control_valid, 1810 mpdu_info->mpdu_ht_control_valid, 1811 mpdu_info->frame_encryption_info_valid); 1812 1813 hal_verbose_debug( 1814 "rx_mpdu_start tlv (2/5) - " 1815 "fr_ds: %x " 1816 "to_ds: %x " 1817 "encrypted: %x " 1818 "mpdu_retry: %x " 1819 "mpdu_sequence_number: %x " 1820 "epd_en: %x " 1821 "all_frames_shall_be_encrypted: %x " 1822 "encrypt_type: %x " 1823 "mesh_sta: %x " 1824 "bssid_hit: %x " 1825 "bssid_number: %x " 1826 "tid: %x " 1827 "pn_31_0: %x " 1828 "pn_63_32: %x " 1829 "pn_95_64: %x " 1830 "pn_127_96: %x " 1831 "peer_meta_data: %x " 1832 "rxpt_classify_info.reo_destination_indication: %x " 1833 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1834 "rx_reo_queue_desc_addr_31_0: %x ", 1835 mpdu_info->fr_ds, 1836 mpdu_info->to_ds, 1837 mpdu_info->encrypted, 1838 mpdu_info->mpdu_retry, 1839 mpdu_info->mpdu_sequence_number, 1840 mpdu_info->epd_en, 1841 mpdu_info->all_frames_shall_be_encrypted, 1842 mpdu_info->encrypt_type, 1843 mpdu_info->mesh_sta, 1844 mpdu_info->bssid_hit, 1845 mpdu_info->bssid_number, 1846 mpdu_info->tid, 1847 mpdu_info->pn_31_0, 1848 mpdu_info->pn_63_32, 1849 mpdu_info->pn_95_64, 1850 mpdu_info->pn_127_96, 1851 mpdu_info->peer_meta_data, 1852 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1853 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1854 mpdu_info->rx_reo_queue_desc_addr_31_0); 1855 1856 hal_verbose_debug( 1857 "rx_mpdu_start tlv (3/5) - " 1858 "rx_reo_queue_desc_addr_39_32: %x " 1859 "receive_queue_number: %x " 1860 "pre_delim_err_warning: %x " 1861 "first_delim_err: %x " 1862 "key_id_octet: %x " 1863 "new_peer_entry: %x " 1864 "decrypt_needed: %x " 1865 "decap_type: %x " 1866 "rx_insert_vlan_c_tag_padding: %x " 1867 "rx_insert_vlan_s_tag_padding: %x " 1868 "strip_vlan_c_tag_decap: %x " 1869 "strip_vlan_s_tag_decap: %x " 1870 "pre_delim_count: %x " 1871 "ampdu_flag: %x " 1872 "bar_frame: %x " 1873 "mpdu_length: %x " 1874 "first_mpdu: %x " 1875 "mcast_bcast: %x " 1876 "ast_index_not_found: %x " 1877 "ast_index_timeout: %x ", 1878 mpdu_info->rx_reo_queue_desc_addr_39_32, 1879 mpdu_info->receive_queue_number, 1880 mpdu_info->pre_delim_err_warning, 1881 mpdu_info->first_delim_err, 1882 mpdu_info->key_id_octet, 1883 mpdu_info->new_peer_entry, 1884 mpdu_info->decrypt_needed, 1885 mpdu_info->decap_type, 1886 mpdu_info->rx_insert_vlan_c_tag_padding, 1887 mpdu_info->rx_insert_vlan_s_tag_padding, 1888 mpdu_info->strip_vlan_c_tag_decap, 1889 mpdu_info->strip_vlan_s_tag_decap, 1890 mpdu_info->pre_delim_count, 1891 mpdu_info->ampdu_flag, 1892 mpdu_info->bar_frame, 1893 mpdu_info->mpdu_length, 1894 mpdu_info->first_mpdu, 1895 mpdu_info->mcast_bcast, 1896 mpdu_info->ast_index_not_found, 1897 mpdu_info->ast_index_timeout); 1898 1899 hal_verbose_debug( 1900 "rx_mpdu_start tlv (4/5) - " 1901 "power_mgmt: %x " 1902 "non_qos: %x " 1903 "null_data: %x " 1904 "mgmt_type: %x " 1905 "ctrl_type: %x " 1906 "more_data: %x " 1907 "eosp: %x " 1908 "fragment_flag: %x " 1909 "order: %x " 1910 "u_apsd_trigger: %x " 1911 "encrypt_required: %x " 1912 "directed: %x " 1913 "mpdu_frame_control_field: %x " 1914 "mpdu_duration_field: %x " 1915 "mac_addr_ad1_31_0: %x " 1916 "mac_addr_ad1_47_32: %x " 1917 "mac_addr_ad2_15_0: %x " 1918 "mac_addr_ad2_47_16: %x " 1919 "mac_addr_ad3_31_0: %x " 1920 "mac_addr_ad3_47_32: %x ", 1921 mpdu_info->power_mgmt, 1922 mpdu_info->non_qos, 1923 mpdu_info->null_data, 1924 mpdu_info->mgmt_type, 1925 mpdu_info->ctrl_type, 1926 mpdu_info->more_data, 1927 mpdu_info->eosp, 1928 mpdu_info->fragment_flag, 1929 mpdu_info->order, 1930 mpdu_info->u_apsd_trigger, 1931 mpdu_info->encrypt_required, 1932 mpdu_info->directed, 1933 mpdu_info->mpdu_frame_control_field, 1934 mpdu_info->mpdu_duration_field, 1935 mpdu_info->mac_addr_ad1_31_0, 1936 mpdu_info->mac_addr_ad1_47_32, 1937 mpdu_info->mac_addr_ad2_15_0, 1938 mpdu_info->mac_addr_ad2_47_16, 1939 mpdu_info->mac_addr_ad3_31_0, 1940 mpdu_info->mac_addr_ad3_47_32); 1941 1942 hal_verbose_debug( 1943 "rx_mpdu_start tlv (5/5) - " 1944 "mpdu_sequence_control_field: %x " 1945 "mac_addr_ad4_31_0: %x " 1946 "mac_addr_ad4_47_32: %x " 1947 "mpdu_qos_control_field: %x " 1948 "mpdu_ht_control_field: %x ", 1949 mpdu_info->mpdu_sequence_control_field, 1950 mpdu_info->mac_addr_ad4_31_0, 1951 mpdu_info->mac_addr_ad4_47_32, 1952 mpdu_info->mpdu_qos_control_field, 1953 mpdu_info->mpdu_ht_control_field); 1954 } 1955 1956 /** 1957 * hal_tx_desc_set_search_type - Set the search type value 1958 * @desc: Handle to Tx Descriptor 1959 * @search_type: search type 1960 * 0 – Normal search 1961 * 1 – Index based address search 1962 * 2 – Index based flow search 1963 * 1964 * Return: void 1965 */ 1966 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 1967 static void hal_tx_desc_set_search_type_generic(void *desc, 1968 uint8_t search_type) 1969 { 1970 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 1971 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 1972 } 1973 #else 1974 static void hal_tx_desc_set_search_type_generic(void *desc, 1975 uint8_t search_type) 1976 { 1977 } 1978 1979 #endif 1980 1981 /** 1982 * hal_tx_desc_set_search_index - Set the search index value 1983 * @desc: Handle to Tx Descriptor 1984 * @search_index: The index that will be used for index based address or 1985 * flow search. The field is valid when 'search_type' is 1986 * 1 0r 2 1987 * 1988 * Return: void 1989 */ 1990 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 1991 static void hal_tx_desc_set_search_index_generic(void *desc, 1992 uint32_t search_index) 1993 { 1994 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 1995 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 1996 } 1997 #else 1998 static void hal_tx_desc_set_search_index_generic(void *desc, 1999 uint32_t search_index) 2000 { 2001 } 2002 #endif 2003 2004 /** 2005 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2006 * @soc: HAL SoC context 2007 * @map: PCP-TID mapping table 2008 * 2009 * PCP are mapped to 8 TID values using TID values programmed 2010 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2011 * The mapping register has TID mapping for 8 PCP values 2012 * 2013 * Return: none 2014 */ 2015 static void hal_tx_set_pcp_tid_map_generic(void *hal_soc, uint8_t *map) 2016 { 2017 uint32_t addr, value; 2018 2019 struct hal_soc *soc = (struct hal_soc *)hal_soc; 2020 2021 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2022 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2023 2024 value = (map[0] | 2025 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2026 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2027 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2028 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2029 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2030 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2031 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2032 2033 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2034 } 2035 2036 /** 2037 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2038 * value received from user-space 2039 * @soc: HAL SoC context 2040 * @pcp: pcp value 2041 * @tid : tid value 2042 * 2043 * Return: void 2044 */ 2045 static 2046 void hal_tx_update_pcp_tid_generic(void *hal_soc, uint8_t pcp, uint8_t tid) 2047 { 2048 uint32_t addr, value, regval; 2049 2050 struct hal_soc *soc = (struct hal_soc *)hal_soc; 2051 2052 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2053 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2054 2055 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2056 2057 /* Read back previous PCP TID config and update 2058 * with new config. 2059 */ 2060 regval = HAL_REG_READ(soc, addr); 2061 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2062 regval |= value; 2063 2064 HAL_REG_WRITE(soc, addr, 2065 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2066 } 2067 2068 /** 2069 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2070 * @soc: HAL SoC context 2071 * @val: priority value 2072 * 2073 * Return: void 2074 */ 2075 static 2076 void hal_tx_update_tidmap_prty_generic(void *hal_soc, uint8_t value) 2077 { 2078 uint32_t addr; 2079 2080 struct hal_soc *soc = (struct hal_soc *)hal_soc; 2081 2082 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2083 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2084 2085 HAL_REG_WRITE(soc, addr, 2086 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2087 } 2088 #endif /* _HAL_GENERIC_API_H_ */ 2089