1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 22 ((struct rx_msdu_desc_info *) \ 23 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 24 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 25 /** 26 * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr 27 * @msdu_details_ptr - Pointer to msdu_details_ptr 28 * Return - Pointer to rx_msdu_desc_info structure. 29 * 30 */ 31 static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) 32 { 33 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 34 } 35 36 37 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 38 ((struct rx_msdu_details *) \ 39 _OFFSET_TO_BYTE_PTR((link_desc),\ 40 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 41 /** 42 * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details 43 * @link_desc - Pointer to link desc 44 * Return - Pointer to rx_msdu_details structure 45 * 46 */ 47 48 static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) 49 { 50 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 51 } 52 53 /** 54 * hal_tx_comp_get_status() - TQM Release reason 55 * @hal_desc: completion ring Tx status 56 * 57 * This function will parse the WBM completion descriptor and populate in 58 * HAL structure 59 * 60 * Return: none 61 */ 62 #if defined(WCSS_VERSION) && \ 63 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 64 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 65 static inline void hal_tx_comp_get_status_generic(void *desc, 66 void *ts1, void *hal) 67 { 68 uint8_t rate_stats_valid = 0; 69 uint32_t rate_stats = 0; 70 struct hal_tx_completion_status *ts = 71 (struct hal_tx_completion_status *)ts1; 72 73 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 74 TQM_STATUS_NUMBER); 75 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 76 ACK_FRAME_RSSI); 77 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 78 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 80 MSDU_PART_OF_AMSDU); 81 82 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 83 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 84 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 85 TRANSMIT_COUNT); 86 87 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 88 TX_RATE_STATS); 89 90 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 91 TX_RATE_STATS_INFO_VALID, rate_stats); 92 93 ts->valid = rate_stats_valid; 94 95 if (rate_stats_valid) { 96 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 97 rate_stats); 98 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 99 TRANSMIT_PKT_TYPE, rate_stats); 100 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 101 TRANSMIT_STBC, rate_stats); 102 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 103 rate_stats); 104 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 105 rate_stats); 106 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 107 rate_stats); 108 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 109 rate_stats); 110 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 111 rate_stats); 112 } 113 114 ts->release_src = hal_tx_comp_get_buffer_source(desc); 115 ts->status = hal_tx_comp_get_release_reason(desc, hal); 116 117 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 118 TX_RATE_STATS_INFO_TX_RATE_STATS); 119 } 120 #else 121 static inline void hal_tx_comp_get_status_generic(void *desc, 122 struct hal_tx_completion_status *ts, void *hal) 123 { 124 125 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 126 TQM_STATUS_NUMBER); 127 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 128 ACK_FRAME_RSSI); 129 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 130 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 131 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 132 MSDU_PART_OF_AMSDU); 133 134 ts->release_src = hal_tx_comp_get_buffer_source(desc); 135 ts->status = hal_tx_comp_get_release_reason(desc, hal); 136 } 137 #endif 138 139 140 /** 141 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 142 * @desc: Handle to Tx Descriptor 143 * @paddr: Physical Address 144 * @pool_id: Return Buffer Manager ID 145 * @desc_id: Descriptor ID 146 * @type: 0 - Address points to a MSDU buffer 147 * 1 - Address points to MSDU extension descriptor 148 * 149 * Return: void 150 */ 151 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 152 dma_addr_t paddr, uint8_t pool_id, 153 uint32_t desc_id, uint8_t type) 154 { 155 /* Set buffer_addr_info.buffer_addr_31_0 */ 156 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 157 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 158 159 /* Set buffer_addr_info.buffer_addr_39_32 */ 160 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 161 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 162 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 163 (((uint64_t) paddr) >> 32)); 164 165 /* Set buffer_addr_info.return_buffer_manager = pool id */ 166 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 167 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 168 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 169 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 170 171 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 172 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 173 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 174 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 175 176 /* Set Buffer or Ext Descriptor Type */ 177 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 178 BUF_OR_EXT_DESC_TYPE) |= 179 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 180 } 181 182 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 183 /** 184 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 185 * tlv_tag: Taf of the TLVs 186 * rx_tlv: the pointer to the TLVs 187 * @ppdu_info: pointer to ppdu_info 188 * 189 * Return: true if the tlv is handled, false if not 190 */ 191 static inline bool 192 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 193 struct hal_rx_ppdu_info *ppdu_info) 194 { 195 uint32_t value; 196 197 switch (tlv_tag) { 198 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 199 { 200 uint8_t *he_sig_a_mu_ul_info = 201 (uint8_t *)rx_tlv + 202 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 203 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 204 ppdu_info->rx_status.he_flags = 1; 205 206 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 207 FORMAT_INDICATION); 208 if (value == 0) { 209 ppdu_info->rx_status.he_data1 = 210 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 211 } else { 212 ppdu_info->rx_status.he_data1 = 213 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 214 } 215 return true; 216 } 217 default: 218 return false; 219 } 220 } 221 #else 222 static inline bool 223 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 224 struct hal_rx_ppdu_info *ppdu_info) 225 { 226 return false; 227 } 228 #endif /* CONFIG_MCL && QCA_WIFI_QCA6290_11AX */ 229 230 /** 231 * hal_rx_status_get_tlv_info() - process receive info TLV 232 * @rx_tlv_hdr: pointer to TLV header 233 * @ppdu_info: pointer to ppdu_info 234 * 235 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 236 */ 237 static inline uint32_t 238 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 239 void *halsoc) 240 { 241 struct hal_soc *hal = (struct hal_soc *)halsoc; 242 uint32_t tlv_tag, user_id, tlv_len, value; 243 uint8_t group_id = 0; 244 uint8_t he_dcm = 0; 245 uint8_t he_stbc = 0; 246 uint16_t he_gi = 0; 247 uint16_t he_ltf = 0; 248 void *rx_tlv; 249 bool unhandled = false; 250 struct hal_rx_ppdu_info *ppdu_info = 251 (struct hal_rx_ppdu_info *)ppduinfo; 252 253 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 254 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 255 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 256 257 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 258 switch (tlv_tag) { 259 260 case WIFIRX_PPDU_START_E: 261 ppdu_info->com_info.ppdu_id = 262 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 263 PHY_PPDU_ID); 264 /* channel number is set in PHY meta data */ 265 ppdu_info->rx_status.chan_num = 266 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 267 SW_PHY_META_DATA); 268 ppdu_info->com_info.ppdu_timestamp = 269 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 270 PPDU_START_TIMESTAMP); 271 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 272 break; 273 274 case WIFIRX_PPDU_START_USER_INFO_E: 275 break; 276 277 case WIFIRX_PPDU_END_E: 278 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 279 "[%s][%d] ppdu_end_e len=%d", 280 __func__, __LINE__, tlv_len); 281 /* This is followed by sub-TLVs of PPDU_END */ 282 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 283 break; 284 285 case WIFIRXPCU_PPDU_END_INFO_E: 286 ppdu_info->rx_status.tsft = 287 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 288 WB_TIMESTAMP_UPPER_32); 289 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 290 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 291 WB_TIMESTAMP_LOWER_32); 292 ppdu_info->rx_status.duration = 293 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 294 RX_PPDU_DURATION); 295 break; 296 297 case WIFIRX_PPDU_END_USER_STATS_E: 298 { 299 unsigned long tid = 0; 300 uint16_t seq = 0; 301 302 ppdu_info->rx_status.ast_index = 303 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 304 AST_INDEX); 305 306 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 307 RECEIVED_QOS_DATA_TID_BITMAP); 308 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 309 310 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 311 ppdu_info->rx_status.tid = HAL_TID_INVALID; 312 313 ppdu_info->rx_status.tcp_msdu_count = 314 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 315 TCP_MSDU_COUNT) + 316 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 317 TCP_ACK_MSDU_COUNT); 318 ppdu_info->rx_status.udp_msdu_count = 319 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 320 UDP_MSDU_COUNT); 321 ppdu_info->rx_status.other_msdu_count = 322 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 323 OTHER_MSDU_COUNT); 324 325 ppdu_info->rx_status.frame_control_info_valid = 326 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 327 FRAME_CONTROL_INFO_VALID); 328 329 if (ppdu_info->rx_status.frame_control_info_valid) 330 ppdu_info->rx_status.frame_control = 331 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 332 FRAME_CONTROL_FIELD); 333 334 ppdu_info->rx_status.data_sequence_control_info_valid = 335 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 336 DATA_SEQUENCE_CONTROL_INFO_VALID); 337 338 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 339 FIRST_DATA_SEQ_CTRL); 340 if (ppdu_info->rx_status.data_sequence_control_info_valid) 341 ppdu_info->rx_status.first_data_seq_ctrl = seq; 342 343 ppdu_info->rx_status.preamble_type = 344 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 345 HT_CONTROL_FIELD_PKT_TYPE); 346 switch (ppdu_info->rx_status.preamble_type) { 347 case HAL_RX_PKT_TYPE_11N: 348 ppdu_info->rx_status.ht_flags = 1; 349 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 350 break; 351 case HAL_RX_PKT_TYPE_11AC: 352 ppdu_info->rx_status.vht_flags = 1; 353 break; 354 case HAL_RX_PKT_TYPE_11AX: 355 ppdu_info->rx_status.he_flags = 1; 356 break; 357 default: 358 break; 359 } 360 361 ppdu_info->com_info.mpdu_cnt_fcs_ok = 362 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 363 MPDU_CNT_FCS_OK); 364 ppdu_info->com_info.mpdu_cnt_fcs_err = 365 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 366 MPDU_CNT_FCS_ERR); 367 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 368 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 369 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 370 else 371 ppdu_info->rx_status.rs_flags &= 372 (~IEEE80211_AMPDU_FLAG); 373 break; 374 } 375 376 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 377 break; 378 379 case WIFIRX_PPDU_END_STATUS_DONE_E: 380 return HAL_TLV_STATUS_PPDU_DONE; 381 382 case WIFIDUMMY_E: 383 return HAL_TLV_STATUS_BUF_DONE; 384 385 case WIFIPHYRX_HT_SIG_E: 386 { 387 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 388 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 389 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 390 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 391 FEC_CODING); 392 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 393 1 : 0; 394 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 395 HT_SIG_INFO_0, MCS); 396 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 397 HT_SIG_INFO_0, CBW); 398 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 399 HT_SIG_INFO_1, SHORT_GI); 400 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 401 break; 402 } 403 404 case WIFIPHYRX_L_SIG_B_E: 405 { 406 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 407 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 408 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 409 410 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 411 switch (value) { 412 case 1: 413 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 414 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 415 break; 416 case 2: 417 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 418 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 419 break; 420 case 3: 421 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 422 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 423 break; 424 case 4: 425 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 426 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 427 break; 428 case 5: 429 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 430 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 431 break; 432 case 6: 433 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 434 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 435 break; 436 case 7: 437 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 438 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 439 break; 440 default: 441 break; 442 } 443 ppdu_info->rx_status.cck_flag = 1; 444 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 445 break; 446 } 447 448 case WIFIPHYRX_L_SIG_A_E: 449 { 450 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 451 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 452 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 453 454 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 455 switch (value) { 456 case 8: 457 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 458 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 459 break; 460 case 9: 461 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 462 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 463 break; 464 case 10: 465 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 466 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 467 break; 468 case 11: 469 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 470 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 471 break; 472 case 12: 473 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 474 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 475 break; 476 case 13: 477 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 478 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 479 break; 480 case 14: 481 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 482 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 483 break; 484 case 15: 485 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 486 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 487 break; 488 default: 489 break; 490 } 491 ppdu_info->rx_status.ofdm_flag = 1; 492 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 493 break; 494 } 495 496 case WIFIPHYRX_VHT_SIG_A_E: 497 { 498 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 499 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 500 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 501 502 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 503 SU_MU_CODING); 504 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 505 1 : 0; 506 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 507 ppdu_info->rx_status.vht_flag_values5 = group_id; 508 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 509 VHT_SIG_A_INFO_1, MCS); 510 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 511 VHT_SIG_A_INFO_1, GI_SETTING); 512 513 switch (hal->target_type) { 514 case TARGET_TYPE_QCA8074: 515 case TARGET_TYPE_QCA8074V2: 516 ppdu_info->rx_status.is_stbc = 517 HAL_RX_GET(vht_sig_a_info, 518 VHT_SIG_A_INFO_0, STBC); 519 value = HAL_RX_GET(vht_sig_a_info, 520 VHT_SIG_A_INFO_0, N_STS); 521 if (ppdu_info->rx_status.is_stbc && (value > 0)) 522 value = ((value + 1) >> 1) - 1; 523 ppdu_info->rx_status.nss = 524 ((value & VHT_SIG_SU_NSS_MASK) + 1); 525 526 break; 527 case TARGET_TYPE_QCA6290: 528 #if !defined(QCA_WIFI_QCA6290_11AX) 529 ppdu_info->rx_status.is_stbc = 530 HAL_RX_GET(vht_sig_a_info, 531 VHT_SIG_A_INFO_0, STBC); 532 value = HAL_RX_GET(vht_sig_a_info, 533 VHT_SIG_A_INFO_0, N_STS); 534 if (ppdu_info->rx_status.is_stbc && (value > 0)) 535 value = ((value + 1) >> 1) - 1; 536 ppdu_info->rx_status.nss = 537 ((value & VHT_SIG_SU_NSS_MASK) + 1); 538 #else 539 ppdu_info->rx_status.nss = 0; 540 #endif 541 break; 542 #ifdef QCA_WIFI_QCA6390 543 case TARGET_TYPE_QCA6390: 544 ppdu_info->rx_status.nss = 0; 545 break; 546 #endif 547 default: 548 break; 549 } 550 ppdu_info->rx_status.vht_flag_values3[0] = 551 (((ppdu_info->rx_status.mcs) << 4) 552 | ppdu_info->rx_status.nss); 553 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 554 VHT_SIG_A_INFO_0, BANDWIDTH); 555 ppdu_info->rx_status.vht_flag_values2 = 556 ppdu_info->rx_status.bw; 557 ppdu_info->rx_status.vht_flag_values4 = 558 HAL_RX_GET(vht_sig_a_info, 559 VHT_SIG_A_INFO_1, SU_MU_CODING); 560 561 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 562 VHT_SIG_A_INFO_1, BEAMFORMED); 563 if (group_id == 0 || group_id == 63) 564 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 565 else 566 ppdu_info->rx_status.reception_type = 567 HAL_RX_TYPE_MU_MIMO; 568 569 break; 570 } 571 case WIFIPHYRX_HE_SIG_A_SU_E: 572 { 573 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 574 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 575 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 576 ppdu_info->rx_status.he_flags = 1; 577 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 578 FORMAT_INDICATION); 579 if (value == 0) { 580 ppdu_info->rx_status.he_data1 = 581 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 582 } else { 583 ppdu_info->rx_status.he_data1 = 584 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 585 } 586 587 /* data1 */ 588 ppdu_info->rx_status.he_data1 |= 589 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 590 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 591 QDF_MON_STATUS_HE_DL_UL_KNOWN | 592 QDF_MON_STATUS_HE_MCS_KNOWN | 593 QDF_MON_STATUS_HE_DCM_KNOWN | 594 QDF_MON_STATUS_HE_CODING_KNOWN | 595 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 596 QDF_MON_STATUS_HE_STBC_KNOWN | 597 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 598 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 599 600 /* data2 */ 601 ppdu_info->rx_status.he_data2 = 602 QDF_MON_STATUS_HE_GI_KNOWN; 603 ppdu_info->rx_status.he_data2 |= 604 QDF_MON_STATUS_TXBF_KNOWN | 605 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 606 QDF_MON_STATUS_TXOP_KNOWN | 607 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 608 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 609 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 610 611 /* data3 */ 612 value = HAL_RX_GET(he_sig_a_su_info, 613 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 614 ppdu_info->rx_status.he_data3 = value; 615 value = HAL_RX_GET(he_sig_a_su_info, 616 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 617 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 618 ppdu_info->rx_status.he_data3 |= value; 619 value = HAL_RX_GET(he_sig_a_su_info, 620 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 621 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 622 ppdu_info->rx_status.he_data3 |= value; 623 624 value = HAL_RX_GET(he_sig_a_su_info, 625 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 626 ppdu_info->rx_status.mcs = value; 627 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 628 ppdu_info->rx_status.he_data3 |= value; 629 630 value = HAL_RX_GET(he_sig_a_su_info, 631 HE_SIG_A_SU_INFO_0, DCM); 632 he_dcm = value; 633 value = value << QDF_MON_STATUS_DCM_SHIFT; 634 ppdu_info->rx_status.he_data3 |= value; 635 value = HAL_RX_GET(he_sig_a_su_info, 636 HE_SIG_A_SU_INFO_1, CODING); 637 value = value << QDF_MON_STATUS_CODING_SHIFT; 638 ppdu_info->rx_status.he_data3 |= value; 639 value = HAL_RX_GET(he_sig_a_su_info, 640 HE_SIG_A_SU_INFO_1, 641 LDPC_EXTRA_SYMBOL); 642 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 643 ppdu_info->rx_status.he_data3 |= value; 644 value = HAL_RX_GET(he_sig_a_su_info, 645 HE_SIG_A_SU_INFO_1, STBC); 646 he_stbc = value; 647 value = value << QDF_MON_STATUS_STBC_SHIFT; 648 ppdu_info->rx_status.he_data3 |= value; 649 650 /* data4 */ 651 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 652 SPATIAL_REUSE); 653 ppdu_info->rx_status.he_data4 = value; 654 655 /* data5 */ 656 value = HAL_RX_GET(he_sig_a_su_info, 657 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 658 ppdu_info->rx_status.he_data5 = value; 659 ppdu_info->rx_status.bw = value; 660 value = HAL_RX_GET(he_sig_a_su_info, 661 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 662 switch (value) { 663 case 0: 664 he_gi = HE_GI_0_8; 665 he_ltf = HE_LTF_1_X; 666 break; 667 case 1: 668 he_gi = HE_GI_0_8; 669 he_ltf = HE_LTF_2_X; 670 break; 671 case 2: 672 he_gi = HE_GI_1_6; 673 he_ltf = HE_LTF_2_X; 674 break; 675 case 3: 676 if (he_dcm && he_stbc) { 677 he_gi = HE_GI_0_8; 678 he_ltf = HE_LTF_4_X; 679 } else { 680 he_gi = HE_GI_3_2; 681 he_ltf = HE_LTF_4_X; 682 } 683 break; 684 } 685 ppdu_info->rx_status.sgi = he_gi; 686 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 687 ppdu_info->rx_status.he_data5 |= value; 688 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 689 ppdu_info->rx_status.he_data5 |= value; 690 691 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 692 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 693 ppdu_info->rx_status.he_data5 |= value; 694 695 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 696 PACKET_EXTENSION_A_FACTOR); 697 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 698 ppdu_info->rx_status.he_data5 |= value; 699 700 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 701 value = value << QDF_MON_STATUS_TXBF_SHIFT; 702 ppdu_info->rx_status.he_data5 |= value; 703 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 704 PACKET_EXTENSION_PE_DISAMBIGUITY); 705 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 706 ppdu_info->rx_status.he_data5 |= value; 707 708 /* data6 */ 709 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 710 value++; 711 ppdu_info->rx_status.nss = value; 712 ppdu_info->rx_status.he_data6 = value; 713 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 714 DOPPLER_INDICATION); 715 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 716 ppdu_info->rx_status.he_data6 |= value; 717 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 718 TXOP_DURATION); 719 value = value << QDF_MON_STATUS_TXOP_SHIFT; 720 ppdu_info->rx_status.he_data6 |= value; 721 722 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 723 HE_SIG_A_SU_INFO_1, TXBF); 724 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 725 break; 726 } 727 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 728 { 729 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 730 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 731 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 732 733 ppdu_info->rx_status.he_mu_flags = 1; 734 735 /* HE Flags */ 736 /*data1*/ 737 ppdu_info->rx_status.he_data1 = 738 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 739 ppdu_info->rx_status.he_data1 |= 740 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 741 QDF_MON_STATUS_HE_DL_UL_KNOWN | 742 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 743 QDF_MON_STATUS_HE_STBC_KNOWN | 744 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 745 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 746 747 /* data2 */ 748 ppdu_info->rx_status.he_data2 = 749 QDF_MON_STATUS_HE_GI_KNOWN; 750 ppdu_info->rx_status.he_data2 |= 751 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 752 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 753 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 754 QDF_MON_STATUS_TXOP_KNOWN | 755 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 756 757 /*data3*/ 758 value = HAL_RX_GET(he_sig_a_mu_dl_info, 759 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 760 ppdu_info->rx_status.he_data3 = value; 761 762 value = HAL_RX_GET(he_sig_a_mu_dl_info, 763 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 764 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 765 ppdu_info->rx_status.he_data3 |= value; 766 767 value = HAL_RX_GET(he_sig_a_mu_dl_info, 768 HE_SIG_A_MU_DL_INFO_1, 769 LDPC_EXTRA_SYMBOL); 770 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 771 ppdu_info->rx_status.he_data3 |= value; 772 773 value = HAL_RX_GET(he_sig_a_mu_dl_info, 774 HE_SIG_A_MU_DL_INFO_1, STBC); 775 he_stbc = value; 776 value = value << QDF_MON_STATUS_STBC_SHIFT; 777 ppdu_info->rx_status.he_data3 |= value; 778 779 /*data4*/ 780 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 781 SPATIAL_REUSE); 782 ppdu_info->rx_status.he_data4 = value; 783 784 /*data5*/ 785 value = HAL_RX_GET(he_sig_a_mu_dl_info, 786 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 787 ppdu_info->rx_status.he_data5 = value; 788 ppdu_info->rx_status.bw = value; 789 790 value = HAL_RX_GET(he_sig_a_mu_dl_info, 791 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 792 switch (value) { 793 case 0: 794 he_gi = HE_GI_0_8; 795 he_ltf = HE_LTF_4_X; 796 break; 797 case 1: 798 he_gi = HE_GI_0_8; 799 he_ltf = HE_LTF_2_X; 800 break; 801 case 2: 802 he_gi = HE_GI_1_6; 803 he_ltf = HE_LTF_2_X; 804 break; 805 case 3: 806 he_gi = HE_GI_3_2; 807 he_ltf = HE_LTF_4_X; 808 break; 809 } 810 ppdu_info->rx_status.sgi = he_gi; 811 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 812 ppdu_info->rx_status.he_data5 |= value; 813 814 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 815 ppdu_info->rx_status.he_data5 |= value; 816 817 value = HAL_RX_GET(he_sig_a_mu_dl_info, 818 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 819 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 820 ppdu_info->rx_status.he_data5 |= value; 821 822 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 823 PACKET_EXTENSION_A_FACTOR); 824 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 825 ppdu_info->rx_status.he_data5 |= value; 826 827 828 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 829 PACKET_EXTENSION_PE_DISAMBIGUITY); 830 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 831 ppdu_info->rx_status.he_data5 |= value; 832 833 /*data6*/ 834 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 835 DOPPLER_INDICATION); 836 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 837 ppdu_info->rx_status.he_data6 |= value; 838 839 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 840 TXOP_DURATION); 841 value = value << QDF_MON_STATUS_TXOP_SHIFT; 842 ppdu_info->rx_status.he_data6 |= value; 843 844 /* HE-MU Flags */ 845 /* HE-MU-flags1 */ 846 ppdu_info->rx_status.he_flags1 = 847 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 848 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 849 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 850 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 851 QDF_MON_STATUS_RU_0_KNOWN; 852 853 value = HAL_RX_GET(he_sig_a_mu_dl_info, 854 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 855 ppdu_info->rx_status.he_flags1 |= value; 856 value = HAL_RX_GET(he_sig_a_mu_dl_info, 857 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 858 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 859 ppdu_info->rx_status.he_flags1 |= value; 860 861 /* HE-MU-flags2 */ 862 ppdu_info->rx_status.he_flags2 = 863 QDF_MON_STATUS_BW_KNOWN; 864 865 value = HAL_RX_GET(he_sig_a_mu_dl_info, 866 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 867 ppdu_info->rx_status.he_flags2 |= value; 868 value = HAL_RX_GET(he_sig_a_mu_dl_info, 869 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 870 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 871 ppdu_info->rx_status.he_flags2 |= value; 872 value = HAL_RX_GET(he_sig_a_mu_dl_info, 873 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 874 value = value - 1; 875 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 876 ppdu_info->rx_status.he_flags2 |= value; 877 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 878 break; 879 } 880 case WIFIPHYRX_HE_SIG_B1_MU_E: 881 { 882 883 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 884 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 885 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 886 887 ppdu_info->rx_status.he_sig_b_common_known |= 888 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 889 /* TODO: Check on the availability of other fields in 890 * sig_b_common 891 */ 892 893 value = HAL_RX_GET(he_sig_b1_mu_info, 894 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 895 ppdu_info->rx_status.he_RU[0] = value; 896 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 897 break; 898 } 899 case WIFIPHYRX_HE_SIG_B2_MU_E: 900 { 901 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 902 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 903 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 904 /* 905 * Not all "HE" fields can be updated from 906 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 907 * to populate rest of the "HE" fields for MU scenarios. 908 */ 909 910 /* HE-data1 */ 911 ppdu_info->rx_status.he_data1 |= 912 QDF_MON_STATUS_HE_MCS_KNOWN | 913 QDF_MON_STATUS_HE_CODING_KNOWN; 914 915 /* HE-data2 */ 916 917 /* HE-data3 */ 918 value = HAL_RX_GET(he_sig_b2_mu_info, 919 HE_SIG_B2_MU_INFO_0, STA_MCS); 920 ppdu_info->rx_status.mcs = value; 921 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 922 ppdu_info->rx_status.he_data3 |= value; 923 924 925 value = HAL_RX_GET(he_sig_b2_mu_info, 926 HE_SIG_B2_MU_INFO_0, STA_CODING); 927 value = value << QDF_MON_STATUS_CODING_SHIFT; 928 ppdu_info->rx_status.he_data3 |= value; 929 930 /* HE-data4 */ 931 value = HAL_RX_GET(he_sig_b2_mu_info, 932 HE_SIG_B2_MU_INFO_0, STA_ID); 933 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 934 ppdu_info->rx_status.he_data4 |= value; 935 936 /* HE-data5 */ 937 938 /* HE-data6 */ 939 value = HAL_RX_GET(he_sig_b2_mu_info, 940 HE_SIG_B2_MU_INFO_0, NSTS); 941 /* value n indicates n+1 spatial streams */ 942 value++; 943 ppdu_info->rx_status.nss = value; 944 ppdu_info->rx_status.he_data6 |= value; 945 946 break; 947 948 } 949 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 950 { 951 uint8_t *he_sig_b2_ofdma_info = 952 (uint8_t *)rx_tlv + 953 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 954 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 955 956 /* 957 * Not all "HE" fields can be updated from 958 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 959 * to populate rest of "HE" fields for MU OFDMA scenarios. 960 */ 961 962 /* HE-data1 */ 963 ppdu_info->rx_status.he_data1 |= 964 QDF_MON_STATUS_HE_MCS_KNOWN | 965 QDF_MON_STATUS_HE_DCM_KNOWN | 966 QDF_MON_STATUS_HE_CODING_KNOWN; 967 968 /* HE-data2 */ 969 ppdu_info->rx_status.he_data2 |= 970 QDF_MON_STATUS_TXBF_KNOWN; 971 972 /* HE-data3 */ 973 value = HAL_RX_GET(he_sig_b2_ofdma_info, 974 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 975 ppdu_info->rx_status.mcs = value; 976 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 977 ppdu_info->rx_status.he_data3 |= value; 978 979 value = HAL_RX_GET(he_sig_b2_ofdma_info, 980 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 981 he_dcm = value; 982 value = value << QDF_MON_STATUS_DCM_SHIFT; 983 ppdu_info->rx_status.he_data3 |= value; 984 985 value = HAL_RX_GET(he_sig_b2_ofdma_info, 986 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 987 value = value << QDF_MON_STATUS_CODING_SHIFT; 988 ppdu_info->rx_status.he_data3 |= value; 989 990 /* HE-data4 */ 991 value = HAL_RX_GET(he_sig_b2_ofdma_info, 992 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 993 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 994 ppdu_info->rx_status.he_data4 |= value; 995 996 /* HE-data5 */ 997 value = HAL_RX_GET(he_sig_b2_ofdma_info, 998 HE_SIG_B2_OFDMA_INFO_0, TXBF); 999 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1000 ppdu_info->rx_status.he_data5 |= value; 1001 1002 /* HE-data6 */ 1003 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1004 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1005 /* value n indicates n+1 spatial streams */ 1006 value++; 1007 ppdu_info->rx_status.nss = value; 1008 ppdu_info->rx_status.he_data6 |= value; 1009 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1010 break; 1011 } 1012 case WIFIPHYRX_RSSI_LEGACY_E: 1013 { 1014 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1015 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_3, 1016 RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS); 1017 1018 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1019 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1020 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1021 ppdu_info->rx_status.he_re = 0; 1022 1023 value = HAL_RX_GET(rssi_info_tlv, 1024 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1025 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1026 "RSSI_PRI20_CHAIN0: %d\n", value); 1027 1028 value = HAL_RX_GET(rssi_info_tlv, 1029 RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0); 1030 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1031 "RSSI_EXT20_CHAIN0: %d\n", value); 1032 1033 value = HAL_RX_GET(rssi_info_tlv, 1034 RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0); 1035 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1036 "RSSI_EXT40_LOW20_CHAIN0: %d\n", value); 1037 1038 value = HAL_RX_GET(rssi_info_tlv, 1039 RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0); 1040 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1041 "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value); 1042 1043 value = HAL_RX_GET(rssi_info_tlv, 1044 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0); 1045 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1046 "RSSI_EXT80_LOW20_CHAIN0: %d\n", value); 1047 1048 value = HAL_RX_GET(rssi_info_tlv, 1049 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0); 1050 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1051 "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value); 1052 1053 value = HAL_RX_GET(rssi_info_tlv, 1054 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0); 1055 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1056 "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value); 1057 1058 value = HAL_RX_GET(rssi_info_tlv, 1059 RECEIVE_RSSI_INFO_1, 1060 RSSI_EXT80_HIGH20_CHAIN0); 1061 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1062 "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value); 1063 break; 1064 } 1065 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1066 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1067 ppdu_info); 1068 break; 1069 case WIFIRX_HEADER_E: 1070 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1071 ppdu_info->msdu_info.payload_len = tlv_len; 1072 break; 1073 case WIFIRX_MPDU_START_E: 1074 { 1075 uint8_t *rx_mpdu_start = 1076 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1077 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1078 uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1079 PHY_PPDU_ID); 1080 uint8_t filter_category = 0; 1081 1082 ppdu_info->nac_info.fc_valid = 1083 HAL_RX_GET(rx_mpdu_start, 1084 RX_MPDU_INFO_2, 1085 MPDU_FRAME_CONTROL_VALID); 1086 1087 ppdu_info->nac_info.to_ds_flag = 1088 HAL_RX_GET(rx_mpdu_start, 1089 RX_MPDU_INFO_2, 1090 TO_DS); 1091 1092 ppdu_info->nac_info.mac_addr2_valid = 1093 HAL_RX_GET(rx_mpdu_start, 1094 RX_MPDU_INFO_2, 1095 MAC_ADDR_AD2_VALID); 1096 1097 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1098 HAL_RX_GET(rx_mpdu_start, 1099 RX_MPDU_INFO_16, 1100 MAC_ADDR_AD2_15_0); 1101 1102 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1103 HAL_RX_GET(rx_mpdu_start, 1104 RX_MPDU_INFO_17, 1105 MAC_ADDR_AD2_47_16); 1106 1107 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1108 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1109 ppdu_info->rx_status.ppdu_len = 1110 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1111 MPDU_LENGTH); 1112 } else { 1113 ppdu_info->rx_status.ppdu_len += 1114 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1115 MPDU_LENGTH); 1116 } 1117 1118 filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1119 RXPCU_MPDU_FILTER_IN_CATEGORY); 1120 if (filter_category == 1) 1121 ppdu_info->rx_status.monitor_direct_used = 1; 1122 break; 1123 } 1124 case 0: 1125 return HAL_TLV_STATUS_PPDU_DONE; 1126 1127 default: 1128 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1129 unhandled = false; 1130 else 1131 unhandled = true; 1132 break; 1133 } 1134 1135 if (!unhandled) 1136 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1137 "%s TLV type: %d, TLV len:%d %s", 1138 __func__, tlv_tag, tlv_len, 1139 unhandled == true ? "unhandled" : ""); 1140 1141 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1142 rx_tlv, tlv_len); 1143 1144 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1145 } 1146 /** 1147 * hal_reo_status_get_header_generic - Process reo desc info 1148 * @d - Pointer to reo descriptior 1149 * @b - tlv type info 1150 * @h1 - Pointer to hal_reo_status_header where info to be stored 1151 * 1152 * Return - none. 1153 * 1154 */ 1155 static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) 1156 { 1157 1158 uint32_t val1 = 0; 1159 struct hal_reo_status_header *h = 1160 (struct hal_reo_status_header *)h1; 1161 1162 switch (b) { 1163 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1164 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1165 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1166 break; 1167 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1168 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1169 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1170 break; 1171 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1172 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1173 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1174 break; 1175 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1176 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1177 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1178 break; 1179 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1180 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1181 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1182 break; 1183 case HAL_REO_DESC_THRES_STATUS_TLV: 1184 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1185 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1186 break; 1187 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1188 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1189 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1190 break; 1191 default: 1192 pr_err("ERROR: Unknown tlv\n"); 1193 break; 1194 } 1195 h->cmd_num = 1196 HAL_GET_FIELD( 1197 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1198 val1); 1199 h->exec_time = 1200 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1201 CMD_EXECUTION_TIME, val1); 1202 h->status = 1203 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1204 REO_CMD_EXECUTION_STATUS, val1); 1205 switch (b) { 1206 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1207 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1208 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1209 break; 1210 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1211 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1212 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1213 break; 1214 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1215 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1216 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1217 break; 1218 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1219 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1220 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1221 break; 1222 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1223 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1224 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1225 break; 1226 case HAL_REO_DESC_THRES_STATUS_TLV: 1227 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1228 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1229 break; 1230 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1231 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1232 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1233 break; 1234 default: 1235 pr_err("ERROR: Unknown tlv\n"); 1236 break; 1237 } 1238 h->tstamp = 1239 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1240 } 1241 1242 /** 1243 * hal_reo_setup - Initialize HW REO block 1244 * 1245 * @hal_soc: Opaque HAL SOC handle 1246 * @reo_params: parameters needed by HAL for REO config 1247 */ 1248 static void hal_reo_setup_generic(void *hal_soc, 1249 void *reoparams) 1250 { 1251 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1252 uint32_t reg_val; 1253 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1254 1255 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1256 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1257 1258 reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | 1259 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | 1260 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); 1261 1262 reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, 1263 FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | 1264 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | 1265 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); 1266 1267 HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1268 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1269 1270 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1271 1272 /* TODO: Setup destination ring mapping if enabled */ 1273 1274 /* TODO: Error destination ring setting is left to default. 1275 * Default setting is to send all errors to release ring. 1276 */ 1277 1278 HAL_REG_WRITE(soc, 1279 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1280 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1281 HAL_DEFAULT_REO_TIMEOUT_MS * 1000); 1282 1283 HAL_REG_WRITE(soc, 1284 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1285 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1286 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1287 1288 HAL_REG_WRITE(soc, 1289 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1290 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1291 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1292 1293 HAL_REG_WRITE(soc, 1294 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1295 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1296 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1297 1298 /* 1299 * When hash based routing is enabled, routing of the rx packet 1300 * is done based on the following value: 1 _ _ _ _ The last 4 1301 * bits are based on hash[3:0]. This means the possible values 1302 * are 0x10 to 0x1f. This value is used to look-up the 1303 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1304 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1305 * registers need to be configured to set-up the 16 entries to 1306 * map the hash values to a ring number. There are 3 bits per 1307 * hash entry – which are mapped as follows: 1308 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1309 * 7: NOT_USED. 1310 */ 1311 if (reo_params->rx_hash_enabled) { 1312 HAL_REG_WRITE(soc, 1313 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1314 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1315 reo_params->remap1); 1316 1317 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1318 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), 1319 HAL_REG_READ(soc, 1320 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1321 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1322 1323 HAL_REG_WRITE(soc, 1324 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1325 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1326 reo_params->remap2); 1327 1328 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1329 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), 1330 HAL_REG_READ(soc, 1331 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1332 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1333 } 1334 1335 1336 /* TODO: Check if the following registers shoould be setup by host: 1337 * AGING_CONTROL 1338 * HIGH_MEMORY_THRESHOLD 1339 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1340 * GLOBAL_LINK_DESC_COUNT_CTRL 1341 */ 1342 } 1343 1344 /** 1345 * hal_srng_src_hw_init - Private function to initialize SRNG 1346 * source ring HW 1347 * @hal_soc: HAL SOC handle 1348 * @srng: SRNG ring pointer 1349 */ 1350 static inline void hal_srng_src_hw_init_generic(void *halsoc, 1351 struct hal_srng *srng) 1352 { 1353 struct hal_soc *hal = (struct hal_soc *)halsoc; 1354 uint32_t reg_val = 0; 1355 uint64_t tp_addr = 0; 1356 1357 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1358 1359 if (srng->flags & HAL_SRNG_MSI_INTR) { 1360 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1361 srng->msi_addr & 0xffffffff); 1362 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1363 (uint64_t)(srng->msi_addr) >> 32) | 1364 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1365 MSI1_ENABLE), 1); 1366 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1367 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1368 } 1369 1370 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1371 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1372 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1373 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1374 srng->entry_size * srng->num_entries); 1375 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1376 1377 #if defined(WCSS_VERSION) && \ 1378 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1379 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1380 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1381 #else 1382 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) | 1383 SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1384 #endif 1385 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1386 1387 /** 1388 * Interrupt setup: 1389 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1390 * if level mode is required 1391 */ 1392 reg_val = 0; 1393 1394 /* 1395 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1396 * programmed in terms of 1us resolution instead of 8us resolution as 1397 * given in MLD. 1398 */ 1399 if (srng->intr_timer_thres_us) { 1400 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1401 INTERRUPT_TIMER_THRESHOLD), 1402 srng->intr_timer_thres_us); 1403 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1404 } 1405 1406 if (srng->intr_batch_cntr_thres_entries) { 1407 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1408 BATCH_COUNTER_THRESHOLD), 1409 srng->intr_batch_cntr_thres_entries * 1410 srng->entry_size); 1411 } 1412 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1413 1414 reg_val = 0; 1415 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1416 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1417 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1418 } 1419 1420 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1421 1422 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1423 * remain 0 to avoid some WBM stability issues. Remote head/tail 1424 * pointers are not required since this ring is completely managed 1425 * by WBM HW 1426 */ 1427 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1428 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1429 ((unsigned long)(srng->u.src_ring.tp_addr) - 1430 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1431 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1432 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1433 } 1434 1435 /* Initilaize head and tail pointers to indicate ring is empty */ 1436 SRNG_SRC_REG_WRITE(srng, HP, 0); 1437 SRNG_SRC_REG_WRITE(srng, TP, 0); 1438 *(srng->u.src_ring.tp_addr) = 0; 1439 1440 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1441 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1442 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1443 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1444 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1445 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1446 1447 /* Loop count is not used for SRC rings */ 1448 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1449 1450 /* 1451 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1452 * todo: update fw_api and replace with above line 1453 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1454 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1455 */ 1456 reg_val |= 0x40; 1457 1458 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1459 1460 } 1461 1462 /** 1463 * hal_srng_dst_hw_init - Private function to initialize SRNG 1464 * destination ring HW 1465 * @hal_soc: HAL SOC handle 1466 * @srng: SRNG ring pointer 1467 */ 1468 static inline void hal_srng_dst_hw_init_generic(void *halsoc, 1469 struct hal_srng *srng) 1470 { 1471 struct hal_soc *hal = (struct hal_soc *)halsoc; 1472 uint32_t reg_val = 0; 1473 uint64_t hp_addr = 0; 1474 1475 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1476 1477 if (srng->flags & HAL_SRNG_MSI_INTR) { 1478 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1479 srng->msi_addr & 0xffffffff); 1480 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1481 (uint64_t)(srng->msi_addr) >> 32) | 1482 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1483 MSI1_ENABLE), 1); 1484 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1485 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1486 } 1487 1488 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1489 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1490 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1491 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1492 srng->entry_size * srng->num_entries); 1493 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1494 1495 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1496 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1497 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1498 1499 1500 /** 1501 * Interrupt setup: 1502 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1503 * if level mode is required 1504 */ 1505 reg_val = 0; 1506 if (srng->intr_timer_thres_us) { 1507 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1508 INTERRUPT_TIMER_THRESHOLD), 1509 srng->intr_timer_thres_us >> 3); 1510 } 1511 1512 if (srng->intr_batch_cntr_thres_entries) { 1513 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1514 BATCH_COUNTER_THRESHOLD), 1515 srng->intr_batch_cntr_thres_entries * 1516 srng->entry_size); 1517 } 1518 1519 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1520 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1521 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1522 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1523 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1524 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1525 1526 /* Initilaize head and tail pointers to indicate ring is empty */ 1527 SRNG_DST_REG_WRITE(srng, HP, 0); 1528 SRNG_DST_REG_WRITE(srng, TP, 0); 1529 *(srng->u.dst_ring.hp_addr) = 0; 1530 1531 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1532 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1533 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1534 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1535 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1536 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1537 1538 /* 1539 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1540 * todo: update fw_api and replace with above line 1541 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1542 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1543 */ 1544 reg_val |= 0x40; 1545 1546 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1547 1548 } 1549 1550 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1551 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1552 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1553 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1554 1555 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1556 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1557 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1558 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1559 1560 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1561 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1562 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1563 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1564 1565 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1566 (((*(((uint32_t *) wbm_desc) + \ 1567 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1568 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1569 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1570 1571 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1572 (((*(((uint32_t *) wbm_desc) + \ 1573 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1574 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1575 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1576 1577 /** 1578 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1579 * save it to hal_wbm_err_desc_info structure passed by caller 1580 * @wbm_desc: wbm ring descriptor 1581 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1582 * Return: void 1583 */ 1584 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1585 void *wbm_er_info1) 1586 { 1587 struct hal_wbm_err_desc_info *wbm_er_info = 1588 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1589 1590 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1591 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1592 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1593 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1594 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1595 } 1596 1597 /** 1598 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1599 * @hal_desc: completion ring descriptor pointer 1600 * 1601 * This function will return the type of pointer - buffer or descriptor 1602 * 1603 * Return: buffer type 1604 */ 1605 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1606 { 1607 uint32_t comp_desc = 1608 *(uint32_t *) (((uint8_t *) hal_desc) + 1609 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1610 1611 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1612 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1613 } 1614 1615 /** 1616 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1617 * human readable format. 1618 * @mpdu_start: pointer the rx_attention TLV in pkt. 1619 * @dbg_level: log level. 1620 * 1621 * Return: void 1622 */ 1623 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1624 uint8_t dbg_level) 1625 { 1626 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1627 struct rx_mpdu_info *mpdu_info = 1628 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1629 1630 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1631 "rx_mpdu_start tlv - " 1632 "rxpcu_mpdu_filter_in_category: %d " 1633 "sw_frame_group_id: %d " 1634 "ndp_frame: %d " 1635 "phy_err: %d " 1636 "phy_err_during_mpdu_header: %d " 1637 "protocol_version_err: %d " 1638 "ast_based_lookup_valid: %d " 1639 "phy_ppdu_id: %d " 1640 "ast_index: %d " 1641 "sw_peer_id: %d " 1642 "mpdu_frame_control_valid: %d " 1643 "mpdu_duration_valid: %d " 1644 "mac_addr_ad1_valid: %d " 1645 "mac_addr_ad2_valid: %d " 1646 "mac_addr_ad3_valid: %d " 1647 "mac_addr_ad4_valid: %d " 1648 "mpdu_sequence_control_valid: %d " 1649 "mpdu_qos_control_valid: %d " 1650 "mpdu_ht_control_valid: %d " 1651 "frame_encryption_info_valid: %d " 1652 "fr_ds: %d " 1653 "to_ds: %d " 1654 "encrypted: %d " 1655 "mpdu_retry: %d " 1656 "mpdu_sequence_number: %d " 1657 "epd_en: %d " 1658 "all_frames_shall_be_encrypted: %d " 1659 "encrypt_type: %d " 1660 "mesh_sta: %d " 1661 "bssid_hit: %d " 1662 "bssid_number: %d " 1663 "tid: %d " 1664 "pn_31_0: %d " 1665 "pn_63_32: %d " 1666 "pn_95_64: %d " 1667 "pn_127_96: %d " 1668 "peer_meta_data: %d " 1669 "rxpt_classify_info.reo_destination_indication: %d " 1670 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %d " 1671 "rx_reo_queue_desc_addr_31_0: %d " 1672 "rx_reo_queue_desc_addr_39_32: %d " 1673 "receive_queue_number: %d " 1674 "pre_delim_err_warning: %d " 1675 "first_delim_err: %d " 1676 "key_id_octet: %d " 1677 "new_peer_entry: %d " 1678 "decrypt_needed: %d " 1679 "decap_type: %d " 1680 "rx_insert_vlan_c_tag_padding: %d " 1681 "rx_insert_vlan_s_tag_padding: %d " 1682 "strip_vlan_c_tag_decap: %d " 1683 "strip_vlan_s_tag_decap: %d " 1684 "pre_delim_count: %d " 1685 "ampdu_flag: %d " 1686 "bar_frame: %d " 1687 "mpdu_length: %d " 1688 "first_mpdu: %d " 1689 "mcast_bcast: %d " 1690 "ast_index_not_found: %d " 1691 "ast_index_timeout: %d " 1692 "power_mgmt: %d " 1693 "non_qos: %d " 1694 "null_data: %d " 1695 "mgmt_type: %d " 1696 "ctrl_type: %d " 1697 "more_data: %d " 1698 "eosp: %d " 1699 "fragment_flag: %d " 1700 "order: %d " 1701 "u_apsd_trigger: %d " 1702 "encrypt_required: %d " 1703 "directed: %d " 1704 "mpdu_frame_control_field: %d " 1705 "mpdu_duration_field: %d " 1706 "mac_addr_ad1_31_0: %d " 1707 "mac_addr_ad1_47_32: %d " 1708 "mac_addr_ad2_15_0: %d " 1709 "mac_addr_ad2_47_16: %d " 1710 "mac_addr_ad3_31_0: %d " 1711 "mac_addr_ad3_47_32: %d " 1712 "mpdu_sequence_control_field: %d " 1713 "mac_addr_ad4_31_0: %d " 1714 "mac_addr_ad4_47_32: %d " 1715 "mpdu_qos_control_field: %d " 1716 "mpdu_ht_control_field: %d ", 1717 mpdu_info->rxpcu_mpdu_filter_in_category, 1718 mpdu_info->sw_frame_group_id, 1719 mpdu_info->ndp_frame, 1720 mpdu_info->phy_err, 1721 mpdu_info->phy_err_during_mpdu_header, 1722 mpdu_info->protocol_version_err, 1723 mpdu_info->ast_based_lookup_valid, 1724 mpdu_info->phy_ppdu_id, 1725 mpdu_info->ast_index, 1726 mpdu_info->sw_peer_id, 1727 mpdu_info->mpdu_frame_control_valid, 1728 mpdu_info->mpdu_duration_valid, 1729 mpdu_info->mac_addr_ad1_valid, 1730 mpdu_info->mac_addr_ad2_valid, 1731 mpdu_info->mac_addr_ad3_valid, 1732 mpdu_info->mac_addr_ad4_valid, 1733 mpdu_info->mpdu_sequence_control_valid, 1734 mpdu_info->mpdu_qos_control_valid, 1735 mpdu_info->mpdu_ht_control_valid, 1736 mpdu_info->frame_encryption_info_valid, 1737 mpdu_info->fr_ds, 1738 mpdu_info->to_ds, 1739 mpdu_info->encrypted, 1740 mpdu_info->mpdu_retry, 1741 mpdu_info->mpdu_sequence_number, 1742 mpdu_info->epd_en, 1743 mpdu_info->all_frames_shall_be_encrypted, 1744 mpdu_info->encrypt_type, 1745 mpdu_info->mesh_sta, 1746 mpdu_info->bssid_hit, 1747 mpdu_info->bssid_number, 1748 mpdu_info->tid, 1749 mpdu_info->pn_31_0, 1750 mpdu_info->pn_63_32, 1751 mpdu_info->pn_95_64, 1752 mpdu_info->pn_127_96, 1753 mpdu_info->peer_meta_data, 1754 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1755 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1756 mpdu_info->rx_reo_queue_desc_addr_31_0, 1757 mpdu_info->rx_reo_queue_desc_addr_39_32, 1758 mpdu_info->receive_queue_number, 1759 mpdu_info->pre_delim_err_warning, 1760 mpdu_info->first_delim_err, 1761 mpdu_info->key_id_octet, 1762 mpdu_info->new_peer_entry, 1763 mpdu_info->decrypt_needed, 1764 mpdu_info->decap_type, 1765 mpdu_info->rx_insert_vlan_c_tag_padding, 1766 mpdu_info->rx_insert_vlan_s_tag_padding, 1767 mpdu_info->strip_vlan_c_tag_decap, 1768 mpdu_info->strip_vlan_s_tag_decap, 1769 mpdu_info->pre_delim_count, 1770 mpdu_info->ampdu_flag, 1771 mpdu_info->bar_frame, 1772 mpdu_info->mpdu_length, 1773 mpdu_info->first_mpdu, 1774 mpdu_info->mcast_bcast, 1775 mpdu_info->ast_index_not_found, 1776 mpdu_info->ast_index_timeout, 1777 mpdu_info->power_mgmt, 1778 mpdu_info->non_qos, 1779 mpdu_info->null_data, 1780 mpdu_info->mgmt_type, 1781 mpdu_info->ctrl_type, 1782 mpdu_info->more_data, 1783 mpdu_info->eosp, 1784 mpdu_info->fragment_flag, 1785 mpdu_info->order, 1786 mpdu_info->u_apsd_trigger, 1787 mpdu_info->encrypt_required, 1788 mpdu_info->directed, 1789 mpdu_info->mpdu_frame_control_field, 1790 mpdu_info->mpdu_duration_field, 1791 mpdu_info->mac_addr_ad1_31_0, 1792 mpdu_info->mac_addr_ad1_47_32, 1793 mpdu_info->mac_addr_ad2_15_0, 1794 mpdu_info->mac_addr_ad2_47_16, 1795 mpdu_info->mac_addr_ad3_31_0, 1796 mpdu_info->mac_addr_ad3_47_32, 1797 mpdu_info->mpdu_sequence_control_field, 1798 mpdu_info->mac_addr_ad4_31_0, 1799 mpdu_info->mac_addr_ad4_47_32, 1800 mpdu_info->mpdu_qos_control_field, 1801 mpdu_info->mpdu_ht_control_field); 1802 } 1803 #endif 1804 1805 /** 1806 * hal_tx_desc_set_search_type - Set the search type value 1807 * @desc: Handle to Tx Descriptor 1808 * @search_type: search type 1809 * 0 – Normal search 1810 * 1 – Index based address search 1811 * 2 – Index based flow search 1812 * 1813 * Return: void 1814 */ 1815 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 1816 static void hal_tx_desc_set_search_type_generic(void *desc, 1817 uint8_t search_type) 1818 { 1819 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 1820 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 1821 } 1822 #else 1823 static void hal_tx_desc_set_search_type_generic(void *desc, 1824 uint8_t search_type) 1825 { 1826 } 1827 1828 #endif 1829 1830 /** 1831 * hal_tx_desc_set_search_index - Set the search index value 1832 * @desc: Handle to Tx Descriptor 1833 * @search_index: The index that will be used for index based address or 1834 * flow search. The field is valid when 'search_type' is 1835 * 1 0r 2 1836 * 1837 * Return: void 1838 */ 1839 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 1840 static void hal_tx_desc_set_search_index_generic(void *desc, 1841 uint32_t search_index) 1842 { 1843 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 1844 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 1845 } 1846 #else 1847 static void hal_tx_desc_set_search_index_generic(void *desc, 1848 uint32_t search_index) 1849 { 1850 } 1851 #endif 1852