1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 23 /** 24 * hal_tx_comp_get_status() - TQM Release reason 25 * @hal_desc: completion ring Tx status 26 * 27 * This function will parse the WBM completion descriptor and populate in 28 * HAL structure 29 * 30 * Return: none 31 */ 32 static inline 33 void hal_tx_comp_get_status_generic(void *desc, 34 void *ts1, 35 struct hal_soc *hal) 36 { 37 uint8_t rate_stats_valid = 0; 38 uint32_t rate_stats = 0; 39 struct hal_tx_completion_status *ts = 40 (struct hal_tx_completion_status *)ts1; 41 42 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 43 TQM_STATUS_NUMBER); 44 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 45 ACK_FRAME_RSSI); 46 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 47 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 48 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 49 MSDU_PART_OF_AMSDU); 50 51 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 52 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 53 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 54 TRANSMIT_COUNT); 55 56 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 57 TX_RATE_STATS); 58 59 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 60 TX_RATE_STATS_INFO_VALID, rate_stats); 61 62 ts->valid = rate_stats_valid; 63 64 if (rate_stats_valid) { 65 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 66 rate_stats); 67 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 68 TRANSMIT_PKT_TYPE, rate_stats); 69 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 70 TRANSMIT_STBC, rate_stats); 71 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 72 rate_stats); 73 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 74 rate_stats); 75 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 76 rate_stats); 77 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 78 rate_stats); 79 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 80 rate_stats); 81 } 82 83 ts->release_src = hal_tx_comp_get_buffer_source(desc); 84 ts->status = hal_tx_comp_get_release_reason( 85 desc, 86 hal_soc_to_hal_soc_handle(hal)); 87 88 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 89 TX_RATE_STATS_INFO_TX_RATE_STATS); 90 } 91 92 /** 93 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 94 * @desc: Handle to Tx Descriptor 95 * @paddr: Physical Address 96 * @pool_id: Return Buffer Manager ID 97 * @desc_id: Descriptor ID 98 * @type: 0 - Address points to a MSDU buffer 99 * 1 - Address points to MSDU extension descriptor 100 * 101 * Return: void 102 */ 103 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 104 dma_addr_t paddr, uint8_t rbm_id, 105 uint32_t desc_id, uint8_t type) 106 { 107 /* Set buffer_addr_info.buffer_addr_31_0 */ 108 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 109 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 110 111 /* Set buffer_addr_info.buffer_addr_39_32 */ 112 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 113 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 114 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 115 (((uint64_t) paddr) >> 32)); 116 117 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 118 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 119 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 120 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 121 RETURN_BUFFER_MANAGER, rbm_id); 122 123 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 124 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 125 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 126 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 127 128 /* Set Buffer or Ext Descriptor Type */ 129 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 130 BUF_OR_EXT_DESC_TYPE) |= 131 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 132 } 133 134 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 135 /** 136 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 137 * tlv_tag: Taf of the TLVs 138 * rx_tlv: the pointer to the TLVs 139 * @ppdu_info: pointer to ppdu_info 140 * 141 * Return: true if the tlv is handled, false if not 142 */ 143 static inline bool 144 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 145 struct hal_rx_ppdu_info *ppdu_info) 146 { 147 uint32_t value; 148 149 switch (tlv_tag) { 150 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 151 { 152 uint8_t *he_sig_a_mu_ul_info = 153 (uint8_t *)rx_tlv + 154 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 155 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 156 ppdu_info->rx_status.he_flags = 1; 157 158 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 159 FORMAT_INDICATION); 160 if (value == 0) { 161 ppdu_info->rx_status.he_data1 = 162 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 163 } else { 164 ppdu_info->rx_status.he_data1 = 165 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 166 } 167 168 /* data1 */ 169 ppdu_info->rx_status.he_data1 |= 170 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 171 QDF_MON_STATUS_HE_DL_UL_KNOWN | 172 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 173 174 /* data2 */ 175 ppdu_info->rx_status.he_data2 |= 176 QDF_MON_STATUS_TXOP_KNOWN; 177 178 /*data3*/ 179 value = HAL_RX_GET(he_sig_a_mu_ul_info, 180 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 181 ppdu_info->rx_status.he_data3 = value; 182 /* 1 for UL and 0 for DL */ 183 value = 1; 184 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 185 ppdu_info->rx_status.he_data3 |= value; 186 187 /*data4*/ 188 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 189 SPATIAL_REUSE); 190 ppdu_info->rx_status.he_data4 = value; 191 192 /*data5*/ 193 value = HAL_RX_GET(he_sig_a_mu_ul_info, 194 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 195 ppdu_info->rx_status.he_data5 = value; 196 ppdu_info->rx_status.bw = value; 197 198 /*data6*/ 199 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 200 TXOP_DURATION); 201 value = value << QDF_MON_STATUS_TXOP_SHIFT; 202 ppdu_info->rx_status.he_data6 |= value; 203 return true; 204 } 205 default: 206 return false; 207 } 208 } 209 #else 210 static inline bool 211 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 212 struct hal_rx_ppdu_info *ppdu_info) 213 { 214 return false; 215 } 216 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 217 218 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 219 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 220 221 static inline void 222 hal_rx_handle_mu_ul_info( 223 void *rx_tlv, 224 struct mon_rx_user_status *mon_rx_user_status) 225 { 226 mon_rx_user_status->mu_ul_user_v0_word0 = 227 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 228 SW_RESPONSE_REFERENCE_PTR); 229 230 mon_rx_user_status->mu_ul_user_v0_word1 = 231 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 232 SW_RESPONSE_REFERENCE_PTR_EXT); 233 } 234 235 static inline void 236 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 237 struct mon_rx_user_status *mon_rx_user_status) 238 { 239 uint32_t mpdu_ok_byte_count; 240 uint32_t mpdu_err_byte_count; 241 242 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 243 RX_PPDU_END_USER_STATS_17, 244 MPDU_OK_BYTE_COUNT); 245 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 246 RX_PPDU_END_USER_STATS_19, 247 MPDU_ERR_BYTE_COUNT); 248 249 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 250 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 251 } 252 #else 253 static inline void 254 hal_rx_handle_mu_ul_info(void *rx_tlv, 255 struct mon_rx_user_status *mon_rx_user_status) 256 { 257 } 258 259 static inline void 260 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 261 struct mon_rx_user_status *mon_rx_user_status) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = 264 (struct hal_rx_ppdu_info *)ppduinfo; 265 266 /* HKV1: doesn't support mpdu byte count */ 267 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 268 mon_rx_user_status->mpdu_err_byte_count = 0; 269 } 270 #endif 271 272 static inline void 273 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, 274 struct mon_rx_user_status *mon_rx_user_status) 275 { 276 struct hal_rx_ppdu_info *ppdu_info = 277 (struct hal_rx_ppdu_info *)ppduinfo; 278 279 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 280 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 281 mon_rx_user_status->tcp_msdu_count = 282 ppdu_info->rx_status.tcp_msdu_count; 283 mon_rx_user_status->udp_msdu_count = 284 ppdu_info->rx_status.udp_msdu_count; 285 mon_rx_user_status->other_msdu_count = 286 ppdu_info->rx_status.other_msdu_count; 287 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 288 mon_rx_user_status->frame_control_info_valid = 289 ppdu_info->rx_status.frame_control_info_valid; 290 mon_rx_user_status->data_sequence_control_info_valid = 291 ppdu_info->rx_status.data_sequence_control_info_valid; 292 mon_rx_user_status->first_data_seq_ctrl = 293 ppdu_info->rx_status.first_data_seq_ctrl; 294 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 295 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 296 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 297 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 298 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 299 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 300 301 mon_rx_user_status->mpdu_cnt_fcs_ok = 302 ppdu_info->com_info.mpdu_cnt_fcs_ok; 303 mon_rx_user_status->mpdu_cnt_fcs_err = 304 ppdu_info->com_info.mpdu_cnt_fcs_err; 305 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 306 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 307 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 308 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 309 310 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 311 } 312 313 #ifdef WLAN_TX_PKT_CAPTURE_ENH 314 static inline void 315 hal_rx_populate_tx_capture_user_info(void *ppduinfo, 316 uint32_t user_id) 317 { 318 struct hal_rx_ppdu_info *ppdu_info; 319 struct mon_rx_info *mon_rx_info; 320 struct mon_rx_user_info *mon_rx_user_info; 321 322 ppdu_info = (struct hal_rx_ppdu_info *)ppduinfo; 323 mon_rx_info = &ppdu_info->rx_info; 324 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 325 mon_rx_user_info->qos_control_info_valid = 326 mon_rx_info->qos_control_info_valid; 327 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 328 } 329 #else 330 static inline void 331 hal_rx_populate_tx_capture_user_info(void *ppduinfo, 332 uint32_t user_id) 333 { 334 } 335 #endif 336 337 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 338 ppdu_info, rssi_info_tlv) \ 339 { \ 340 ppdu_info->rx_status.rssi_chain[chain][0] = \ 341 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 342 RSSI_PRI20_CHAIN##chain); \ 343 ppdu_info->rx_status.rssi_chain[chain][1] = \ 344 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 345 RSSI_EXT20_CHAIN##chain); \ 346 ppdu_info->rx_status.rssi_chain[chain][2] = \ 347 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 348 RSSI_EXT40_LOW20_CHAIN##chain); \ 349 ppdu_info->rx_status.rssi_chain[chain][3] = \ 350 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 351 RSSI_EXT40_HIGH20_CHAIN##chain); \ 352 ppdu_info->rx_status.rssi_chain[chain][4] = \ 353 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 354 RSSI_EXT80_LOW20_CHAIN##chain); \ 355 ppdu_info->rx_status.rssi_chain[chain][5] = \ 356 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 357 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 358 ppdu_info->rx_status.rssi_chain[chain][6] = \ 359 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 360 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 361 ppdu_info->rx_status.rssi_chain[chain][7] = \ 362 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 363 RSSI_EXT80_HIGH20_CHAIN##chain); \ 364 } \ 365 366 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 367 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 368 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 369 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 370 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 371 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 372 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 373 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 374 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 375 376 static inline uint32_t 377 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 378 uint8_t *rssi_info_tlv) 379 { 380 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 381 return 0; 382 } 383 384 #ifdef WLAN_TX_PKT_CAPTURE_ENH 385 static inline void 386 hal_get_qos_control(void *rx_tlv, 387 struct hal_rx_ppdu_info *ppdu_info) 388 { 389 ppdu_info->rx_info.qos_control_info_valid = 390 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 391 QOS_CONTROL_INFO_VALID); 392 393 if (ppdu_info->rx_info.qos_control_info_valid) 394 ppdu_info->rx_info.qos_control = 395 HAL_RX_GET(rx_tlv, 396 RX_PPDU_END_USER_STATS_5, 397 QOS_CONTROL_FIELD); 398 } 399 400 static inline void 401 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 402 struct hal_rx_ppdu_info *ppdu_info) 403 { 404 if ((ppdu_info->sw_frame_group_id 405 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 406 (ppdu_info->sw_frame_group_id == 407 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 408 ppdu_info->rx_info.mac_addr1_valid = 409 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 410 411 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 412 HAL_RX_GET(rx_mpdu_start, 413 RX_MPDU_INFO_15, 414 MAC_ADDR_AD1_31_0); 415 if (ppdu_info->sw_frame_group_id == 416 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 417 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 418 HAL_RX_GET(rx_mpdu_start, 419 RX_MPDU_INFO_16, 420 MAC_ADDR_AD1_47_32); 421 } 422 } 423 } 424 #else 425 static inline void 426 hal_get_qos_control(void *rx_tlv, 427 struct hal_rx_ppdu_info *ppdu_info) 428 { 429 } 430 431 static inline void 432 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 433 struct hal_rx_ppdu_info *ppdu_info) 434 { 435 } 436 #endif 437 438 /** 439 * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value 440 * from stats enum to radiotap enum 441 * @he_gi: HE GI value used in stats 442 * @he_ltf: HE LTF value used in stats 443 * 444 * Return: void 445 */ 446 static inline void hal_get_radiotap_he_gi_ltf(uint16_t *he_gi, uint16_t *he_ltf) 447 { 448 switch (*he_gi) { 449 case HE_GI_0_8: 450 *he_gi = HE_GI_RADIOTAP_0_8; 451 break; 452 case HE_GI_1_6: 453 *he_gi = HE_GI_RADIOTAP_1_6; 454 break; 455 case HE_GI_3_2: 456 *he_gi = HE_GI_RADIOTAP_3_2; 457 break; 458 default: 459 *he_gi = HE_GI_RADIOTAP_RESERVED; 460 } 461 462 switch (*he_ltf) { 463 case HE_LTF_1_X: 464 *he_ltf = HE_LTF_RADIOTAP_1_X; 465 break; 466 case HE_LTF_2_X: 467 *he_ltf = HE_LTF_RADIOTAP_2_X; 468 break; 469 case HE_LTF_4_X: 470 *he_ltf = HE_LTF_RADIOTAP_4_X; 471 break; 472 default: 473 *he_ltf = HE_LTF_RADIOTAP_UNKNOWN; 474 } 475 } 476 477 /* channel number to freq conversion */ 478 #define CHANNEL_NUM_14 14 479 #define CHANNEL_NUM_15 15 480 #define CHANNEL_NUM_27 27 481 #define CHANNEL_NUM_35 35 482 #define CHANNEL_NUM_182 182 483 #define CHANNEL_NUM_197 197 484 #define CHANNEL_FREQ_2484 2484 485 #define CHANNEL_FREQ_2407 2407 486 #define CHANNEL_FREQ_2512 2512 487 #define CHANNEL_FREQ_5000 5000 488 #define CHANNEL_FREQ_5940 5940 489 #define CHANNEL_FREQ_4000 4000 490 #define CHANNEL_FREQ_5150 5150 491 #define FREQ_MULTIPLIER_CONST_5MHZ 5 492 #define FREQ_MULTIPLIER_CONST_20MHZ 20 493 /** 494 * hal_rx_radiotap_num_to_freq() - Get frequency from chan number 495 * @chan_num - Input channel number 496 * @center_freq - Input Channel Center frequency 497 * 498 * Return - Channel frequency in Mhz 499 */ 500 static uint16_t 501 hal_rx_radiotap_num_to_freq(uint16_t chan_num, qdf_freq_t center_freq) 502 { 503 if (center_freq < CHANNEL_FREQ_5940) { 504 if (chan_num == CHANNEL_NUM_14) 505 return CHANNEL_FREQ_2484; 506 if (chan_num < CHANNEL_NUM_14) 507 return CHANNEL_FREQ_2407 + 508 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 509 510 if (chan_num < CHANNEL_NUM_27) 511 return CHANNEL_FREQ_2512 + 512 ((chan_num - CHANNEL_NUM_15) * 513 FREQ_MULTIPLIER_CONST_20MHZ); 514 515 if (chan_num > CHANNEL_NUM_182 && 516 chan_num < CHANNEL_NUM_197) 517 return ((chan_num * FREQ_MULTIPLIER_CONST_5MHZ) + 518 CHANNEL_FREQ_4000); 519 520 return CHANNEL_FREQ_5000 + 521 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 522 } else { 523 return CHANNEL_FREQ_5940 + 524 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 525 } 526 } 527 528 /** 529 * hal_rx_status_get_tlv_info() - process receive info TLV 530 * @rx_tlv_hdr: pointer to TLV header 531 * @ppdu_info: pointer to ppdu_info 532 * 533 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 534 */ 535 static inline uint32_t 536 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 537 hal_soc_handle_t hal_soc_hdl, 538 qdf_nbuf_t nbuf) 539 { 540 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 541 uint32_t tlv_tag, user_id, tlv_len, value; 542 uint8_t group_id = 0; 543 uint8_t he_dcm = 0; 544 uint8_t he_stbc = 0; 545 uint16_t he_gi = 0; 546 uint16_t he_ltf = 0; 547 void *rx_tlv; 548 bool unhandled = false; 549 struct mon_rx_user_status *mon_rx_user_status; 550 struct hal_rx_ppdu_info *ppdu_info = 551 (struct hal_rx_ppdu_info *)ppduinfo; 552 553 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 554 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 555 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 556 557 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 558 559 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 560 rx_tlv, tlv_len); 561 562 switch (tlv_tag) { 563 564 case WIFIRX_PPDU_START_E: 565 { 566 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 567 568 ppdu_info->com_info.ppdu_id = 569 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 570 PHY_PPDU_ID); 571 /* channel number is set in PHY meta data */ 572 ppdu_info->rx_status.chan_num = 573 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 574 SW_PHY_META_DATA) & 0x0000FFFF); 575 ppdu_info->rx_status.chan_freq = 576 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 577 SW_PHY_META_DATA) & 0xFFFF0000)>>16; 578 if (ppdu_info->rx_status.chan_num && 579 ppdu_info->rx_status.chan_freq) { 580 ppdu_info->rx_status.chan_freq = 581 hal_rx_radiotap_num_to_freq( 582 ppdu_info->rx_status.chan_num, 583 ppdu_info->rx_status.chan_freq); 584 } 585 ppdu_info->com_info.ppdu_timestamp = 586 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 587 PPDU_START_TIMESTAMP); 588 ppdu_info->rx_status.ppdu_timestamp = 589 ppdu_info->com_info.ppdu_timestamp; 590 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 591 592 /* If last ppdu_id doesn't match new ppdu_id, 593 * 1. reset mpdu_cnt 594 * 2. update last_ppdu_id with new 595 * 3. reset mpdu fcs bitmap 596 */ 597 if (com_info->ppdu_id != com_info->last_ppdu_id) { 598 com_info->mpdu_cnt = 0; 599 com_info->last_ppdu_id = 600 com_info->ppdu_id; 601 com_info->num_users = 0; 602 qdf_mem_zero(&com_info->mpdu_fcs_ok_bitmap, 603 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 604 sizeof(com_info->mpdu_fcs_ok_bitmap[0])); 605 } 606 break; 607 } 608 609 case WIFIRX_PPDU_START_USER_INFO_E: 610 break; 611 612 case WIFIRX_PPDU_END_E: 613 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 614 "[%s][%d] ppdu_end_e len=%d", 615 __func__, __LINE__, tlv_len); 616 /* This is followed by sub-TLVs of PPDU_END */ 617 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 618 break; 619 620 case WIFIPHYRX_PKT_END_E: 621 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 622 break; 623 624 case WIFIRXPCU_PPDU_END_INFO_E: 625 ppdu_info->rx_status.rx_antenna = 626 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 627 ppdu_info->rx_status.tsft = 628 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 629 WB_TIMESTAMP_UPPER_32); 630 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 631 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 632 WB_TIMESTAMP_LOWER_32); 633 ppdu_info->rx_status.duration = 634 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 635 RX_PPDU_DURATION); 636 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 637 break; 638 639 /* 640 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 641 * for MU, based on num users we see this tlv that many times. 642 */ 643 case WIFIRX_PPDU_END_USER_STATS_E: 644 { 645 unsigned long tid = 0; 646 uint16_t seq = 0; 647 648 ppdu_info->rx_status.ast_index = 649 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 650 AST_INDEX); 651 652 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 653 RECEIVED_QOS_DATA_TID_BITMAP); 654 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 655 656 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 657 ppdu_info->rx_status.tid = HAL_TID_INVALID; 658 659 ppdu_info->rx_status.tcp_msdu_count = 660 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 661 TCP_MSDU_COUNT) + 662 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 663 TCP_ACK_MSDU_COUNT); 664 ppdu_info->rx_status.udp_msdu_count = 665 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 666 UDP_MSDU_COUNT); 667 ppdu_info->rx_status.other_msdu_count = 668 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 669 OTHER_MSDU_COUNT); 670 671 if (ppdu_info->sw_frame_group_id 672 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 673 ppdu_info->rx_status.frame_control_info_valid = 674 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 675 FRAME_CONTROL_INFO_VALID); 676 677 if (ppdu_info->rx_status.frame_control_info_valid) 678 ppdu_info->rx_status.frame_control = 679 HAL_RX_GET(rx_tlv, 680 RX_PPDU_END_USER_STATS_4, 681 FRAME_CONTROL_FIELD); 682 683 hal_get_qos_control(rx_tlv, ppdu_info); 684 } 685 686 ppdu_info->rx_status.data_sequence_control_info_valid = 687 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 688 DATA_SEQUENCE_CONTROL_INFO_VALID); 689 690 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 691 FIRST_DATA_SEQ_CTRL); 692 if (ppdu_info->rx_status.data_sequence_control_info_valid) 693 ppdu_info->rx_status.first_data_seq_ctrl = seq; 694 695 ppdu_info->rx_status.preamble_type = 696 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 697 HT_CONTROL_FIELD_PKT_TYPE); 698 switch (ppdu_info->rx_status.preamble_type) { 699 case HAL_RX_PKT_TYPE_11N: 700 ppdu_info->rx_status.ht_flags = 1; 701 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 702 break; 703 case HAL_RX_PKT_TYPE_11AC: 704 ppdu_info->rx_status.vht_flags = 1; 705 break; 706 case HAL_RX_PKT_TYPE_11AX: 707 ppdu_info->rx_status.he_flags = 1; 708 break; 709 default: 710 break; 711 } 712 713 ppdu_info->com_info.mpdu_cnt_fcs_ok = 714 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 715 MPDU_CNT_FCS_OK); 716 ppdu_info->com_info.mpdu_cnt_fcs_err = 717 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 718 MPDU_CNT_FCS_ERR); 719 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 720 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 721 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 722 else 723 ppdu_info->rx_status.rs_flags &= 724 (~IEEE80211_AMPDU_FLAG); 725 726 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 727 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 728 FCS_OK_BITMAP_31_0); 729 730 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 731 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 732 FCS_OK_BITMAP_63_32); 733 734 if (user_id < HAL_MAX_UL_MU_USERS) { 735 mon_rx_user_status = 736 &ppdu_info->rx_user_status[user_id]; 737 738 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 739 740 ppdu_info->com_info.num_users++; 741 742 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 743 mon_rx_user_status); 744 745 hal_rx_populate_tx_capture_user_info(ppdu_info, 746 user_id); 747 748 } 749 break; 750 } 751 752 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 753 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 754 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 755 FCS_OK_BITMAP_95_64); 756 757 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 758 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 759 FCS_OK_BITMAP_127_96); 760 761 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 762 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 763 FCS_OK_BITMAP_159_128); 764 765 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 766 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 767 FCS_OK_BITMAP_191_160); 768 769 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 770 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 771 FCS_OK_BITMAP_223_192); 772 773 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 774 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 775 FCS_OK_BITMAP_255_224); 776 break; 777 778 case WIFIRX_PPDU_END_STATUS_DONE_E: 779 return HAL_TLV_STATUS_PPDU_DONE; 780 781 case WIFIDUMMY_E: 782 return HAL_TLV_STATUS_BUF_DONE; 783 784 case WIFIPHYRX_HT_SIG_E: 785 { 786 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 787 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 788 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 789 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 790 FEC_CODING); 791 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 792 1 : 0; 793 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 794 HT_SIG_INFO_0, MCS); 795 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 796 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 797 HT_SIG_INFO_0, CBW); 798 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 799 HT_SIG_INFO_1, SHORT_GI); 800 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 801 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 802 HT_SIG_SU_NSS_SHIFT) + 1; 803 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 804 break; 805 } 806 807 case WIFIPHYRX_L_SIG_B_E: 808 { 809 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 810 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 811 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 812 813 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 814 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 815 switch (value) { 816 case 1: 817 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 818 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 819 break; 820 case 2: 821 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 822 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 823 break; 824 case 3: 825 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 826 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 827 break; 828 case 4: 829 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 830 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 831 break; 832 case 5: 833 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 834 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 835 break; 836 case 6: 837 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 838 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 839 break; 840 case 7: 841 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 842 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 843 break; 844 default: 845 break; 846 } 847 ppdu_info->rx_status.cck_flag = 1; 848 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 849 break; 850 } 851 852 case WIFIPHYRX_L_SIG_A_E: 853 { 854 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 855 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 856 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 857 858 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 859 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 860 switch (value) { 861 case 8: 862 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 863 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 864 break; 865 case 9: 866 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 867 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 868 break; 869 case 10: 870 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 871 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 872 break; 873 case 11: 874 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 875 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 876 break; 877 case 12: 878 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 879 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 880 break; 881 case 13: 882 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 883 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 884 break; 885 case 14: 886 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 887 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 888 break; 889 case 15: 890 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 891 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 892 break; 893 default: 894 break; 895 } 896 ppdu_info->rx_status.ofdm_flag = 1; 897 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 898 break; 899 } 900 901 case WIFIPHYRX_VHT_SIG_A_E: 902 { 903 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 904 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 905 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 906 907 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 908 SU_MU_CODING); 909 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 910 1 : 0; 911 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 912 ppdu_info->rx_status.vht_flag_values5 = group_id; 913 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 914 VHT_SIG_A_INFO_1, MCS); 915 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 916 VHT_SIG_A_INFO_1, GI_SETTING); 917 918 switch (hal->target_type) { 919 case TARGET_TYPE_QCA8074: 920 case TARGET_TYPE_QCA8074V2: 921 case TARGET_TYPE_QCA6018: 922 case TARGET_TYPE_QCA5018: 923 case TARGET_TYPE_QCN9000: 924 #ifdef QCA_WIFI_QCA6390 925 case TARGET_TYPE_QCA6390: 926 #endif 927 ppdu_info->rx_status.is_stbc = 928 HAL_RX_GET(vht_sig_a_info, 929 VHT_SIG_A_INFO_0, STBC); 930 value = HAL_RX_GET(vht_sig_a_info, 931 VHT_SIG_A_INFO_0, N_STS); 932 value = value & VHT_SIG_SU_NSS_MASK; 933 if (ppdu_info->rx_status.is_stbc && (value > 0)) 934 value = ((value + 1) >> 1) - 1; 935 ppdu_info->rx_status.nss = 936 ((value & VHT_SIG_SU_NSS_MASK) + 1); 937 938 break; 939 case TARGET_TYPE_QCA6290: 940 #if !defined(QCA_WIFI_QCA6290_11AX) 941 ppdu_info->rx_status.is_stbc = 942 HAL_RX_GET(vht_sig_a_info, 943 VHT_SIG_A_INFO_0, STBC); 944 value = HAL_RX_GET(vht_sig_a_info, 945 VHT_SIG_A_INFO_0, N_STS); 946 value = value & VHT_SIG_SU_NSS_MASK; 947 if (ppdu_info->rx_status.is_stbc && (value > 0)) 948 value = ((value + 1) >> 1) - 1; 949 ppdu_info->rx_status.nss = 950 ((value & VHT_SIG_SU_NSS_MASK) + 1); 951 #else 952 ppdu_info->rx_status.nss = 0; 953 #endif 954 break; 955 case TARGET_TYPE_QCA6490: 956 case TARGET_TYPE_QCA6750: 957 ppdu_info->rx_status.nss = 0; 958 break; 959 default: 960 break; 961 } 962 ppdu_info->rx_status.vht_flag_values3[0] = 963 (((ppdu_info->rx_status.mcs) << 4) 964 | ppdu_info->rx_status.nss); 965 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 966 VHT_SIG_A_INFO_0, BANDWIDTH); 967 ppdu_info->rx_status.vht_flag_values2 = 968 ppdu_info->rx_status.bw; 969 ppdu_info->rx_status.vht_flag_values4 = 970 HAL_RX_GET(vht_sig_a_info, 971 VHT_SIG_A_INFO_1, SU_MU_CODING); 972 973 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 974 VHT_SIG_A_INFO_1, BEAMFORMED); 975 if (group_id == 0 || group_id == 63) 976 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 977 else 978 ppdu_info->rx_status.reception_type = 979 HAL_RX_TYPE_MU_MIMO; 980 981 break; 982 } 983 case WIFIPHYRX_HE_SIG_A_SU_E: 984 { 985 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 986 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 987 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 988 ppdu_info->rx_status.he_flags = 1; 989 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 990 FORMAT_INDICATION); 991 if (value == 0) { 992 ppdu_info->rx_status.he_data1 = 993 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 994 } else { 995 ppdu_info->rx_status.he_data1 = 996 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 997 } 998 999 /* data1 */ 1000 ppdu_info->rx_status.he_data1 |= 1001 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1002 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 1003 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1004 QDF_MON_STATUS_HE_MCS_KNOWN | 1005 QDF_MON_STATUS_HE_DCM_KNOWN | 1006 QDF_MON_STATUS_HE_CODING_KNOWN | 1007 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1008 QDF_MON_STATUS_HE_STBC_KNOWN | 1009 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1010 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1011 1012 /* data2 */ 1013 ppdu_info->rx_status.he_data2 = 1014 QDF_MON_STATUS_HE_GI_KNOWN; 1015 ppdu_info->rx_status.he_data2 |= 1016 QDF_MON_STATUS_TXBF_KNOWN | 1017 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1018 QDF_MON_STATUS_TXOP_KNOWN | 1019 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1020 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1021 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1022 1023 /* data3 */ 1024 value = HAL_RX_GET(he_sig_a_su_info, 1025 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1026 ppdu_info->rx_status.he_data3 = value; 1027 value = HAL_RX_GET(he_sig_a_su_info, 1028 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1029 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1030 ppdu_info->rx_status.he_data3 |= value; 1031 value = HAL_RX_GET(he_sig_a_su_info, 1032 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1033 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1034 ppdu_info->rx_status.he_data3 |= value; 1035 1036 value = HAL_RX_GET(he_sig_a_su_info, 1037 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1038 ppdu_info->rx_status.mcs = value; 1039 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1040 ppdu_info->rx_status.he_data3 |= value; 1041 1042 value = HAL_RX_GET(he_sig_a_su_info, 1043 HE_SIG_A_SU_INFO_0, DCM); 1044 he_dcm = value; 1045 value = value << QDF_MON_STATUS_DCM_SHIFT; 1046 ppdu_info->rx_status.he_data3 |= value; 1047 value = HAL_RX_GET(he_sig_a_su_info, 1048 HE_SIG_A_SU_INFO_1, CODING); 1049 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1050 1 : 0; 1051 value = value << QDF_MON_STATUS_CODING_SHIFT; 1052 ppdu_info->rx_status.he_data3 |= value; 1053 value = HAL_RX_GET(he_sig_a_su_info, 1054 HE_SIG_A_SU_INFO_1, 1055 LDPC_EXTRA_SYMBOL); 1056 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1057 ppdu_info->rx_status.he_data3 |= value; 1058 value = HAL_RX_GET(he_sig_a_su_info, 1059 HE_SIG_A_SU_INFO_1, STBC); 1060 he_stbc = value; 1061 value = value << QDF_MON_STATUS_STBC_SHIFT; 1062 ppdu_info->rx_status.he_data3 |= value; 1063 1064 /* data4 */ 1065 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1066 SPATIAL_REUSE); 1067 ppdu_info->rx_status.he_data4 = value; 1068 1069 /* data5 */ 1070 value = HAL_RX_GET(he_sig_a_su_info, 1071 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1072 ppdu_info->rx_status.he_data5 = value; 1073 ppdu_info->rx_status.bw = value; 1074 value = HAL_RX_GET(he_sig_a_su_info, 1075 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1076 switch (value) { 1077 case 0: 1078 he_gi = HE_GI_0_8; 1079 he_ltf = HE_LTF_1_X; 1080 break; 1081 case 1: 1082 he_gi = HE_GI_0_8; 1083 he_ltf = HE_LTF_2_X; 1084 break; 1085 case 2: 1086 he_gi = HE_GI_1_6; 1087 he_ltf = HE_LTF_2_X; 1088 break; 1089 case 3: 1090 if (he_dcm && he_stbc) { 1091 he_gi = HE_GI_0_8; 1092 he_ltf = HE_LTF_4_X; 1093 } else { 1094 he_gi = HE_GI_3_2; 1095 he_ltf = HE_LTF_4_X; 1096 } 1097 break; 1098 } 1099 ppdu_info->rx_status.sgi = he_gi; 1100 ppdu_info->rx_status.ltf_size = he_ltf; 1101 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1102 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1103 ppdu_info->rx_status.he_data5 |= value; 1104 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1105 ppdu_info->rx_status.he_data5 |= value; 1106 1107 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1108 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1109 ppdu_info->rx_status.he_data5 |= value; 1110 1111 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1112 PACKET_EXTENSION_A_FACTOR); 1113 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1114 ppdu_info->rx_status.he_data5 |= value; 1115 1116 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1117 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1118 ppdu_info->rx_status.he_data5 |= value; 1119 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1120 PACKET_EXTENSION_PE_DISAMBIGUITY); 1121 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1122 ppdu_info->rx_status.he_data5 |= value; 1123 1124 /* data6 */ 1125 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1126 value++; 1127 ppdu_info->rx_status.nss = value; 1128 ppdu_info->rx_status.he_data6 = value; 1129 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1130 DOPPLER_INDICATION); 1131 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1132 ppdu_info->rx_status.he_data6 |= value; 1133 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1134 TXOP_DURATION); 1135 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1136 ppdu_info->rx_status.he_data6 |= value; 1137 1138 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1139 HE_SIG_A_SU_INFO_1, TXBF); 1140 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1141 break; 1142 } 1143 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1144 { 1145 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1146 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1147 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1148 1149 ppdu_info->rx_status.he_mu_flags = 1; 1150 1151 /* HE Flags */ 1152 /*data1*/ 1153 ppdu_info->rx_status.he_data1 = 1154 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1155 ppdu_info->rx_status.he_data1 |= 1156 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1157 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1158 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1159 QDF_MON_STATUS_HE_STBC_KNOWN | 1160 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1161 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1162 1163 /* data2 */ 1164 ppdu_info->rx_status.he_data2 = 1165 QDF_MON_STATUS_HE_GI_KNOWN; 1166 ppdu_info->rx_status.he_data2 |= 1167 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1168 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1169 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1170 QDF_MON_STATUS_TXOP_KNOWN | 1171 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1172 1173 /*data3*/ 1174 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1175 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1176 ppdu_info->rx_status.he_data3 = value; 1177 1178 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1179 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1180 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1181 ppdu_info->rx_status.he_data3 |= value; 1182 1183 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1184 HE_SIG_A_MU_DL_INFO_1, 1185 LDPC_EXTRA_SYMBOL); 1186 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1187 ppdu_info->rx_status.he_data3 |= value; 1188 1189 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1190 HE_SIG_A_MU_DL_INFO_1, STBC); 1191 he_stbc = value; 1192 value = value << QDF_MON_STATUS_STBC_SHIFT; 1193 ppdu_info->rx_status.he_data3 |= value; 1194 1195 /*data4*/ 1196 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1197 SPATIAL_REUSE); 1198 ppdu_info->rx_status.he_data4 = value; 1199 1200 /*data5*/ 1201 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1202 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1203 ppdu_info->rx_status.he_data5 = value; 1204 ppdu_info->rx_status.bw = value; 1205 1206 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1207 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1208 switch (value) { 1209 case 0: 1210 he_gi = HE_GI_0_8; 1211 he_ltf = HE_LTF_4_X; 1212 break; 1213 case 1: 1214 he_gi = HE_GI_0_8; 1215 he_ltf = HE_LTF_2_X; 1216 break; 1217 case 2: 1218 he_gi = HE_GI_1_6; 1219 he_ltf = HE_LTF_2_X; 1220 break; 1221 case 3: 1222 he_gi = HE_GI_3_2; 1223 he_ltf = HE_LTF_4_X; 1224 break; 1225 } 1226 ppdu_info->rx_status.sgi = he_gi; 1227 ppdu_info->rx_status.ltf_size = he_ltf; 1228 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1229 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1230 ppdu_info->rx_status.he_data5 |= value; 1231 1232 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1233 ppdu_info->rx_status.he_data5 |= value; 1234 1235 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1236 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1237 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1238 ppdu_info->rx_status.he_data5 |= value; 1239 1240 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1241 PACKET_EXTENSION_A_FACTOR); 1242 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1243 ppdu_info->rx_status.he_data5 |= value; 1244 1245 1246 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1247 PACKET_EXTENSION_PE_DISAMBIGUITY); 1248 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1249 ppdu_info->rx_status.he_data5 |= value; 1250 1251 /*data6*/ 1252 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1253 DOPPLER_INDICATION); 1254 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1255 ppdu_info->rx_status.he_data6 |= value; 1256 1257 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1258 TXOP_DURATION); 1259 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1260 ppdu_info->rx_status.he_data6 |= value; 1261 1262 /* HE-MU Flags */ 1263 /* HE-MU-flags1 */ 1264 ppdu_info->rx_status.he_flags1 = 1265 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1266 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1267 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1268 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1269 QDF_MON_STATUS_RU_0_KNOWN; 1270 1271 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1272 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1273 ppdu_info->rx_status.he_flags1 |= value; 1274 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1275 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1276 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1277 ppdu_info->rx_status.he_flags1 |= value; 1278 1279 /* HE-MU-flags2 */ 1280 ppdu_info->rx_status.he_flags2 = 1281 QDF_MON_STATUS_BW_KNOWN; 1282 1283 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1284 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1285 ppdu_info->rx_status.he_flags2 |= value; 1286 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1287 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1288 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1289 ppdu_info->rx_status.he_flags2 |= value; 1290 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1291 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1292 value = value - 1; 1293 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1294 ppdu_info->rx_status.he_flags2 |= value; 1295 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1296 break; 1297 } 1298 case WIFIPHYRX_HE_SIG_B1_MU_E: 1299 { 1300 1301 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1302 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1303 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1304 1305 ppdu_info->rx_status.he_sig_b_common_known |= 1306 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1307 /* TODO: Check on the availability of other fields in 1308 * sig_b_common 1309 */ 1310 1311 value = HAL_RX_GET(he_sig_b1_mu_info, 1312 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1313 ppdu_info->rx_status.he_RU[0] = value; 1314 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1315 break; 1316 } 1317 case WIFIPHYRX_HE_SIG_B2_MU_E: 1318 { 1319 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1320 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1321 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1322 /* 1323 * Not all "HE" fields can be updated from 1324 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1325 * to populate rest of the "HE" fields for MU scenarios. 1326 */ 1327 1328 /* HE-data1 */ 1329 ppdu_info->rx_status.he_data1 |= 1330 QDF_MON_STATUS_HE_MCS_KNOWN | 1331 QDF_MON_STATUS_HE_CODING_KNOWN; 1332 1333 /* HE-data2 */ 1334 1335 /* HE-data3 */ 1336 value = HAL_RX_GET(he_sig_b2_mu_info, 1337 HE_SIG_B2_MU_INFO_0, STA_MCS); 1338 ppdu_info->rx_status.mcs = value; 1339 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1340 ppdu_info->rx_status.he_data3 |= value; 1341 1342 1343 value = HAL_RX_GET(he_sig_b2_mu_info, 1344 HE_SIG_B2_MU_INFO_0, STA_CODING); 1345 value = value << QDF_MON_STATUS_CODING_SHIFT; 1346 ppdu_info->rx_status.he_data3 |= value; 1347 1348 /* HE-data4 */ 1349 value = HAL_RX_GET(he_sig_b2_mu_info, 1350 HE_SIG_B2_MU_INFO_0, STA_ID); 1351 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1352 ppdu_info->rx_status.he_data4 |= value; 1353 1354 /* HE-data5 */ 1355 1356 /* HE-data6 */ 1357 value = HAL_RX_GET(he_sig_b2_mu_info, 1358 HE_SIG_B2_MU_INFO_0, NSTS); 1359 /* value n indicates n+1 spatial streams */ 1360 value++; 1361 ppdu_info->rx_status.nss = value; 1362 ppdu_info->rx_status.he_data6 |= value; 1363 1364 break; 1365 1366 } 1367 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1368 { 1369 uint8_t *he_sig_b2_ofdma_info = 1370 (uint8_t *)rx_tlv + 1371 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1372 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1373 1374 /* 1375 * Not all "HE" fields can be updated from 1376 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1377 * to populate rest of "HE" fields for MU OFDMA scenarios. 1378 */ 1379 1380 /* HE-data1 */ 1381 ppdu_info->rx_status.he_data1 |= 1382 QDF_MON_STATUS_HE_MCS_KNOWN | 1383 QDF_MON_STATUS_HE_DCM_KNOWN | 1384 QDF_MON_STATUS_HE_CODING_KNOWN; 1385 1386 /* HE-data2 */ 1387 ppdu_info->rx_status.he_data2 |= 1388 QDF_MON_STATUS_TXBF_KNOWN; 1389 1390 /* HE-data3 */ 1391 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1392 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1393 ppdu_info->rx_status.mcs = value; 1394 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1395 ppdu_info->rx_status.he_data3 |= value; 1396 1397 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1398 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1399 he_dcm = value; 1400 value = value << QDF_MON_STATUS_DCM_SHIFT; 1401 ppdu_info->rx_status.he_data3 |= value; 1402 1403 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1404 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1405 value = value << QDF_MON_STATUS_CODING_SHIFT; 1406 ppdu_info->rx_status.he_data3 |= value; 1407 1408 /* HE-data4 */ 1409 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1410 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1411 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1412 ppdu_info->rx_status.he_data4 |= value; 1413 1414 /* HE-data5 */ 1415 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1416 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1417 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1418 ppdu_info->rx_status.he_data5 |= value; 1419 1420 /* HE-data6 */ 1421 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1422 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1423 /* value n indicates n+1 spatial streams */ 1424 value++; 1425 ppdu_info->rx_status.nss = value; 1426 ppdu_info->rx_status.he_data6 |= value; 1427 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1428 break; 1429 } 1430 case WIFIPHYRX_RSSI_LEGACY_E: 1431 { 1432 uint8_t reception_type; 1433 int8_t rssi_value; 1434 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1435 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1436 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1437 1438 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1439 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1440 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1441 ppdu_info->rx_status.he_re = 0; 1442 1443 reception_type = HAL_RX_GET(rx_tlv, 1444 PHYRX_RSSI_LEGACY_0, 1445 RECEPTION_TYPE); 1446 switch (reception_type) { 1447 case QDF_RECEPTION_TYPE_ULOFMDA: 1448 ppdu_info->rx_status.reception_type = 1449 HAL_RX_TYPE_MU_OFDMA; 1450 ppdu_info->rx_status.ulofdma_flag = 1; 1451 ppdu_info->rx_status.he_data1 = 1452 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1453 break; 1454 case QDF_RECEPTION_TYPE_ULMIMO: 1455 ppdu_info->rx_status.reception_type = 1456 HAL_RX_TYPE_MU_MIMO; 1457 ppdu_info->rx_status.he_data1 = 1458 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1459 break; 1460 default: 1461 ppdu_info->rx_status.reception_type = 1462 HAL_RX_TYPE_SU; 1463 break; 1464 } 1465 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1466 rssi_value = HAL_RX_GET(rssi_info_tlv, 1467 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1468 ppdu_info->rx_status.rssi[0] = rssi_value; 1469 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1470 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1471 1472 rssi_value = HAL_RX_GET(rssi_info_tlv, 1473 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1474 ppdu_info->rx_status.rssi[1] = rssi_value; 1475 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1476 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1477 1478 rssi_value = HAL_RX_GET(rssi_info_tlv, 1479 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1480 ppdu_info->rx_status.rssi[2] = rssi_value; 1481 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1482 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1483 1484 rssi_value = HAL_RX_GET(rssi_info_tlv, 1485 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1486 ppdu_info->rx_status.rssi[3] = rssi_value; 1487 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1488 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1489 1490 rssi_value = HAL_RX_GET(rssi_info_tlv, 1491 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1492 ppdu_info->rx_status.rssi[4] = rssi_value; 1493 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1494 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1495 1496 rssi_value = HAL_RX_GET(rssi_info_tlv, 1497 RECEIVE_RSSI_INFO_10, 1498 RSSI_PRI20_CHAIN5); 1499 ppdu_info->rx_status.rssi[5] = rssi_value; 1500 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1501 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1502 1503 rssi_value = HAL_RX_GET(rssi_info_tlv, 1504 RECEIVE_RSSI_INFO_12, 1505 RSSI_PRI20_CHAIN6); 1506 ppdu_info->rx_status.rssi[6] = rssi_value; 1507 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1508 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1509 1510 rssi_value = HAL_RX_GET(rssi_info_tlv, 1511 RECEIVE_RSSI_INFO_14, 1512 RSSI_PRI20_CHAIN7); 1513 ppdu_info->rx_status.rssi[7] = rssi_value; 1514 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1515 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1516 break; 1517 } 1518 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1519 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1520 ppdu_info); 1521 break; 1522 case WIFIRX_HEADER_E: 1523 { 1524 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1525 1526 if (ppdu_info->fcs_ok_cnt >= 1527 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1528 hal_err("Number of MPDUs(%d) per status buff exceeded", 1529 ppdu_info->fcs_ok_cnt); 1530 break; 1531 } 1532 1533 /* Update first_msdu_payload for every mpdu and increment 1534 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1535 */ 1536 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1537 rx_tlv; 1538 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1539 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1540 ppdu_info->msdu_info.payload_len = tlv_len; 1541 ppdu_info->user_id = user_id; 1542 ppdu_info->hdr_len = tlv_len; 1543 ppdu_info->data = rx_tlv; 1544 ppdu_info->data += 4; 1545 1546 /* for every RX_HEADER TLV increment mpdu_cnt */ 1547 com_info->mpdu_cnt++; 1548 return HAL_TLV_STATUS_HEADER; 1549 } 1550 case WIFIRX_MPDU_START_E: 1551 { 1552 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1553 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1554 uint8_t filter_category = 0; 1555 1556 ppdu_info->nac_info.fc_valid = 1557 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1558 1559 ppdu_info->nac_info.to_ds_flag = 1560 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1561 1562 ppdu_info->nac_info.frame_control = 1563 HAL_RX_GET(rx_mpdu_start, 1564 RX_MPDU_INFO_14, 1565 MPDU_FRAME_CONTROL_FIELD); 1566 1567 ppdu_info->sw_frame_group_id = 1568 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1569 1570 if (ppdu_info->sw_frame_group_id == 1571 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1572 ppdu_info->rx_status.frame_control_info_valid = 1573 ppdu_info->nac_info.fc_valid; 1574 ppdu_info->rx_status.frame_control = 1575 ppdu_info->nac_info.frame_control; 1576 } 1577 1578 hal_get_mac_addr1(rx_mpdu_start, 1579 ppdu_info); 1580 1581 ppdu_info->nac_info.mac_addr2_valid = 1582 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1583 1584 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1585 HAL_RX_GET(rx_mpdu_start, 1586 RX_MPDU_INFO_16, 1587 MAC_ADDR_AD2_15_0); 1588 1589 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1590 HAL_RX_GET(rx_mpdu_start, 1591 RX_MPDU_INFO_17, 1592 MAC_ADDR_AD2_47_16); 1593 1594 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1595 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1596 ppdu_info->rx_status.ppdu_len = 1597 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1598 MPDU_LENGTH); 1599 } else { 1600 ppdu_info->rx_status.ppdu_len += 1601 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1602 MPDU_LENGTH); 1603 } 1604 1605 filter_category = 1606 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1607 1608 if (filter_category == 0) 1609 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1610 else if (filter_category == 1) 1611 ppdu_info->rx_status.monitor_direct_used = 1; 1612 1613 ppdu_info->nac_info.mcast_bcast = 1614 HAL_RX_GET(rx_mpdu_start, 1615 RX_MPDU_INFO_13, 1616 MCAST_BCAST); 1617 break; 1618 } 1619 case WIFIRX_MPDU_END_E: 1620 ppdu_info->user_id = user_id; 1621 ppdu_info->fcs_err = 1622 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1623 FCS_ERR); 1624 return HAL_TLV_STATUS_MPDU_END; 1625 case WIFIRX_MSDU_END_E: 1626 if (user_id < HAL_MAX_UL_MU_USERS) { 1627 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1628 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1629 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1630 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1631 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1632 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1633 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1634 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1635 ppdu_info->rx_msdu_info[user_id].flow_idx = 1636 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1637 } 1638 return HAL_TLV_STATUS_MSDU_END; 1639 case 0: 1640 return HAL_TLV_STATUS_PPDU_DONE; 1641 1642 default: 1643 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1644 unhandled = false; 1645 else 1646 unhandled = true; 1647 break; 1648 } 1649 1650 if (!unhandled) 1651 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1652 "%s TLV type: %d, TLV len:%d %s", 1653 __func__, tlv_tag, tlv_len, 1654 unhandled == true ? "unhandled" : ""); 1655 1656 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1657 rx_tlv, tlv_len); 1658 1659 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1660 } 1661 1662 /** 1663 * hal_reo_setup - Initialize HW REO block 1664 * 1665 * @hal_soc: Opaque HAL SOC handle 1666 * @reo_params: parameters needed by HAL for REO config 1667 */ 1668 static void hal_reo_setup_generic(struct hal_soc *soc, 1669 void *reoparams) 1670 { 1671 uint32_t reg_val; 1672 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1673 1674 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1675 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1676 1677 hal_reo_config(soc, reg_val, reo_params); 1678 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1679 1680 /* TODO: Setup destination ring mapping if enabled */ 1681 1682 /* TODO: Error destination ring setting is left to default. 1683 * Default setting is to send all errors to release ring. 1684 */ 1685 1686 HAL_REG_WRITE(soc, 1687 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1688 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1689 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1690 1691 HAL_REG_WRITE(soc, 1692 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1693 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1694 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1695 1696 HAL_REG_WRITE(soc, 1697 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1698 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1699 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1700 1701 HAL_REG_WRITE(soc, 1702 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1703 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1704 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1705 1706 /* 1707 * When hash based routing is enabled, routing of the rx packet 1708 * is done based on the following value: 1 _ _ _ _ The last 4 1709 * bits are based on hash[3:0]. This means the possible values 1710 * are 0x10 to 0x1f. This value is used to look-up the 1711 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1712 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1713 * registers need to be configured to set-up the 16 entries to 1714 * map the hash values to a ring number. There are 3 bits per 1715 * hash entry – which are mapped as follows: 1716 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1717 * 7: NOT_USED. 1718 */ 1719 if (reo_params->rx_hash_enabled) { 1720 HAL_REG_WRITE(soc, 1721 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1722 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1723 reo_params->remap1); 1724 1725 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1726 HAL_REG_READ(soc, 1727 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1728 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1729 1730 HAL_REG_WRITE(soc, 1731 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1732 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1733 reo_params->remap2); 1734 1735 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1736 HAL_REG_READ(soc, 1737 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1738 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1739 } 1740 1741 /* TODO: Check if the following registers shoould be setup by host: 1742 * AGING_CONTROL 1743 * HIGH_MEMORY_THRESHOLD 1744 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1745 * GLOBAL_LINK_DESC_COUNT_CTRL 1746 */ 1747 } 1748 1749 /** 1750 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1751 * @hal_soc: Opaque HAL SOC handle 1752 * @hal_ring: Source ring pointer 1753 * @headp: Head Pointer 1754 * @tailp: Tail Pointer 1755 * @ring: Ring type 1756 * 1757 * Return: Update tail pointer and head pointer in arguments. 1758 */ 1759 static inline 1760 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 1761 hal_ring_handle_t hal_ring_hdl, 1762 uint32_t *headp, uint32_t *tailp, 1763 uint8_t ring) 1764 { 1765 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1766 struct hal_hw_srng_config *ring_config; 1767 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1768 1769 if (!hal_soc || !srng) { 1770 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1771 "%s: Context is Null", __func__); 1772 return; 1773 } 1774 1775 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 1776 if (!ring_config->lmac_ring) { 1777 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1778 *headp = SRNG_SRC_REG_READ(srng, HP); 1779 *tailp = SRNG_SRC_REG_READ(srng, TP); 1780 } else { 1781 *headp = SRNG_DST_REG_READ(srng, HP); 1782 *tailp = SRNG_DST_REG_READ(srng, TP); 1783 } 1784 } 1785 } 1786 1787 #if defined(WBM_IDLE_LSB_WRITE_CONFIRM_WAR) 1788 /** 1789 * hal_wbm_idle_lsb_write_confirm() - Check and update WBM_IDLE_LINK ring LSB 1790 * @srng: srng handle 1791 * 1792 * Return: None 1793 */ 1794 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 1795 { 1796 if (srng->ring_id == HAL_SRNG_WBM_IDLE_LINK) { 1797 while (SRNG_SRC_REG_READ(srng, BASE_LSB) != 1798 ((unsigned int)srng->ring_base_paddr & 0xffffffff)) 1799 SRNG_SRC_REG_WRITE(srng, BASE_LSB, 1800 srng->ring_base_paddr & 1801 0xffffffff); 1802 } 1803 } 1804 #else 1805 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 1806 { 1807 } 1808 #endif 1809 1810 /** 1811 * hal_srng_src_hw_init - Private function to initialize SRNG 1812 * source ring HW 1813 * @hal_soc: HAL SOC handle 1814 * @srng: SRNG ring pointer 1815 */ 1816 static inline 1817 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 1818 struct hal_srng *srng) 1819 { 1820 uint32_t reg_val = 0; 1821 uint64_t tp_addr = 0; 1822 1823 hal_debug("hw_init srng %d", srng->ring_id); 1824 1825 if (srng->flags & HAL_SRNG_MSI_INTR) { 1826 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1827 srng->msi_addr & 0xffffffff); 1828 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1829 (uint64_t)(srng->msi_addr) >> 32) | 1830 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1831 MSI1_ENABLE), 1); 1832 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1833 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1834 } 1835 1836 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1837 hal_wbm_idle_lsb_write_confirm(srng); 1838 1839 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1840 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1841 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1842 srng->entry_size * srng->num_entries); 1843 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1844 1845 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1846 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1847 1848 /** 1849 * Interrupt setup: 1850 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1851 * if level mode is required 1852 */ 1853 reg_val = 0; 1854 1855 /* 1856 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1857 * programmed in terms of 1us resolution instead of 8us resolution as 1858 * given in MLD. 1859 */ 1860 if (srng->intr_timer_thres_us) { 1861 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1862 INTERRUPT_TIMER_THRESHOLD), 1863 srng->intr_timer_thres_us); 1864 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1865 } 1866 1867 if (srng->intr_batch_cntr_thres_entries) { 1868 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1869 BATCH_COUNTER_THRESHOLD), 1870 srng->intr_batch_cntr_thres_entries * 1871 srng->entry_size); 1872 } 1873 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1874 1875 reg_val = 0; 1876 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1877 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1878 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1879 } 1880 1881 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1882 1883 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1884 * remain 0 to avoid some WBM stability issues. Remote head/tail 1885 * pointers are not required since this ring is completely managed 1886 * by WBM HW 1887 */ 1888 reg_val = 0; 1889 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1890 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1891 ((unsigned long)(srng->u.src_ring.tp_addr) - 1892 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1893 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1894 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1895 } else { 1896 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1897 } 1898 1899 /* Initilaize head and tail pointers to indicate ring is empty */ 1900 SRNG_SRC_REG_WRITE(srng, HP, 0); 1901 SRNG_SRC_REG_WRITE(srng, TP, 0); 1902 *(srng->u.src_ring.tp_addr) = 0; 1903 1904 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1905 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1906 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1907 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1908 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1909 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1910 1911 /* Loop count is not used for SRC rings */ 1912 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1913 1914 /* 1915 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1916 * todo: update fw_api and replace with above line 1917 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1918 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1919 */ 1920 reg_val |= 0x40; 1921 1922 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1923 } 1924 1925 /** 1926 * hal_srng_dst_hw_init - Private function to initialize SRNG 1927 * destination ring HW 1928 * @hal_soc: HAL SOC handle 1929 * @srng: SRNG ring pointer 1930 */ 1931 static inline 1932 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 1933 struct hal_srng *srng) 1934 { 1935 uint32_t reg_val = 0; 1936 uint64_t hp_addr = 0; 1937 1938 hal_debug("hw_init srng %d", srng->ring_id); 1939 1940 if (srng->flags & HAL_SRNG_MSI_INTR) { 1941 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1942 srng->msi_addr & 0xffffffff); 1943 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1944 (uint64_t)(srng->msi_addr) >> 32) | 1945 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1946 MSI1_ENABLE), 1); 1947 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1948 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1949 } 1950 1951 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1952 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1953 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1954 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1955 srng->entry_size * srng->num_entries); 1956 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1957 1958 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1959 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1960 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1961 1962 1963 /** 1964 * Interrupt setup: 1965 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1966 * if level mode is required 1967 */ 1968 reg_val = 0; 1969 if (srng->intr_timer_thres_us) { 1970 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1971 INTERRUPT_TIMER_THRESHOLD), 1972 srng->intr_timer_thres_us >> 3); 1973 } 1974 1975 if (srng->intr_batch_cntr_thres_entries) { 1976 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1977 BATCH_COUNTER_THRESHOLD), 1978 srng->intr_batch_cntr_thres_entries * 1979 srng->entry_size); 1980 } 1981 1982 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1983 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1984 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1985 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1986 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1987 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1988 1989 /* Initilaize head and tail pointers to indicate ring is empty */ 1990 SRNG_DST_REG_WRITE(srng, HP, 0); 1991 SRNG_DST_REG_WRITE(srng, TP, 0); 1992 *(srng->u.dst_ring.hp_addr) = 0; 1993 1994 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1995 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1996 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1997 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1998 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1999 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 2000 2001 /* 2002 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 2003 * todo: update fw_api and replace with above line 2004 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 2005 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 2006 */ 2007 reg_val |= 0x40; 2008 2009 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 2010 2011 } 2012 2013 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2014 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 2015 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 2016 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 2017 2018 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2019 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 2020 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 2021 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 2022 2023 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2024 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 2025 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 2026 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 2027 2028 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 2029 (((*(((uint32_t *) wbm_desc) + \ 2030 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 2031 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 2032 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 2033 2034 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 2035 (((*(((uint32_t *) wbm_desc) + \ 2036 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 2037 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 2038 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 2039 2040 /** 2041 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 2042 * save it to hal_wbm_err_desc_info structure passed by caller 2043 * @wbm_desc: wbm ring descriptor 2044 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 2045 * Return: void 2046 */ 2047 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 2048 void *wbm_er_info1) 2049 { 2050 struct hal_wbm_err_desc_info *wbm_er_info = 2051 (struct hal_wbm_err_desc_info *)wbm_er_info1; 2052 2053 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 2054 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 2055 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 2056 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 2057 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 2058 } 2059 2060 /** 2061 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 2062 * @hal_desc: completion ring descriptor pointer 2063 * 2064 * This function will return the type of pointer - buffer or descriptor 2065 * 2066 * Return: buffer type 2067 */ 2068 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 2069 { 2070 uint32_t comp_desc = 2071 *(uint32_t *) (((uint8_t *) hal_desc) + 2072 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 2073 2074 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 2075 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 2076 } 2077 2078 /** 2079 * hal_get_wbm_internal_error_generic() - is WBM internal error 2080 * @hal_desc: completion ring descriptor pointer 2081 * 2082 * This function will return 0 or 1 - is it WBM internal error or not 2083 * 2084 * Return: uint8_t 2085 */ 2086 static inline uint8_t hal_get_wbm_internal_error_generic(void *hal_desc) 2087 { 2088 uint32_t comp_desc = 2089 *(uint32_t *)(((uint8_t *)hal_desc) + 2090 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET); 2091 2092 return (comp_desc & WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK) >> 2093 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB; 2094 } 2095 2096 /** 2097 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 2098 * human readable format. 2099 * @mpdu_start: pointer the rx_attention TLV in pkt. 2100 * @dbg_level: log level. 2101 * 2102 * Return: void 2103 */ 2104 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 2105 uint8_t dbg_level) 2106 { 2107 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 2108 struct rx_mpdu_info *mpdu_info = 2109 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 2110 2111 hal_verbose_debug( 2112 "rx_mpdu_start tlv (1/5) - " 2113 "rxpcu_mpdu_filter_in_category: %x " 2114 "sw_frame_group_id: %x " 2115 "ndp_frame: %x " 2116 "phy_err: %x " 2117 "phy_err_during_mpdu_header: %x " 2118 "protocol_version_err: %x " 2119 "ast_based_lookup_valid: %x " 2120 "phy_ppdu_id: %x " 2121 "ast_index: %x " 2122 "sw_peer_id: %x " 2123 "mpdu_frame_control_valid: %x " 2124 "mpdu_duration_valid: %x " 2125 "mac_addr_ad1_valid: %x " 2126 "mac_addr_ad2_valid: %x " 2127 "mac_addr_ad3_valid: %x " 2128 "mac_addr_ad4_valid: %x " 2129 "mpdu_sequence_control_valid: %x " 2130 "mpdu_qos_control_valid: %x " 2131 "mpdu_ht_control_valid: %x " 2132 "frame_encryption_info_valid: %x ", 2133 mpdu_info->rxpcu_mpdu_filter_in_category, 2134 mpdu_info->sw_frame_group_id, 2135 mpdu_info->ndp_frame, 2136 mpdu_info->phy_err, 2137 mpdu_info->phy_err_during_mpdu_header, 2138 mpdu_info->protocol_version_err, 2139 mpdu_info->ast_based_lookup_valid, 2140 mpdu_info->phy_ppdu_id, 2141 mpdu_info->ast_index, 2142 mpdu_info->sw_peer_id, 2143 mpdu_info->mpdu_frame_control_valid, 2144 mpdu_info->mpdu_duration_valid, 2145 mpdu_info->mac_addr_ad1_valid, 2146 mpdu_info->mac_addr_ad2_valid, 2147 mpdu_info->mac_addr_ad3_valid, 2148 mpdu_info->mac_addr_ad4_valid, 2149 mpdu_info->mpdu_sequence_control_valid, 2150 mpdu_info->mpdu_qos_control_valid, 2151 mpdu_info->mpdu_ht_control_valid, 2152 mpdu_info->frame_encryption_info_valid); 2153 2154 hal_verbose_debug( 2155 "rx_mpdu_start tlv (2/5) - " 2156 "fr_ds: %x " 2157 "to_ds: %x " 2158 "encrypted: %x " 2159 "mpdu_retry: %x " 2160 "mpdu_sequence_number: %x " 2161 "epd_en: %x " 2162 "all_frames_shall_be_encrypted: %x " 2163 "encrypt_type: %x " 2164 "mesh_sta: %x " 2165 "bssid_hit: %x " 2166 "bssid_number: %x " 2167 "tid: %x " 2168 "pn_31_0: %x " 2169 "pn_63_32: %x " 2170 "pn_95_64: %x " 2171 "pn_127_96: %x " 2172 "peer_meta_data: %x " 2173 "rxpt_classify_info.reo_destination_indication: %x " 2174 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 2175 "rx_reo_queue_desc_addr_31_0: %x ", 2176 mpdu_info->fr_ds, 2177 mpdu_info->to_ds, 2178 mpdu_info->encrypted, 2179 mpdu_info->mpdu_retry, 2180 mpdu_info->mpdu_sequence_number, 2181 mpdu_info->epd_en, 2182 mpdu_info->all_frames_shall_be_encrypted, 2183 mpdu_info->encrypt_type, 2184 mpdu_info->mesh_sta, 2185 mpdu_info->bssid_hit, 2186 mpdu_info->bssid_number, 2187 mpdu_info->tid, 2188 mpdu_info->pn_31_0, 2189 mpdu_info->pn_63_32, 2190 mpdu_info->pn_95_64, 2191 mpdu_info->pn_127_96, 2192 mpdu_info->peer_meta_data, 2193 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 2194 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 2195 mpdu_info->rx_reo_queue_desc_addr_31_0); 2196 2197 hal_verbose_debug( 2198 "rx_mpdu_start tlv (3/5) - " 2199 "rx_reo_queue_desc_addr_39_32: %x " 2200 "receive_queue_number: %x " 2201 "pre_delim_err_warning: %x " 2202 "first_delim_err: %x " 2203 "key_id_octet: %x " 2204 "new_peer_entry: %x " 2205 "decrypt_needed: %x " 2206 "decap_type: %x " 2207 "rx_insert_vlan_c_tag_padding: %x " 2208 "rx_insert_vlan_s_tag_padding: %x " 2209 "strip_vlan_c_tag_decap: %x " 2210 "strip_vlan_s_tag_decap: %x " 2211 "pre_delim_count: %x " 2212 "ampdu_flag: %x " 2213 "bar_frame: %x " 2214 "mpdu_length: %x " 2215 "first_mpdu: %x " 2216 "mcast_bcast: %x " 2217 "ast_index_not_found: %x " 2218 "ast_index_timeout: %x ", 2219 mpdu_info->rx_reo_queue_desc_addr_39_32, 2220 mpdu_info->receive_queue_number, 2221 mpdu_info->pre_delim_err_warning, 2222 mpdu_info->first_delim_err, 2223 mpdu_info->key_id_octet, 2224 mpdu_info->new_peer_entry, 2225 mpdu_info->decrypt_needed, 2226 mpdu_info->decap_type, 2227 mpdu_info->rx_insert_vlan_c_tag_padding, 2228 mpdu_info->rx_insert_vlan_s_tag_padding, 2229 mpdu_info->strip_vlan_c_tag_decap, 2230 mpdu_info->strip_vlan_s_tag_decap, 2231 mpdu_info->pre_delim_count, 2232 mpdu_info->ampdu_flag, 2233 mpdu_info->bar_frame, 2234 mpdu_info->mpdu_length, 2235 mpdu_info->first_mpdu, 2236 mpdu_info->mcast_bcast, 2237 mpdu_info->ast_index_not_found, 2238 mpdu_info->ast_index_timeout); 2239 2240 hal_verbose_debug( 2241 "rx_mpdu_start tlv (4/5) - " 2242 "power_mgmt: %x " 2243 "non_qos: %x " 2244 "null_data: %x " 2245 "mgmt_type: %x " 2246 "ctrl_type: %x " 2247 "more_data: %x " 2248 "eosp: %x " 2249 "fragment_flag: %x " 2250 "order: %x " 2251 "u_apsd_trigger: %x " 2252 "encrypt_required: %x " 2253 "directed: %x " 2254 "mpdu_frame_control_field: %x " 2255 "mpdu_duration_field: %x " 2256 "mac_addr_ad1_31_0: %x " 2257 "mac_addr_ad1_47_32: %x " 2258 "mac_addr_ad2_15_0: %x " 2259 "mac_addr_ad2_47_16: %x " 2260 "mac_addr_ad3_31_0: %x " 2261 "mac_addr_ad3_47_32: %x ", 2262 mpdu_info->power_mgmt, 2263 mpdu_info->non_qos, 2264 mpdu_info->null_data, 2265 mpdu_info->mgmt_type, 2266 mpdu_info->ctrl_type, 2267 mpdu_info->more_data, 2268 mpdu_info->eosp, 2269 mpdu_info->fragment_flag, 2270 mpdu_info->order, 2271 mpdu_info->u_apsd_trigger, 2272 mpdu_info->encrypt_required, 2273 mpdu_info->directed, 2274 mpdu_info->mpdu_frame_control_field, 2275 mpdu_info->mpdu_duration_field, 2276 mpdu_info->mac_addr_ad1_31_0, 2277 mpdu_info->mac_addr_ad1_47_32, 2278 mpdu_info->mac_addr_ad2_15_0, 2279 mpdu_info->mac_addr_ad2_47_16, 2280 mpdu_info->mac_addr_ad3_31_0, 2281 mpdu_info->mac_addr_ad3_47_32); 2282 2283 hal_verbose_debug( 2284 "rx_mpdu_start tlv (5/5) - " 2285 "mpdu_sequence_control_field: %x " 2286 "mac_addr_ad4_31_0: %x " 2287 "mac_addr_ad4_47_32: %x " 2288 "mpdu_qos_control_field: %x " 2289 "mpdu_ht_control_field: %x ", 2290 mpdu_info->mpdu_sequence_control_field, 2291 mpdu_info->mac_addr_ad4_31_0, 2292 mpdu_info->mac_addr_ad4_47_32, 2293 mpdu_info->mpdu_qos_control_field, 2294 mpdu_info->mpdu_ht_control_field); 2295 } 2296 2297 /** 2298 * hal_tx_desc_set_search_type - Set the search type value 2299 * @desc: Handle to Tx Descriptor 2300 * @search_type: search type 2301 * 0 – Normal search 2302 * 1 – Index based address search 2303 * 2 – Index based flow search 2304 * 2305 * Return: void 2306 */ 2307 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2308 static void hal_tx_desc_set_search_type_generic(void *desc, 2309 uint8_t search_type) 2310 { 2311 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2312 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2313 } 2314 #else 2315 static void hal_tx_desc_set_search_type_generic(void *desc, 2316 uint8_t search_type) 2317 { 2318 } 2319 2320 #endif 2321 2322 /** 2323 * hal_tx_desc_set_search_index - Set the search index value 2324 * @desc: Handle to Tx Descriptor 2325 * @search_index: The index that will be used for index based address or 2326 * flow search. The field is valid when 'search_type' is 2327 * 1 0r 2 2328 * 2329 * Return: void 2330 */ 2331 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2332 static void hal_tx_desc_set_search_index_generic(void *desc, 2333 uint32_t search_index) 2334 { 2335 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2336 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2337 } 2338 #else 2339 static void hal_tx_desc_set_search_index_generic(void *desc, 2340 uint32_t search_index) 2341 { 2342 } 2343 #endif 2344 2345 /** 2346 * hal_tx_desc_set_cache_set_num_generic - Set the cache-set-num value 2347 * @desc: Handle to Tx Descriptor 2348 * @cache_num: Cache set number that should be used to cache the index 2349 * based search results, for address and flow search. 2350 * This value should be equal to LSB four bits of the hash value 2351 * of match data, in case of search index points to an entry 2352 * which may be used in content based search also. The value can 2353 * be anything when the entry pointed by search index will not be 2354 * used for content based search. 2355 * 2356 * Return: void 2357 */ 2358 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2359 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2360 uint8_t cache_num) 2361 { 2362 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2363 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2364 } 2365 #else 2366 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2367 uint8_t cache_num) 2368 { 2369 } 2370 #endif 2371 2372 /** 2373 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2374 * @soc: HAL SoC context 2375 * @map: PCP-TID mapping table 2376 * 2377 * PCP are mapped to 8 TID values using TID values programmed 2378 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2379 * The mapping register has TID mapping for 8 PCP values 2380 * 2381 * Return: none 2382 */ 2383 static void hal_tx_set_pcp_tid_map_generic(struct hal_soc *soc, uint8_t *map) 2384 { 2385 uint32_t addr, value; 2386 2387 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2388 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2389 2390 value = (map[0] | 2391 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2392 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2393 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2394 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2395 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2396 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2397 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2398 2399 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2400 } 2401 2402 /** 2403 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2404 * value received from user-space 2405 * @soc: HAL SoC context 2406 * @pcp: pcp value 2407 * @tid : tid value 2408 * 2409 * Return: void 2410 */ 2411 static 2412 void hal_tx_update_pcp_tid_generic(struct hal_soc *soc, 2413 uint8_t pcp, uint8_t tid) 2414 { 2415 uint32_t addr, value, regval; 2416 2417 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2418 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2419 2420 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2421 2422 /* Read back previous PCP TID config and update 2423 * with new config. 2424 */ 2425 regval = HAL_REG_READ(soc, addr); 2426 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2427 regval |= value; 2428 2429 HAL_REG_WRITE(soc, addr, 2430 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2431 } 2432 2433 /** 2434 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2435 * @soc: HAL SoC context 2436 * @val: priority value 2437 * 2438 * Return: void 2439 */ 2440 static 2441 void hal_tx_update_tidmap_prty_generic(struct hal_soc *soc, uint8_t value) 2442 { 2443 uint32_t addr; 2444 2445 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2446 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2447 2448 HAL_REG_WRITE(soc, addr, 2449 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2450 } 2451 2452 /** 2453 * hal_rx_msdu_packet_metadata_get(): API to get the 2454 * msdu information from rx_msdu_end TLV 2455 * 2456 * @ buf: pointer to the start of RX PKT TLV headers 2457 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2458 */ 2459 static void 2460 hal_rx_msdu_packet_metadata_get_generic(uint8_t *buf, 2461 void *pkt_msdu_metadata) 2462 { 2463 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2464 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2465 struct hal_rx_msdu_metadata *msdu_metadata = 2466 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2467 2468 msdu_metadata->l3_hdr_pad = 2469 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2470 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2471 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2472 msdu_metadata->sa_sw_peer_id = 2473 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2474 } 2475 2476 /** 2477 * hal_rx_msdu_end_offset_get_generic(): API to get the 2478 * msdu_end structure offset rx_pkt_tlv structure 2479 * 2480 * NOTE: API returns offset of msdu_end TLV from structure 2481 * rx_pkt_tlvs 2482 */ 2483 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2484 { 2485 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2486 } 2487 2488 /** 2489 * hal_rx_attn_offset_get_generic(): API to get the 2490 * msdu_end structure offset rx_pkt_tlv structure 2491 * 2492 * NOTE: API returns offset of attn TLV from structure 2493 * rx_pkt_tlvs 2494 */ 2495 static uint32_t hal_rx_attn_offset_get_generic(void) 2496 { 2497 return RX_PKT_TLV_OFFSET(attn_tlv); 2498 } 2499 2500 /** 2501 * hal_rx_msdu_start_offset_get_generic(): API to get the 2502 * msdu_start structure offset rx_pkt_tlv structure 2503 * 2504 * NOTE: API returns offset of attn TLV from structure 2505 * rx_pkt_tlvs 2506 */ 2507 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2508 { 2509 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2510 } 2511 2512 /** 2513 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2514 * mpdu_start structure offset rx_pkt_tlv structure 2515 * 2516 * NOTE: API returns offset of attn TLV from structure 2517 * rx_pkt_tlvs 2518 */ 2519 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2520 { 2521 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2522 } 2523 2524 /** 2525 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2526 * mpdu_end structure offset rx_pkt_tlv structure 2527 * 2528 * NOTE: API returns offset of attn TLV from structure 2529 * rx_pkt_tlvs 2530 */ 2531 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2532 { 2533 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2534 } 2535 #endif /* HAL_GENERIC_API_H_ */ 2536