1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 23 /** 24 * hal_tx_comp_get_status() - TQM Release reason 25 * @hal_desc: completion ring Tx status 26 * 27 * This function will parse the WBM completion descriptor and populate in 28 * HAL structure 29 * 30 * Return: none 31 */ 32 static inline 33 void hal_tx_comp_get_status_generic(void *desc, 34 void *ts1, 35 struct hal_soc *hal) 36 { 37 uint8_t rate_stats_valid = 0; 38 uint32_t rate_stats = 0; 39 struct hal_tx_completion_status *ts = 40 (struct hal_tx_completion_status *)ts1; 41 42 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 43 TQM_STATUS_NUMBER); 44 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 45 ACK_FRAME_RSSI); 46 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 47 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 48 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 49 MSDU_PART_OF_AMSDU); 50 51 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 52 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 53 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 54 TRANSMIT_COUNT); 55 56 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 57 TX_RATE_STATS); 58 59 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 60 TX_RATE_STATS_INFO_VALID, rate_stats); 61 62 ts->valid = rate_stats_valid; 63 64 if (rate_stats_valid) { 65 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 66 rate_stats); 67 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 68 TRANSMIT_PKT_TYPE, rate_stats); 69 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 70 TRANSMIT_STBC, rate_stats); 71 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 72 rate_stats); 73 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 74 rate_stats); 75 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 76 rate_stats); 77 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 78 rate_stats); 79 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 80 rate_stats); 81 } 82 83 ts->release_src = hal_tx_comp_get_buffer_source(desc); 84 ts->status = hal_tx_comp_get_release_reason( 85 desc, 86 hal_soc_to_hal_soc_handle(hal)); 87 88 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 89 TX_RATE_STATS_INFO_TX_RATE_STATS); 90 } 91 92 /** 93 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 94 * @desc: Handle to Tx Descriptor 95 * @paddr: Physical Address 96 * @pool_id: Return Buffer Manager ID 97 * @desc_id: Descriptor ID 98 * @type: 0 - Address points to a MSDU buffer 99 * 1 - Address points to MSDU extension descriptor 100 * 101 * Return: void 102 */ 103 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 104 dma_addr_t paddr, uint8_t rbm_id, 105 uint32_t desc_id, uint8_t type) 106 { 107 /* Set buffer_addr_info.buffer_addr_31_0 */ 108 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 109 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 110 111 /* Set buffer_addr_info.buffer_addr_39_32 */ 112 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 113 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 114 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 115 (((uint64_t) paddr) >> 32)); 116 117 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 118 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 119 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 120 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 121 RETURN_BUFFER_MANAGER, rbm_id); 122 123 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 124 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 125 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 126 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 127 128 /* Set Buffer or Ext Descriptor Type */ 129 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 130 BUF_OR_EXT_DESC_TYPE) |= 131 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 132 } 133 134 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 135 /** 136 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 137 * tlv_tag: Taf of the TLVs 138 * rx_tlv: the pointer to the TLVs 139 * @ppdu_info: pointer to ppdu_info 140 * 141 * Return: true if the tlv is handled, false if not 142 */ 143 static inline bool 144 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 145 struct hal_rx_ppdu_info *ppdu_info) 146 { 147 uint32_t value; 148 149 switch (tlv_tag) { 150 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 151 { 152 uint8_t *he_sig_a_mu_ul_info = 153 (uint8_t *)rx_tlv + 154 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 155 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 156 ppdu_info->rx_status.he_flags = 1; 157 158 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 159 FORMAT_INDICATION); 160 if (value == 0) { 161 ppdu_info->rx_status.he_data1 = 162 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 163 } else { 164 ppdu_info->rx_status.he_data1 = 165 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 166 } 167 168 /* data1 */ 169 ppdu_info->rx_status.he_data1 |= 170 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 171 QDF_MON_STATUS_HE_DL_UL_KNOWN | 172 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 173 174 /* data2 */ 175 ppdu_info->rx_status.he_data2 |= 176 QDF_MON_STATUS_TXOP_KNOWN; 177 178 /*data3*/ 179 value = HAL_RX_GET(he_sig_a_mu_ul_info, 180 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 181 ppdu_info->rx_status.he_data3 = value; 182 /* 1 for UL and 0 for DL */ 183 value = 1; 184 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 185 ppdu_info->rx_status.he_data3 |= value; 186 187 /*data4*/ 188 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 189 SPATIAL_REUSE); 190 ppdu_info->rx_status.he_data4 = value; 191 192 /*data5*/ 193 value = HAL_RX_GET(he_sig_a_mu_ul_info, 194 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 195 ppdu_info->rx_status.he_data5 = value; 196 ppdu_info->rx_status.bw = value; 197 198 /*data6*/ 199 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 200 TXOP_DURATION); 201 value = value << QDF_MON_STATUS_TXOP_SHIFT; 202 ppdu_info->rx_status.he_data6 |= value; 203 return true; 204 } 205 default: 206 return false; 207 } 208 } 209 #else 210 static inline bool 211 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 212 struct hal_rx_ppdu_info *ppdu_info) 213 { 214 return false; 215 } 216 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 217 218 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 219 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 220 221 static inline void 222 hal_rx_handle_mu_ul_info( 223 void *rx_tlv, 224 struct mon_rx_user_status *mon_rx_user_status) 225 { 226 mon_rx_user_status->mu_ul_user_v0_word0 = 227 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 228 SW_RESPONSE_REFERENCE_PTR); 229 230 mon_rx_user_status->mu_ul_user_v0_word1 = 231 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 232 SW_RESPONSE_REFERENCE_PTR_EXT); 233 } 234 235 static inline void 236 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 237 struct mon_rx_user_status *mon_rx_user_status) 238 { 239 uint32_t mpdu_ok_byte_count; 240 uint32_t mpdu_err_byte_count; 241 242 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 243 RX_PPDU_END_USER_STATS_17, 244 MPDU_OK_BYTE_COUNT); 245 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 246 RX_PPDU_END_USER_STATS_19, 247 MPDU_ERR_BYTE_COUNT); 248 249 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 250 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 251 } 252 #else 253 static inline void 254 hal_rx_handle_mu_ul_info(void *rx_tlv, 255 struct mon_rx_user_status *mon_rx_user_status) 256 { 257 } 258 259 static inline void 260 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 261 struct mon_rx_user_status *mon_rx_user_status) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = 264 (struct hal_rx_ppdu_info *)ppduinfo; 265 266 /* HKV1: doesn't support mpdu byte count */ 267 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 268 mon_rx_user_status->mpdu_err_byte_count = 0; 269 } 270 #endif 271 272 static inline void 273 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 274 struct mon_rx_user_status *mon_rx_user_status) 275 { 276 struct mon_rx_info *mon_rx_info; 277 struct mon_rx_user_info *mon_rx_user_info; 278 struct hal_rx_ppdu_info *ppdu_info = 279 (struct hal_rx_ppdu_info *)ppduinfo; 280 281 mon_rx_info = &ppdu_info->rx_info; 282 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 283 mon_rx_user_info->qos_control_info_valid = 284 mon_rx_info->qos_control_info_valid; 285 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 286 287 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 288 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 289 mon_rx_user_status->tcp_msdu_count = 290 ppdu_info->rx_status.tcp_msdu_count; 291 mon_rx_user_status->udp_msdu_count = 292 ppdu_info->rx_status.udp_msdu_count; 293 mon_rx_user_status->other_msdu_count = 294 ppdu_info->rx_status.other_msdu_count; 295 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 296 mon_rx_user_status->frame_control_info_valid = 297 ppdu_info->rx_status.frame_control_info_valid; 298 mon_rx_user_status->data_sequence_control_info_valid = 299 ppdu_info->rx_status.data_sequence_control_info_valid; 300 mon_rx_user_status->first_data_seq_ctrl = 301 ppdu_info->rx_status.first_data_seq_ctrl; 302 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 303 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 304 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 305 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 306 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 307 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 308 309 mon_rx_user_status->mpdu_cnt_fcs_ok = 310 ppdu_info->com_info.mpdu_cnt_fcs_ok; 311 mon_rx_user_status->mpdu_cnt_fcs_err = 312 ppdu_info->com_info.mpdu_cnt_fcs_err; 313 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 314 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 315 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 316 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 317 318 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 319 } 320 321 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 322 ppdu_info, rssi_info_tlv) \ 323 { \ 324 ppdu_info->rx_status.rssi_chain[chain][0] = \ 325 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 326 RSSI_PRI20_CHAIN##chain); \ 327 ppdu_info->rx_status.rssi_chain[chain][1] = \ 328 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 329 RSSI_EXT20_CHAIN##chain); \ 330 ppdu_info->rx_status.rssi_chain[chain][2] = \ 331 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 332 RSSI_EXT40_LOW20_CHAIN##chain); \ 333 ppdu_info->rx_status.rssi_chain[chain][3] = \ 334 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 335 RSSI_EXT40_HIGH20_CHAIN##chain); \ 336 ppdu_info->rx_status.rssi_chain[chain][4] = \ 337 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 338 RSSI_EXT80_LOW20_CHAIN##chain); \ 339 ppdu_info->rx_status.rssi_chain[chain][5] = \ 340 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 341 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 342 ppdu_info->rx_status.rssi_chain[chain][6] = \ 343 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 344 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 345 ppdu_info->rx_status.rssi_chain[chain][7] = \ 346 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 347 RSSI_EXT80_HIGH20_CHAIN##chain); \ 348 } \ 349 350 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 351 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 352 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 353 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 354 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 355 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 356 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 357 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 358 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 359 360 static inline uint32_t 361 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 362 uint8_t *rssi_info_tlv) 363 { 364 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 365 return 0; 366 } 367 368 #ifdef WLAN_TX_PKT_CAPTURE_ENH 369 static inline void 370 hal_get_qos_control(void *rx_tlv, 371 struct hal_rx_ppdu_info *ppdu_info) 372 { 373 ppdu_info->rx_info.qos_control_info_valid = 374 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 375 QOS_CONTROL_INFO_VALID); 376 377 if (ppdu_info->rx_info.qos_control_info_valid) 378 ppdu_info->rx_info.qos_control = 379 HAL_RX_GET(rx_tlv, 380 RX_PPDU_END_USER_STATS_5, 381 QOS_CONTROL_FIELD); 382 } 383 384 static inline void 385 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 386 struct hal_rx_ppdu_info *ppdu_info) 387 { 388 if ((ppdu_info->sw_frame_group_id 389 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 390 (ppdu_info->sw_frame_group_id == 391 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 392 ppdu_info->rx_info.mac_addr1_valid = 393 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 394 395 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 396 HAL_RX_GET(rx_mpdu_start, 397 RX_MPDU_INFO_15, 398 MAC_ADDR_AD1_31_0); 399 if (ppdu_info->sw_frame_group_id == 400 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 401 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 402 HAL_RX_GET(rx_mpdu_start, 403 RX_MPDU_INFO_16, 404 MAC_ADDR_AD1_47_32); 405 } 406 } 407 } 408 #else 409 static inline void 410 hal_get_qos_control(void *rx_tlv, 411 struct hal_rx_ppdu_info *ppdu_info) 412 { 413 } 414 415 static inline void 416 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 417 struct hal_rx_ppdu_info *ppdu_info) 418 { 419 } 420 #endif 421 422 /** 423 * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value 424 * from stats enum to radiotap enum 425 * @he_gi: HE GI value used in stats 426 * @he_ltf: HE LTF value used in stats 427 * 428 * Return: void 429 */ 430 static inline void hal_get_radiotap_he_gi_ltf(uint16_t *he_gi, uint16_t *he_ltf) 431 { 432 switch (*he_gi) { 433 case HE_GI_0_8: 434 *he_gi = HE_GI_RADIOTAP_0_8; 435 break; 436 case HE_GI_1_6: 437 *he_gi = HE_GI_RADIOTAP_1_6; 438 break; 439 case HE_GI_3_2: 440 *he_gi = HE_GI_RADIOTAP_3_2; 441 break; 442 default: 443 *he_gi = HE_GI_RADIOTAP_RESERVED; 444 } 445 446 switch (*he_ltf) { 447 case HE_LTF_1_X: 448 *he_ltf = HE_LTF_RADIOTAP_1_X; 449 break; 450 case HE_LTF_2_X: 451 *he_ltf = HE_LTF_RADIOTAP_2_X; 452 break; 453 case HE_LTF_4_X: 454 *he_ltf = HE_LTF_RADIOTAP_4_X; 455 break; 456 default: 457 *he_ltf = HE_LTF_RADIOTAP_UNKNOWN; 458 } 459 } 460 461 /* channel number to freq conversion */ 462 #define CHANNEL_NUM_14 14 463 #define CHANNEL_NUM_15 15 464 #define CHANNEL_NUM_27 27 465 #define CHANNEL_NUM_35 35 466 #define CHANNEL_NUM_182 182 467 #define CHANNEL_NUM_197 197 468 #define CHANNEL_FREQ_2484 2484 469 #define CHANNEL_FREQ_2407 2407 470 #define CHANNEL_FREQ_2512 2512 471 #define CHANNEL_FREQ_5000 5000 472 #define CHANNEL_FREQ_5950 5950 473 #define CHANNEL_FREQ_4000 4000 474 #define CHANNEL_FREQ_5150 5150 475 #define CHANNEL_FREQ_5920 5920 476 #define CHANNEL_FREQ_5935 5935 477 #define FREQ_MULTIPLIER_CONST_5MHZ 5 478 #define FREQ_MULTIPLIER_CONST_20MHZ 20 479 /** 480 * hal_rx_radiotap_num_to_freq() - Get frequency from chan number 481 * @chan_num - Input channel number 482 * @center_freq - Input Channel Center frequency 483 * 484 * Return - Channel frequency in Mhz 485 */ 486 static uint16_t 487 hal_rx_radiotap_num_to_freq(uint16_t chan_num, qdf_freq_t center_freq) 488 { 489 if (center_freq > CHANNEL_FREQ_5920 && center_freq < CHANNEL_FREQ_5950) 490 return CHANNEL_FREQ_5935; 491 492 if (center_freq < CHANNEL_FREQ_5950) { 493 if (chan_num == CHANNEL_NUM_14) 494 return CHANNEL_FREQ_2484; 495 if (chan_num < CHANNEL_NUM_14) 496 return CHANNEL_FREQ_2407 + 497 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 498 499 if (chan_num < CHANNEL_NUM_27) 500 return CHANNEL_FREQ_2512 + 501 ((chan_num - CHANNEL_NUM_15) * 502 FREQ_MULTIPLIER_CONST_20MHZ); 503 504 if (chan_num > CHANNEL_NUM_182 && 505 chan_num < CHANNEL_NUM_197) 506 return ((chan_num * FREQ_MULTIPLIER_CONST_5MHZ) + 507 CHANNEL_FREQ_4000); 508 509 return CHANNEL_FREQ_5000 + 510 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 511 } else { 512 return CHANNEL_FREQ_5950 + 513 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 514 } 515 } 516 517 /** 518 * hal_rx_status_get_tlv_info() - process receive info TLV 519 * @rx_tlv_hdr: pointer to TLV header 520 * @ppdu_info: pointer to ppdu_info 521 * 522 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 523 */ 524 static inline uint32_t 525 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 526 hal_soc_handle_t hal_soc_hdl, 527 qdf_nbuf_t nbuf) 528 { 529 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 530 uint32_t tlv_tag, user_id, tlv_len, value; 531 uint8_t group_id = 0; 532 uint8_t he_dcm = 0; 533 uint8_t he_stbc = 0; 534 uint16_t he_gi = 0; 535 uint16_t he_ltf = 0; 536 void *rx_tlv; 537 bool unhandled = false; 538 struct mon_rx_user_status *mon_rx_user_status; 539 struct hal_rx_ppdu_info *ppdu_info = 540 (struct hal_rx_ppdu_info *)ppduinfo; 541 542 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 543 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 544 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 545 546 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 547 548 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 549 rx_tlv, tlv_len); 550 551 switch (tlv_tag) { 552 553 case WIFIRX_PPDU_START_E: 554 { 555 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 556 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) 557 hal_err("Matching ppdu_id(%u) detected", 558 ppdu_info->com_info.last_ppdu_id); 559 560 /* Reset ppdu_info before processing the ppdu */ 561 qdf_mem_zero(ppdu_info, 562 sizeof(struct hal_rx_ppdu_info)); 563 564 ppdu_info->com_info.last_ppdu_id = 565 ppdu_info->com_info.ppdu_id = 566 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 567 PHY_PPDU_ID); 568 569 /* channel number is set in PHY meta data */ 570 ppdu_info->rx_status.chan_num = 571 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 572 SW_PHY_META_DATA) & 0x0000FFFF); 573 ppdu_info->rx_status.chan_freq = 574 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 575 SW_PHY_META_DATA) & 0xFFFF0000)>>16; 576 if (ppdu_info->rx_status.chan_num && 577 ppdu_info->rx_status.chan_freq) { 578 ppdu_info->rx_status.chan_freq = 579 hal_rx_radiotap_num_to_freq( 580 ppdu_info->rx_status.chan_num, 581 ppdu_info->rx_status.chan_freq); 582 } 583 ppdu_info->com_info.ppdu_timestamp = 584 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 585 PPDU_START_TIMESTAMP); 586 ppdu_info->rx_status.ppdu_timestamp = 587 ppdu_info->com_info.ppdu_timestamp; 588 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 589 590 break; 591 } 592 593 case WIFIRX_PPDU_START_USER_INFO_E: 594 break; 595 596 case WIFIRX_PPDU_END_E: 597 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 598 "[%s][%d] ppdu_end_e len=%d", 599 __func__, __LINE__, tlv_len); 600 /* This is followed by sub-TLVs of PPDU_END */ 601 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 602 break; 603 604 case WIFIPHYRX_PKT_END_E: 605 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 606 break; 607 608 case WIFIRXPCU_PPDU_END_INFO_E: 609 ppdu_info->rx_status.rx_antenna = 610 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 611 ppdu_info->rx_status.tsft = 612 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 613 WB_TIMESTAMP_UPPER_32); 614 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 615 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 616 WB_TIMESTAMP_LOWER_32); 617 ppdu_info->rx_status.duration = 618 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 619 RX_PPDU_DURATION); 620 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 621 break; 622 623 /* 624 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 625 * for MU, based on num users we see this tlv that many times. 626 */ 627 case WIFIRX_PPDU_END_USER_STATS_E: 628 { 629 unsigned long tid = 0; 630 uint16_t seq = 0; 631 632 ppdu_info->rx_status.ast_index = 633 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 634 AST_INDEX); 635 636 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 637 RECEIVED_QOS_DATA_TID_BITMAP); 638 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 639 640 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 641 ppdu_info->rx_status.tid = HAL_TID_INVALID; 642 643 ppdu_info->rx_status.tcp_msdu_count = 644 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 645 TCP_MSDU_COUNT) + 646 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 647 TCP_ACK_MSDU_COUNT); 648 ppdu_info->rx_status.udp_msdu_count = 649 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 650 UDP_MSDU_COUNT); 651 ppdu_info->rx_status.other_msdu_count = 652 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 653 OTHER_MSDU_COUNT); 654 655 if (ppdu_info->sw_frame_group_id 656 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 657 ppdu_info->rx_status.frame_control_info_valid = 658 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 659 FRAME_CONTROL_INFO_VALID); 660 661 if (ppdu_info->rx_status.frame_control_info_valid) 662 ppdu_info->rx_status.frame_control = 663 HAL_RX_GET(rx_tlv, 664 RX_PPDU_END_USER_STATS_4, 665 FRAME_CONTROL_FIELD); 666 667 hal_get_qos_control(rx_tlv, ppdu_info); 668 } 669 670 ppdu_info->rx_status.data_sequence_control_info_valid = 671 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 672 DATA_SEQUENCE_CONTROL_INFO_VALID); 673 674 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 675 FIRST_DATA_SEQ_CTRL); 676 if (ppdu_info->rx_status.data_sequence_control_info_valid) 677 ppdu_info->rx_status.first_data_seq_ctrl = seq; 678 679 ppdu_info->rx_status.preamble_type = 680 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 681 HT_CONTROL_FIELD_PKT_TYPE); 682 switch (ppdu_info->rx_status.preamble_type) { 683 case HAL_RX_PKT_TYPE_11N: 684 ppdu_info->rx_status.ht_flags = 1; 685 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 686 break; 687 case HAL_RX_PKT_TYPE_11AC: 688 ppdu_info->rx_status.vht_flags = 1; 689 break; 690 case HAL_RX_PKT_TYPE_11AX: 691 ppdu_info->rx_status.he_flags = 1; 692 break; 693 default: 694 break; 695 } 696 697 ppdu_info->com_info.mpdu_cnt_fcs_ok = 698 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 699 MPDU_CNT_FCS_OK); 700 ppdu_info->com_info.mpdu_cnt_fcs_err = 701 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 702 MPDU_CNT_FCS_ERR); 703 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 704 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 705 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 706 else 707 ppdu_info->rx_status.rs_flags &= 708 (~IEEE80211_AMPDU_FLAG); 709 710 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 711 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 712 FCS_OK_BITMAP_31_0); 713 714 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 715 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 716 FCS_OK_BITMAP_63_32); 717 718 if (user_id < HAL_MAX_UL_MU_USERS) { 719 mon_rx_user_status = 720 &ppdu_info->rx_user_status[user_id]; 721 722 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 723 724 ppdu_info->com_info.num_users++; 725 726 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 727 user_id, 728 mon_rx_user_status); 729 730 } 731 break; 732 } 733 734 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 735 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 736 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 737 FCS_OK_BITMAP_95_64); 738 739 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 740 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 741 FCS_OK_BITMAP_127_96); 742 743 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 744 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 745 FCS_OK_BITMAP_159_128); 746 747 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 748 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 749 FCS_OK_BITMAP_191_160); 750 751 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 752 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 753 FCS_OK_BITMAP_223_192); 754 755 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 756 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 757 FCS_OK_BITMAP_255_224); 758 break; 759 760 case WIFIRX_PPDU_END_STATUS_DONE_E: 761 return HAL_TLV_STATUS_PPDU_DONE; 762 763 case WIFIDUMMY_E: 764 return HAL_TLV_STATUS_BUF_DONE; 765 766 case WIFIPHYRX_HT_SIG_E: 767 { 768 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 769 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 770 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 771 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 772 FEC_CODING); 773 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 774 1 : 0; 775 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 776 HT_SIG_INFO_0, MCS); 777 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 778 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 779 HT_SIG_INFO_0, CBW); 780 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 781 HT_SIG_INFO_1, SHORT_GI); 782 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 783 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 784 HT_SIG_SU_NSS_SHIFT) + 1; 785 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 786 break; 787 } 788 789 case WIFIPHYRX_L_SIG_B_E: 790 { 791 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 792 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 793 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 794 795 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 796 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 797 switch (value) { 798 case 1: 799 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 800 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 801 break; 802 case 2: 803 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 804 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 805 break; 806 case 3: 807 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 808 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 809 break; 810 case 4: 811 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 812 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 813 break; 814 case 5: 815 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 816 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 817 break; 818 case 6: 819 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 820 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 821 break; 822 case 7: 823 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 824 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 825 break; 826 default: 827 break; 828 } 829 ppdu_info->rx_status.cck_flag = 1; 830 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 831 break; 832 } 833 834 case WIFIPHYRX_L_SIG_A_E: 835 { 836 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 837 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 838 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 839 840 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 841 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 842 switch (value) { 843 case 8: 844 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 845 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 846 break; 847 case 9: 848 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 849 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 850 break; 851 case 10: 852 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 853 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 854 break; 855 case 11: 856 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 857 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 858 break; 859 case 12: 860 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 861 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 862 break; 863 case 13: 864 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 865 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 866 break; 867 case 14: 868 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 869 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 870 break; 871 case 15: 872 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 873 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 874 break; 875 default: 876 break; 877 } 878 ppdu_info->rx_status.ofdm_flag = 1; 879 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 880 break; 881 } 882 883 case WIFIPHYRX_VHT_SIG_A_E: 884 { 885 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 886 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 887 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 888 889 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 890 SU_MU_CODING); 891 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 892 1 : 0; 893 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 894 ppdu_info->rx_status.vht_flag_values5 = group_id; 895 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 896 VHT_SIG_A_INFO_1, MCS); 897 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 898 VHT_SIG_A_INFO_1, GI_SETTING); 899 900 switch (hal->target_type) { 901 case TARGET_TYPE_QCA8074: 902 case TARGET_TYPE_QCA8074V2: 903 case TARGET_TYPE_QCA6018: 904 case TARGET_TYPE_QCA5018: 905 case TARGET_TYPE_QCN9000: 906 case TARGET_TYPE_QCN9100: 907 #ifdef QCA_WIFI_QCA6390 908 case TARGET_TYPE_QCA6390: 909 #endif 910 ppdu_info->rx_status.is_stbc = 911 HAL_RX_GET(vht_sig_a_info, 912 VHT_SIG_A_INFO_0, STBC); 913 value = HAL_RX_GET(vht_sig_a_info, 914 VHT_SIG_A_INFO_0, N_STS); 915 value = value & VHT_SIG_SU_NSS_MASK; 916 if (ppdu_info->rx_status.is_stbc && (value > 0)) 917 value = ((value + 1) >> 1) - 1; 918 ppdu_info->rx_status.nss = 919 ((value & VHT_SIG_SU_NSS_MASK) + 1); 920 921 break; 922 case TARGET_TYPE_QCA6290: 923 #if !defined(QCA_WIFI_QCA6290_11AX) 924 ppdu_info->rx_status.is_stbc = 925 HAL_RX_GET(vht_sig_a_info, 926 VHT_SIG_A_INFO_0, STBC); 927 value = HAL_RX_GET(vht_sig_a_info, 928 VHT_SIG_A_INFO_0, N_STS); 929 value = value & VHT_SIG_SU_NSS_MASK; 930 if (ppdu_info->rx_status.is_stbc && (value > 0)) 931 value = ((value + 1) >> 1) - 1; 932 ppdu_info->rx_status.nss = 933 ((value & VHT_SIG_SU_NSS_MASK) + 1); 934 #else 935 ppdu_info->rx_status.nss = 0; 936 #endif 937 break; 938 case TARGET_TYPE_QCA6490: 939 case TARGET_TYPE_QCA6750: 940 ppdu_info->rx_status.nss = 0; 941 break; 942 default: 943 break; 944 } 945 ppdu_info->rx_status.vht_flag_values3[0] = 946 (((ppdu_info->rx_status.mcs) << 4) 947 | ppdu_info->rx_status.nss); 948 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 949 VHT_SIG_A_INFO_0, BANDWIDTH); 950 ppdu_info->rx_status.vht_flag_values2 = 951 ppdu_info->rx_status.bw; 952 ppdu_info->rx_status.vht_flag_values4 = 953 HAL_RX_GET(vht_sig_a_info, 954 VHT_SIG_A_INFO_1, SU_MU_CODING); 955 956 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 957 VHT_SIG_A_INFO_1, BEAMFORMED); 958 if (group_id == 0 || group_id == 63) 959 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 960 else 961 ppdu_info->rx_status.reception_type = 962 HAL_RX_TYPE_MU_MIMO; 963 964 break; 965 } 966 case WIFIPHYRX_HE_SIG_A_SU_E: 967 { 968 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 969 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 970 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 971 ppdu_info->rx_status.he_flags = 1; 972 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 973 FORMAT_INDICATION); 974 if (value == 0) { 975 ppdu_info->rx_status.he_data1 = 976 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 977 } else { 978 ppdu_info->rx_status.he_data1 = 979 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 980 } 981 982 /* data1 */ 983 ppdu_info->rx_status.he_data1 |= 984 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 985 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 986 QDF_MON_STATUS_HE_DL_UL_KNOWN | 987 QDF_MON_STATUS_HE_MCS_KNOWN | 988 QDF_MON_STATUS_HE_DCM_KNOWN | 989 QDF_MON_STATUS_HE_CODING_KNOWN | 990 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 991 QDF_MON_STATUS_HE_STBC_KNOWN | 992 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 993 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 994 995 /* data2 */ 996 ppdu_info->rx_status.he_data2 = 997 QDF_MON_STATUS_HE_GI_KNOWN; 998 ppdu_info->rx_status.he_data2 |= 999 QDF_MON_STATUS_TXBF_KNOWN | 1000 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1001 QDF_MON_STATUS_TXOP_KNOWN | 1002 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1003 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1004 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1005 1006 /* data3 */ 1007 value = HAL_RX_GET(he_sig_a_su_info, 1008 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1009 ppdu_info->rx_status.he_data3 = value; 1010 value = HAL_RX_GET(he_sig_a_su_info, 1011 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1012 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1013 ppdu_info->rx_status.he_data3 |= value; 1014 value = HAL_RX_GET(he_sig_a_su_info, 1015 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1016 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1017 ppdu_info->rx_status.he_data3 |= value; 1018 1019 value = HAL_RX_GET(he_sig_a_su_info, 1020 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1021 ppdu_info->rx_status.mcs = value; 1022 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1023 ppdu_info->rx_status.he_data3 |= value; 1024 1025 value = HAL_RX_GET(he_sig_a_su_info, 1026 HE_SIG_A_SU_INFO_0, DCM); 1027 he_dcm = value; 1028 value = value << QDF_MON_STATUS_DCM_SHIFT; 1029 ppdu_info->rx_status.he_data3 |= value; 1030 value = HAL_RX_GET(he_sig_a_su_info, 1031 HE_SIG_A_SU_INFO_1, CODING); 1032 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1033 1 : 0; 1034 value = value << QDF_MON_STATUS_CODING_SHIFT; 1035 ppdu_info->rx_status.he_data3 |= value; 1036 value = HAL_RX_GET(he_sig_a_su_info, 1037 HE_SIG_A_SU_INFO_1, 1038 LDPC_EXTRA_SYMBOL); 1039 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1040 ppdu_info->rx_status.he_data3 |= value; 1041 value = HAL_RX_GET(he_sig_a_su_info, 1042 HE_SIG_A_SU_INFO_1, STBC); 1043 he_stbc = value; 1044 value = value << QDF_MON_STATUS_STBC_SHIFT; 1045 ppdu_info->rx_status.he_data3 |= value; 1046 1047 /* data4 */ 1048 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1049 SPATIAL_REUSE); 1050 ppdu_info->rx_status.he_data4 = value; 1051 1052 /* data5 */ 1053 value = HAL_RX_GET(he_sig_a_su_info, 1054 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1055 ppdu_info->rx_status.he_data5 = value; 1056 ppdu_info->rx_status.bw = value; 1057 value = HAL_RX_GET(he_sig_a_su_info, 1058 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1059 switch (value) { 1060 case 0: 1061 he_gi = HE_GI_0_8; 1062 he_ltf = HE_LTF_1_X; 1063 break; 1064 case 1: 1065 he_gi = HE_GI_0_8; 1066 he_ltf = HE_LTF_2_X; 1067 break; 1068 case 2: 1069 he_gi = HE_GI_1_6; 1070 he_ltf = HE_LTF_2_X; 1071 break; 1072 case 3: 1073 if (he_dcm && he_stbc) { 1074 he_gi = HE_GI_0_8; 1075 he_ltf = HE_LTF_4_X; 1076 } else { 1077 he_gi = HE_GI_3_2; 1078 he_ltf = HE_LTF_4_X; 1079 } 1080 break; 1081 } 1082 ppdu_info->rx_status.sgi = he_gi; 1083 ppdu_info->rx_status.ltf_size = he_ltf; 1084 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1085 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1086 ppdu_info->rx_status.he_data5 |= value; 1087 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1088 ppdu_info->rx_status.he_data5 |= value; 1089 1090 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1091 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1092 ppdu_info->rx_status.he_data5 |= value; 1093 1094 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1095 PACKET_EXTENSION_A_FACTOR); 1096 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1097 ppdu_info->rx_status.he_data5 |= value; 1098 1099 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1100 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1101 ppdu_info->rx_status.he_data5 |= value; 1102 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1103 PACKET_EXTENSION_PE_DISAMBIGUITY); 1104 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1105 ppdu_info->rx_status.he_data5 |= value; 1106 1107 /* data6 */ 1108 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1109 value++; 1110 ppdu_info->rx_status.nss = value; 1111 ppdu_info->rx_status.he_data6 = value; 1112 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1113 DOPPLER_INDICATION); 1114 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1115 ppdu_info->rx_status.he_data6 |= value; 1116 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1117 TXOP_DURATION); 1118 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1119 ppdu_info->rx_status.he_data6 |= value; 1120 1121 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1122 HE_SIG_A_SU_INFO_1, TXBF); 1123 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1124 break; 1125 } 1126 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1127 { 1128 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1129 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1130 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1131 1132 ppdu_info->rx_status.he_mu_flags = 1; 1133 1134 /* HE Flags */ 1135 /*data1*/ 1136 ppdu_info->rx_status.he_data1 = 1137 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1138 ppdu_info->rx_status.he_data1 |= 1139 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1140 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1141 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1142 QDF_MON_STATUS_HE_STBC_KNOWN | 1143 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1144 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1145 1146 /* data2 */ 1147 ppdu_info->rx_status.he_data2 = 1148 QDF_MON_STATUS_HE_GI_KNOWN; 1149 ppdu_info->rx_status.he_data2 |= 1150 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1151 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1152 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1153 QDF_MON_STATUS_TXOP_KNOWN | 1154 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1155 1156 /*data3*/ 1157 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1158 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1159 ppdu_info->rx_status.he_data3 = value; 1160 1161 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1162 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1163 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1164 ppdu_info->rx_status.he_data3 |= value; 1165 1166 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1167 HE_SIG_A_MU_DL_INFO_1, 1168 LDPC_EXTRA_SYMBOL); 1169 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1170 ppdu_info->rx_status.he_data3 |= value; 1171 1172 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1173 HE_SIG_A_MU_DL_INFO_1, STBC); 1174 he_stbc = value; 1175 value = value << QDF_MON_STATUS_STBC_SHIFT; 1176 ppdu_info->rx_status.he_data3 |= value; 1177 1178 /*data4*/ 1179 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1180 SPATIAL_REUSE); 1181 ppdu_info->rx_status.he_data4 = value; 1182 1183 /*data5*/ 1184 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1185 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1186 ppdu_info->rx_status.he_data5 = value; 1187 ppdu_info->rx_status.bw = value; 1188 1189 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1190 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1191 switch (value) { 1192 case 0: 1193 he_gi = HE_GI_0_8; 1194 he_ltf = HE_LTF_4_X; 1195 break; 1196 case 1: 1197 he_gi = HE_GI_0_8; 1198 he_ltf = HE_LTF_2_X; 1199 break; 1200 case 2: 1201 he_gi = HE_GI_1_6; 1202 he_ltf = HE_LTF_2_X; 1203 break; 1204 case 3: 1205 he_gi = HE_GI_3_2; 1206 he_ltf = HE_LTF_4_X; 1207 break; 1208 } 1209 ppdu_info->rx_status.sgi = he_gi; 1210 ppdu_info->rx_status.ltf_size = he_ltf; 1211 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1212 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1213 ppdu_info->rx_status.he_data5 |= value; 1214 1215 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1216 ppdu_info->rx_status.he_data5 |= value; 1217 1218 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1219 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1220 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1221 ppdu_info->rx_status.he_data5 |= value; 1222 1223 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1224 PACKET_EXTENSION_A_FACTOR); 1225 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1226 ppdu_info->rx_status.he_data5 |= value; 1227 1228 1229 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1230 PACKET_EXTENSION_PE_DISAMBIGUITY); 1231 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1232 ppdu_info->rx_status.he_data5 |= value; 1233 1234 /*data6*/ 1235 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1236 DOPPLER_INDICATION); 1237 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1238 ppdu_info->rx_status.he_data6 |= value; 1239 1240 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1241 TXOP_DURATION); 1242 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1243 ppdu_info->rx_status.he_data6 |= value; 1244 1245 /* HE-MU Flags */ 1246 /* HE-MU-flags1 */ 1247 ppdu_info->rx_status.he_flags1 = 1248 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1249 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1250 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1251 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1252 QDF_MON_STATUS_RU_0_KNOWN; 1253 1254 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1255 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1256 ppdu_info->rx_status.he_flags1 |= value; 1257 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1258 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1259 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1260 ppdu_info->rx_status.he_flags1 |= value; 1261 1262 /* HE-MU-flags2 */ 1263 ppdu_info->rx_status.he_flags2 = 1264 QDF_MON_STATUS_BW_KNOWN; 1265 1266 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1267 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1268 ppdu_info->rx_status.he_flags2 |= value; 1269 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1270 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1271 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1272 ppdu_info->rx_status.he_flags2 |= value; 1273 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1274 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1275 value = value - 1; 1276 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1277 ppdu_info->rx_status.he_flags2 |= value; 1278 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1279 break; 1280 } 1281 case WIFIPHYRX_HE_SIG_B1_MU_E: 1282 { 1283 1284 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1285 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1286 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1287 1288 ppdu_info->rx_status.he_sig_b_common_known |= 1289 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1290 /* TODO: Check on the availability of other fields in 1291 * sig_b_common 1292 */ 1293 1294 value = HAL_RX_GET(he_sig_b1_mu_info, 1295 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1296 ppdu_info->rx_status.he_RU[0] = value; 1297 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1298 break; 1299 } 1300 case WIFIPHYRX_HE_SIG_B2_MU_E: 1301 { 1302 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1303 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1304 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1305 /* 1306 * Not all "HE" fields can be updated from 1307 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1308 * to populate rest of the "HE" fields for MU scenarios. 1309 */ 1310 1311 /* HE-data1 */ 1312 ppdu_info->rx_status.he_data1 |= 1313 QDF_MON_STATUS_HE_MCS_KNOWN | 1314 QDF_MON_STATUS_HE_CODING_KNOWN; 1315 1316 /* HE-data2 */ 1317 1318 /* HE-data3 */ 1319 value = HAL_RX_GET(he_sig_b2_mu_info, 1320 HE_SIG_B2_MU_INFO_0, STA_MCS); 1321 ppdu_info->rx_status.mcs = value; 1322 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1323 ppdu_info->rx_status.he_data3 |= value; 1324 1325 1326 value = HAL_RX_GET(he_sig_b2_mu_info, 1327 HE_SIG_B2_MU_INFO_0, STA_CODING); 1328 value = value << QDF_MON_STATUS_CODING_SHIFT; 1329 ppdu_info->rx_status.he_data3 |= value; 1330 1331 /* HE-data4 */ 1332 value = HAL_RX_GET(he_sig_b2_mu_info, 1333 HE_SIG_B2_MU_INFO_0, STA_ID); 1334 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1335 ppdu_info->rx_status.he_data4 |= value; 1336 1337 /* HE-data5 */ 1338 1339 /* HE-data6 */ 1340 value = HAL_RX_GET(he_sig_b2_mu_info, 1341 HE_SIG_B2_MU_INFO_0, NSTS); 1342 /* value n indicates n+1 spatial streams */ 1343 value++; 1344 ppdu_info->rx_status.nss = value; 1345 ppdu_info->rx_status.he_data6 |= value; 1346 1347 break; 1348 1349 } 1350 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1351 { 1352 uint8_t *he_sig_b2_ofdma_info = 1353 (uint8_t *)rx_tlv + 1354 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1355 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1356 1357 /* 1358 * Not all "HE" fields can be updated from 1359 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1360 * to populate rest of "HE" fields for MU OFDMA scenarios. 1361 */ 1362 1363 /* HE-data1 */ 1364 ppdu_info->rx_status.he_data1 |= 1365 QDF_MON_STATUS_HE_MCS_KNOWN | 1366 QDF_MON_STATUS_HE_DCM_KNOWN | 1367 QDF_MON_STATUS_HE_CODING_KNOWN; 1368 1369 /* HE-data2 */ 1370 ppdu_info->rx_status.he_data2 |= 1371 QDF_MON_STATUS_TXBF_KNOWN; 1372 1373 /* HE-data3 */ 1374 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1375 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1376 ppdu_info->rx_status.mcs = value; 1377 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1378 ppdu_info->rx_status.he_data3 |= value; 1379 1380 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1381 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1382 he_dcm = value; 1383 value = value << QDF_MON_STATUS_DCM_SHIFT; 1384 ppdu_info->rx_status.he_data3 |= value; 1385 1386 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1387 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1388 value = value << QDF_MON_STATUS_CODING_SHIFT; 1389 ppdu_info->rx_status.he_data3 |= value; 1390 1391 /* HE-data4 */ 1392 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1393 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1394 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1395 ppdu_info->rx_status.he_data4 |= value; 1396 1397 /* HE-data5 */ 1398 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1399 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1400 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1401 ppdu_info->rx_status.he_data5 |= value; 1402 1403 /* HE-data6 */ 1404 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1405 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1406 /* value n indicates n+1 spatial streams */ 1407 value++; 1408 ppdu_info->rx_status.nss = value; 1409 ppdu_info->rx_status.he_data6 |= value; 1410 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1411 break; 1412 } 1413 case WIFIPHYRX_RSSI_LEGACY_E: 1414 { 1415 uint8_t reception_type; 1416 int8_t rssi_value; 1417 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1418 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1419 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1420 1421 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1422 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1423 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1424 ppdu_info->rx_status.he_re = 0; 1425 1426 reception_type = HAL_RX_GET(rx_tlv, 1427 PHYRX_RSSI_LEGACY_0, 1428 RECEPTION_TYPE); 1429 switch (reception_type) { 1430 case QDF_RECEPTION_TYPE_ULOFMDA: 1431 ppdu_info->rx_status.reception_type = 1432 HAL_RX_TYPE_MU_OFDMA; 1433 ppdu_info->rx_status.ulofdma_flag = 1; 1434 ppdu_info->rx_status.he_data1 = 1435 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1436 break; 1437 case QDF_RECEPTION_TYPE_ULMIMO: 1438 ppdu_info->rx_status.reception_type = 1439 HAL_RX_TYPE_MU_MIMO; 1440 ppdu_info->rx_status.he_data1 = 1441 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1442 break; 1443 default: 1444 ppdu_info->rx_status.reception_type = 1445 HAL_RX_TYPE_SU; 1446 break; 1447 } 1448 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1449 rssi_value = HAL_RX_GET(rssi_info_tlv, 1450 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1451 ppdu_info->rx_status.rssi[0] = rssi_value; 1452 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1453 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1454 1455 rssi_value = HAL_RX_GET(rssi_info_tlv, 1456 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1457 ppdu_info->rx_status.rssi[1] = rssi_value; 1458 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1459 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1460 1461 rssi_value = HAL_RX_GET(rssi_info_tlv, 1462 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1463 ppdu_info->rx_status.rssi[2] = rssi_value; 1464 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1465 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1466 1467 rssi_value = HAL_RX_GET(rssi_info_tlv, 1468 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1469 ppdu_info->rx_status.rssi[3] = rssi_value; 1470 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1471 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1472 1473 rssi_value = HAL_RX_GET(rssi_info_tlv, 1474 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1475 ppdu_info->rx_status.rssi[4] = rssi_value; 1476 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1477 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1478 1479 rssi_value = HAL_RX_GET(rssi_info_tlv, 1480 RECEIVE_RSSI_INFO_10, 1481 RSSI_PRI20_CHAIN5); 1482 ppdu_info->rx_status.rssi[5] = rssi_value; 1483 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1484 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1485 1486 rssi_value = HAL_RX_GET(rssi_info_tlv, 1487 RECEIVE_RSSI_INFO_12, 1488 RSSI_PRI20_CHAIN6); 1489 ppdu_info->rx_status.rssi[6] = rssi_value; 1490 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1491 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1492 1493 rssi_value = HAL_RX_GET(rssi_info_tlv, 1494 RECEIVE_RSSI_INFO_14, 1495 RSSI_PRI20_CHAIN7); 1496 ppdu_info->rx_status.rssi[7] = rssi_value; 1497 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1498 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1499 break; 1500 } 1501 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1502 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1503 ppdu_info); 1504 break; 1505 case WIFIRX_HEADER_E: 1506 { 1507 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1508 1509 if (ppdu_info->fcs_ok_cnt >= 1510 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1511 hal_err("Number of MPDUs(%d) per status buff exceeded", 1512 ppdu_info->fcs_ok_cnt); 1513 break; 1514 } 1515 1516 /* Update first_msdu_payload for every mpdu and increment 1517 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1518 */ 1519 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1520 rx_tlv; 1521 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1522 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1523 ppdu_info->msdu_info.payload_len = tlv_len; 1524 ppdu_info->user_id = user_id; 1525 ppdu_info->hdr_len = tlv_len; 1526 ppdu_info->data = rx_tlv; 1527 ppdu_info->data += 4; 1528 1529 /* for every RX_HEADER TLV increment mpdu_cnt */ 1530 com_info->mpdu_cnt++; 1531 return HAL_TLV_STATUS_HEADER; 1532 } 1533 case WIFIRX_MPDU_START_E: 1534 { 1535 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1536 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1537 uint8_t filter_category = 0; 1538 1539 ppdu_info->nac_info.fc_valid = 1540 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1541 1542 ppdu_info->nac_info.to_ds_flag = 1543 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1544 1545 ppdu_info->nac_info.frame_control = 1546 HAL_RX_GET(rx_mpdu_start, 1547 RX_MPDU_INFO_14, 1548 MPDU_FRAME_CONTROL_FIELD); 1549 1550 ppdu_info->sw_frame_group_id = 1551 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1552 1553 if (ppdu_info->sw_frame_group_id == 1554 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1555 ppdu_info->rx_status.frame_control_info_valid = 1556 ppdu_info->nac_info.fc_valid; 1557 ppdu_info->rx_status.frame_control = 1558 ppdu_info->nac_info.frame_control; 1559 } 1560 1561 hal_get_mac_addr1(rx_mpdu_start, 1562 ppdu_info); 1563 1564 ppdu_info->nac_info.mac_addr2_valid = 1565 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1566 1567 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1568 HAL_RX_GET(rx_mpdu_start, 1569 RX_MPDU_INFO_16, 1570 MAC_ADDR_AD2_15_0); 1571 1572 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1573 HAL_RX_GET(rx_mpdu_start, 1574 RX_MPDU_INFO_17, 1575 MAC_ADDR_AD2_47_16); 1576 1577 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1578 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1579 ppdu_info->rx_status.ppdu_len = 1580 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1581 MPDU_LENGTH); 1582 } else { 1583 ppdu_info->rx_status.ppdu_len += 1584 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1585 MPDU_LENGTH); 1586 } 1587 1588 filter_category = 1589 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1590 1591 if (filter_category == 0) 1592 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1593 else if (filter_category == 1) 1594 ppdu_info->rx_status.monitor_direct_used = 1; 1595 1596 ppdu_info->nac_info.mcast_bcast = 1597 HAL_RX_GET(rx_mpdu_start, 1598 RX_MPDU_INFO_13, 1599 MCAST_BCAST); 1600 break; 1601 } 1602 case WIFIRX_MPDU_END_E: 1603 ppdu_info->user_id = user_id; 1604 ppdu_info->fcs_err = 1605 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1606 FCS_ERR); 1607 return HAL_TLV_STATUS_MPDU_END; 1608 case WIFIRX_MSDU_END_E: 1609 if (user_id < HAL_MAX_UL_MU_USERS) { 1610 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1611 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1612 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1613 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1614 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1615 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1616 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1617 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1618 ppdu_info->rx_msdu_info[user_id].flow_idx = 1619 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1620 } 1621 return HAL_TLV_STATUS_MSDU_END; 1622 case 0: 1623 return HAL_TLV_STATUS_PPDU_DONE; 1624 1625 default: 1626 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1627 unhandled = false; 1628 else 1629 unhandled = true; 1630 break; 1631 } 1632 1633 if (!unhandled) 1634 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1635 "%s TLV type: %d, TLV len:%d %s", 1636 __func__, tlv_tag, tlv_len, 1637 unhandled == true ? "unhandled" : ""); 1638 1639 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1640 rx_tlv, tlv_len); 1641 1642 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1643 } 1644 1645 static void hal_setup_reo_swap(struct hal_soc *soc) 1646 { 1647 uint32_t reg_val; 1648 1649 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 1650 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1651 1652 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); 1653 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); 1654 1655 #if defined(QDF_BIG_ENDIAN_MACHINE) 1656 HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 1657 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1658 #endif 1659 } 1660 1661 /** 1662 * hal_reo_setup - Initialize HW REO block 1663 * 1664 * @hal_soc: Opaque HAL SOC handle 1665 * @reo_params: parameters needed by HAL for REO config 1666 */ 1667 static void hal_reo_setup_generic(struct hal_soc *soc, 1668 void *reoparams) 1669 { 1670 uint32_t reg_val; 1671 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1672 1673 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1674 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1675 1676 hal_reo_config(soc, reg_val, reo_params); 1677 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1678 1679 /* TODO: Setup destination ring mapping if enabled */ 1680 1681 /* TODO: Error destination ring setting is left to default. 1682 * Default setting is to send all errors to release ring. 1683 */ 1684 1685 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1686 hal_setup_reo_swap(soc); 1687 1688 HAL_REG_WRITE(soc, 1689 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1690 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1691 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1692 1693 HAL_REG_WRITE(soc, 1694 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1695 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1696 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1697 1698 HAL_REG_WRITE(soc, 1699 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1700 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1701 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1702 1703 HAL_REG_WRITE(soc, 1704 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1705 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1706 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1707 1708 /* 1709 * When hash based routing is enabled, routing of the rx packet 1710 * is done based on the following value: 1 _ _ _ _ The last 4 1711 * bits are based on hash[3:0]. This means the possible values 1712 * are 0x10 to 0x1f. This value is used to look-up the 1713 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1714 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1715 * registers need to be configured to set-up the 16 entries to 1716 * map the hash values to a ring number. There are 3 bits per 1717 * hash entry – which are mapped as follows: 1718 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1719 * 7: NOT_USED. 1720 */ 1721 if (reo_params->rx_hash_enabled) { 1722 HAL_REG_WRITE(soc, 1723 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1724 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1725 reo_params->remap1); 1726 1727 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1728 HAL_REG_READ(soc, 1729 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1730 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1731 1732 HAL_REG_WRITE(soc, 1733 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1734 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1735 reo_params->remap2); 1736 1737 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1738 HAL_REG_READ(soc, 1739 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1740 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1741 } 1742 1743 /* TODO: Check if the following registers shoould be setup by host: 1744 * AGING_CONTROL 1745 * HIGH_MEMORY_THRESHOLD 1746 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1747 * GLOBAL_LINK_DESC_COUNT_CTRL 1748 */ 1749 } 1750 1751 /** 1752 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1753 * @hal_soc: Opaque HAL SOC handle 1754 * @hal_ring: Source ring pointer 1755 * @headp: Head Pointer 1756 * @tailp: Tail Pointer 1757 * @ring: Ring type 1758 * 1759 * Return: Update tail pointer and head pointer in arguments. 1760 */ 1761 static inline 1762 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 1763 hal_ring_handle_t hal_ring_hdl, 1764 uint32_t *headp, uint32_t *tailp, 1765 uint8_t ring) 1766 { 1767 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1768 struct hal_hw_srng_config *ring_config; 1769 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1770 1771 if (!hal_soc || !srng) { 1772 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1773 "%s: Context is Null", __func__); 1774 return; 1775 } 1776 1777 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 1778 if (!ring_config->lmac_ring) { 1779 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1780 *headp = SRNG_SRC_REG_READ(srng, HP); 1781 *tailp = SRNG_SRC_REG_READ(srng, TP); 1782 } else { 1783 *headp = SRNG_DST_REG_READ(srng, HP); 1784 *tailp = SRNG_DST_REG_READ(srng, TP); 1785 } 1786 } 1787 } 1788 1789 #if defined(WBM_IDLE_LSB_WRITE_CONFIRM_WAR) 1790 /** 1791 * hal_wbm_idle_lsb_write_confirm() - Check and update WBM_IDLE_LINK ring LSB 1792 * @srng: srng handle 1793 * 1794 * Return: None 1795 */ 1796 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 1797 { 1798 if (srng->ring_id == HAL_SRNG_WBM_IDLE_LINK) { 1799 while (SRNG_SRC_REG_READ(srng, BASE_LSB) != 1800 ((unsigned int)srng->ring_base_paddr & 0xffffffff)) 1801 SRNG_SRC_REG_WRITE(srng, BASE_LSB, 1802 srng->ring_base_paddr & 1803 0xffffffff); 1804 } 1805 } 1806 #else 1807 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 1808 { 1809 } 1810 #endif 1811 1812 /** 1813 * hal_srng_src_hw_init - Private function to initialize SRNG 1814 * source ring HW 1815 * @hal_soc: HAL SOC handle 1816 * @srng: SRNG ring pointer 1817 */ 1818 static inline 1819 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 1820 struct hal_srng *srng) 1821 { 1822 uint32_t reg_val = 0; 1823 uint64_t tp_addr = 0; 1824 1825 hal_debug("hw_init srng %d", srng->ring_id); 1826 1827 if (srng->flags & HAL_SRNG_MSI_INTR) { 1828 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1829 srng->msi_addr & 0xffffffff); 1830 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1831 (uint64_t)(srng->msi_addr) >> 32) | 1832 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1833 MSI1_ENABLE), 1); 1834 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1835 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, 1836 qdf_cpu_to_le32(srng->msi_data)); 1837 } 1838 1839 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1840 hal_wbm_idle_lsb_write_confirm(srng); 1841 1842 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1843 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1844 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1845 srng->entry_size * srng->num_entries); 1846 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1847 1848 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1849 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1850 1851 /** 1852 * Interrupt setup: 1853 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1854 * if level mode is required 1855 */ 1856 reg_val = 0; 1857 1858 /* 1859 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1860 * programmed in terms of 1us resolution instead of 8us resolution as 1861 * given in MLD. 1862 */ 1863 if (srng->intr_timer_thres_us) { 1864 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1865 INTERRUPT_TIMER_THRESHOLD), 1866 srng->intr_timer_thres_us); 1867 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1868 } 1869 1870 if (srng->intr_batch_cntr_thres_entries) { 1871 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1872 BATCH_COUNTER_THRESHOLD), 1873 srng->intr_batch_cntr_thres_entries * 1874 srng->entry_size); 1875 } 1876 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1877 1878 reg_val = 0; 1879 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1880 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1881 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1882 } 1883 1884 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1885 1886 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1887 * remain 0 to avoid some WBM stability issues. Remote head/tail 1888 * pointers are not required since this ring is completely managed 1889 * by WBM HW 1890 */ 1891 reg_val = 0; 1892 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1893 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1894 ((unsigned long)(srng->u.src_ring.tp_addr) - 1895 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1896 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1897 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1898 } else { 1899 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1900 } 1901 1902 /* Initilaize head and tail pointers to indicate ring is empty */ 1903 SRNG_SRC_REG_WRITE(srng, HP, 0); 1904 SRNG_SRC_REG_WRITE(srng, TP, 0); 1905 *(srng->u.src_ring.tp_addr) = 0; 1906 1907 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1908 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1909 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1910 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1911 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1912 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1913 1914 /* Loop count is not used for SRC rings */ 1915 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1916 1917 /* 1918 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1919 * todo: update fw_api and replace with above line 1920 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1921 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1922 */ 1923 reg_val |= 0x40; 1924 1925 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1926 } 1927 1928 /** 1929 * hal_srng_dst_hw_init - Private function to initialize SRNG 1930 * destination ring HW 1931 * @hal_soc: HAL SOC handle 1932 * @srng: SRNG ring pointer 1933 */ 1934 static inline 1935 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 1936 struct hal_srng *srng) 1937 { 1938 uint32_t reg_val = 0; 1939 uint64_t hp_addr = 0; 1940 1941 hal_debug("hw_init srng %d", srng->ring_id); 1942 1943 if (srng->flags & HAL_SRNG_MSI_INTR) { 1944 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1945 srng->msi_addr & 0xffffffff); 1946 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1947 (uint64_t)(srng->msi_addr) >> 32) | 1948 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1949 MSI1_ENABLE), 1); 1950 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1951 SRNG_DST_REG_WRITE(srng, MSI1_DATA, 1952 qdf_cpu_to_le32(srng->msi_data)); 1953 } 1954 1955 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1956 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1957 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1958 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1959 srng->entry_size * srng->num_entries); 1960 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1961 1962 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1963 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1964 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1965 1966 1967 /** 1968 * Interrupt setup: 1969 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1970 * if level mode is required 1971 */ 1972 reg_val = 0; 1973 if (srng->intr_timer_thres_us) { 1974 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1975 INTERRUPT_TIMER_THRESHOLD), 1976 srng->intr_timer_thres_us >> 3); 1977 } 1978 1979 if (srng->intr_batch_cntr_thres_entries) { 1980 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1981 BATCH_COUNTER_THRESHOLD), 1982 srng->intr_batch_cntr_thres_entries * 1983 srng->entry_size); 1984 } 1985 1986 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1987 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1988 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1989 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1990 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1991 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1992 1993 /* Initilaize head and tail pointers to indicate ring is empty */ 1994 SRNG_DST_REG_WRITE(srng, HP, 0); 1995 SRNG_DST_REG_WRITE(srng, TP, 0); 1996 *(srng->u.dst_ring.hp_addr) = 0; 1997 1998 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1999 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 2000 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 2001 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 2002 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 2003 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 2004 2005 /* 2006 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 2007 * todo: update fw_api and replace with above line 2008 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 2009 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 2010 */ 2011 reg_val |= 0x40; 2012 2013 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 2014 2015 } 2016 2017 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2018 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 2019 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 2020 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 2021 2022 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2023 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 2024 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 2025 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 2026 2027 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 2028 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 2029 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 2030 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 2031 2032 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 2033 (((*(((uint32_t *) wbm_desc) + \ 2034 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 2035 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 2036 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 2037 2038 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 2039 (((*(((uint32_t *) wbm_desc) + \ 2040 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 2041 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 2042 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 2043 2044 /** 2045 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 2046 * save it to hal_wbm_err_desc_info structure passed by caller 2047 * @wbm_desc: wbm ring descriptor 2048 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 2049 * Return: void 2050 */ 2051 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 2052 void *wbm_er_info1) 2053 { 2054 struct hal_wbm_err_desc_info *wbm_er_info = 2055 (struct hal_wbm_err_desc_info *)wbm_er_info1; 2056 2057 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 2058 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 2059 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 2060 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 2061 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 2062 } 2063 2064 /** 2065 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 2066 * @hal_desc: completion ring descriptor pointer 2067 * 2068 * This function will return the type of pointer - buffer or descriptor 2069 * 2070 * Return: buffer type 2071 */ 2072 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 2073 { 2074 uint32_t comp_desc = 2075 *(uint32_t *) (((uint8_t *) hal_desc) + 2076 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 2077 2078 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 2079 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 2080 } 2081 2082 /** 2083 * hal_get_wbm_internal_error_generic() - is WBM internal error 2084 * @hal_desc: completion ring descriptor pointer 2085 * 2086 * This function will return 0 or 1 - is it WBM internal error or not 2087 * 2088 * Return: uint8_t 2089 */ 2090 static inline uint8_t hal_get_wbm_internal_error_generic(void *hal_desc) 2091 { 2092 uint32_t comp_desc = 2093 *(uint32_t *)(((uint8_t *)hal_desc) + 2094 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET); 2095 2096 return (comp_desc & WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK) >> 2097 WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB; 2098 } 2099 2100 /** 2101 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 2102 * human readable format. 2103 * @mpdu_start: pointer the rx_attention TLV in pkt. 2104 * @dbg_level: log level. 2105 * 2106 * Return: void 2107 */ 2108 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 2109 uint8_t dbg_level) 2110 { 2111 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 2112 struct rx_mpdu_info *mpdu_info = 2113 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 2114 2115 hal_verbose_debug( 2116 "rx_mpdu_start tlv (1/5) - " 2117 "rxpcu_mpdu_filter_in_category: %x " 2118 "sw_frame_group_id: %x " 2119 "ndp_frame: %x " 2120 "phy_err: %x " 2121 "phy_err_during_mpdu_header: %x " 2122 "protocol_version_err: %x " 2123 "ast_based_lookup_valid: %x " 2124 "phy_ppdu_id: %x " 2125 "ast_index: %x " 2126 "sw_peer_id: %x " 2127 "mpdu_frame_control_valid: %x " 2128 "mpdu_duration_valid: %x " 2129 "mac_addr_ad1_valid: %x " 2130 "mac_addr_ad2_valid: %x " 2131 "mac_addr_ad3_valid: %x " 2132 "mac_addr_ad4_valid: %x " 2133 "mpdu_sequence_control_valid: %x " 2134 "mpdu_qos_control_valid: %x " 2135 "mpdu_ht_control_valid: %x " 2136 "frame_encryption_info_valid: %x ", 2137 mpdu_info->rxpcu_mpdu_filter_in_category, 2138 mpdu_info->sw_frame_group_id, 2139 mpdu_info->ndp_frame, 2140 mpdu_info->phy_err, 2141 mpdu_info->phy_err_during_mpdu_header, 2142 mpdu_info->protocol_version_err, 2143 mpdu_info->ast_based_lookup_valid, 2144 mpdu_info->phy_ppdu_id, 2145 mpdu_info->ast_index, 2146 mpdu_info->sw_peer_id, 2147 mpdu_info->mpdu_frame_control_valid, 2148 mpdu_info->mpdu_duration_valid, 2149 mpdu_info->mac_addr_ad1_valid, 2150 mpdu_info->mac_addr_ad2_valid, 2151 mpdu_info->mac_addr_ad3_valid, 2152 mpdu_info->mac_addr_ad4_valid, 2153 mpdu_info->mpdu_sequence_control_valid, 2154 mpdu_info->mpdu_qos_control_valid, 2155 mpdu_info->mpdu_ht_control_valid, 2156 mpdu_info->frame_encryption_info_valid); 2157 2158 hal_verbose_debug( 2159 "rx_mpdu_start tlv (2/5) - " 2160 "fr_ds: %x " 2161 "to_ds: %x " 2162 "encrypted: %x " 2163 "mpdu_retry: %x " 2164 "mpdu_sequence_number: %x " 2165 "epd_en: %x " 2166 "all_frames_shall_be_encrypted: %x " 2167 "encrypt_type: %x " 2168 "mesh_sta: %x " 2169 "bssid_hit: %x " 2170 "bssid_number: %x " 2171 "tid: %x " 2172 "pn_31_0: %x " 2173 "pn_63_32: %x " 2174 "pn_95_64: %x " 2175 "pn_127_96: %x " 2176 "peer_meta_data: %x " 2177 "rxpt_classify_info.reo_destination_indication: %x " 2178 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 2179 "rx_reo_queue_desc_addr_31_0: %x ", 2180 mpdu_info->fr_ds, 2181 mpdu_info->to_ds, 2182 mpdu_info->encrypted, 2183 mpdu_info->mpdu_retry, 2184 mpdu_info->mpdu_sequence_number, 2185 mpdu_info->epd_en, 2186 mpdu_info->all_frames_shall_be_encrypted, 2187 mpdu_info->encrypt_type, 2188 mpdu_info->mesh_sta, 2189 mpdu_info->bssid_hit, 2190 mpdu_info->bssid_number, 2191 mpdu_info->tid, 2192 mpdu_info->pn_31_0, 2193 mpdu_info->pn_63_32, 2194 mpdu_info->pn_95_64, 2195 mpdu_info->pn_127_96, 2196 mpdu_info->peer_meta_data, 2197 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 2198 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 2199 mpdu_info->rx_reo_queue_desc_addr_31_0); 2200 2201 hal_verbose_debug( 2202 "rx_mpdu_start tlv (3/5) - " 2203 "rx_reo_queue_desc_addr_39_32: %x " 2204 "receive_queue_number: %x " 2205 "pre_delim_err_warning: %x " 2206 "first_delim_err: %x " 2207 "key_id_octet: %x " 2208 "new_peer_entry: %x " 2209 "decrypt_needed: %x " 2210 "decap_type: %x " 2211 "rx_insert_vlan_c_tag_padding: %x " 2212 "rx_insert_vlan_s_tag_padding: %x " 2213 "strip_vlan_c_tag_decap: %x " 2214 "strip_vlan_s_tag_decap: %x " 2215 "pre_delim_count: %x " 2216 "ampdu_flag: %x " 2217 "bar_frame: %x " 2218 "mpdu_length: %x " 2219 "first_mpdu: %x " 2220 "mcast_bcast: %x " 2221 "ast_index_not_found: %x " 2222 "ast_index_timeout: %x ", 2223 mpdu_info->rx_reo_queue_desc_addr_39_32, 2224 mpdu_info->receive_queue_number, 2225 mpdu_info->pre_delim_err_warning, 2226 mpdu_info->first_delim_err, 2227 mpdu_info->key_id_octet, 2228 mpdu_info->new_peer_entry, 2229 mpdu_info->decrypt_needed, 2230 mpdu_info->decap_type, 2231 mpdu_info->rx_insert_vlan_c_tag_padding, 2232 mpdu_info->rx_insert_vlan_s_tag_padding, 2233 mpdu_info->strip_vlan_c_tag_decap, 2234 mpdu_info->strip_vlan_s_tag_decap, 2235 mpdu_info->pre_delim_count, 2236 mpdu_info->ampdu_flag, 2237 mpdu_info->bar_frame, 2238 mpdu_info->mpdu_length, 2239 mpdu_info->first_mpdu, 2240 mpdu_info->mcast_bcast, 2241 mpdu_info->ast_index_not_found, 2242 mpdu_info->ast_index_timeout); 2243 2244 hal_verbose_debug( 2245 "rx_mpdu_start tlv (4/5) - " 2246 "power_mgmt: %x " 2247 "non_qos: %x " 2248 "null_data: %x " 2249 "mgmt_type: %x " 2250 "ctrl_type: %x " 2251 "more_data: %x " 2252 "eosp: %x " 2253 "fragment_flag: %x " 2254 "order: %x " 2255 "u_apsd_trigger: %x " 2256 "encrypt_required: %x " 2257 "directed: %x " 2258 "mpdu_frame_control_field: %x " 2259 "mpdu_duration_field: %x " 2260 "mac_addr_ad1_31_0: %x " 2261 "mac_addr_ad1_47_32: %x " 2262 "mac_addr_ad2_15_0: %x " 2263 "mac_addr_ad2_47_16: %x " 2264 "mac_addr_ad3_31_0: %x " 2265 "mac_addr_ad3_47_32: %x ", 2266 mpdu_info->power_mgmt, 2267 mpdu_info->non_qos, 2268 mpdu_info->null_data, 2269 mpdu_info->mgmt_type, 2270 mpdu_info->ctrl_type, 2271 mpdu_info->more_data, 2272 mpdu_info->eosp, 2273 mpdu_info->fragment_flag, 2274 mpdu_info->order, 2275 mpdu_info->u_apsd_trigger, 2276 mpdu_info->encrypt_required, 2277 mpdu_info->directed, 2278 mpdu_info->mpdu_frame_control_field, 2279 mpdu_info->mpdu_duration_field, 2280 mpdu_info->mac_addr_ad1_31_0, 2281 mpdu_info->mac_addr_ad1_47_32, 2282 mpdu_info->mac_addr_ad2_15_0, 2283 mpdu_info->mac_addr_ad2_47_16, 2284 mpdu_info->mac_addr_ad3_31_0, 2285 mpdu_info->mac_addr_ad3_47_32); 2286 2287 hal_verbose_debug( 2288 "rx_mpdu_start tlv (5/5) - " 2289 "mpdu_sequence_control_field: %x " 2290 "mac_addr_ad4_31_0: %x " 2291 "mac_addr_ad4_47_32: %x " 2292 "mpdu_qos_control_field: %x " 2293 "mpdu_ht_control_field: %x ", 2294 mpdu_info->mpdu_sequence_control_field, 2295 mpdu_info->mac_addr_ad4_31_0, 2296 mpdu_info->mac_addr_ad4_47_32, 2297 mpdu_info->mpdu_qos_control_field, 2298 mpdu_info->mpdu_ht_control_field); 2299 } 2300 2301 /** 2302 * hal_tx_desc_set_search_type - Set the search type value 2303 * @desc: Handle to Tx Descriptor 2304 * @search_type: search type 2305 * 0 – Normal search 2306 * 1 – Index based address search 2307 * 2 – Index based flow search 2308 * 2309 * Return: void 2310 */ 2311 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2312 static void hal_tx_desc_set_search_type_generic(void *desc, 2313 uint8_t search_type) 2314 { 2315 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2316 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2317 } 2318 #else 2319 static void hal_tx_desc_set_search_type_generic(void *desc, 2320 uint8_t search_type) 2321 { 2322 } 2323 2324 #endif 2325 2326 /** 2327 * hal_tx_desc_set_search_index - Set the search index value 2328 * @desc: Handle to Tx Descriptor 2329 * @search_index: The index that will be used for index based address or 2330 * flow search. The field is valid when 'search_type' is 2331 * 1 0r 2 2332 * 2333 * Return: void 2334 */ 2335 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2336 static void hal_tx_desc_set_search_index_generic(void *desc, 2337 uint32_t search_index) 2338 { 2339 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2340 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2341 } 2342 #else 2343 static void hal_tx_desc_set_search_index_generic(void *desc, 2344 uint32_t search_index) 2345 { 2346 } 2347 #endif 2348 2349 /** 2350 * hal_tx_desc_set_cache_set_num_generic - Set the cache-set-num value 2351 * @desc: Handle to Tx Descriptor 2352 * @cache_num: Cache set number that should be used to cache the index 2353 * based search results, for address and flow search. 2354 * This value should be equal to LSB four bits of the hash value 2355 * of match data, in case of search index points to an entry 2356 * which may be used in content based search also. The value can 2357 * be anything when the entry pointed by search index will not be 2358 * used for content based search. 2359 * 2360 * Return: void 2361 */ 2362 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2363 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2364 uint8_t cache_num) 2365 { 2366 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2367 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2368 } 2369 #else 2370 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2371 uint8_t cache_num) 2372 { 2373 } 2374 #endif 2375 2376 /** 2377 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2378 * @soc: HAL SoC context 2379 * @map: PCP-TID mapping table 2380 * 2381 * PCP are mapped to 8 TID values using TID values programmed 2382 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2383 * The mapping register has TID mapping for 8 PCP values 2384 * 2385 * Return: none 2386 */ 2387 static void hal_tx_set_pcp_tid_map_generic(struct hal_soc *soc, uint8_t *map) 2388 { 2389 uint32_t addr, value; 2390 2391 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2392 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2393 2394 value = (map[0] | 2395 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2396 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2397 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2398 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2399 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2400 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2401 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2402 2403 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2404 } 2405 2406 /** 2407 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2408 * value received from user-space 2409 * @soc: HAL SoC context 2410 * @pcp: pcp value 2411 * @tid : tid value 2412 * 2413 * Return: void 2414 */ 2415 static 2416 void hal_tx_update_pcp_tid_generic(struct hal_soc *soc, 2417 uint8_t pcp, uint8_t tid) 2418 { 2419 uint32_t addr, value, regval; 2420 2421 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2422 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2423 2424 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2425 2426 /* Read back previous PCP TID config and update 2427 * with new config. 2428 */ 2429 regval = HAL_REG_READ(soc, addr); 2430 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2431 regval |= value; 2432 2433 HAL_REG_WRITE(soc, addr, 2434 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2435 } 2436 2437 /** 2438 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2439 * @soc: HAL SoC context 2440 * @val: priority value 2441 * 2442 * Return: void 2443 */ 2444 static 2445 void hal_tx_update_tidmap_prty_generic(struct hal_soc *soc, uint8_t value) 2446 { 2447 uint32_t addr; 2448 2449 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2450 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2451 2452 HAL_REG_WRITE(soc, addr, 2453 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2454 } 2455 2456 /** 2457 * hal_rx_msdu_packet_metadata_get(): API to get the 2458 * msdu information from rx_msdu_end TLV 2459 * 2460 * @ buf: pointer to the start of RX PKT TLV headers 2461 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2462 */ 2463 static void 2464 hal_rx_msdu_packet_metadata_get_generic(uint8_t *buf, 2465 void *pkt_msdu_metadata) 2466 { 2467 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2468 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2469 struct hal_rx_msdu_metadata *msdu_metadata = 2470 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2471 2472 msdu_metadata->l3_hdr_pad = 2473 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2474 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2475 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2476 msdu_metadata->sa_sw_peer_id = 2477 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2478 } 2479 2480 /** 2481 * hal_rx_msdu_end_offset_get_generic(): API to get the 2482 * msdu_end structure offset rx_pkt_tlv structure 2483 * 2484 * NOTE: API returns offset of msdu_end TLV from structure 2485 * rx_pkt_tlvs 2486 */ 2487 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2488 { 2489 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2490 } 2491 2492 /** 2493 * hal_rx_attn_offset_get_generic(): API to get the 2494 * msdu_end structure offset rx_pkt_tlv structure 2495 * 2496 * NOTE: API returns offset of attn TLV from structure 2497 * rx_pkt_tlvs 2498 */ 2499 static uint32_t hal_rx_attn_offset_get_generic(void) 2500 { 2501 return RX_PKT_TLV_OFFSET(attn_tlv); 2502 } 2503 2504 /** 2505 * hal_rx_msdu_start_offset_get_generic(): API to get the 2506 * msdu_start structure offset rx_pkt_tlv structure 2507 * 2508 * NOTE: API returns offset of attn TLV from structure 2509 * rx_pkt_tlvs 2510 */ 2511 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2512 { 2513 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2514 } 2515 2516 /** 2517 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2518 * mpdu_start structure offset rx_pkt_tlv structure 2519 * 2520 * NOTE: API returns offset of attn TLV from structure 2521 * rx_pkt_tlvs 2522 */ 2523 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2524 { 2525 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2526 } 2527 2528 /** 2529 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2530 * mpdu_end structure offset rx_pkt_tlv structure 2531 * 2532 * NOTE: API returns offset of attn TLV from structure 2533 * rx_pkt_tlvs 2534 */ 2535 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2536 { 2537 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2538 } 2539 #endif /* HAL_GENERIC_API_H_ */ 2540