1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 22 ((struct rx_msdu_desc_info *) \ 23 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 24 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 25 /** 26 * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr 27 * @msdu_details_ptr - Pointer to msdu_details_ptr 28 * Return - Pointer to rx_msdu_desc_info structure. 29 * 30 */ 31 static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) 32 { 33 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 34 } 35 36 37 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 38 ((struct rx_msdu_details *) \ 39 _OFFSET_TO_BYTE_PTR((link_desc),\ 40 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 41 /** 42 * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details 43 * @link_desc - Pointer to link desc 44 * Return - Pointer to rx_msdu_details structure 45 * 46 */ 47 48 static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) 49 { 50 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 51 } 52 53 /** 54 * hal_tx_comp_get_status() - TQM Release reason 55 * @hal_desc: completion ring Tx status 56 * 57 * This function will parse the WBM completion descriptor and populate in 58 * HAL structure 59 * 60 * Return: none 61 */ 62 #if defined(WCSS_VERSION) && \ 63 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 64 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 65 static inline void hal_tx_comp_get_status_generic(void *desc, 66 void *ts1, void *hal) 67 { 68 uint8_t rate_stats_valid = 0; 69 uint32_t rate_stats = 0; 70 struct hal_tx_completion_status *ts = 71 (struct hal_tx_completion_status *)ts1; 72 73 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 74 TQM_STATUS_NUMBER); 75 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 76 ACK_FRAME_RSSI); 77 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 78 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 80 MSDU_PART_OF_AMSDU); 81 82 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 83 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 84 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 85 TRANSMIT_COUNT); 86 87 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 88 TX_RATE_STATS); 89 90 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 91 TX_RATE_STATS_INFO_VALID, rate_stats); 92 93 ts->valid = rate_stats_valid; 94 95 if (rate_stats_valid) { 96 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 97 rate_stats); 98 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 99 TRANSMIT_PKT_TYPE, rate_stats); 100 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 101 TRANSMIT_STBC, rate_stats); 102 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 103 rate_stats); 104 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 105 rate_stats); 106 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 107 rate_stats); 108 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 109 rate_stats); 110 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 111 rate_stats); 112 } 113 114 ts->release_src = hal_tx_comp_get_buffer_source(desc); 115 ts->status = hal_tx_comp_get_release_reason(desc, hal); 116 117 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 118 TX_RATE_STATS_INFO_TX_RATE_STATS); 119 } 120 #else 121 static inline void hal_tx_comp_get_status_generic(void *desc, 122 struct hal_tx_completion_status *ts, void *hal) 123 { 124 125 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 126 TQM_STATUS_NUMBER); 127 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 128 ACK_FRAME_RSSI); 129 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 130 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 131 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 132 MSDU_PART_OF_AMSDU); 133 134 ts->release_src = hal_tx_comp_get_buffer_source(desc); 135 ts->status = hal_tx_comp_get_release_reason(desc, hal); 136 } 137 #endif 138 139 140 /** 141 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 142 * @desc: Handle to Tx Descriptor 143 * @paddr: Physical Address 144 * @pool_id: Return Buffer Manager ID 145 * @desc_id: Descriptor ID 146 * @type: 0 - Address points to a MSDU buffer 147 * 1 - Address points to MSDU extension descriptor 148 * 149 * Return: void 150 */ 151 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 152 dma_addr_t paddr, uint8_t pool_id, 153 uint32_t desc_id, uint8_t type) 154 { 155 /* Set buffer_addr_info.buffer_addr_31_0 */ 156 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 157 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 158 159 /* Set buffer_addr_info.buffer_addr_39_32 */ 160 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 161 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 162 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 163 (((uint64_t) paddr) >> 32)); 164 165 /* Set buffer_addr_info.return_buffer_manager = pool id */ 166 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 167 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 168 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 169 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 170 171 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 172 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 173 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 174 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 175 176 /* Set Buffer or Ext Descriptor Type */ 177 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 178 BUF_OR_EXT_DESC_TYPE) |= 179 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 180 } 181 182 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 183 /** 184 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 185 * tlv_tag: Taf of the TLVs 186 * rx_tlv: the pointer to the TLVs 187 * @ppdu_info: pointer to ppdu_info 188 * 189 * Return: true if the tlv is handled, false if not 190 */ 191 static inline bool 192 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 193 struct hal_rx_ppdu_info *ppdu_info) 194 { 195 uint32_t value; 196 197 switch (tlv_tag) { 198 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 199 { 200 uint8_t *he_sig_a_mu_ul_info = 201 (uint8_t *)rx_tlv + 202 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 203 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 204 ppdu_info->rx_status.he_flags = 1; 205 206 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 207 FORMAT_INDICATION); 208 if (value == 0) { 209 ppdu_info->rx_status.he_data1 = 210 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 211 } else { 212 ppdu_info->rx_status.he_data1 = 213 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 214 } 215 216 /* data1 */ 217 ppdu_info->rx_status.he_data1 |= 218 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 219 QDF_MON_STATUS_HE_DL_UL_KNOWN | 220 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 221 222 /* data2 */ 223 ppdu_info->rx_status.he_data2 |= 224 QDF_MON_STATUS_TXOP_KNOWN; 225 226 /*data3*/ 227 value = HAL_RX_GET(he_sig_a_mu_ul_info, 228 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 229 ppdu_info->rx_status.he_data3 = value; 230 /* 1 for UL and 0 for DL */ 231 value = 1; 232 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 233 ppdu_info->rx_status.he_data3 |= value; 234 235 /*data4*/ 236 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 237 SPATIAL_REUSE); 238 ppdu_info->rx_status.he_data4 = value; 239 240 /*data5*/ 241 value = HAL_RX_GET(he_sig_a_mu_ul_info, 242 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 243 ppdu_info->rx_status.he_data5 = value; 244 ppdu_info->rx_status.bw = value; 245 246 /*data6*/ 247 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 248 TXOP_DURATION); 249 value = value << QDF_MON_STATUS_TXOP_SHIFT; 250 ppdu_info->rx_status.he_data6 |= value; 251 return true; 252 } 253 default: 254 return false; 255 } 256 } 257 #else 258 static inline bool 259 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 260 struct hal_rx_ppdu_info *ppdu_info) 261 { 262 return false; 263 } 264 #endif /* CONFIG_MCL && QCA_WIFI_QCA6290_11AX */ 265 266 /** 267 * hal_rx_status_get_tlv_info() - process receive info TLV 268 * @rx_tlv_hdr: pointer to TLV header 269 * @ppdu_info: pointer to ppdu_info 270 * 271 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 272 */ 273 static inline uint32_t 274 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 275 void *halsoc) 276 { 277 struct hal_soc *hal = (struct hal_soc *)halsoc; 278 uint32_t tlv_tag, user_id, tlv_len, value; 279 uint8_t group_id = 0; 280 uint8_t he_dcm = 0; 281 uint8_t he_stbc = 0; 282 uint16_t he_gi = 0; 283 uint16_t he_ltf = 0; 284 void *rx_tlv; 285 bool unhandled = false; 286 struct hal_rx_ppdu_info *ppdu_info = 287 (struct hal_rx_ppdu_info *)ppduinfo; 288 289 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 290 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 291 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 292 293 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 294 switch (tlv_tag) { 295 296 case WIFIRX_PPDU_START_E: 297 ppdu_info->com_info.ppdu_id = 298 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 299 PHY_PPDU_ID); 300 /* channel number is set in PHY meta data */ 301 ppdu_info->rx_status.chan_num = 302 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 303 SW_PHY_META_DATA); 304 ppdu_info->com_info.ppdu_timestamp = 305 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 306 PPDU_START_TIMESTAMP); 307 ppdu_info->rx_status.ppdu_timestamp = 308 ppdu_info->com_info.ppdu_timestamp; 309 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 310 break; 311 312 case WIFIRX_PPDU_START_USER_INFO_E: 313 break; 314 315 case WIFIRX_PPDU_END_E: 316 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 317 "[%s][%d] ppdu_end_e len=%d", 318 __func__, __LINE__, tlv_len); 319 /* This is followed by sub-TLVs of PPDU_END */ 320 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 321 break; 322 323 case WIFIRXPCU_PPDU_END_INFO_E: 324 ppdu_info->rx_status.tsft = 325 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 326 WB_TIMESTAMP_UPPER_32); 327 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 328 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 329 WB_TIMESTAMP_LOWER_32); 330 ppdu_info->rx_status.duration = 331 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 332 RX_PPDU_DURATION); 333 break; 334 335 case WIFIRX_PPDU_END_USER_STATS_E: 336 { 337 unsigned long tid = 0; 338 uint16_t seq = 0; 339 340 ppdu_info->rx_status.ast_index = 341 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 342 AST_INDEX); 343 344 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 345 RECEIVED_QOS_DATA_TID_BITMAP); 346 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 347 348 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 349 ppdu_info->rx_status.tid = HAL_TID_INVALID; 350 351 ppdu_info->rx_status.tcp_msdu_count = 352 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 353 TCP_MSDU_COUNT) + 354 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 355 TCP_ACK_MSDU_COUNT); 356 ppdu_info->rx_status.udp_msdu_count = 357 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 358 UDP_MSDU_COUNT); 359 ppdu_info->rx_status.other_msdu_count = 360 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 361 OTHER_MSDU_COUNT); 362 363 ppdu_info->rx_status.frame_control_info_valid = 364 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 365 FRAME_CONTROL_INFO_VALID); 366 367 if (ppdu_info->rx_status.frame_control_info_valid) 368 ppdu_info->rx_status.frame_control = 369 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 370 FRAME_CONTROL_FIELD); 371 372 ppdu_info->rx_status.data_sequence_control_info_valid = 373 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 374 DATA_SEQUENCE_CONTROL_INFO_VALID); 375 376 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 377 FIRST_DATA_SEQ_CTRL); 378 if (ppdu_info->rx_status.data_sequence_control_info_valid) 379 ppdu_info->rx_status.first_data_seq_ctrl = seq; 380 381 ppdu_info->rx_status.preamble_type = 382 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 383 HT_CONTROL_FIELD_PKT_TYPE); 384 switch (ppdu_info->rx_status.preamble_type) { 385 case HAL_RX_PKT_TYPE_11N: 386 ppdu_info->rx_status.ht_flags = 1; 387 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 388 break; 389 case HAL_RX_PKT_TYPE_11AC: 390 ppdu_info->rx_status.vht_flags = 1; 391 break; 392 case HAL_RX_PKT_TYPE_11AX: 393 ppdu_info->rx_status.he_flags = 1; 394 break; 395 default: 396 break; 397 } 398 399 ppdu_info->com_info.mpdu_cnt_fcs_ok = 400 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 401 MPDU_CNT_FCS_OK); 402 ppdu_info->com_info.mpdu_cnt_fcs_err = 403 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 404 MPDU_CNT_FCS_ERR); 405 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 406 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 407 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 408 else 409 ppdu_info->rx_status.rs_flags &= 410 (~IEEE80211_AMPDU_FLAG); 411 break; 412 } 413 414 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 415 break; 416 417 case WIFIRX_PPDU_END_STATUS_DONE_E: 418 return HAL_TLV_STATUS_PPDU_DONE; 419 420 case WIFIDUMMY_E: 421 return HAL_TLV_STATUS_BUF_DONE; 422 423 case WIFIPHYRX_HT_SIG_E: 424 { 425 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 426 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 427 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 428 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 429 FEC_CODING); 430 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 431 1 : 0; 432 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 433 HT_SIG_INFO_0, MCS); 434 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 435 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 436 HT_SIG_INFO_0, CBW); 437 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 438 HT_SIG_INFO_1, SHORT_GI); 439 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 440 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 441 HT_SIG_SU_NSS_SHIFT) + 1; 442 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 443 break; 444 } 445 446 case WIFIPHYRX_L_SIG_B_E: 447 { 448 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 449 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 450 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 451 452 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 453 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 454 switch (value) { 455 case 1: 456 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 457 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 458 break; 459 case 2: 460 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 461 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 462 break; 463 case 3: 464 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 465 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 466 break; 467 case 4: 468 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 469 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 470 break; 471 case 5: 472 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 473 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 474 break; 475 case 6: 476 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 477 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 478 break; 479 case 7: 480 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 481 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 482 break; 483 default: 484 break; 485 } 486 ppdu_info->rx_status.cck_flag = 1; 487 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 488 break; 489 } 490 491 case WIFIPHYRX_L_SIG_A_E: 492 { 493 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 494 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 495 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 496 497 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 498 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 499 switch (value) { 500 case 8: 501 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 502 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 503 break; 504 case 9: 505 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 506 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 507 break; 508 case 10: 509 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 510 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 511 break; 512 case 11: 513 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 514 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 515 break; 516 case 12: 517 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 518 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 519 break; 520 case 13: 521 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 522 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 523 break; 524 case 14: 525 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 526 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 527 break; 528 case 15: 529 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 530 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 531 break; 532 default: 533 break; 534 } 535 ppdu_info->rx_status.ofdm_flag = 1; 536 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 537 break; 538 } 539 540 case WIFIPHYRX_VHT_SIG_A_E: 541 { 542 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 543 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 544 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 545 546 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 547 SU_MU_CODING); 548 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 549 1 : 0; 550 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 551 ppdu_info->rx_status.vht_flag_values5 = group_id; 552 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 553 VHT_SIG_A_INFO_1, MCS); 554 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 555 VHT_SIG_A_INFO_1, GI_SETTING); 556 557 switch (hal->target_type) { 558 case TARGET_TYPE_QCA8074: 559 case TARGET_TYPE_QCA8074V2: 560 case TARGET_TYPE_QCA6018: 561 ppdu_info->rx_status.is_stbc = 562 HAL_RX_GET(vht_sig_a_info, 563 VHT_SIG_A_INFO_0, STBC); 564 value = HAL_RX_GET(vht_sig_a_info, 565 VHT_SIG_A_INFO_0, N_STS); 566 if (ppdu_info->rx_status.is_stbc && (value > 0)) 567 value = ((value + 1) >> 1) - 1; 568 ppdu_info->rx_status.nss = 569 ((value & VHT_SIG_SU_NSS_MASK) + 1); 570 571 break; 572 case TARGET_TYPE_QCA6290: 573 #if !defined(QCA_WIFI_QCA6290_11AX) 574 ppdu_info->rx_status.is_stbc = 575 HAL_RX_GET(vht_sig_a_info, 576 VHT_SIG_A_INFO_0, STBC); 577 value = HAL_RX_GET(vht_sig_a_info, 578 VHT_SIG_A_INFO_0, N_STS); 579 if (ppdu_info->rx_status.is_stbc && (value > 0)) 580 value = ((value + 1) >> 1) - 1; 581 ppdu_info->rx_status.nss = 582 ((value & VHT_SIG_SU_NSS_MASK) + 1); 583 #else 584 ppdu_info->rx_status.nss = 0; 585 #endif 586 break; 587 #ifdef QCA_WIFI_QCA6390 588 case TARGET_TYPE_QCA6390: 589 ppdu_info->rx_status.nss = 0; 590 break; 591 #endif 592 default: 593 break; 594 } 595 ppdu_info->rx_status.vht_flag_values3[0] = 596 (((ppdu_info->rx_status.mcs) << 4) 597 | ppdu_info->rx_status.nss); 598 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 599 VHT_SIG_A_INFO_0, BANDWIDTH); 600 ppdu_info->rx_status.vht_flag_values2 = 601 ppdu_info->rx_status.bw; 602 ppdu_info->rx_status.vht_flag_values4 = 603 HAL_RX_GET(vht_sig_a_info, 604 VHT_SIG_A_INFO_1, SU_MU_CODING); 605 606 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 607 VHT_SIG_A_INFO_1, BEAMFORMED); 608 if (group_id == 0 || group_id == 63) 609 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 610 else 611 ppdu_info->rx_status.reception_type = 612 HAL_RX_TYPE_MU_MIMO; 613 614 break; 615 } 616 case WIFIPHYRX_HE_SIG_A_SU_E: 617 { 618 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 619 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 620 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 621 ppdu_info->rx_status.he_flags = 1; 622 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 623 FORMAT_INDICATION); 624 if (value == 0) { 625 ppdu_info->rx_status.he_data1 = 626 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 627 } else { 628 ppdu_info->rx_status.he_data1 = 629 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 630 } 631 632 /* data1 */ 633 ppdu_info->rx_status.he_data1 |= 634 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 635 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 636 QDF_MON_STATUS_HE_DL_UL_KNOWN | 637 QDF_MON_STATUS_HE_MCS_KNOWN | 638 QDF_MON_STATUS_HE_DCM_KNOWN | 639 QDF_MON_STATUS_HE_CODING_KNOWN | 640 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 641 QDF_MON_STATUS_HE_STBC_KNOWN | 642 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 643 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 644 645 /* data2 */ 646 ppdu_info->rx_status.he_data2 = 647 QDF_MON_STATUS_HE_GI_KNOWN; 648 ppdu_info->rx_status.he_data2 |= 649 QDF_MON_STATUS_TXBF_KNOWN | 650 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 651 QDF_MON_STATUS_TXOP_KNOWN | 652 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 653 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 654 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 655 656 /* data3 */ 657 value = HAL_RX_GET(he_sig_a_su_info, 658 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 659 ppdu_info->rx_status.he_data3 = value; 660 value = HAL_RX_GET(he_sig_a_su_info, 661 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 662 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 663 ppdu_info->rx_status.he_data3 |= value; 664 value = HAL_RX_GET(he_sig_a_su_info, 665 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 666 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 667 ppdu_info->rx_status.he_data3 |= value; 668 669 value = HAL_RX_GET(he_sig_a_su_info, 670 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 671 ppdu_info->rx_status.mcs = value; 672 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 673 ppdu_info->rx_status.he_data3 |= value; 674 675 value = HAL_RX_GET(he_sig_a_su_info, 676 HE_SIG_A_SU_INFO_0, DCM); 677 he_dcm = value; 678 value = value << QDF_MON_STATUS_DCM_SHIFT; 679 ppdu_info->rx_status.he_data3 |= value; 680 value = HAL_RX_GET(he_sig_a_su_info, 681 HE_SIG_A_SU_INFO_1, CODING); 682 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 683 1 : 0; 684 value = value << QDF_MON_STATUS_CODING_SHIFT; 685 ppdu_info->rx_status.he_data3 |= value; 686 value = HAL_RX_GET(he_sig_a_su_info, 687 HE_SIG_A_SU_INFO_1, 688 LDPC_EXTRA_SYMBOL); 689 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 690 ppdu_info->rx_status.he_data3 |= value; 691 value = HAL_RX_GET(he_sig_a_su_info, 692 HE_SIG_A_SU_INFO_1, STBC); 693 he_stbc = value; 694 value = value << QDF_MON_STATUS_STBC_SHIFT; 695 ppdu_info->rx_status.he_data3 |= value; 696 697 /* data4 */ 698 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 699 SPATIAL_REUSE); 700 ppdu_info->rx_status.he_data4 = value; 701 702 /* data5 */ 703 value = HAL_RX_GET(he_sig_a_su_info, 704 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 705 ppdu_info->rx_status.he_data5 = value; 706 ppdu_info->rx_status.bw = value; 707 value = HAL_RX_GET(he_sig_a_su_info, 708 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 709 switch (value) { 710 case 0: 711 he_gi = HE_GI_0_8; 712 he_ltf = HE_LTF_1_X; 713 break; 714 case 1: 715 he_gi = HE_GI_0_8; 716 he_ltf = HE_LTF_2_X; 717 break; 718 case 2: 719 he_gi = HE_GI_1_6; 720 he_ltf = HE_LTF_2_X; 721 break; 722 case 3: 723 if (he_dcm && he_stbc) { 724 he_gi = HE_GI_0_8; 725 he_ltf = HE_LTF_4_X; 726 } else { 727 he_gi = HE_GI_3_2; 728 he_ltf = HE_LTF_4_X; 729 } 730 break; 731 } 732 ppdu_info->rx_status.sgi = he_gi; 733 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 734 ppdu_info->rx_status.he_data5 |= value; 735 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 736 ppdu_info->rx_status.he_data5 |= value; 737 738 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 739 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 740 ppdu_info->rx_status.he_data5 |= value; 741 742 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 743 PACKET_EXTENSION_A_FACTOR); 744 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 745 ppdu_info->rx_status.he_data5 |= value; 746 747 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 748 value = value << QDF_MON_STATUS_TXBF_SHIFT; 749 ppdu_info->rx_status.he_data5 |= value; 750 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 751 PACKET_EXTENSION_PE_DISAMBIGUITY); 752 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 753 ppdu_info->rx_status.he_data5 |= value; 754 755 /* data6 */ 756 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 757 value++; 758 ppdu_info->rx_status.nss = value; 759 ppdu_info->rx_status.he_data6 = value; 760 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 761 DOPPLER_INDICATION); 762 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 763 ppdu_info->rx_status.he_data6 |= value; 764 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 765 TXOP_DURATION); 766 value = value << QDF_MON_STATUS_TXOP_SHIFT; 767 ppdu_info->rx_status.he_data6 |= value; 768 769 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 770 HE_SIG_A_SU_INFO_1, TXBF); 771 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 772 break; 773 } 774 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 775 { 776 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 777 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 778 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 779 780 ppdu_info->rx_status.he_mu_flags = 1; 781 782 /* HE Flags */ 783 /*data1*/ 784 ppdu_info->rx_status.he_data1 = 785 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 786 ppdu_info->rx_status.he_data1 |= 787 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 788 QDF_MON_STATUS_HE_DL_UL_KNOWN | 789 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 790 QDF_MON_STATUS_HE_STBC_KNOWN | 791 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 792 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 793 794 /* data2 */ 795 ppdu_info->rx_status.he_data2 = 796 QDF_MON_STATUS_HE_GI_KNOWN; 797 ppdu_info->rx_status.he_data2 |= 798 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 799 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 800 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 801 QDF_MON_STATUS_TXOP_KNOWN | 802 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 803 804 /*data3*/ 805 value = HAL_RX_GET(he_sig_a_mu_dl_info, 806 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 807 ppdu_info->rx_status.he_data3 = value; 808 809 value = HAL_RX_GET(he_sig_a_mu_dl_info, 810 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 811 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 812 ppdu_info->rx_status.he_data3 |= value; 813 814 value = HAL_RX_GET(he_sig_a_mu_dl_info, 815 HE_SIG_A_MU_DL_INFO_1, 816 LDPC_EXTRA_SYMBOL); 817 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 818 ppdu_info->rx_status.he_data3 |= value; 819 820 value = HAL_RX_GET(he_sig_a_mu_dl_info, 821 HE_SIG_A_MU_DL_INFO_1, STBC); 822 he_stbc = value; 823 value = value << QDF_MON_STATUS_STBC_SHIFT; 824 ppdu_info->rx_status.he_data3 |= value; 825 826 /*data4*/ 827 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 828 SPATIAL_REUSE); 829 ppdu_info->rx_status.he_data4 = value; 830 831 /*data5*/ 832 value = HAL_RX_GET(he_sig_a_mu_dl_info, 833 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 834 ppdu_info->rx_status.he_data5 = value; 835 ppdu_info->rx_status.bw = value; 836 837 value = HAL_RX_GET(he_sig_a_mu_dl_info, 838 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 839 switch (value) { 840 case 0: 841 he_gi = HE_GI_0_8; 842 he_ltf = HE_LTF_4_X; 843 break; 844 case 1: 845 he_gi = HE_GI_0_8; 846 he_ltf = HE_LTF_2_X; 847 break; 848 case 2: 849 he_gi = HE_GI_1_6; 850 he_ltf = HE_LTF_2_X; 851 break; 852 case 3: 853 he_gi = HE_GI_3_2; 854 he_ltf = HE_LTF_4_X; 855 break; 856 } 857 ppdu_info->rx_status.sgi = he_gi; 858 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 859 ppdu_info->rx_status.he_data5 |= value; 860 861 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 862 ppdu_info->rx_status.he_data5 |= value; 863 864 value = HAL_RX_GET(he_sig_a_mu_dl_info, 865 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 866 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 867 ppdu_info->rx_status.he_data5 |= value; 868 869 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 870 PACKET_EXTENSION_A_FACTOR); 871 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 872 ppdu_info->rx_status.he_data5 |= value; 873 874 875 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 876 PACKET_EXTENSION_PE_DISAMBIGUITY); 877 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 878 ppdu_info->rx_status.he_data5 |= value; 879 880 /*data6*/ 881 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 882 DOPPLER_INDICATION); 883 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 884 ppdu_info->rx_status.he_data6 |= value; 885 886 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 887 TXOP_DURATION); 888 value = value << QDF_MON_STATUS_TXOP_SHIFT; 889 ppdu_info->rx_status.he_data6 |= value; 890 891 /* HE-MU Flags */ 892 /* HE-MU-flags1 */ 893 ppdu_info->rx_status.he_flags1 = 894 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 895 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 896 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 897 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 898 QDF_MON_STATUS_RU_0_KNOWN; 899 900 value = HAL_RX_GET(he_sig_a_mu_dl_info, 901 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 902 ppdu_info->rx_status.he_flags1 |= value; 903 value = HAL_RX_GET(he_sig_a_mu_dl_info, 904 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 905 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 906 ppdu_info->rx_status.he_flags1 |= value; 907 908 /* HE-MU-flags2 */ 909 ppdu_info->rx_status.he_flags2 = 910 QDF_MON_STATUS_BW_KNOWN; 911 912 value = HAL_RX_GET(he_sig_a_mu_dl_info, 913 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 914 ppdu_info->rx_status.he_flags2 |= value; 915 value = HAL_RX_GET(he_sig_a_mu_dl_info, 916 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 917 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 918 ppdu_info->rx_status.he_flags2 |= value; 919 value = HAL_RX_GET(he_sig_a_mu_dl_info, 920 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 921 value = value - 1; 922 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 923 ppdu_info->rx_status.he_flags2 |= value; 924 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 925 break; 926 } 927 case WIFIPHYRX_HE_SIG_B1_MU_E: 928 { 929 930 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 931 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 932 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 933 934 ppdu_info->rx_status.he_sig_b_common_known |= 935 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 936 /* TODO: Check on the availability of other fields in 937 * sig_b_common 938 */ 939 940 value = HAL_RX_GET(he_sig_b1_mu_info, 941 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 942 ppdu_info->rx_status.he_RU[0] = value; 943 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 944 break; 945 } 946 case WIFIPHYRX_HE_SIG_B2_MU_E: 947 { 948 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 949 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 950 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 951 /* 952 * Not all "HE" fields can be updated from 953 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 954 * to populate rest of the "HE" fields for MU scenarios. 955 */ 956 957 /* HE-data1 */ 958 ppdu_info->rx_status.he_data1 |= 959 QDF_MON_STATUS_HE_MCS_KNOWN | 960 QDF_MON_STATUS_HE_CODING_KNOWN; 961 962 /* HE-data2 */ 963 964 /* HE-data3 */ 965 value = HAL_RX_GET(he_sig_b2_mu_info, 966 HE_SIG_B2_MU_INFO_0, STA_MCS); 967 ppdu_info->rx_status.mcs = value; 968 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 969 ppdu_info->rx_status.he_data3 |= value; 970 971 972 value = HAL_RX_GET(he_sig_b2_mu_info, 973 HE_SIG_B2_MU_INFO_0, STA_CODING); 974 value = value << QDF_MON_STATUS_CODING_SHIFT; 975 ppdu_info->rx_status.he_data3 |= value; 976 977 /* HE-data4 */ 978 value = HAL_RX_GET(he_sig_b2_mu_info, 979 HE_SIG_B2_MU_INFO_0, STA_ID); 980 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 981 ppdu_info->rx_status.he_data4 |= value; 982 983 /* HE-data5 */ 984 985 /* HE-data6 */ 986 value = HAL_RX_GET(he_sig_b2_mu_info, 987 HE_SIG_B2_MU_INFO_0, NSTS); 988 /* value n indicates n+1 spatial streams */ 989 value++; 990 ppdu_info->rx_status.nss = value; 991 ppdu_info->rx_status.he_data6 |= value; 992 993 break; 994 995 } 996 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 997 { 998 uint8_t *he_sig_b2_ofdma_info = 999 (uint8_t *)rx_tlv + 1000 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1001 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1002 1003 /* 1004 * Not all "HE" fields can be updated from 1005 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1006 * to populate rest of "HE" fields for MU OFDMA scenarios. 1007 */ 1008 1009 /* HE-data1 */ 1010 ppdu_info->rx_status.he_data1 |= 1011 QDF_MON_STATUS_HE_MCS_KNOWN | 1012 QDF_MON_STATUS_HE_DCM_KNOWN | 1013 QDF_MON_STATUS_HE_CODING_KNOWN; 1014 1015 /* HE-data2 */ 1016 ppdu_info->rx_status.he_data2 |= 1017 QDF_MON_STATUS_TXBF_KNOWN; 1018 1019 /* HE-data3 */ 1020 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1021 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1022 ppdu_info->rx_status.mcs = value; 1023 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1024 ppdu_info->rx_status.he_data3 |= value; 1025 1026 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1027 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1028 he_dcm = value; 1029 value = value << QDF_MON_STATUS_DCM_SHIFT; 1030 ppdu_info->rx_status.he_data3 |= value; 1031 1032 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1033 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1034 value = value << QDF_MON_STATUS_CODING_SHIFT; 1035 ppdu_info->rx_status.he_data3 |= value; 1036 1037 /* HE-data4 */ 1038 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1039 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1040 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1041 ppdu_info->rx_status.he_data4 |= value; 1042 1043 /* HE-data5 */ 1044 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1045 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1046 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1047 ppdu_info->rx_status.he_data5 |= value; 1048 1049 /* HE-data6 */ 1050 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1051 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1052 /* value n indicates n+1 spatial streams */ 1053 value++; 1054 ppdu_info->rx_status.nss = value; 1055 ppdu_info->rx_status.he_data6 |= value; 1056 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1057 break; 1058 } 1059 case WIFIPHYRX_RSSI_LEGACY_E: 1060 { 1061 uint8_t reception_type; 1062 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1063 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_3, 1064 RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS); 1065 1066 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1067 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1068 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1069 ppdu_info->rx_status.he_re = 0; 1070 1071 reception_type = HAL_RX_GET(rx_tlv, 1072 PHYRX_RSSI_LEGACY_0, 1073 RECEPTION_TYPE); 1074 switch (reception_type) { 1075 case QDF_RECEPTION_TYPE_ULOFMDA: 1076 ppdu_info->rx_status.ulofdma_flag = 1; 1077 ppdu_info->rx_status.he_data1 = 1078 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1079 break; 1080 case QDF_RECEPTION_TYPE_ULMIMO: 1081 ppdu_info->rx_status.he_data1 = 1082 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1083 break; 1084 default: 1085 break; 1086 } 1087 value = HAL_RX_GET(rssi_info_tlv, 1088 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1089 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1090 "RSSI_PRI20_CHAIN0: %d\n", value); 1091 1092 value = HAL_RX_GET(rssi_info_tlv, 1093 RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0); 1094 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1095 "RSSI_EXT20_CHAIN0: %d\n", value); 1096 1097 value = HAL_RX_GET(rssi_info_tlv, 1098 RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0); 1099 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1100 "RSSI_EXT40_LOW20_CHAIN0: %d\n", value); 1101 1102 value = HAL_RX_GET(rssi_info_tlv, 1103 RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0); 1104 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1105 "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value); 1106 1107 value = HAL_RX_GET(rssi_info_tlv, 1108 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0); 1109 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1110 "RSSI_EXT80_LOW20_CHAIN0: %d\n", value); 1111 1112 value = HAL_RX_GET(rssi_info_tlv, 1113 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0); 1114 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1115 "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value); 1116 1117 value = HAL_RX_GET(rssi_info_tlv, 1118 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0); 1119 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1120 "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value); 1121 1122 value = HAL_RX_GET(rssi_info_tlv, 1123 RECEIVE_RSSI_INFO_1, 1124 RSSI_EXT80_HIGH20_CHAIN0); 1125 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1126 "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value); 1127 break; 1128 } 1129 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1130 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1131 ppdu_info); 1132 break; 1133 case WIFIRX_HEADER_E: 1134 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1135 ppdu_info->msdu_info.payload_len = tlv_len; 1136 break; 1137 case WIFIRX_MPDU_START_E: 1138 { 1139 uint8_t *rx_mpdu_start = 1140 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1141 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1142 uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1143 PHY_PPDU_ID); 1144 uint8_t filter_category = 0; 1145 1146 ppdu_info->nac_info.fc_valid = 1147 HAL_RX_GET(rx_mpdu_start, 1148 RX_MPDU_INFO_2, 1149 MPDU_FRAME_CONTROL_VALID); 1150 1151 ppdu_info->nac_info.to_ds_flag = 1152 HAL_RX_GET(rx_mpdu_start, 1153 RX_MPDU_INFO_2, 1154 TO_DS); 1155 1156 ppdu_info->nac_info.mac_addr2_valid = 1157 HAL_RX_GET(rx_mpdu_start, 1158 RX_MPDU_INFO_2, 1159 MAC_ADDR_AD2_VALID); 1160 1161 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1162 HAL_RX_GET(rx_mpdu_start, 1163 RX_MPDU_INFO_16, 1164 MAC_ADDR_AD2_15_0); 1165 1166 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1167 HAL_RX_GET(rx_mpdu_start, 1168 RX_MPDU_INFO_17, 1169 MAC_ADDR_AD2_47_16); 1170 1171 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1172 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1173 ppdu_info->rx_status.ppdu_len = 1174 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1175 MPDU_LENGTH); 1176 } else { 1177 ppdu_info->rx_status.ppdu_len += 1178 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1179 MPDU_LENGTH); 1180 } 1181 1182 filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1183 RXPCU_MPDU_FILTER_IN_CATEGORY); 1184 if (filter_category == 1) 1185 ppdu_info->rx_status.monitor_direct_used = 1; 1186 break; 1187 } 1188 case 0: 1189 return HAL_TLV_STATUS_PPDU_DONE; 1190 1191 default: 1192 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1193 unhandled = false; 1194 else 1195 unhandled = true; 1196 break; 1197 } 1198 1199 if (!unhandled) 1200 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1201 "%s TLV type: %d, TLV len:%d %s", 1202 __func__, tlv_tag, tlv_len, 1203 unhandled == true ? "unhandled" : ""); 1204 1205 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1206 rx_tlv, tlv_len); 1207 1208 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1209 } 1210 /** 1211 * hal_reo_status_get_header_generic - Process reo desc info 1212 * @d - Pointer to reo descriptior 1213 * @b - tlv type info 1214 * @h1 - Pointer to hal_reo_status_header where info to be stored 1215 * 1216 * Return - none. 1217 * 1218 */ 1219 static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) 1220 { 1221 1222 uint32_t val1 = 0; 1223 struct hal_reo_status_header *h = 1224 (struct hal_reo_status_header *)h1; 1225 1226 switch (b) { 1227 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1228 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1229 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1230 break; 1231 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1232 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1233 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1234 break; 1235 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1236 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1237 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1238 break; 1239 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1240 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1241 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1242 break; 1243 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1244 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1245 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1246 break; 1247 case HAL_REO_DESC_THRES_STATUS_TLV: 1248 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1249 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1250 break; 1251 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1252 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1253 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1254 break; 1255 default: 1256 pr_err("ERROR: Unknown tlv\n"); 1257 break; 1258 } 1259 h->cmd_num = 1260 HAL_GET_FIELD( 1261 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1262 val1); 1263 h->exec_time = 1264 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1265 CMD_EXECUTION_TIME, val1); 1266 h->status = 1267 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1268 REO_CMD_EXECUTION_STATUS, val1); 1269 switch (b) { 1270 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1271 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1272 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1273 break; 1274 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1275 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1276 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1277 break; 1278 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1279 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1280 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1281 break; 1282 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1283 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1284 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1285 break; 1286 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1287 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1288 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1289 break; 1290 case HAL_REO_DESC_THRES_STATUS_TLV: 1291 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1292 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1293 break; 1294 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1295 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1296 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1297 break; 1298 default: 1299 pr_err("ERROR: Unknown tlv\n"); 1300 break; 1301 } 1302 h->tstamp = 1303 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1304 } 1305 1306 /** 1307 * hal_reo_setup - Initialize HW REO block 1308 * 1309 * @hal_soc: Opaque HAL SOC handle 1310 * @reo_params: parameters needed by HAL for REO config 1311 */ 1312 static void hal_reo_setup_generic(void *hal_soc, 1313 void *reoparams) 1314 { 1315 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1316 uint32_t reg_val; 1317 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1318 1319 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1320 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1321 1322 reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | 1323 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | 1324 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); 1325 1326 reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, 1327 FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | 1328 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | 1329 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); 1330 1331 HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1332 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1333 1334 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1335 1336 /* TODO: Setup destination ring mapping if enabled */ 1337 1338 /* TODO: Error destination ring setting is left to default. 1339 * Default setting is to send all errors to release ring. 1340 */ 1341 1342 HAL_REG_WRITE(soc, 1343 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1344 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1345 HAL_DEFAULT_REO_TIMEOUT_MS * 1000); 1346 1347 HAL_REG_WRITE(soc, 1348 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1349 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1350 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1351 1352 HAL_REG_WRITE(soc, 1353 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1354 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1355 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1356 1357 HAL_REG_WRITE(soc, 1358 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1359 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1360 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1361 1362 /* 1363 * When hash based routing is enabled, routing of the rx packet 1364 * is done based on the following value: 1 _ _ _ _ The last 4 1365 * bits are based on hash[3:0]. This means the possible values 1366 * are 0x10 to 0x1f. This value is used to look-up the 1367 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1368 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1369 * registers need to be configured to set-up the 16 entries to 1370 * map the hash values to a ring number. There are 3 bits per 1371 * hash entry – which are mapped as follows: 1372 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1373 * 7: NOT_USED. 1374 */ 1375 if (reo_params->rx_hash_enabled) { 1376 HAL_REG_WRITE(soc, 1377 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1378 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1379 reo_params->remap1); 1380 1381 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1382 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), 1383 HAL_REG_READ(soc, 1384 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1385 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1386 1387 HAL_REG_WRITE(soc, 1388 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1389 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1390 reo_params->remap2); 1391 1392 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1393 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), 1394 HAL_REG_READ(soc, 1395 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1396 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1397 } 1398 1399 1400 /* TODO: Check if the following registers shoould be setup by host: 1401 * AGING_CONTROL 1402 * HIGH_MEMORY_THRESHOLD 1403 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1404 * GLOBAL_LINK_DESC_COUNT_CTRL 1405 */ 1406 } 1407 1408 /** 1409 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1410 * @hal_soc: Opaque HAL SOC handle 1411 * @hal_ring: Source ring pointer 1412 * @headp: Head Pointer 1413 * @tailp: Tail Pointer 1414 * @ring: Ring type 1415 * 1416 * Return: Update tail pointer and head pointer in arguments. 1417 */ 1418 static inline 1419 void hal_get_hw_hptp_generic(struct hal_soc *soc, void *hal_ring, 1420 uint32_t *headp, uint32_t *tailp, 1421 uint8_t ring) 1422 { 1423 struct hal_srng *srng = (struct hal_srng *)hal_ring; 1424 struct hal_hw_srng_config *ring_config; 1425 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1426 1427 if (!soc || !srng) { 1428 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1429 "%s: Context is Null", __func__); 1430 return; 1431 } 1432 1433 ring_config = HAL_SRNG_CONFIG(soc, ring_type); 1434 if (!ring_config->lmac_ring) { 1435 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1436 *headp = 1437 (SRNG_SRC_REG_READ(srng, HP)) / srng->entry_size; 1438 *tailp = 1439 (SRNG_SRC_REG_READ(srng, TP)) / srng->entry_size; 1440 } else { 1441 *headp = 1442 (SRNG_DST_REG_READ(srng, HP)) / srng->entry_size; 1443 *tailp = 1444 (SRNG_DST_REG_READ(srng, TP)) / srng->entry_size; 1445 } 1446 } 1447 } 1448 1449 /** 1450 * hal_srng_src_hw_init - Private function to initialize SRNG 1451 * source ring HW 1452 * @hal_soc: HAL SOC handle 1453 * @srng: SRNG ring pointer 1454 */ 1455 static inline void hal_srng_src_hw_init_generic(void *halsoc, 1456 struct hal_srng *srng) 1457 { 1458 struct hal_soc *hal = (struct hal_soc *)halsoc; 1459 uint32_t reg_val = 0; 1460 uint64_t tp_addr = 0; 1461 1462 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1463 1464 if (srng->flags & HAL_SRNG_MSI_INTR) { 1465 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1466 srng->msi_addr & 0xffffffff); 1467 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1468 (uint64_t)(srng->msi_addr) >> 32) | 1469 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1470 MSI1_ENABLE), 1); 1471 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1472 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1473 } 1474 1475 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1476 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1477 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1478 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1479 srng->entry_size * srng->num_entries); 1480 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1481 1482 #if defined(WCSS_VERSION) && \ 1483 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1484 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1485 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1486 #else 1487 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) | 1488 SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1489 #endif 1490 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1491 1492 /** 1493 * Interrupt setup: 1494 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1495 * if level mode is required 1496 */ 1497 reg_val = 0; 1498 1499 /* 1500 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1501 * programmed in terms of 1us resolution instead of 8us resolution as 1502 * given in MLD. 1503 */ 1504 if (srng->intr_timer_thres_us) { 1505 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1506 INTERRUPT_TIMER_THRESHOLD), 1507 srng->intr_timer_thres_us); 1508 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1509 } 1510 1511 if (srng->intr_batch_cntr_thres_entries) { 1512 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1513 BATCH_COUNTER_THRESHOLD), 1514 srng->intr_batch_cntr_thres_entries * 1515 srng->entry_size); 1516 } 1517 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1518 1519 reg_val = 0; 1520 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1521 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1522 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1523 } 1524 1525 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1526 1527 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1528 * remain 0 to avoid some WBM stability issues. Remote head/tail 1529 * pointers are not required since this ring is completely managed 1530 * by WBM HW 1531 */ 1532 reg_val = 0; 1533 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1534 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1535 ((unsigned long)(srng->u.src_ring.tp_addr) - 1536 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1537 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1538 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1539 } else { 1540 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1541 } 1542 1543 /* Initilaize head and tail pointers to indicate ring is empty */ 1544 SRNG_SRC_REG_WRITE(srng, HP, 0); 1545 SRNG_SRC_REG_WRITE(srng, TP, 0); 1546 *(srng->u.src_ring.tp_addr) = 0; 1547 1548 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1549 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1550 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1551 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1552 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1553 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1554 1555 /* Loop count is not used for SRC rings */ 1556 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1557 1558 /* 1559 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1560 * todo: update fw_api and replace with above line 1561 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1562 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1563 */ 1564 reg_val |= 0x40; 1565 1566 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1567 } 1568 1569 /** 1570 * hal_srng_dst_hw_init - Private function to initialize SRNG 1571 * destination ring HW 1572 * @hal_soc: HAL SOC handle 1573 * @srng: SRNG ring pointer 1574 */ 1575 static inline void hal_srng_dst_hw_init_generic(void *halsoc, 1576 struct hal_srng *srng) 1577 { 1578 struct hal_soc *hal = (struct hal_soc *)halsoc; 1579 uint32_t reg_val = 0; 1580 uint64_t hp_addr = 0; 1581 1582 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1583 1584 if (srng->flags & HAL_SRNG_MSI_INTR) { 1585 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1586 srng->msi_addr & 0xffffffff); 1587 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1588 (uint64_t)(srng->msi_addr) >> 32) | 1589 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1590 MSI1_ENABLE), 1); 1591 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1592 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1593 } 1594 1595 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1596 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1597 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1598 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1599 srng->entry_size * srng->num_entries); 1600 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1601 1602 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1603 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1604 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1605 1606 1607 /** 1608 * Interrupt setup: 1609 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1610 * if level mode is required 1611 */ 1612 reg_val = 0; 1613 if (srng->intr_timer_thres_us) { 1614 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1615 INTERRUPT_TIMER_THRESHOLD), 1616 srng->intr_timer_thres_us >> 3); 1617 } 1618 1619 if (srng->intr_batch_cntr_thres_entries) { 1620 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1621 BATCH_COUNTER_THRESHOLD), 1622 srng->intr_batch_cntr_thres_entries * 1623 srng->entry_size); 1624 } 1625 1626 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1627 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1628 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1629 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1630 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1631 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1632 1633 /* Initilaize head and tail pointers to indicate ring is empty */ 1634 SRNG_DST_REG_WRITE(srng, HP, 0); 1635 SRNG_DST_REG_WRITE(srng, TP, 0); 1636 *(srng->u.dst_ring.hp_addr) = 0; 1637 1638 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1639 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1640 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1641 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1642 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1643 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1644 1645 /* 1646 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1647 * todo: update fw_api and replace with above line 1648 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1649 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1650 */ 1651 reg_val |= 0x40; 1652 1653 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1654 1655 } 1656 1657 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1658 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1659 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1660 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1661 1662 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1663 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1664 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1665 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1666 1667 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1668 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1669 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1670 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1671 1672 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1673 (((*(((uint32_t *) wbm_desc) + \ 1674 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1675 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1676 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1677 1678 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1679 (((*(((uint32_t *) wbm_desc) + \ 1680 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1681 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1682 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1683 1684 /** 1685 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1686 * save it to hal_wbm_err_desc_info structure passed by caller 1687 * @wbm_desc: wbm ring descriptor 1688 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1689 * Return: void 1690 */ 1691 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1692 void *wbm_er_info1) 1693 { 1694 struct hal_wbm_err_desc_info *wbm_er_info = 1695 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1696 1697 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1698 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1699 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1700 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1701 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1702 } 1703 1704 /** 1705 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1706 * @hal_desc: completion ring descriptor pointer 1707 * 1708 * This function will return the type of pointer - buffer or descriptor 1709 * 1710 * Return: buffer type 1711 */ 1712 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1713 { 1714 uint32_t comp_desc = 1715 *(uint32_t *) (((uint8_t *) hal_desc) + 1716 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1717 1718 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1719 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1720 } 1721 1722 /** 1723 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1724 * human readable format. 1725 * @mpdu_start: pointer the rx_attention TLV in pkt. 1726 * @dbg_level: log level. 1727 * 1728 * Return: void 1729 */ 1730 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1731 uint8_t dbg_level) 1732 { 1733 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1734 struct rx_mpdu_info *mpdu_info = 1735 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1736 1737 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1738 "rx_mpdu_start tlv (1/5) - " 1739 "rxpcu_mpdu_filter_in_category: %x " 1740 "sw_frame_group_id: %x " 1741 "ndp_frame: %x " 1742 "phy_err: %x " 1743 "phy_err_during_mpdu_header: %x " 1744 "protocol_version_err: %x " 1745 "ast_based_lookup_valid: %x " 1746 "phy_ppdu_id: %x " 1747 "ast_index: %x " 1748 "sw_peer_id: %x " 1749 "mpdu_frame_control_valid: %x " 1750 "mpdu_duration_valid: %x " 1751 "mac_addr_ad1_valid: %x " 1752 "mac_addr_ad2_valid: %x " 1753 "mac_addr_ad3_valid: %x " 1754 "mac_addr_ad4_valid: %x " 1755 "mpdu_sequence_control_valid: %x " 1756 "mpdu_qos_control_valid: %x " 1757 "mpdu_ht_control_valid: %x " 1758 "frame_encryption_info_valid: %x ", 1759 mpdu_info->rxpcu_mpdu_filter_in_category, 1760 mpdu_info->sw_frame_group_id, 1761 mpdu_info->ndp_frame, 1762 mpdu_info->phy_err, 1763 mpdu_info->phy_err_during_mpdu_header, 1764 mpdu_info->protocol_version_err, 1765 mpdu_info->ast_based_lookup_valid, 1766 mpdu_info->phy_ppdu_id, 1767 mpdu_info->ast_index, 1768 mpdu_info->sw_peer_id, 1769 mpdu_info->mpdu_frame_control_valid, 1770 mpdu_info->mpdu_duration_valid, 1771 mpdu_info->mac_addr_ad1_valid, 1772 mpdu_info->mac_addr_ad2_valid, 1773 mpdu_info->mac_addr_ad3_valid, 1774 mpdu_info->mac_addr_ad4_valid, 1775 mpdu_info->mpdu_sequence_control_valid, 1776 mpdu_info->mpdu_qos_control_valid, 1777 mpdu_info->mpdu_ht_control_valid, 1778 mpdu_info->frame_encryption_info_valid); 1779 1780 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1781 "rx_mpdu_start tlv (2/5) - " 1782 "fr_ds: %x " 1783 "to_ds: %x " 1784 "encrypted: %x " 1785 "mpdu_retry: %x " 1786 "mpdu_sequence_number: %x " 1787 "epd_en: %x " 1788 "all_frames_shall_be_encrypted: %x " 1789 "encrypt_type: %x " 1790 "mesh_sta: %x " 1791 "bssid_hit: %x " 1792 "bssid_number: %x " 1793 "tid: %x " 1794 "pn_31_0: %x " 1795 "pn_63_32: %x " 1796 "pn_95_64: %x " 1797 "pn_127_96: %x " 1798 "peer_meta_data: %x " 1799 "rxpt_classify_info.reo_destination_indication: %x " 1800 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1801 "rx_reo_queue_desc_addr_31_0: %x ", 1802 mpdu_info->fr_ds, 1803 mpdu_info->to_ds, 1804 mpdu_info->encrypted, 1805 mpdu_info->mpdu_retry, 1806 mpdu_info->mpdu_sequence_number, 1807 mpdu_info->epd_en, 1808 mpdu_info->all_frames_shall_be_encrypted, 1809 mpdu_info->encrypt_type, 1810 mpdu_info->mesh_sta, 1811 mpdu_info->bssid_hit, 1812 mpdu_info->bssid_number, 1813 mpdu_info->tid, 1814 mpdu_info->pn_31_0, 1815 mpdu_info->pn_63_32, 1816 mpdu_info->pn_95_64, 1817 mpdu_info->pn_127_96, 1818 mpdu_info->peer_meta_data, 1819 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1820 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1821 mpdu_info->rx_reo_queue_desc_addr_31_0); 1822 1823 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1824 "rx_mpdu_start tlv (3/5) - " 1825 "rx_reo_queue_desc_addr_39_32: %x " 1826 "receive_queue_number: %x " 1827 "pre_delim_err_warning: %x " 1828 "first_delim_err: %x " 1829 "key_id_octet: %x " 1830 "new_peer_entry: %x " 1831 "decrypt_needed: %x " 1832 "decap_type: %x " 1833 "rx_insert_vlan_c_tag_padding: %x " 1834 "rx_insert_vlan_s_tag_padding: %x " 1835 "strip_vlan_c_tag_decap: %x " 1836 "strip_vlan_s_tag_decap: %x " 1837 "pre_delim_count: %x " 1838 "ampdu_flag: %x " 1839 "bar_frame: %x " 1840 "mpdu_length: %x " 1841 "first_mpdu: %x " 1842 "mcast_bcast: %x " 1843 "ast_index_not_found: %x " 1844 "ast_index_timeout: %x ", 1845 mpdu_info->rx_reo_queue_desc_addr_39_32, 1846 mpdu_info->receive_queue_number, 1847 mpdu_info->pre_delim_err_warning, 1848 mpdu_info->first_delim_err, 1849 mpdu_info->key_id_octet, 1850 mpdu_info->new_peer_entry, 1851 mpdu_info->decrypt_needed, 1852 mpdu_info->decap_type, 1853 mpdu_info->rx_insert_vlan_c_tag_padding, 1854 mpdu_info->rx_insert_vlan_s_tag_padding, 1855 mpdu_info->strip_vlan_c_tag_decap, 1856 mpdu_info->strip_vlan_s_tag_decap, 1857 mpdu_info->pre_delim_count, 1858 mpdu_info->ampdu_flag, 1859 mpdu_info->bar_frame, 1860 mpdu_info->mpdu_length, 1861 mpdu_info->first_mpdu, 1862 mpdu_info->mcast_bcast, 1863 mpdu_info->ast_index_not_found, 1864 mpdu_info->ast_index_timeout); 1865 1866 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1867 "rx_mpdu_start tlv (4/5) - " 1868 "power_mgmt: %x " 1869 "non_qos: %x " 1870 "null_data: %x " 1871 "mgmt_type: %x " 1872 "ctrl_type: %x " 1873 "more_data: %x " 1874 "eosp: %x " 1875 "fragment_flag: %x " 1876 "order: %x " 1877 "u_apsd_trigger: %x " 1878 "encrypt_required: %x " 1879 "directed: %x " 1880 "mpdu_frame_control_field: %x " 1881 "mpdu_duration_field: %x " 1882 "mac_addr_ad1_31_0: %x " 1883 "mac_addr_ad1_47_32: %x " 1884 "mac_addr_ad2_15_0: %x " 1885 "mac_addr_ad2_47_16: %x " 1886 "mac_addr_ad3_31_0: %x " 1887 "mac_addr_ad3_47_32: %x ", 1888 mpdu_info->power_mgmt, 1889 mpdu_info->non_qos, 1890 mpdu_info->null_data, 1891 mpdu_info->mgmt_type, 1892 mpdu_info->ctrl_type, 1893 mpdu_info->more_data, 1894 mpdu_info->eosp, 1895 mpdu_info->fragment_flag, 1896 mpdu_info->order, 1897 mpdu_info->u_apsd_trigger, 1898 mpdu_info->encrypt_required, 1899 mpdu_info->directed, 1900 mpdu_info->mpdu_frame_control_field, 1901 mpdu_info->mpdu_duration_field, 1902 mpdu_info->mac_addr_ad1_31_0, 1903 mpdu_info->mac_addr_ad1_47_32, 1904 mpdu_info->mac_addr_ad2_15_0, 1905 mpdu_info->mac_addr_ad2_47_16, 1906 mpdu_info->mac_addr_ad3_31_0, 1907 mpdu_info->mac_addr_ad3_47_32); 1908 1909 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1910 "rx_mpdu_start tlv (5/5) - " 1911 "mpdu_sequence_control_field: %x " 1912 "mac_addr_ad4_31_0: %x " 1913 "mac_addr_ad4_47_32: %x " 1914 "mpdu_qos_control_field: %x " 1915 "mpdu_ht_control_field: %x ", 1916 mpdu_info->mpdu_sequence_control_field, 1917 mpdu_info->mac_addr_ad4_31_0, 1918 mpdu_info->mac_addr_ad4_47_32, 1919 mpdu_info->mpdu_qos_control_field, 1920 mpdu_info->mpdu_ht_control_field); 1921 } 1922 #endif 1923 1924 /** 1925 * hal_tx_desc_set_search_type - Set the search type value 1926 * @desc: Handle to Tx Descriptor 1927 * @search_type: search type 1928 * 0 – Normal search 1929 * 1 – Index based address search 1930 * 2 – Index based flow search 1931 * 1932 * Return: void 1933 */ 1934 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 1935 static void hal_tx_desc_set_search_type_generic(void *desc, 1936 uint8_t search_type) 1937 { 1938 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 1939 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 1940 } 1941 #else 1942 static void hal_tx_desc_set_search_type_generic(void *desc, 1943 uint8_t search_type) 1944 { 1945 } 1946 1947 #endif 1948 1949 /** 1950 * hal_tx_desc_set_search_index - Set the search index value 1951 * @desc: Handle to Tx Descriptor 1952 * @search_index: The index that will be used for index based address or 1953 * flow search. The field is valid when 'search_type' is 1954 * 1 0r 2 1955 * 1956 * Return: void 1957 */ 1958 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 1959 static void hal_tx_desc_set_search_index_generic(void *desc, 1960 uint32_t search_index) 1961 { 1962 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 1963 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 1964 } 1965 #else 1966 static void hal_tx_desc_set_search_index_generic(void *desc, 1967 uint32_t search_index) 1968 { 1969 } 1970 #endif 1971