1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 22 ((struct rx_msdu_desc_info *) \ 23 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 24 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 25 /** 26 * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr 27 * @msdu_details_ptr - Pointer to msdu_details_ptr 28 * Return - Pointer to rx_msdu_desc_info structure. 29 * 30 */ 31 static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) 32 { 33 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 34 } 35 36 37 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 38 ((struct rx_msdu_details *) \ 39 _OFFSET_TO_BYTE_PTR((link_desc),\ 40 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 41 /** 42 * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details 43 * @link_desc - Pointer to link desc 44 * Return - Pointer to rx_msdu_details structure 45 * 46 */ 47 48 static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) 49 { 50 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 51 } 52 53 /** 54 * hal_tx_comp_get_status() - TQM Release reason 55 * @hal_desc: completion ring Tx status 56 * 57 * This function will parse the WBM completion descriptor and populate in 58 * HAL structure 59 * 60 * Return: none 61 */ 62 #if defined(WCSS_VERSION) && \ 63 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 64 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 65 static inline void hal_tx_comp_get_status_generic(void *desc, 66 void *ts1) 67 { 68 uint8_t rate_stats_valid = 0; 69 uint32_t rate_stats = 0; 70 struct hal_tx_completion_status *ts = 71 (struct hal_tx_completion_status *)ts1; 72 73 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 74 TQM_STATUS_NUMBER); 75 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 76 ACK_FRAME_RSSI); 77 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 78 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 79 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 80 MSDU_PART_OF_AMSDU); 81 82 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 83 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 84 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 85 TRANSMIT_COUNT); 86 87 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 88 TX_RATE_STATS); 89 90 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 91 TX_RATE_STATS_INFO_VALID, rate_stats); 92 93 ts->valid = rate_stats_valid; 94 95 if (rate_stats_valid) { 96 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 97 rate_stats); 98 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 99 TRANSMIT_PKT_TYPE, rate_stats); 100 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 101 TRANSMIT_STBC, rate_stats); 102 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 103 rate_stats); 104 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 105 rate_stats); 106 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 107 rate_stats); 108 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 109 rate_stats); 110 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 111 rate_stats); 112 } 113 114 ts->release_src = hal_tx_comp_get_buffer_source(desc); 115 ts->status = hal_tx_comp_get_release_reason(desc); 116 117 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 118 TX_RATE_STATS_INFO_TX_RATE_STATS); 119 } 120 #else 121 static inline void hal_tx_comp_get_status_generic(void *desc, 122 struct hal_tx_completion_status *ts) 123 { 124 125 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 126 TQM_STATUS_NUMBER); 127 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 128 ACK_FRAME_RSSI); 129 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 130 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 131 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 132 MSDU_PART_OF_AMSDU); 133 134 ts->release_src = hal_tx_comp_get_buffer_source(desc); 135 ts->status = hal_tx_comp_get_release_reason(desc); 136 } 137 #endif 138 139 140 /** 141 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 142 * @desc: Handle to Tx Descriptor 143 * @paddr: Physical Address 144 * @pool_id: Return Buffer Manager ID 145 * @desc_id: Descriptor ID 146 * @type: 0 - Address points to a MSDU buffer 147 * 1 - Address points to MSDU extension descriptor 148 * 149 * Return: void 150 */ 151 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 152 dma_addr_t paddr, uint8_t pool_id, 153 uint32_t desc_id, uint8_t type) 154 { 155 /* Set buffer_addr_info.buffer_addr_31_0 */ 156 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 157 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 158 159 /* Set buffer_addr_info.buffer_addr_39_32 */ 160 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 161 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 162 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 163 (((uint64_t) paddr) >> 32)); 164 165 /* Set buffer_addr_info.return_buffer_manager = pool id */ 166 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 167 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 168 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 169 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 170 171 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 172 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 173 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 174 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 175 176 /* Set Buffer or Ext Descriptor Type */ 177 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 178 BUF_OR_EXT_DESC_TYPE) |= 179 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 180 } 181 182 #if defined(CONFIG_MCL) && defined(QCA_WIFI_QCA6290_11AX) 183 /** 184 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 185 * tlv_tag: Taf of the TLVs 186 * rx_tlv: the pointer to the TLVs 187 * @ppdu_info: pointer to ppdu_info 188 * 189 * Return: true if the tlv is handled, false if not 190 */ 191 static inline bool 192 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 193 struct hal_rx_ppdu_info *ppdu_info) 194 { 195 uint32_t value; 196 197 switch (tlv_tag) { 198 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 199 { 200 uint8_t *he_sig_a_mu_ul_info = 201 (uint8_t *)rx_tlv + 202 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 203 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 204 ppdu_info->rx_status.he_flags = 1; 205 206 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 207 FORMAT_INDICATION); 208 if (value == 0) { 209 ppdu_info->rx_status.he_data1 = 210 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 211 } else { 212 ppdu_info->rx_status.he_data1 = 213 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 214 } 215 return true; 216 } 217 default: 218 return false; 219 } 220 } 221 #else 222 static inline bool 223 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 224 struct hal_rx_ppdu_info *ppdu_info) 225 { 226 return false; 227 } 228 #endif /* CONFIG_MCL && QCA_WIFI_QCA6290_11AX */ 229 230 /** 231 * hal_rx_status_get_tlv_info() - process receive info TLV 232 * @rx_tlv_hdr: pointer to TLV header 233 * @ppdu_info: pointer to ppdu_info 234 * 235 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 236 */ 237 static inline uint32_t 238 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 239 void *halsoc) 240 { 241 struct hal_soc *hal = (struct hal_soc *)halsoc; 242 uint32_t tlv_tag, user_id, tlv_len, value; 243 uint8_t group_id = 0; 244 uint8_t he_dcm = 0; 245 uint8_t he_stbc = 0; 246 uint16_t he_gi = 0; 247 uint16_t he_ltf = 0; 248 void *rx_tlv; 249 bool unhandled = false; 250 struct hal_rx_ppdu_info *ppdu_info = 251 (struct hal_rx_ppdu_info *)ppduinfo; 252 253 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 254 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 255 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 256 257 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 258 switch (tlv_tag) { 259 260 case WIFIRX_PPDU_START_E: 261 ppdu_info->com_info.ppdu_id = 262 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 263 PHY_PPDU_ID); 264 /* channel number is set in PHY meta data */ 265 ppdu_info->rx_status.chan_num = 266 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 267 SW_PHY_META_DATA); 268 ppdu_info->com_info.ppdu_timestamp = 269 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 270 PPDU_START_TIMESTAMP); 271 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 272 break; 273 274 case WIFIRX_PPDU_START_USER_INFO_E: 275 break; 276 277 case WIFIRX_PPDU_END_E: 278 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 279 "[%s][%d] ppdu_end_e len=%d", 280 __func__, __LINE__, tlv_len); 281 /* This is followed by sub-TLVs of PPDU_END */ 282 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 283 break; 284 285 case WIFIRXPCU_PPDU_END_INFO_E: 286 ppdu_info->rx_status.tsft = 287 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 288 WB_TIMESTAMP_UPPER_32); 289 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 290 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 291 WB_TIMESTAMP_LOWER_32); 292 ppdu_info->rx_status.duration = 293 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 294 RX_PPDU_DURATION); 295 break; 296 297 case WIFIRX_PPDU_END_USER_STATS_E: 298 { 299 unsigned long tid = 0; 300 uint16_t seq = 0; 301 302 ppdu_info->rx_status.ast_index = 303 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 304 AST_INDEX); 305 306 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 307 RECEIVED_QOS_DATA_TID_BITMAP); 308 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 309 310 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 311 ppdu_info->rx_status.tid = HAL_TID_INVALID; 312 313 ppdu_info->rx_status.tcp_msdu_count = 314 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 315 TCP_MSDU_COUNT) + 316 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 317 TCP_ACK_MSDU_COUNT); 318 ppdu_info->rx_status.udp_msdu_count = 319 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 320 UDP_MSDU_COUNT); 321 ppdu_info->rx_status.other_msdu_count = 322 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 323 OTHER_MSDU_COUNT); 324 325 ppdu_info->rx_status.frame_control_info_valid = 326 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 327 DATA_SEQUENCE_CONTROL_INFO_VALID); 328 329 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 330 FIRST_DATA_SEQ_CTRL); 331 if (ppdu_info->rx_status.frame_control_info_valid) 332 ppdu_info->rx_status.first_data_seq_ctrl = seq; 333 334 ppdu_info->rx_status.preamble_type = 335 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 336 HT_CONTROL_FIELD_PKT_TYPE); 337 switch (ppdu_info->rx_status.preamble_type) { 338 case HAL_RX_PKT_TYPE_11N: 339 ppdu_info->rx_status.ht_flags = 1; 340 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 341 break; 342 case HAL_RX_PKT_TYPE_11AC: 343 ppdu_info->rx_status.vht_flags = 1; 344 break; 345 case HAL_RX_PKT_TYPE_11AX: 346 ppdu_info->rx_status.he_flags = 1; 347 break; 348 default: 349 break; 350 } 351 352 ppdu_info->com_info.mpdu_cnt_fcs_ok = 353 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 354 MPDU_CNT_FCS_OK); 355 ppdu_info->com_info.mpdu_cnt_fcs_err = 356 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 357 MPDU_CNT_FCS_ERR); 358 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 359 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 360 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 361 else 362 ppdu_info->rx_status.rs_flags &= 363 (~IEEE80211_AMPDU_FLAG); 364 break; 365 } 366 367 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 368 break; 369 370 case WIFIRX_PPDU_END_STATUS_DONE_E: 371 return HAL_TLV_STATUS_PPDU_DONE; 372 373 case WIFIDUMMY_E: 374 return HAL_TLV_STATUS_BUF_DONE; 375 376 case WIFIPHYRX_HT_SIG_E: 377 { 378 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 379 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 380 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 381 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 382 FEC_CODING); 383 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 384 1 : 0; 385 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 386 HT_SIG_INFO_0, MCS); 387 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 388 HT_SIG_INFO_0, CBW); 389 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 390 HT_SIG_INFO_1, SHORT_GI); 391 break; 392 } 393 394 case WIFIPHYRX_L_SIG_B_E: 395 { 396 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 397 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 398 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 399 400 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 401 switch (value) { 402 case 1: 403 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 404 break; 405 case 2: 406 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 407 break; 408 case 3: 409 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 410 break; 411 case 4: 412 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 413 break; 414 case 5: 415 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 416 break; 417 case 6: 418 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 419 break; 420 case 7: 421 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 422 break; 423 default: 424 break; 425 } 426 ppdu_info->rx_status.cck_flag = 1; 427 break; 428 } 429 430 case WIFIPHYRX_L_SIG_A_E: 431 { 432 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 433 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 434 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 435 436 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 437 switch (value) { 438 case 8: 439 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 440 break; 441 case 9: 442 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 443 break; 444 case 10: 445 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 446 break; 447 case 11: 448 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 449 break; 450 case 12: 451 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 452 break; 453 case 13: 454 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 455 break; 456 case 14: 457 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 458 break; 459 case 15: 460 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 461 break; 462 default: 463 break; 464 } 465 ppdu_info->rx_status.ofdm_flag = 1; 466 break; 467 } 468 469 case WIFIPHYRX_VHT_SIG_A_E: 470 { 471 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 472 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 473 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 474 475 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 476 SU_MU_CODING); 477 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 478 1 : 0; 479 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 480 ppdu_info->rx_status.vht_flag_values5 = group_id; 481 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 482 VHT_SIG_A_INFO_1, MCS); 483 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 484 VHT_SIG_A_INFO_1, GI_SETTING); 485 486 switch (hal->target_type) { 487 case TARGET_TYPE_QCA8074: 488 case TARGET_TYPE_QCA8074V2: 489 ppdu_info->rx_status.is_stbc = 490 HAL_RX_GET(vht_sig_a_info, 491 VHT_SIG_A_INFO_0, STBC); 492 value = HAL_RX_GET(vht_sig_a_info, 493 VHT_SIG_A_INFO_0, N_STS); 494 if (ppdu_info->rx_status.is_stbc && (value > 0)) 495 value = ((value + 1) >> 1) - 1; 496 ppdu_info->rx_status.nss = 497 ((value & VHT_SIG_SU_NSS_MASK) + 1); 498 499 break; 500 case TARGET_TYPE_QCA6290: 501 #if !defined(QCA_WIFI_QCA6290_11AX) 502 ppdu_info->rx_status.is_stbc = 503 HAL_RX_GET(vht_sig_a_info, 504 VHT_SIG_A_INFO_0, STBC); 505 value = HAL_RX_GET(vht_sig_a_info, 506 VHT_SIG_A_INFO_0, N_STS); 507 if (ppdu_info->rx_status.is_stbc && (value > 0)) 508 value = ((value + 1) >> 1) - 1; 509 ppdu_info->rx_status.nss = 510 ((value & VHT_SIG_SU_NSS_MASK) + 1); 511 #else 512 ppdu_info->rx_status.nss = 0; 513 #endif 514 break; 515 #ifdef QCA_WIFI_QCA6390 516 case TARGET_TYPE_QCA6390: 517 ppdu_info->rx_status.nss = 0; 518 break; 519 #endif 520 default: 521 break; 522 } 523 ppdu_info->rx_status.vht_flag_values3[0] = 524 (((ppdu_info->rx_status.mcs) << 4) 525 | ppdu_info->rx_status.nss); 526 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 527 VHT_SIG_A_INFO_0, BANDWIDTH); 528 ppdu_info->rx_status.vht_flag_values2 = 529 ppdu_info->rx_status.bw; 530 ppdu_info->rx_status.vht_flag_values4 = 531 HAL_RX_GET(vht_sig_a_info, 532 VHT_SIG_A_INFO_1, SU_MU_CODING); 533 534 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 535 VHT_SIG_A_INFO_1, BEAMFORMED); 536 537 break; 538 } 539 case WIFIPHYRX_HE_SIG_A_SU_E: 540 { 541 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 542 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 543 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 544 ppdu_info->rx_status.he_flags = 1; 545 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 546 FORMAT_INDICATION); 547 if (value == 0) { 548 ppdu_info->rx_status.he_data1 = 549 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 550 } else { 551 ppdu_info->rx_status.he_data1 = 552 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 553 } 554 555 /* data1 */ 556 ppdu_info->rx_status.he_data1 |= 557 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 558 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 559 QDF_MON_STATUS_HE_DL_UL_KNOWN | 560 QDF_MON_STATUS_HE_MCS_KNOWN | 561 QDF_MON_STATUS_HE_DCM_KNOWN | 562 QDF_MON_STATUS_HE_CODING_KNOWN | 563 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 564 QDF_MON_STATUS_HE_STBC_KNOWN | 565 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 566 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 567 568 /* data2 */ 569 ppdu_info->rx_status.he_data2 = 570 QDF_MON_STATUS_HE_GI_KNOWN; 571 ppdu_info->rx_status.he_data2 |= 572 QDF_MON_STATUS_TXBF_KNOWN | 573 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 574 QDF_MON_STATUS_TXOP_KNOWN | 575 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 576 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 577 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 578 579 /* data3 */ 580 value = HAL_RX_GET(he_sig_a_su_info, 581 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 582 ppdu_info->rx_status.he_data3 = value; 583 value = HAL_RX_GET(he_sig_a_su_info, 584 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 585 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 586 ppdu_info->rx_status.he_data3 |= value; 587 value = HAL_RX_GET(he_sig_a_su_info, 588 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 589 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 590 ppdu_info->rx_status.he_data3 |= value; 591 592 value = HAL_RX_GET(he_sig_a_su_info, 593 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 594 ppdu_info->rx_status.mcs = value; 595 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 596 ppdu_info->rx_status.he_data3 |= value; 597 598 value = HAL_RX_GET(he_sig_a_su_info, 599 HE_SIG_A_SU_INFO_0, DCM); 600 he_dcm = value; 601 value = value << QDF_MON_STATUS_DCM_SHIFT; 602 ppdu_info->rx_status.he_data3 |= value; 603 value = HAL_RX_GET(he_sig_a_su_info, 604 HE_SIG_A_SU_INFO_1, CODING); 605 value = value << QDF_MON_STATUS_CODING_SHIFT; 606 ppdu_info->rx_status.he_data3 |= value; 607 value = HAL_RX_GET(he_sig_a_su_info, 608 HE_SIG_A_SU_INFO_1, 609 LDPC_EXTRA_SYMBOL); 610 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 611 ppdu_info->rx_status.he_data3 |= value; 612 value = HAL_RX_GET(he_sig_a_su_info, 613 HE_SIG_A_SU_INFO_1, STBC); 614 he_stbc = value; 615 value = value << QDF_MON_STATUS_STBC_SHIFT; 616 ppdu_info->rx_status.he_data3 |= value; 617 618 /* data4 */ 619 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 620 SPATIAL_REUSE); 621 ppdu_info->rx_status.he_data4 = value; 622 623 /* data5 */ 624 value = HAL_RX_GET(he_sig_a_su_info, 625 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 626 ppdu_info->rx_status.he_data5 = value; 627 ppdu_info->rx_status.bw = value; 628 value = HAL_RX_GET(he_sig_a_su_info, 629 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 630 switch (value) { 631 case 0: 632 he_gi = HE_GI_0_8; 633 he_ltf = HE_LTF_1_X; 634 break; 635 case 1: 636 he_gi = HE_GI_0_8; 637 he_ltf = HE_LTF_2_X; 638 break; 639 case 2: 640 he_gi = HE_GI_1_6; 641 he_ltf = HE_LTF_2_X; 642 break; 643 case 3: 644 if (he_dcm && he_stbc) { 645 he_gi = HE_GI_0_8; 646 he_ltf = HE_LTF_4_X; 647 } else { 648 he_gi = HE_GI_3_2; 649 he_ltf = HE_LTF_4_X; 650 } 651 break; 652 } 653 ppdu_info->rx_status.sgi = he_gi; 654 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 655 ppdu_info->rx_status.he_data5 |= value; 656 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 657 ppdu_info->rx_status.he_data5 |= value; 658 659 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 660 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 661 ppdu_info->rx_status.he_data5 |= value; 662 663 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 664 PACKET_EXTENSION_A_FACTOR); 665 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 666 ppdu_info->rx_status.he_data5 |= value; 667 668 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 669 value = value << QDF_MON_STATUS_TXBF_SHIFT; 670 ppdu_info->rx_status.he_data5 |= value; 671 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 672 PACKET_EXTENSION_PE_DISAMBIGUITY); 673 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 674 ppdu_info->rx_status.he_data5 |= value; 675 676 /* data6 */ 677 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 678 value++; 679 ppdu_info->rx_status.nss = value; 680 ppdu_info->rx_status.he_data6 = value; 681 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 682 DOPPLER_INDICATION); 683 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 684 ppdu_info->rx_status.he_data6 |= value; 685 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 686 TXOP_DURATION); 687 value = value << QDF_MON_STATUS_TXOP_SHIFT; 688 ppdu_info->rx_status.he_data6 |= value; 689 690 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 691 HE_SIG_A_SU_INFO_1, TXBF); 692 break; 693 } 694 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 695 { 696 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 697 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 698 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 699 700 ppdu_info->rx_status.he_mu_flags = 1; 701 702 /* HE Flags */ 703 /*data1*/ 704 ppdu_info->rx_status.he_data1 = 705 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 706 ppdu_info->rx_status.he_data1 |= 707 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 708 QDF_MON_STATUS_HE_DL_UL_KNOWN | 709 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 710 QDF_MON_STATUS_HE_STBC_KNOWN | 711 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 712 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 713 714 /* data2 */ 715 ppdu_info->rx_status.he_data2 = 716 QDF_MON_STATUS_HE_GI_KNOWN; 717 ppdu_info->rx_status.he_data2 |= 718 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 719 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 720 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 721 QDF_MON_STATUS_TXOP_KNOWN | 722 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 723 724 /*data3*/ 725 value = HAL_RX_GET(he_sig_a_mu_dl_info, 726 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 727 ppdu_info->rx_status.he_data3 = value; 728 729 value = HAL_RX_GET(he_sig_a_mu_dl_info, 730 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 731 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 732 ppdu_info->rx_status.he_data3 |= value; 733 734 value = HAL_RX_GET(he_sig_a_mu_dl_info, 735 HE_SIG_A_MU_DL_INFO_1, 736 LDPC_EXTRA_SYMBOL); 737 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 738 ppdu_info->rx_status.he_data3 |= value; 739 740 value = HAL_RX_GET(he_sig_a_mu_dl_info, 741 HE_SIG_A_MU_DL_INFO_1, STBC); 742 he_stbc = value; 743 value = value << QDF_MON_STATUS_STBC_SHIFT; 744 ppdu_info->rx_status.he_data3 |= value; 745 746 /*data4*/ 747 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 748 SPATIAL_REUSE); 749 ppdu_info->rx_status.he_data4 = value; 750 751 /*data5*/ 752 value = HAL_RX_GET(he_sig_a_mu_dl_info, 753 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 754 ppdu_info->rx_status.he_data5 = value; 755 ppdu_info->rx_status.bw = value; 756 757 value = HAL_RX_GET(he_sig_a_mu_dl_info, 758 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 759 switch (value) { 760 case 0: 761 he_gi = HE_GI_0_8; 762 he_ltf = HE_LTF_4_X; 763 break; 764 case 1: 765 he_gi = HE_GI_0_8; 766 he_ltf = HE_LTF_2_X; 767 break; 768 case 2: 769 he_gi = HE_GI_1_6; 770 he_ltf = HE_LTF_2_X; 771 break; 772 case 3: 773 he_gi = HE_GI_3_2; 774 he_ltf = HE_LTF_4_X; 775 break; 776 } 777 ppdu_info->rx_status.sgi = he_gi; 778 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 779 ppdu_info->rx_status.he_data5 |= value; 780 781 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 782 ppdu_info->rx_status.he_data5 |= value; 783 784 value = HAL_RX_GET(he_sig_a_mu_dl_info, 785 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 786 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 787 ppdu_info->rx_status.he_data5 |= value; 788 789 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 790 PACKET_EXTENSION_A_FACTOR); 791 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 792 ppdu_info->rx_status.he_data5 |= value; 793 794 795 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 796 PACKET_EXTENSION_PE_DISAMBIGUITY); 797 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 798 ppdu_info->rx_status.he_data5 |= value; 799 800 /*data6*/ 801 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 802 DOPPLER_INDICATION); 803 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 804 ppdu_info->rx_status.he_data6 |= value; 805 806 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 807 TXOP_DURATION); 808 value = value << QDF_MON_STATUS_TXOP_SHIFT; 809 ppdu_info->rx_status.he_data6 |= value; 810 811 /* HE-MU Flags */ 812 /* HE-MU-flags1 */ 813 ppdu_info->rx_status.he_flags1 = 814 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 815 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 816 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 817 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 818 QDF_MON_STATUS_RU_0_KNOWN; 819 820 value = HAL_RX_GET(he_sig_a_mu_dl_info, 821 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 822 ppdu_info->rx_status.he_flags1 |= value; 823 value = HAL_RX_GET(he_sig_a_mu_dl_info, 824 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 825 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 826 ppdu_info->rx_status.he_flags1 |= value; 827 828 /* HE-MU-flags2 */ 829 ppdu_info->rx_status.he_flags2 = 830 QDF_MON_STATUS_BW_KNOWN; 831 832 value = HAL_RX_GET(he_sig_a_mu_dl_info, 833 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 834 ppdu_info->rx_status.he_flags2 |= value; 835 value = HAL_RX_GET(he_sig_a_mu_dl_info, 836 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 837 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 838 ppdu_info->rx_status.he_flags2 |= value; 839 value = HAL_RX_GET(he_sig_a_mu_dl_info, 840 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 841 value = value - 1; 842 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 843 ppdu_info->rx_status.he_flags2 |= value; 844 break; 845 } 846 case WIFIPHYRX_HE_SIG_B1_MU_E: 847 { 848 849 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 850 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 851 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 852 853 ppdu_info->rx_status.he_sig_b_common_known |= 854 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 855 /* TODO: Check on the availability of other fields in 856 * sig_b_common 857 */ 858 859 value = HAL_RX_GET(he_sig_b1_mu_info, 860 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 861 ppdu_info->rx_status.he_RU[0] = value; 862 break; 863 } 864 case WIFIPHYRX_HE_SIG_B2_MU_E: 865 { 866 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 867 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 868 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 869 /* 870 * Not all "HE" fields can be updated from 871 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 872 * to populate rest of the "HE" fields for MU scenarios. 873 */ 874 875 /* HE-data1 */ 876 ppdu_info->rx_status.he_data1 |= 877 QDF_MON_STATUS_HE_MCS_KNOWN | 878 QDF_MON_STATUS_HE_CODING_KNOWN; 879 880 /* HE-data2 */ 881 882 /* HE-data3 */ 883 value = HAL_RX_GET(he_sig_b2_mu_info, 884 HE_SIG_B2_MU_INFO_0, STA_MCS); 885 ppdu_info->rx_status.mcs = value; 886 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 887 ppdu_info->rx_status.he_data3 |= value; 888 889 890 value = HAL_RX_GET(he_sig_b2_mu_info, 891 HE_SIG_B2_MU_INFO_0, STA_CODING); 892 value = value << QDF_MON_STATUS_CODING_SHIFT; 893 ppdu_info->rx_status.he_data3 |= value; 894 895 /* HE-data4 */ 896 value = HAL_RX_GET(he_sig_b2_mu_info, 897 HE_SIG_B2_MU_INFO_0, STA_ID); 898 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 899 ppdu_info->rx_status.he_data4 |= value; 900 901 /* HE-data5 */ 902 903 /* HE-data6 */ 904 value = HAL_RX_GET(he_sig_b2_mu_info, 905 HE_SIG_B2_MU_INFO_0, NSTS); 906 /* value n indicates n+1 spatial streams */ 907 value++; 908 ppdu_info->rx_status.nss = value; 909 ppdu_info->rx_status.he_data6 |= value; 910 911 break; 912 913 } 914 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 915 { 916 uint8_t *he_sig_b2_ofdma_info = 917 (uint8_t *)rx_tlv + 918 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 919 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 920 921 /* 922 * Not all "HE" fields can be updated from 923 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 924 * to populate rest of "HE" fields for MU OFDMA scenarios. 925 */ 926 927 /* HE-data1 */ 928 ppdu_info->rx_status.he_data1 |= 929 QDF_MON_STATUS_HE_MCS_KNOWN | 930 QDF_MON_STATUS_HE_DCM_KNOWN | 931 QDF_MON_STATUS_HE_CODING_KNOWN; 932 933 /* HE-data2 */ 934 ppdu_info->rx_status.he_data2 |= 935 QDF_MON_STATUS_TXBF_KNOWN; 936 937 /* HE-data3 */ 938 value = HAL_RX_GET(he_sig_b2_ofdma_info, 939 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 940 ppdu_info->rx_status.mcs = value; 941 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 942 ppdu_info->rx_status.he_data3 |= value; 943 944 value = HAL_RX_GET(he_sig_b2_ofdma_info, 945 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 946 he_dcm = value; 947 value = value << QDF_MON_STATUS_DCM_SHIFT; 948 ppdu_info->rx_status.he_data3 |= value; 949 950 value = HAL_RX_GET(he_sig_b2_ofdma_info, 951 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 952 value = value << QDF_MON_STATUS_CODING_SHIFT; 953 ppdu_info->rx_status.he_data3 |= value; 954 955 /* HE-data4 */ 956 value = HAL_RX_GET(he_sig_b2_ofdma_info, 957 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 958 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 959 ppdu_info->rx_status.he_data4 |= value; 960 961 /* HE-data5 */ 962 value = HAL_RX_GET(he_sig_b2_ofdma_info, 963 HE_SIG_B2_OFDMA_INFO_0, TXBF); 964 value = value << QDF_MON_STATUS_TXBF_SHIFT; 965 ppdu_info->rx_status.he_data5 |= value; 966 967 /* HE-data6 */ 968 value = HAL_RX_GET(he_sig_b2_ofdma_info, 969 HE_SIG_B2_OFDMA_INFO_0, NSTS); 970 /* value n indicates n+1 spatial streams */ 971 value++; 972 ppdu_info->rx_status.nss = value; 973 ppdu_info->rx_status.he_data6 |= value; 974 975 break; 976 } 977 case WIFIPHYRX_RSSI_LEGACY_E: 978 { 979 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 980 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_3, 981 RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS); 982 983 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 984 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 985 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 986 ppdu_info->rx_status.he_re = 0; 987 988 ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv, 989 PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE); 990 991 value = HAL_RX_GET(rssi_info_tlv, 992 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 993 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 994 "RSSI_PRI20_CHAIN0: %d\n", value); 995 996 value = HAL_RX_GET(rssi_info_tlv, 997 RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0); 998 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 999 "RSSI_EXT20_CHAIN0: %d\n", value); 1000 1001 value = HAL_RX_GET(rssi_info_tlv, 1002 RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0); 1003 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1004 "RSSI_EXT40_LOW20_CHAIN0: %d\n", value); 1005 1006 value = HAL_RX_GET(rssi_info_tlv, 1007 RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0); 1008 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1009 "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value); 1010 1011 value = HAL_RX_GET(rssi_info_tlv, 1012 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0); 1013 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1014 "RSSI_EXT80_LOW20_CHAIN0: %d\n", value); 1015 1016 value = HAL_RX_GET(rssi_info_tlv, 1017 RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0); 1018 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1019 "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value); 1020 1021 value = HAL_RX_GET(rssi_info_tlv, 1022 RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0); 1023 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1024 "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value); 1025 1026 value = HAL_RX_GET(rssi_info_tlv, 1027 RECEIVE_RSSI_INFO_1, 1028 RSSI_EXT80_HIGH20_CHAIN0); 1029 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1030 "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value); 1031 break; 1032 } 1033 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1034 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1035 ppdu_info); 1036 break; 1037 case WIFIRX_HEADER_E: 1038 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1039 ppdu_info->msdu_info.payload_len = tlv_len; 1040 break; 1041 case WIFIRX_MPDU_START_E: 1042 { 1043 uint8_t *rx_mpdu_start = 1044 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1045 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1046 uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1047 PHY_PPDU_ID); 1048 uint8_t filter_category = 0; 1049 1050 ppdu_info->nac_info.fc_valid = 1051 HAL_RX_GET(rx_mpdu_start, 1052 RX_MPDU_INFO_2, 1053 MPDU_FRAME_CONTROL_VALID); 1054 1055 ppdu_info->nac_info.to_ds_flag = 1056 HAL_RX_GET(rx_mpdu_start, 1057 RX_MPDU_INFO_2, 1058 TO_DS); 1059 1060 ppdu_info->nac_info.mac_addr2_valid = 1061 HAL_RX_GET(rx_mpdu_start, 1062 RX_MPDU_INFO_2, 1063 MAC_ADDR_AD2_VALID); 1064 1065 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1066 HAL_RX_GET(rx_mpdu_start, 1067 RX_MPDU_INFO_16, 1068 MAC_ADDR_AD2_15_0); 1069 1070 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1071 HAL_RX_GET(rx_mpdu_start, 1072 RX_MPDU_INFO_17, 1073 MAC_ADDR_AD2_47_16); 1074 1075 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1076 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1077 ppdu_info->rx_status.ppdu_len = 1078 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1079 MPDU_LENGTH); 1080 } else { 1081 ppdu_info->rx_status.ppdu_len += 1082 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1083 MPDU_LENGTH); 1084 } 1085 1086 filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, 1087 RXPCU_MPDU_FILTER_IN_CATEGORY); 1088 if (filter_category == 1) 1089 ppdu_info->rx_status.monitor_direct_used = 1; 1090 break; 1091 } 1092 case 0: 1093 return HAL_TLV_STATUS_PPDU_DONE; 1094 1095 default: 1096 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1097 unhandled = false; 1098 else 1099 unhandled = true; 1100 break; 1101 } 1102 1103 if (!unhandled) 1104 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1105 "%s TLV type: %d, TLV len:%d %s", 1106 __func__, tlv_tag, tlv_len, 1107 unhandled == true ? "unhandled" : ""); 1108 1109 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1110 rx_tlv, tlv_len); 1111 1112 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1113 } 1114 /** 1115 * hal_reo_status_get_header_generic - Process reo desc info 1116 * @d - Pointer to reo descriptior 1117 * @b - tlv type info 1118 * @h1 - Pointer to hal_reo_status_header where info to be stored 1119 * 1120 * Return - none. 1121 * 1122 */ 1123 static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) 1124 { 1125 1126 uint32_t val1 = 0; 1127 struct hal_reo_status_header *h = 1128 (struct hal_reo_status_header *)h1; 1129 1130 switch (b) { 1131 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1132 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1133 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1134 break; 1135 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1136 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1137 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1138 break; 1139 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1140 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1141 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1142 break; 1143 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1144 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1145 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1146 break; 1147 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1148 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1149 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1150 break; 1151 case HAL_REO_DESC_THRES_STATUS_TLV: 1152 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1153 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1154 break; 1155 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1156 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1157 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1158 break; 1159 default: 1160 pr_err("ERROR: Unknown tlv\n"); 1161 break; 1162 } 1163 h->cmd_num = 1164 HAL_GET_FIELD( 1165 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1166 val1); 1167 h->exec_time = 1168 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1169 CMD_EXECUTION_TIME, val1); 1170 h->status = 1171 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1172 REO_CMD_EXECUTION_STATUS, val1); 1173 switch (b) { 1174 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1175 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1176 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1177 break; 1178 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1179 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1180 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1181 break; 1182 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1183 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1184 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1185 break; 1186 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1187 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1188 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1189 break; 1190 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1191 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1192 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1193 break; 1194 case HAL_REO_DESC_THRES_STATUS_TLV: 1195 val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1196 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1197 break; 1198 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1199 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1200 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1201 break; 1202 default: 1203 pr_err("ERROR: Unknown tlv\n"); 1204 break; 1205 } 1206 h->tstamp = 1207 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1208 } 1209 1210 /** 1211 * hal_reo_setup - Initialize HW REO block 1212 * 1213 * @hal_soc: Opaque HAL SOC handle 1214 * @reo_params: parameters needed by HAL for REO config 1215 */ 1216 static void hal_reo_setup_generic(void *hal_soc, 1217 void *reoparams) 1218 { 1219 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1220 uint32_t reg_val; 1221 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1222 1223 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1224 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1225 1226 reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | 1227 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | 1228 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); 1229 1230 reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, 1231 FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | 1232 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | 1233 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); 1234 1235 HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1236 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 1237 1238 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1239 1240 /* TODO: Setup destination ring mapping if enabled */ 1241 1242 /* TODO: Error destination ring setting is left to default. 1243 * Default setting is to send all errors to release ring. 1244 */ 1245 1246 HAL_REG_WRITE(soc, 1247 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1248 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1249 HAL_DEFAULT_REO_TIMEOUT_MS * 1000); 1250 1251 HAL_REG_WRITE(soc, 1252 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1253 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1254 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1255 1256 HAL_REG_WRITE(soc, 1257 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1258 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1259 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1260 1261 HAL_REG_WRITE(soc, 1262 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1263 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1264 (HAL_DEFAULT_REO_TIMEOUT_MS * 1000)); 1265 1266 /* 1267 * When hash based routing is enabled, routing of the rx packet 1268 * is done based on the following value: 1 _ _ _ _ The last 4 1269 * bits are based on hash[3:0]. This means the possible values 1270 * are 0x10 to 0x1f. This value is used to look-up the 1271 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1272 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1273 * registers need to be configured to set-up the 16 entries to 1274 * map the hash values to a ring number. There are 3 bits per 1275 * hash entry – which are mapped as follows: 1276 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1277 * 7: NOT_USED. 1278 */ 1279 if (reo_params->rx_hash_enabled) { 1280 HAL_REG_WRITE(soc, 1281 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1282 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1283 reo_params->remap1); 1284 1285 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1286 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), 1287 HAL_REG_READ(soc, 1288 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1289 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1290 1291 HAL_REG_WRITE(soc, 1292 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1293 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1294 reo_params->remap2); 1295 1296 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1297 FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), 1298 HAL_REG_READ(soc, 1299 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1300 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1301 } 1302 1303 1304 /* TODO: Check if the following registers shoould be setup by host: 1305 * AGING_CONTROL 1306 * HIGH_MEMORY_THRESHOLD 1307 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1308 * GLOBAL_LINK_DESC_COUNT_CTRL 1309 */ 1310 } 1311 1312 /** 1313 * hal_srng_src_hw_init - Private function to initialize SRNG 1314 * source ring HW 1315 * @hal_soc: HAL SOC handle 1316 * @srng: SRNG ring pointer 1317 */ 1318 static inline void hal_srng_src_hw_init_generic(void *halsoc, 1319 struct hal_srng *srng) 1320 { 1321 struct hal_soc *hal = (struct hal_soc *)halsoc; 1322 uint32_t reg_val = 0; 1323 uint64_t tp_addr = 0; 1324 1325 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1326 1327 if (srng->flags & HAL_SRNG_MSI_INTR) { 1328 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1329 srng->msi_addr & 0xffffffff); 1330 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1331 (uint64_t)(srng->msi_addr) >> 32) | 1332 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1333 MSI1_ENABLE), 1); 1334 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1335 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1336 } 1337 1338 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1339 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1340 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1341 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1342 srng->entry_size * srng->num_entries); 1343 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1344 1345 #if defined(WCSS_VERSION) && \ 1346 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 1347 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 1348 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1349 #else 1350 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) | 1351 SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1352 #endif 1353 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1354 1355 /** 1356 * Interrupt setup: 1357 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1358 * if level mode is required 1359 */ 1360 reg_val = 0; 1361 1362 /* 1363 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1364 * programmed in terms of 1us resolution instead of 8us resolution as 1365 * given in MLD. 1366 */ 1367 if (srng->intr_timer_thres_us) { 1368 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1369 INTERRUPT_TIMER_THRESHOLD), 1370 srng->intr_timer_thres_us); 1371 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1372 } 1373 1374 if (srng->intr_batch_cntr_thres_entries) { 1375 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1376 BATCH_COUNTER_THRESHOLD), 1377 srng->intr_batch_cntr_thres_entries * 1378 srng->entry_size); 1379 } 1380 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1381 1382 reg_val = 0; 1383 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1384 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1385 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1386 } 1387 1388 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1389 1390 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1391 * remain 0 to avoid some WBM stability issues. Remote head/tail 1392 * pointers are not required since this ring is completely managed 1393 * by WBM HW 1394 */ 1395 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1396 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1397 ((unsigned long)(srng->u.src_ring.tp_addr) - 1398 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1399 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1400 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1401 } 1402 1403 /* Initilaize head and tail pointers to indicate ring is empty */ 1404 SRNG_SRC_REG_WRITE(srng, HP, 0); 1405 SRNG_SRC_REG_WRITE(srng, TP, 0); 1406 *(srng->u.src_ring.tp_addr) = 0; 1407 1408 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1409 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1410 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1411 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1412 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1413 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1414 1415 /* Loop count is not used for SRC rings */ 1416 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1417 1418 /* 1419 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1420 * todo: update fw_api and replace with above line 1421 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1422 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1423 */ 1424 reg_val |= 0x40; 1425 1426 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1427 1428 } 1429 1430 /** 1431 * hal_srng_dst_hw_init - Private function to initialize SRNG 1432 * destination ring HW 1433 * @hal_soc: HAL SOC handle 1434 * @srng: SRNG ring pointer 1435 */ 1436 static inline void hal_srng_dst_hw_init_generic(void *halsoc, 1437 struct hal_srng *srng) 1438 { 1439 struct hal_soc *hal = (struct hal_soc *)halsoc; 1440 uint32_t reg_val = 0; 1441 uint64_t hp_addr = 0; 1442 1443 HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); 1444 1445 if (srng->flags & HAL_SRNG_MSI_INTR) { 1446 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1447 srng->msi_addr & 0xffffffff); 1448 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1449 (uint64_t)(srng->msi_addr) >> 32) | 1450 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1451 MSI1_ENABLE), 1); 1452 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1453 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1454 } 1455 1456 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1457 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1458 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1459 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1460 srng->entry_size * srng->num_entries); 1461 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1462 1463 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1464 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1465 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1466 1467 1468 /** 1469 * Interrupt setup: 1470 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1471 * if level mode is required 1472 */ 1473 reg_val = 0; 1474 if (srng->intr_timer_thres_us) { 1475 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1476 INTERRUPT_TIMER_THRESHOLD), 1477 srng->intr_timer_thres_us >> 3); 1478 } 1479 1480 if (srng->intr_batch_cntr_thres_entries) { 1481 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1482 BATCH_COUNTER_THRESHOLD), 1483 srng->intr_batch_cntr_thres_entries * 1484 srng->entry_size); 1485 } 1486 1487 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1488 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1489 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1490 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1491 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1492 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1493 1494 /* Initilaize head and tail pointers to indicate ring is empty */ 1495 SRNG_DST_REG_WRITE(srng, HP, 0); 1496 SRNG_DST_REG_WRITE(srng, TP, 0); 1497 *(srng->u.dst_ring.hp_addr) = 0; 1498 1499 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1500 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1501 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1502 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1503 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1504 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1505 1506 /* 1507 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1508 * todo: update fw_api and replace with above line 1509 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1510 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1511 */ 1512 reg_val |= 0x40; 1513 1514 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1515 1516 } 1517 #endif 1518