1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 23 /** 24 * hal_tx_comp_get_status() - TQM Release reason 25 * @hal_desc: completion ring Tx status 26 * 27 * This function will parse the WBM completion descriptor and populate in 28 * HAL structure 29 * 30 * Return: none 31 */ 32 static inline 33 void hal_tx_comp_get_status_generic(void *desc, 34 void *ts1, 35 struct hal_soc *hal) 36 { 37 uint8_t rate_stats_valid = 0; 38 uint32_t rate_stats = 0; 39 struct hal_tx_completion_status *ts = 40 (struct hal_tx_completion_status *)ts1; 41 42 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 43 TQM_STATUS_NUMBER); 44 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 45 ACK_FRAME_RSSI); 46 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 47 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 48 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 49 MSDU_PART_OF_AMSDU); 50 51 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 52 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 53 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 54 TRANSMIT_COUNT); 55 56 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 57 TX_RATE_STATS); 58 59 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 60 TX_RATE_STATS_INFO_VALID, rate_stats); 61 62 ts->valid = rate_stats_valid; 63 64 if (rate_stats_valid) { 65 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 66 rate_stats); 67 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 68 TRANSMIT_PKT_TYPE, rate_stats); 69 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 70 TRANSMIT_STBC, rate_stats); 71 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 72 rate_stats); 73 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 74 rate_stats); 75 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 76 rate_stats); 77 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 78 rate_stats); 79 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 80 rate_stats); 81 } 82 83 ts->release_src = hal_tx_comp_get_buffer_source(desc); 84 ts->status = hal_tx_comp_get_release_reason( 85 desc, 86 hal_soc_to_hal_soc_handle(hal)); 87 88 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 89 TX_RATE_STATS_INFO_TX_RATE_STATS); 90 } 91 92 /** 93 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 94 * @desc: Handle to Tx Descriptor 95 * @paddr: Physical Address 96 * @pool_id: Return Buffer Manager ID 97 * @desc_id: Descriptor ID 98 * @type: 0 - Address points to a MSDU buffer 99 * 1 - Address points to MSDU extension descriptor 100 * 101 * Return: void 102 */ 103 static inline void hal_tx_desc_set_buf_addr_generic(void *desc, 104 dma_addr_t paddr, uint8_t pool_id, 105 uint32_t desc_id, uint8_t type) 106 { 107 /* Set buffer_addr_info.buffer_addr_31_0 */ 108 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 109 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 110 111 /* Set buffer_addr_info.buffer_addr_39_32 */ 112 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 113 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 114 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 115 (((uint64_t) paddr) >> 32)); 116 117 /* Set buffer_addr_info.return_buffer_manager = pool id */ 118 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 119 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 120 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 121 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 122 123 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 124 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 125 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 126 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 127 128 /* Set Buffer or Ext Descriptor Type */ 129 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 130 BUF_OR_EXT_DESC_TYPE) |= 131 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 132 } 133 134 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 135 /** 136 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 137 * tlv_tag: Taf of the TLVs 138 * rx_tlv: the pointer to the TLVs 139 * @ppdu_info: pointer to ppdu_info 140 * 141 * Return: true if the tlv is handled, false if not 142 */ 143 static inline bool 144 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 145 struct hal_rx_ppdu_info *ppdu_info) 146 { 147 uint32_t value; 148 149 switch (tlv_tag) { 150 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 151 { 152 uint8_t *he_sig_a_mu_ul_info = 153 (uint8_t *)rx_tlv + 154 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 155 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 156 ppdu_info->rx_status.he_flags = 1; 157 158 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 159 FORMAT_INDICATION); 160 if (value == 0) { 161 ppdu_info->rx_status.he_data1 = 162 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 163 } else { 164 ppdu_info->rx_status.he_data1 = 165 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 166 } 167 168 /* data1 */ 169 ppdu_info->rx_status.he_data1 |= 170 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 171 QDF_MON_STATUS_HE_DL_UL_KNOWN | 172 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 173 174 /* data2 */ 175 ppdu_info->rx_status.he_data2 |= 176 QDF_MON_STATUS_TXOP_KNOWN; 177 178 /*data3*/ 179 value = HAL_RX_GET(he_sig_a_mu_ul_info, 180 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 181 ppdu_info->rx_status.he_data3 = value; 182 /* 1 for UL and 0 for DL */ 183 value = 1; 184 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 185 ppdu_info->rx_status.he_data3 |= value; 186 187 /*data4*/ 188 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 189 SPATIAL_REUSE); 190 ppdu_info->rx_status.he_data4 = value; 191 192 /*data5*/ 193 value = HAL_RX_GET(he_sig_a_mu_ul_info, 194 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 195 ppdu_info->rx_status.he_data5 = value; 196 ppdu_info->rx_status.bw = value; 197 198 /*data6*/ 199 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 200 TXOP_DURATION); 201 value = value << QDF_MON_STATUS_TXOP_SHIFT; 202 ppdu_info->rx_status.he_data6 |= value; 203 return true; 204 } 205 default: 206 return false; 207 } 208 } 209 #else 210 static inline bool 211 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 212 struct hal_rx_ppdu_info *ppdu_info) 213 { 214 return false; 215 } 216 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 217 218 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 219 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 220 221 static inline void 222 hal_rx_handle_mu_ul_info( 223 void *rx_tlv, 224 struct mon_rx_user_status *mon_rx_user_status) 225 { 226 mon_rx_user_status->mu_ul_user_v0_word0 = 227 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 228 SW_RESPONSE_REFERENCE_PTR); 229 230 mon_rx_user_status->mu_ul_user_v0_word1 = 231 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 232 SW_RESPONSE_REFERENCE_PTR_EXT); 233 } 234 235 static inline void 236 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 237 struct mon_rx_user_status *mon_rx_user_status) 238 { 239 uint32_t mpdu_ok_byte_count; 240 uint32_t mpdu_err_byte_count; 241 242 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 243 RX_PPDU_END_USER_STATS_17, 244 MPDU_OK_BYTE_COUNT); 245 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 246 RX_PPDU_END_USER_STATS_19, 247 MPDU_ERR_BYTE_COUNT); 248 249 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 250 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 251 } 252 #else 253 static inline void 254 hal_rx_handle_mu_ul_info(void *rx_tlv, 255 struct mon_rx_user_status *mon_rx_user_status) 256 { 257 } 258 259 static inline void 260 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 261 struct mon_rx_user_status *mon_rx_user_status) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = 264 (struct hal_rx_ppdu_info *)ppduinfo; 265 266 /* HKV1: doesn't support mpdu byte count */ 267 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 268 mon_rx_user_status->mpdu_err_byte_count = 0; 269 } 270 #endif 271 272 static inline void 273 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, 274 struct mon_rx_user_status *mon_rx_user_status) 275 { 276 struct hal_rx_ppdu_info *ppdu_info = 277 (struct hal_rx_ppdu_info *)ppduinfo; 278 279 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 280 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 281 mon_rx_user_status->tcp_msdu_count = 282 ppdu_info->rx_status.tcp_msdu_count; 283 mon_rx_user_status->udp_msdu_count = 284 ppdu_info->rx_status.udp_msdu_count; 285 mon_rx_user_status->other_msdu_count = 286 ppdu_info->rx_status.other_msdu_count; 287 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 288 mon_rx_user_status->frame_control_info_valid = 289 ppdu_info->rx_status.frame_control_info_valid; 290 mon_rx_user_status->data_sequence_control_info_valid = 291 ppdu_info->rx_status.data_sequence_control_info_valid; 292 mon_rx_user_status->first_data_seq_ctrl = 293 ppdu_info->rx_status.first_data_seq_ctrl; 294 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 295 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 296 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 297 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 298 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 299 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 300 301 mon_rx_user_status->mpdu_cnt_fcs_ok = 302 ppdu_info->com_info.mpdu_cnt_fcs_ok; 303 mon_rx_user_status->mpdu_cnt_fcs_err = 304 ppdu_info->com_info.mpdu_cnt_fcs_err; 305 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 306 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 307 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 308 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 309 310 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 311 } 312 313 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 314 ppdu_info, rssi_info_tlv) \ 315 { \ 316 ppdu_info->rx_status.rssi_chain[chain][0] = \ 317 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 318 RSSI_PRI20_CHAIN##chain); \ 319 ppdu_info->rx_status.rssi_chain[chain][1] = \ 320 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 321 RSSI_EXT20_CHAIN##chain); \ 322 ppdu_info->rx_status.rssi_chain[chain][2] = \ 323 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 324 RSSI_EXT40_LOW20_CHAIN##chain); \ 325 ppdu_info->rx_status.rssi_chain[chain][3] = \ 326 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 327 RSSI_EXT40_HIGH20_CHAIN##chain); \ 328 ppdu_info->rx_status.rssi_chain[chain][4] = \ 329 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 330 RSSI_EXT80_LOW20_CHAIN##chain); \ 331 ppdu_info->rx_status.rssi_chain[chain][5] = \ 332 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 333 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 334 ppdu_info->rx_status.rssi_chain[chain][6] = \ 335 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 336 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 337 ppdu_info->rx_status.rssi_chain[chain][7] = \ 338 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 339 RSSI_EXT80_HIGH20_CHAIN##chain); \ 340 } \ 341 342 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 343 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 344 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 345 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 346 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 347 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 348 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 349 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 350 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 351 352 static inline uint32_t 353 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 354 uint8_t *rssi_info_tlv) 355 { 356 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 357 return 0; 358 } 359 360 /** 361 * hal_rx_status_get_tlv_info() - process receive info TLV 362 * @rx_tlv_hdr: pointer to TLV header 363 * @ppdu_info: pointer to ppdu_info 364 * 365 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 366 */ 367 static inline uint32_t 368 hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, 369 hal_soc_handle_t hal_soc_hdl, 370 qdf_nbuf_t nbuf) 371 { 372 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 373 uint32_t tlv_tag, user_id, tlv_len, value; 374 uint8_t group_id = 0; 375 uint8_t he_dcm = 0; 376 uint8_t he_stbc = 0; 377 uint16_t he_gi = 0; 378 uint16_t he_ltf = 0; 379 void *rx_tlv; 380 bool unhandled = false; 381 struct mon_rx_user_status *mon_rx_user_status; 382 struct hal_rx_ppdu_info *ppdu_info = 383 (struct hal_rx_ppdu_info *)ppduinfo; 384 385 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 386 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 387 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 388 389 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 390 391 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 392 rx_tlv, tlv_len); 393 394 switch (tlv_tag) { 395 396 case WIFIRX_PPDU_START_E: 397 { 398 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 399 400 ppdu_info->com_info.ppdu_id = 401 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 402 PHY_PPDU_ID); 403 /* channel number is set in PHY meta data */ 404 ppdu_info->rx_status.chan_num = 405 HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 406 SW_PHY_META_DATA); 407 ppdu_info->com_info.ppdu_timestamp = 408 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 409 PPDU_START_TIMESTAMP); 410 ppdu_info->rx_status.ppdu_timestamp = 411 ppdu_info->com_info.ppdu_timestamp; 412 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 413 414 /* If last ppdu_id doesn't match new ppdu_id, 415 * 1. reset mpdu_cnt 416 * 2. update last_ppdu_id with new 417 * 3. reset mpdu fcs bitmap 418 */ 419 if (com_info->ppdu_id != com_info->last_ppdu_id) { 420 com_info->mpdu_cnt = 0; 421 com_info->last_ppdu_id = 422 com_info->ppdu_id; 423 com_info->num_users = 0; 424 qdf_mem_zero(&com_info->mpdu_fcs_ok_bitmap, 425 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 426 sizeof(com_info->mpdu_fcs_ok_bitmap[0])); 427 } 428 break; 429 } 430 431 case WIFIRX_PPDU_START_USER_INFO_E: 432 break; 433 434 case WIFIRX_PPDU_END_E: 435 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 436 "[%s][%d] ppdu_end_e len=%d", 437 __func__, __LINE__, tlv_len); 438 /* This is followed by sub-TLVs of PPDU_END */ 439 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 440 break; 441 442 case WIFIPHYRX_PKT_END_E: 443 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 444 break; 445 446 case WIFIRXPCU_PPDU_END_INFO_E: 447 ppdu_info->rx_status.rx_antenna = 448 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 449 ppdu_info->rx_status.tsft = 450 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 451 WB_TIMESTAMP_UPPER_32); 452 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 453 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 454 WB_TIMESTAMP_LOWER_32); 455 ppdu_info->rx_status.duration = 456 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 457 RX_PPDU_DURATION); 458 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 459 break; 460 461 /* 462 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 463 * for MU, based on num users we see this tlv that many times. 464 */ 465 case WIFIRX_PPDU_END_USER_STATS_E: 466 { 467 unsigned long tid = 0; 468 uint16_t seq = 0; 469 470 ppdu_info->rx_status.ast_index = 471 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 472 AST_INDEX); 473 474 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 475 RECEIVED_QOS_DATA_TID_BITMAP); 476 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); 477 478 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 479 ppdu_info->rx_status.tid = HAL_TID_INVALID; 480 481 ppdu_info->rx_status.tcp_msdu_count = 482 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 483 TCP_MSDU_COUNT) + 484 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 485 TCP_ACK_MSDU_COUNT); 486 ppdu_info->rx_status.udp_msdu_count = 487 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 488 UDP_MSDU_COUNT); 489 ppdu_info->rx_status.other_msdu_count = 490 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 491 OTHER_MSDU_COUNT); 492 493 if (ppdu_info->sw_frame_group_id 494 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 495 ppdu_info->rx_status.frame_control_info_valid = 496 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 497 FRAME_CONTROL_INFO_VALID); 498 499 if (ppdu_info->rx_status.frame_control_info_valid) 500 ppdu_info->rx_status.frame_control = 501 HAL_RX_GET(rx_tlv, 502 RX_PPDU_END_USER_STATS_4, 503 FRAME_CONTROL_FIELD); 504 } 505 506 ppdu_info->rx_status.data_sequence_control_info_valid = 507 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 508 DATA_SEQUENCE_CONTROL_INFO_VALID); 509 510 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 511 FIRST_DATA_SEQ_CTRL); 512 if (ppdu_info->rx_status.data_sequence_control_info_valid) 513 ppdu_info->rx_status.first_data_seq_ctrl = seq; 514 515 ppdu_info->rx_status.preamble_type = 516 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 517 HT_CONTROL_FIELD_PKT_TYPE); 518 switch (ppdu_info->rx_status.preamble_type) { 519 case HAL_RX_PKT_TYPE_11N: 520 ppdu_info->rx_status.ht_flags = 1; 521 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 522 break; 523 case HAL_RX_PKT_TYPE_11AC: 524 ppdu_info->rx_status.vht_flags = 1; 525 break; 526 case HAL_RX_PKT_TYPE_11AX: 527 ppdu_info->rx_status.he_flags = 1; 528 break; 529 default: 530 break; 531 } 532 533 ppdu_info->com_info.mpdu_cnt_fcs_ok = 534 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 535 MPDU_CNT_FCS_OK); 536 ppdu_info->com_info.mpdu_cnt_fcs_err = 537 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 538 MPDU_CNT_FCS_ERR); 539 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 540 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 541 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 542 else 543 ppdu_info->rx_status.rs_flags &= 544 (~IEEE80211_AMPDU_FLAG); 545 546 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 547 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 548 FCS_OK_BITMAP_31_0); 549 550 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 551 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 552 FCS_OK_BITMAP_63_32); 553 554 if (user_id < HAL_MAX_UL_MU_USERS) { 555 mon_rx_user_status = 556 &ppdu_info->rx_user_status[user_id]; 557 558 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 559 560 ppdu_info->com_info.num_users++; 561 562 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 563 mon_rx_user_status); 564 } 565 break; 566 } 567 568 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 569 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 570 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 571 FCS_OK_BITMAP_95_64); 572 573 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 574 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 575 FCS_OK_BITMAP_127_96); 576 577 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 578 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 579 FCS_OK_BITMAP_159_128); 580 581 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 582 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 583 FCS_OK_BITMAP_191_160); 584 585 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 586 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 587 FCS_OK_BITMAP_223_192); 588 589 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 590 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 591 FCS_OK_BITMAP_255_224); 592 break; 593 594 case WIFIRX_PPDU_END_STATUS_DONE_E: 595 return HAL_TLV_STATUS_PPDU_DONE; 596 597 case WIFIDUMMY_E: 598 return HAL_TLV_STATUS_BUF_DONE; 599 600 case WIFIPHYRX_HT_SIG_E: 601 { 602 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 603 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 604 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 605 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 606 FEC_CODING); 607 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 608 1 : 0; 609 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 610 HT_SIG_INFO_0, MCS); 611 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 612 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 613 HT_SIG_INFO_0, CBW); 614 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 615 HT_SIG_INFO_1, SHORT_GI); 616 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 617 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 618 HT_SIG_SU_NSS_SHIFT) + 1; 619 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 620 break; 621 } 622 623 case WIFIPHYRX_L_SIG_B_E: 624 { 625 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 626 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 627 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 628 629 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 630 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 631 switch (value) { 632 case 1: 633 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 634 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 635 break; 636 case 2: 637 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 638 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 639 break; 640 case 3: 641 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 642 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 643 break; 644 case 4: 645 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 646 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 647 break; 648 case 5: 649 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 650 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 651 break; 652 case 6: 653 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 654 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 655 break; 656 case 7: 657 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 658 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 659 break; 660 default: 661 break; 662 } 663 ppdu_info->rx_status.cck_flag = 1; 664 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 665 break; 666 } 667 668 case WIFIPHYRX_L_SIG_A_E: 669 { 670 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 671 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 672 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 673 674 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 675 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 676 switch (value) { 677 case 8: 678 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 679 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 680 break; 681 case 9: 682 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 683 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 684 break; 685 case 10: 686 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 687 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 688 break; 689 case 11: 690 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 691 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 692 break; 693 case 12: 694 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 695 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 696 break; 697 case 13: 698 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 699 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 700 break; 701 case 14: 702 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 703 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 704 break; 705 case 15: 706 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 707 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 708 break; 709 default: 710 break; 711 } 712 ppdu_info->rx_status.ofdm_flag = 1; 713 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 714 break; 715 } 716 717 case WIFIPHYRX_VHT_SIG_A_E: 718 { 719 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 720 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 721 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 722 723 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 724 SU_MU_CODING); 725 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 726 1 : 0; 727 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); 728 ppdu_info->rx_status.vht_flag_values5 = group_id; 729 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 730 VHT_SIG_A_INFO_1, MCS); 731 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 732 VHT_SIG_A_INFO_1, GI_SETTING); 733 734 switch (hal->target_type) { 735 case TARGET_TYPE_QCA8074: 736 case TARGET_TYPE_QCA8074V2: 737 case TARGET_TYPE_QCA6018: 738 case TARGET_TYPE_QCN9000: 739 #ifdef QCA_WIFI_QCA6390 740 case TARGET_TYPE_QCA6390: 741 #endif 742 ppdu_info->rx_status.is_stbc = 743 HAL_RX_GET(vht_sig_a_info, 744 VHT_SIG_A_INFO_0, STBC); 745 value = HAL_RX_GET(vht_sig_a_info, 746 VHT_SIG_A_INFO_0, N_STS); 747 value = value & VHT_SIG_SU_NSS_MASK; 748 if (ppdu_info->rx_status.is_stbc && (value > 0)) 749 value = ((value + 1) >> 1) - 1; 750 ppdu_info->rx_status.nss = 751 ((value & VHT_SIG_SU_NSS_MASK) + 1); 752 753 break; 754 case TARGET_TYPE_QCA6290: 755 #if !defined(QCA_WIFI_QCA6290_11AX) 756 ppdu_info->rx_status.is_stbc = 757 HAL_RX_GET(vht_sig_a_info, 758 VHT_SIG_A_INFO_0, STBC); 759 value = HAL_RX_GET(vht_sig_a_info, 760 VHT_SIG_A_INFO_0, N_STS); 761 value = value & VHT_SIG_SU_NSS_MASK; 762 if (ppdu_info->rx_status.is_stbc && (value > 0)) 763 value = ((value + 1) >> 1) - 1; 764 ppdu_info->rx_status.nss = 765 ((value & VHT_SIG_SU_NSS_MASK) + 1); 766 #else 767 ppdu_info->rx_status.nss = 0; 768 #endif 769 break; 770 case TARGET_TYPE_QCA6490: 771 ppdu_info->rx_status.nss = 0; 772 break; 773 default: 774 break; 775 } 776 ppdu_info->rx_status.vht_flag_values3[0] = 777 (((ppdu_info->rx_status.mcs) << 4) 778 | ppdu_info->rx_status.nss); 779 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 780 VHT_SIG_A_INFO_0, BANDWIDTH); 781 ppdu_info->rx_status.vht_flag_values2 = 782 ppdu_info->rx_status.bw; 783 ppdu_info->rx_status.vht_flag_values4 = 784 HAL_RX_GET(vht_sig_a_info, 785 VHT_SIG_A_INFO_1, SU_MU_CODING); 786 787 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 788 VHT_SIG_A_INFO_1, BEAMFORMED); 789 if (group_id == 0 || group_id == 63) 790 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 791 else 792 ppdu_info->rx_status.reception_type = 793 HAL_RX_TYPE_MU_MIMO; 794 795 break; 796 } 797 case WIFIPHYRX_HE_SIG_A_SU_E: 798 { 799 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 800 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 801 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 802 ppdu_info->rx_status.he_flags = 1; 803 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 804 FORMAT_INDICATION); 805 if (value == 0) { 806 ppdu_info->rx_status.he_data1 = 807 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 808 } else { 809 ppdu_info->rx_status.he_data1 = 810 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 811 } 812 813 /* data1 */ 814 ppdu_info->rx_status.he_data1 |= 815 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 816 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 817 QDF_MON_STATUS_HE_DL_UL_KNOWN | 818 QDF_MON_STATUS_HE_MCS_KNOWN | 819 QDF_MON_STATUS_HE_DCM_KNOWN | 820 QDF_MON_STATUS_HE_CODING_KNOWN | 821 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 822 QDF_MON_STATUS_HE_STBC_KNOWN | 823 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 824 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 825 826 /* data2 */ 827 ppdu_info->rx_status.he_data2 = 828 QDF_MON_STATUS_HE_GI_KNOWN; 829 ppdu_info->rx_status.he_data2 |= 830 QDF_MON_STATUS_TXBF_KNOWN | 831 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 832 QDF_MON_STATUS_TXOP_KNOWN | 833 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 834 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 835 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 836 837 /* data3 */ 838 value = HAL_RX_GET(he_sig_a_su_info, 839 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 840 ppdu_info->rx_status.he_data3 = value; 841 value = HAL_RX_GET(he_sig_a_su_info, 842 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 843 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 844 ppdu_info->rx_status.he_data3 |= value; 845 value = HAL_RX_GET(he_sig_a_su_info, 846 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 847 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 848 ppdu_info->rx_status.he_data3 |= value; 849 850 value = HAL_RX_GET(he_sig_a_su_info, 851 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 852 ppdu_info->rx_status.mcs = value; 853 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 854 ppdu_info->rx_status.he_data3 |= value; 855 856 value = HAL_RX_GET(he_sig_a_su_info, 857 HE_SIG_A_SU_INFO_0, DCM); 858 he_dcm = value; 859 value = value << QDF_MON_STATUS_DCM_SHIFT; 860 ppdu_info->rx_status.he_data3 |= value; 861 value = HAL_RX_GET(he_sig_a_su_info, 862 HE_SIG_A_SU_INFO_1, CODING); 863 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 864 1 : 0; 865 value = value << QDF_MON_STATUS_CODING_SHIFT; 866 ppdu_info->rx_status.he_data3 |= value; 867 value = HAL_RX_GET(he_sig_a_su_info, 868 HE_SIG_A_SU_INFO_1, 869 LDPC_EXTRA_SYMBOL); 870 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 871 ppdu_info->rx_status.he_data3 |= value; 872 value = HAL_RX_GET(he_sig_a_su_info, 873 HE_SIG_A_SU_INFO_1, STBC); 874 he_stbc = value; 875 value = value << QDF_MON_STATUS_STBC_SHIFT; 876 ppdu_info->rx_status.he_data3 |= value; 877 878 /* data4 */ 879 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 880 SPATIAL_REUSE); 881 ppdu_info->rx_status.he_data4 = value; 882 883 /* data5 */ 884 value = HAL_RX_GET(he_sig_a_su_info, 885 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 886 ppdu_info->rx_status.he_data5 = value; 887 ppdu_info->rx_status.bw = value; 888 value = HAL_RX_GET(he_sig_a_su_info, 889 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 890 switch (value) { 891 case 0: 892 he_gi = HE_GI_0_8; 893 he_ltf = HE_LTF_1_X; 894 break; 895 case 1: 896 he_gi = HE_GI_0_8; 897 he_ltf = HE_LTF_2_X; 898 break; 899 case 2: 900 he_gi = HE_GI_1_6; 901 he_ltf = HE_LTF_2_X; 902 break; 903 case 3: 904 if (he_dcm && he_stbc) { 905 he_gi = HE_GI_0_8; 906 he_ltf = HE_LTF_4_X; 907 } else { 908 he_gi = HE_GI_3_2; 909 he_ltf = HE_LTF_4_X; 910 } 911 break; 912 } 913 ppdu_info->rx_status.sgi = he_gi; 914 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 915 ppdu_info->rx_status.he_data5 |= value; 916 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 917 ppdu_info->rx_status.ltf_size = he_ltf; 918 ppdu_info->rx_status.he_data5 |= value; 919 920 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 921 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 922 ppdu_info->rx_status.he_data5 |= value; 923 924 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 925 PACKET_EXTENSION_A_FACTOR); 926 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 927 ppdu_info->rx_status.he_data5 |= value; 928 929 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 930 value = value << QDF_MON_STATUS_TXBF_SHIFT; 931 ppdu_info->rx_status.he_data5 |= value; 932 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 933 PACKET_EXTENSION_PE_DISAMBIGUITY); 934 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 935 ppdu_info->rx_status.he_data5 |= value; 936 937 /* data6 */ 938 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 939 value++; 940 ppdu_info->rx_status.nss = value; 941 ppdu_info->rx_status.he_data6 = value; 942 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 943 DOPPLER_INDICATION); 944 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 945 ppdu_info->rx_status.he_data6 |= value; 946 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 947 TXOP_DURATION); 948 value = value << QDF_MON_STATUS_TXOP_SHIFT; 949 ppdu_info->rx_status.he_data6 |= value; 950 951 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 952 HE_SIG_A_SU_INFO_1, TXBF); 953 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 954 break; 955 } 956 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 957 { 958 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 959 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 960 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 961 962 ppdu_info->rx_status.he_mu_flags = 1; 963 964 /* HE Flags */ 965 /*data1*/ 966 ppdu_info->rx_status.he_data1 = 967 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 968 ppdu_info->rx_status.he_data1 |= 969 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 970 QDF_MON_STATUS_HE_DL_UL_KNOWN | 971 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 972 QDF_MON_STATUS_HE_STBC_KNOWN | 973 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 974 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 975 976 /* data2 */ 977 ppdu_info->rx_status.he_data2 = 978 QDF_MON_STATUS_HE_GI_KNOWN; 979 ppdu_info->rx_status.he_data2 |= 980 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 981 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 982 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 983 QDF_MON_STATUS_TXOP_KNOWN | 984 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 985 986 /*data3*/ 987 value = HAL_RX_GET(he_sig_a_mu_dl_info, 988 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 989 ppdu_info->rx_status.he_data3 = value; 990 991 value = HAL_RX_GET(he_sig_a_mu_dl_info, 992 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 993 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 994 ppdu_info->rx_status.he_data3 |= value; 995 996 value = HAL_RX_GET(he_sig_a_mu_dl_info, 997 HE_SIG_A_MU_DL_INFO_1, 998 LDPC_EXTRA_SYMBOL); 999 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1000 ppdu_info->rx_status.he_data3 |= value; 1001 1002 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1003 HE_SIG_A_MU_DL_INFO_1, STBC); 1004 he_stbc = value; 1005 value = value << QDF_MON_STATUS_STBC_SHIFT; 1006 ppdu_info->rx_status.he_data3 |= value; 1007 1008 /*data4*/ 1009 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1010 SPATIAL_REUSE); 1011 ppdu_info->rx_status.he_data4 = value; 1012 1013 /*data5*/ 1014 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1015 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1016 ppdu_info->rx_status.he_data5 = value; 1017 ppdu_info->rx_status.bw = value; 1018 1019 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1020 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1021 switch (value) { 1022 case 0: 1023 he_gi = HE_GI_0_8; 1024 he_ltf = HE_LTF_4_X; 1025 break; 1026 case 1: 1027 he_gi = HE_GI_0_8; 1028 he_ltf = HE_LTF_2_X; 1029 break; 1030 case 2: 1031 he_gi = HE_GI_1_6; 1032 he_ltf = HE_LTF_2_X; 1033 break; 1034 case 3: 1035 he_gi = HE_GI_3_2; 1036 he_ltf = HE_LTF_4_X; 1037 break; 1038 } 1039 ppdu_info->rx_status.sgi = he_gi; 1040 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1041 ppdu_info->rx_status.he_data5 |= value; 1042 1043 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1044 ppdu_info->rx_status.he_data5 |= value; 1045 1046 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1047 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1048 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1049 ppdu_info->rx_status.he_data5 |= value; 1050 1051 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1052 PACKET_EXTENSION_A_FACTOR); 1053 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1054 ppdu_info->rx_status.he_data5 |= value; 1055 1056 1057 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1058 PACKET_EXTENSION_PE_DISAMBIGUITY); 1059 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1060 ppdu_info->rx_status.he_data5 |= value; 1061 1062 /*data6*/ 1063 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1064 DOPPLER_INDICATION); 1065 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1066 ppdu_info->rx_status.he_data6 |= value; 1067 1068 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1069 TXOP_DURATION); 1070 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1071 ppdu_info->rx_status.he_data6 |= value; 1072 1073 /* HE-MU Flags */ 1074 /* HE-MU-flags1 */ 1075 ppdu_info->rx_status.he_flags1 = 1076 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1077 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1078 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1079 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1080 QDF_MON_STATUS_RU_0_KNOWN; 1081 1082 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1083 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1084 ppdu_info->rx_status.he_flags1 |= value; 1085 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1086 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1087 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1088 ppdu_info->rx_status.he_flags1 |= value; 1089 1090 /* HE-MU-flags2 */ 1091 ppdu_info->rx_status.he_flags2 = 1092 QDF_MON_STATUS_BW_KNOWN; 1093 1094 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1095 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1096 ppdu_info->rx_status.he_flags2 |= value; 1097 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1098 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1099 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1100 ppdu_info->rx_status.he_flags2 |= value; 1101 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1102 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1103 value = value - 1; 1104 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1105 ppdu_info->rx_status.he_flags2 |= value; 1106 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1107 break; 1108 } 1109 case WIFIPHYRX_HE_SIG_B1_MU_E: 1110 { 1111 1112 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1113 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1114 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1115 1116 ppdu_info->rx_status.he_sig_b_common_known |= 1117 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1118 /* TODO: Check on the availability of other fields in 1119 * sig_b_common 1120 */ 1121 1122 value = HAL_RX_GET(he_sig_b1_mu_info, 1123 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1124 ppdu_info->rx_status.he_RU[0] = value; 1125 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1126 break; 1127 } 1128 case WIFIPHYRX_HE_SIG_B2_MU_E: 1129 { 1130 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1131 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1132 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1133 /* 1134 * Not all "HE" fields can be updated from 1135 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1136 * to populate rest of the "HE" fields for MU scenarios. 1137 */ 1138 1139 /* HE-data1 */ 1140 ppdu_info->rx_status.he_data1 |= 1141 QDF_MON_STATUS_HE_MCS_KNOWN | 1142 QDF_MON_STATUS_HE_CODING_KNOWN; 1143 1144 /* HE-data2 */ 1145 1146 /* HE-data3 */ 1147 value = HAL_RX_GET(he_sig_b2_mu_info, 1148 HE_SIG_B2_MU_INFO_0, STA_MCS); 1149 ppdu_info->rx_status.mcs = value; 1150 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1151 ppdu_info->rx_status.he_data3 |= value; 1152 1153 1154 value = HAL_RX_GET(he_sig_b2_mu_info, 1155 HE_SIG_B2_MU_INFO_0, STA_CODING); 1156 value = value << QDF_MON_STATUS_CODING_SHIFT; 1157 ppdu_info->rx_status.he_data3 |= value; 1158 1159 /* HE-data4 */ 1160 value = HAL_RX_GET(he_sig_b2_mu_info, 1161 HE_SIG_B2_MU_INFO_0, STA_ID); 1162 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1163 ppdu_info->rx_status.he_data4 |= value; 1164 1165 /* HE-data5 */ 1166 1167 /* HE-data6 */ 1168 value = HAL_RX_GET(he_sig_b2_mu_info, 1169 HE_SIG_B2_MU_INFO_0, NSTS); 1170 /* value n indicates n+1 spatial streams */ 1171 value++; 1172 ppdu_info->rx_status.nss = value; 1173 ppdu_info->rx_status.he_data6 |= value; 1174 1175 break; 1176 1177 } 1178 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1179 { 1180 uint8_t *he_sig_b2_ofdma_info = 1181 (uint8_t *)rx_tlv + 1182 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1183 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1184 1185 /* 1186 * Not all "HE" fields can be updated from 1187 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1188 * to populate rest of "HE" fields for MU OFDMA scenarios. 1189 */ 1190 1191 /* HE-data1 */ 1192 ppdu_info->rx_status.he_data1 |= 1193 QDF_MON_STATUS_HE_MCS_KNOWN | 1194 QDF_MON_STATUS_HE_DCM_KNOWN | 1195 QDF_MON_STATUS_HE_CODING_KNOWN; 1196 1197 /* HE-data2 */ 1198 ppdu_info->rx_status.he_data2 |= 1199 QDF_MON_STATUS_TXBF_KNOWN; 1200 1201 /* HE-data3 */ 1202 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1203 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1204 ppdu_info->rx_status.mcs = value; 1205 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1206 ppdu_info->rx_status.he_data3 |= value; 1207 1208 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1209 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1210 he_dcm = value; 1211 value = value << QDF_MON_STATUS_DCM_SHIFT; 1212 ppdu_info->rx_status.he_data3 |= value; 1213 1214 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1215 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1216 value = value << QDF_MON_STATUS_CODING_SHIFT; 1217 ppdu_info->rx_status.he_data3 |= value; 1218 1219 /* HE-data4 */ 1220 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1221 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1222 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1223 ppdu_info->rx_status.he_data4 |= value; 1224 1225 /* HE-data5 */ 1226 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1227 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1228 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1229 ppdu_info->rx_status.he_data5 |= value; 1230 1231 /* HE-data6 */ 1232 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1233 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1234 /* value n indicates n+1 spatial streams */ 1235 value++; 1236 ppdu_info->rx_status.nss = value; 1237 ppdu_info->rx_status.he_data6 |= value; 1238 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1239 break; 1240 } 1241 case WIFIPHYRX_RSSI_LEGACY_E: 1242 { 1243 uint8_t reception_type; 1244 int8_t rssi_value; 1245 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1246 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1247 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1248 1249 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1250 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1251 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1252 ppdu_info->rx_status.he_re = 0; 1253 1254 reception_type = HAL_RX_GET(rx_tlv, 1255 PHYRX_RSSI_LEGACY_0, 1256 RECEPTION_TYPE); 1257 switch (reception_type) { 1258 case QDF_RECEPTION_TYPE_ULOFMDA: 1259 ppdu_info->rx_status.reception_type = 1260 HAL_RX_TYPE_MU_OFDMA; 1261 ppdu_info->rx_status.ulofdma_flag = 1; 1262 ppdu_info->rx_status.he_data1 = 1263 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1264 break; 1265 case QDF_RECEPTION_TYPE_ULMIMO: 1266 ppdu_info->rx_status.reception_type = 1267 HAL_RX_TYPE_MU_MIMO; 1268 ppdu_info->rx_status.he_data1 = 1269 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1270 break; 1271 default: 1272 ppdu_info->rx_status.reception_type = 1273 HAL_RX_TYPE_SU; 1274 break; 1275 } 1276 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1277 rssi_value = HAL_RX_GET(rssi_info_tlv, 1278 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1279 ppdu_info->rx_status.rssi[0] = rssi_value; 1280 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1281 "RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1282 1283 rssi_value = HAL_RX_GET(rssi_info_tlv, 1284 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1285 ppdu_info->rx_status.rssi[1] = rssi_value; 1286 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1287 "RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1288 1289 rssi_value = HAL_RX_GET(rssi_info_tlv, 1290 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1291 ppdu_info->rx_status.rssi[2] = rssi_value; 1292 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1293 "RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1294 1295 rssi_value = HAL_RX_GET(rssi_info_tlv, 1296 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1297 ppdu_info->rx_status.rssi[3] = rssi_value; 1298 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1299 "RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1300 1301 rssi_value = HAL_RX_GET(rssi_info_tlv, 1302 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1303 ppdu_info->rx_status.rssi[4] = rssi_value; 1304 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1305 "RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1306 1307 rssi_value = HAL_RX_GET(rssi_info_tlv, 1308 RECEIVE_RSSI_INFO_10, 1309 RSSI_PRI20_CHAIN5); 1310 ppdu_info->rx_status.rssi[5] = rssi_value; 1311 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1312 "RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1313 1314 rssi_value = HAL_RX_GET(rssi_info_tlv, 1315 RECEIVE_RSSI_INFO_12, 1316 RSSI_PRI20_CHAIN6); 1317 ppdu_info->rx_status.rssi[6] = rssi_value; 1318 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1319 "RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1320 1321 rssi_value = HAL_RX_GET(rssi_info_tlv, 1322 RECEIVE_RSSI_INFO_14, 1323 RSSI_PRI20_CHAIN7); 1324 ppdu_info->rx_status.rssi[7] = rssi_value; 1325 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1326 "RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1327 break; 1328 } 1329 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1330 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1331 ppdu_info); 1332 break; 1333 case WIFIRX_HEADER_E: 1334 { 1335 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1336 uint16_t mpdu_cnt = com_info->mpdu_cnt; 1337 1338 if (mpdu_cnt >= HAL_RX_MAX_MPDU) { 1339 hal_alert("Number of MPDUs per PPDU exceeded"); 1340 break; 1341 } 1342 /* Update first_msdu_payload for every mpdu and increment 1343 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1344 */ 1345 ppdu_info->ppdu_msdu_info[mpdu_cnt].first_msdu_payload = 1346 rx_tlv; 1347 ppdu_info->ppdu_msdu_info[mpdu_cnt].payload_len = tlv_len; 1348 ppdu_info->ppdu_msdu_info[mpdu_cnt].nbuf = nbuf; 1349 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1350 ppdu_info->msdu_info.payload_len = tlv_len; 1351 ppdu_info->user_id = user_id; 1352 ppdu_info->hdr_len = tlv_len; 1353 ppdu_info->data = rx_tlv; 1354 ppdu_info->data += 4; 1355 1356 /* for every RX_HEADER TLV increment mpdu_cnt */ 1357 com_info->mpdu_cnt++; 1358 return HAL_TLV_STATUS_HEADER; 1359 } 1360 case WIFIRX_MPDU_START_E: 1361 { 1362 uint8_t *rx_mpdu_start = 1363 (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, 1364 RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); 1365 uint32_t ppdu_id = 1366 HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1367 uint8_t filter_category = 0; 1368 1369 ppdu_info->nac_info.fc_valid = 1370 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1371 1372 ppdu_info->nac_info.to_ds_flag = 1373 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1374 1375 ppdu_info->nac_info.frame_control = 1376 HAL_RX_GET(rx_mpdu_start, 1377 RX_MPDU_INFO_14, 1378 MPDU_FRAME_CONTROL_FIELD); 1379 1380 ppdu_info->sw_frame_group_id = 1381 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1382 1383 if (ppdu_info->sw_frame_group_id == 1384 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1385 ppdu_info->rx_status.frame_control_info_valid = 1386 ppdu_info->nac_info.fc_valid; 1387 ppdu_info->rx_status.frame_control = 1388 ppdu_info->nac_info.frame_control; 1389 } 1390 1391 ppdu_info->nac_info.mac_addr2_valid = 1392 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1393 1394 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1395 HAL_RX_GET(rx_mpdu_start, 1396 RX_MPDU_INFO_16, 1397 MAC_ADDR_AD2_15_0); 1398 1399 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1400 HAL_RX_GET(rx_mpdu_start, 1401 RX_MPDU_INFO_17, 1402 MAC_ADDR_AD2_47_16); 1403 1404 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1405 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1406 ppdu_info->rx_status.ppdu_len = 1407 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1408 MPDU_LENGTH); 1409 } else { 1410 ppdu_info->rx_status.ppdu_len += 1411 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1412 MPDU_LENGTH); 1413 } 1414 1415 filter_category = 1416 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1417 1418 if (filter_category == 0) 1419 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1420 else if (filter_category == 1) 1421 ppdu_info->rx_status.monitor_direct_used = 1; 1422 1423 ppdu_info->nac_info.mcast_bcast = 1424 HAL_RX_GET(rx_mpdu_start, 1425 RX_MPDU_INFO_13, 1426 MCAST_BCAST); 1427 break; 1428 } 1429 case WIFIRX_MPDU_END_E: 1430 ppdu_info->user_id = user_id; 1431 ppdu_info->fcs_err = 1432 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1433 FCS_ERR); 1434 return HAL_TLV_STATUS_MPDU_END; 1435 case WIFIRX_MSDU_END_E: 1436 if (user_id < HAL_MAX_UL_MU_USERS) { 1437 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1438 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1439 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1440 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1441 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1442 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1443 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1444 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1445 ppdu_info->rx_msdu_info[user_id].flow_idx = 1446 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1447 } 1448 return HAL_TLV_STATUS_MSDU_END; 1449 case 0: 1450 return HAL_TLV_STATUS_PPDU_DONE; 1451 1452 default: 1453 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1454 unhandled = false; 1455 else 1456 unhandled = true; 1457 break; 1458 } 1459 1460 if (!unhandled) 1461 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1462 "%s TLV type: %d, TLV len:%d %s", 1463 __func__, tlv_tag, tlv_len, 1464 unhandled == true ? "unhandled" : ""); 1465 1466 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1467 rx_tlv, tlv_len); 1468 1469 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1470 } 1471 1472 /** 1473 * hal_reo_setup - Initialize HW REO block 1474 * 1475 * @hal_soc: Opaque HAL SOC handle 1476 * @reo_params: parameters needed by HAL for REO config 1477 */ 1478 static void hal_reo_setup_generic(struct hal_soc *soc, 1479 void *reoparams) 1480 { 1481 uint32_t reg_val; 1482 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1483 1484 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1485 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 1486 1487 hal_reo_config(soc, reg_val, reo_params); 1488 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1489 1490 /* TODO: Setup destination ring mapping if enabled */ 1491 1492 /* TODO: Error destination ring setting is left to default. 1493 * Default setting is to send all errors to release ring. 1494 */ 1495 1496 HAL_REG_WRITE(soc, 1497 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 1498 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1499 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1500 1501 HAL_REG_WRITE(soc, 1502 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 1503 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1504 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1505 1506 HAL_REG_WRITE(soc, 1507 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 1508 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1509 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1510 1511 HAL_REG_WRITE(soc, 1512 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 1513 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1514 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1515 1516 /* 1517 * When hash based routing is enabled, routing of the rx packet 1518 * is done based on the following value: 1 _ _ _ _ The last 4 1519 * bits are based on hash[3:0]. This means the possible values 1520 * are 0x10 to 0x1f. This value is used to look-up the 1521 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1522 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1523 * registers need to be configured to set-up the 16 entries to 1524 * map the hash values to a ring number. There are 3 bits per 1525 * hash entry – which are mapped as follows: 1526 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1527 * 7: NOT_USED. 1528 */ 1529 if (reo_params->rx_hash_enabled) { 1530 HAL_REG_WRITE(soc, 1531 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1532 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1533 reo_params->remap1); 1534 1535 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1536 HAL_REG_READ(soc, 1537 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1538 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1539 1540 HAL_REG_WRITE(soc, 1541 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1542 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1543 reo_params->remap2); 1544 1545 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1546 HAL_REG_READ(soc, 1547 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1548 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 1549 } 1550 1551 1552 /* TODO: Check if the following registers shoould be setup by host: 1553 * AGING_CONTROL 1554 * HIGH_MEMORY_THRESHOLD 1555 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1556 * GLOBAL_LINK_DESC_COUNT_CTRL 1557 */ 1558 } 1559 1560 /** 1561 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 1562 * @hal_soc: Opaque HAL SOC handle 1563 * @hal_ring: Source ring pointer 1564 * @headp: Head Pointer 1565 * @tailp: Tail Pointer 1566 * @ring: Ring type 1567 * 1568 * Return: Update tail pointer and head pointer in arguments. 1569 */ 1570 static inline 1571 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 1572 hal_ring_handle_t hal_ring_hdl, 1573 uint32_t *headp, uint32_t *tailp, 1574 uint8_t ring) 1575 { 1576 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1577 struct hal_hw_srng_config *ring_config; 1578 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 1579 1580 if (!hal_soc || !srng) { 1581 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 1582 "%s: Context is Null", __func__); 1583 return; 1584 } 1585 1586 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 1587 if (!ring_config->lmac_ring) { 1588 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1589 *headp = SRNG_SRC_REG_READ(srng, HP); 1590 *tailp = SRNG_SRC_REG_READ(srng, TP); 1591 } else { 1592 *headp = SRNG_DST_REG_READ(srng, HP); 1593 *tailp = SRNG_DST_REG_READ(srng, TP); 1594 } 1595 } 1596 } 1597 1598 /** 1599 * hal_srng_src_hw_init - Private function to initialize SRNG 1600 * source ring HW 1601 * @hal_soc: HAL SOC handle 1602 * @srng: SRNG ring pointer 1603 */ 1604 static inline 1605 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 1606 struct hal_srng *srng) 1607 { 1608 uint32_t reg_val = 0; 1609 uint64_t tp_addr = 0; 1610 1611 hal_debug("hw_init srng %d", srng->ring_id); 1612 1613 if (srng->flags & HAL_SRNG_MSI_INTR) { 1614 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 1615 srng->msi_addr & 0xffffffff); 1616 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 1617 (uint64_t)(srng->msi_addr) >> 32) | 1618 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 1619 MSI1_ENABLE), 1); 1620 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1621 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1622 } 1623 1624 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1625 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1626 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1627 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 1628 srng->entry_size * srng->num_entries); 1629 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 1630 1631 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 1632 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 1633 1634 /** 1635 * Interrupt setup: 1636 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1637 * if level mode is required 1638 */ 1639 reg_val = 0; 1640 1641 /* 1642 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 1643 * programmed in terms of 1us resolution instead of 8us resolution as 1644 * given in MLD. 1645 */ 1646 if (srng->intr_timer_thres_us) { 1647 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1648 INTERRUPT_TIMER_THRESHOLD), 1649 srng->intr_timer_thres_us); 1650 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 1651 } 1652 1653 if (srng->intr_batch_cntr_thres_entries) { 1654 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 1655 BATCH_COUNTER_THRESHOLD), 1656 srng->intr_batch_cntr_thres_entries * 1657 srng->entry_size); 1658 } 1659 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 1660 1661 reg_val = 0; 1662 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 1663 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 1664 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 1665 } 1666 1667 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 1668 1669 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 1670 * remain 0 to avoid some WBM stability issues. Remote head/tail 1671 * pointers are not required since this ring is completely managed 1672 * by WBM HW 1673 */ 1674 reg_val = 0; 1675 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 1676 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1677 ((unsigned long)(srng->u.src_ring.tp_addr) - 1678 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1679 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 1680 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 1681 } else { 1682 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 1683 } 1684 1685 /* Initilaize head and tail pointers to indicate ring is empty */ 1686 SRNG_SRC_REG_WRITE(srng, HP, 0); 1687 SRNG_SRC_REG_WRITE(srng, TP, 0); 1688 *(srng->u.src_ring.tp_addr) = 0; 1689 1690 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1691 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1692 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1693 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1694 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1695 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1696 1697 /* Loop count is not used for SRC rings */ 1698 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 1699 1700 /* 1701 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1702 * todo: update fw_api and replace with above line 1703 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1704 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1705 */ 1706 reg_val |= 0x40; 1707 1708 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 1709 } 1710 1711 /** 1712 * hal_srng_dst_hw_init - Private function to initialize SRNG 1713 * destination ring HW 1714 * @hal_soc: HAL SOC handle 1715 * @srng: SRNG ring pointer 1716 */ 1717 static inline 1718 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 1719 struct hal_srng *srng) 1720 { 1721 uint32_t reg_val = 0; 1722 uint64_t hp_addr = 0; 1723 1724 hal_debug("hw_init srng %d", srng->ring_id); 1725 1726 if (srng->flags & HAL_SRNG_MSI_INTR) { 1727 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 1728 srng->msi_addr & 0xffffffff); 1729 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 1730 (uint64_t)(srng->msi_addr) >> 32) | 1731 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 1732 MSI1_ENABLE), 1); 1733 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 1734 SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); 1735 } 1736 1737 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 1738 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 1739 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 1740 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 1741 srng->entry_size * srng->num_entries); 1742 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 1743 1744 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 1745 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 1746 SRNG_DST_REG_WRITE(srng, ID, reg_val); 1747 1748 1749 /** 1750 * Interrupt setup: 1751 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 1752 * if level mode is required 1753 */ 1754 reg_val = 0; 1755 if (srng->intr_timer_thres_us) { 1756 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1757 INTERRUPT_TIMER_THRESHOLD), 1758 srng->intr_timer_thres_us >> 3); 1759 } 1760 1761 if (srng->intr_batch_cntr_thres_entries) { 1762 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 1763 BATCH_COUNTER_THRESHOLD), 1764 srng->intr_batch_cntr_thres_entries * 1765 srng->entry_size); 1766 } 1767 1768 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 1769 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 1770 ((unsigned long)(srng->u.dst_ring.hp_addr) - 1771 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 1772 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 1773 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 1774 1775 /* Initilaize head and tail pointers to indicate ring is empty */ 1776 SRNG_DST_REG_WRITE(srng, HP, 0); 1777 SRNG_DST_REG_WRITE(srng, TP, 0); 1778 *(srng->u.dst_ring.hp_addr) = 0; 1779 1780 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 1781 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 1782 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 1783 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 1784 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 1785 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 1786 1787 /* 1788 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 1789 * todo: update fw_api and replace with above line 1790 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 1791 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 1792 */ 1793 reg_val |= 0x40; 1794 1795 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 1796 1797 } 1798 1799 #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1800 (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 1801 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ 1802 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) 1803 1804 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1805 (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ 1806 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ 1807 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) 1808 1809 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ 1810 (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ 1811 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ 1812 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) 1813 1814 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 1815 (((*(((uint32_t *) wbm_desc) + \ 1816 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 1817 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 1818 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 1819 1820 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 1821 (((*(((uint32_t *) wbm_desc) + \ 1822 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 1823 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 1824 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 1825 1826 /** 1827 * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and 1828 * save it to hal_wbm_err_desc_info structure passed by caller 1829 * @wbm_desc: wbm ring descriptor 1830 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 1831 * Return: void 1832 */ 1833 static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, 1834 void *wbm_er_info1) 1835 { 1836 struct hal_wbm_err_desc_info *wbm_er_info = 1837 (struct hal_wbm_err_desc_info *)wbm_er_info1; 1838 1839 wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); 1840 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 1841 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 1842 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 1843 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 1844 } 1845 1846 /** 1847 * hal_tx_comp_get_release_reason_generic() - TQM Release reason 1848 * @hal_desc: completion ring descriptor pointer 1849 * 1850 * This function will return the type of pointer - buffer or descriptor 1851 * 1852 * Return: buffer type 1853 */ 1854 static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) 1855 { 1856 uint32_t comp_desc = 1857 *(uint32_t *) (((uint8_t *) hal_desc) + 1858 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1859 1860 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1861 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1862 } 1863 1864 /** 1865 * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured 1866 * human readable format. 1867 * @mpdu_start: pointer the rx_attention TLV in pkt. 1868 * @dbg_level: log level. 1869 * 1870 * Return: void 1871 */ 1872 static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, 1873 uint8_t dbg_level) 1874 { 1875 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1876 struct rx_mpdu_info *mpdu_info = 1877 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1878 1879 hal_verbose_debug( 1880 "rx_mpdu_start tlv (1/5) - " 1881 "rxpcu_mpdu_filter_in_category: %x " 1882 "sw_frame_group_id: %x " 1883 "ndp_frame: %x " 1884 "phy_err: %x " 1885 "phy_err_during_mpdu_header: %x " 1886 "protocol_version_err: %x " 1887 "ast_based_lookup_valid: %x " 1888 "phy_ppdu_id: %x " 1889 "ast_index: %x " 1890 "sw_peer_id: %x " 1891 "mpdu_frame_control_valid: %x " 1892 "mpdu_duration_valid: %x " 1893 "mac_addr_ad1_valid: %x " 1894 "mac_addr_ad2_valid: %x " 1895 "mac_addr_ad3_valid: %x " 1896 "mac_addr_ad4_valid: %x " 1897 "mpdu_sequence_control_valid: %x " 1898 "mpdu_qos_control_valid: %x " 1899 "mpdu_ht_control_valid: %x " 1900 "frame_encryption_info_valid: %x ", 1901 mpdu_info->rxpcu_mpdu_filter_in_category, 1902 mpdu_info->sw_frame_group_id, 1903 mpdu_info->ndp_frame, 1904 mpdu_info->phy_err, 1905 mpdu_info->phy_err_during_mpdu_header, 1906 mpdu_info->protocol_version_err, 1907 mpdu_info->ast_based_lookup_valid, 1908 mpdu_info->phy_ppdu_id, 1909 mpdu_info->ast_index, 1910 mpdu_info->sw_peer_id, 1911 mpdu_info->mpdu_frame_control_valid, 1912 mpdu_info->mpdu_duration_valid, 1913 mpdu_info->mac_addr_ad1_valid, 1914 mpdu_info->mac_addr_ad2_valid, 1915 mpdu_info->mac_addr_ad3_valid, 1916 mpdu_info->mac_addr_ad4_valid, 1917 mpdu_info->mpdu_sequence_control_valid, 1918 mpdu_info->mpdu_qos_control_valid, 1919 mpdu_info->mpdu_ht_control_valid, 1920 mpdu_info->frame_encryption_info_valid); 1921 1922 hal_verbose_debug( 1923 "rx_mpdu_start tlv (2/5) - " 1924 "fr_ds: %x " 1925 "to_ds: %x " 1926 "encrypted: %x " 1927 "mpdu_retry: %x " 1928 "mpdu_sequence_number: %x " 1929 "epd_en: %x " 1930 "all_frames_shall_be_encrypted: %x " 1931 "encrypt_type: %x " 1932 "mesh_sta: %x " 1933 "bssid_hit: %x " 1934 "bssid_number: %x " 1935 "tid: %x " 1936 "pn_31_0: %x " 1937 "pn_63_32: %x " 1938 "pn_95_64: %x " 1939 "pn_127_96: %x " 1940 "peer_meta_data: %x " 1941 "rxpt_classify_info.reo_destination_indication: %x " 1942 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1943 "rx_reo_queue_desc_addr_31_0: %x ", 1944 mpdu_info->fr_ds, 1945 mpdu_info->to_ds, 1946 mpdu_info->encrypted, 1947 mpdu_info->mpdu_retry, 1948 mpdu_info->mpdu_sequence_number, 1949 mpdu_info->epd_en, 1950 mpdu_info->all_frames_shall_be_encrypted, 1951 mpdu_info->encrypt_type, 1952 mpdu_info->mesh_sta, 1953 mpdu_info->bssid_hit, 1954 mpdu_info->bssid_number, 1955 mpdu_info->tid, 1956 mpdu_info->pn_31_0, 1957 mpdu_info->pn_63_32, 1958 mpdu_info->pn_95_64, 1959 mpdu_info->pn_127_96, 1960 mpdu_info->peer_meta_data, 1961 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1962 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1963 mpdu_info->rx_reo_queue_desc_addr_31_0); 1964 1965 hal_verbose_debug( 1966 "rx_mpdu_start tlv (3/5) - " 1967 "rx_reo_queue_desc_addr_39_32: %x " 1968 "receive_queue_number: %x " 1969 "pre_delim_err_warning: %x " 1970 "first_delim_err: %x " 1971 "key_id_octet: %x " 1972 "new_peer_entry: %x " 1973 "decrypt_needed: %x " 1974 "decap_type: %x " 1975 "rx_insert_vlan_c_tag_padding: %x " 1976 "rx_insert_vlan_s_tag_padding: %x " 1977 "strip_vlan_c_tag_decap: %x " 1978 "strip_vlan_s_tag_decap: %x " 1979 "pre_delim_count: %x " 1980 "ampdu_flag: %x " 1981 "bar_frame: %x " 1982 "mpdu_length: %x " 1983 "first_mpdu: %x " 1984 "mcast_bcast: %x " 1985 "ast_index_not_found: %x " 1986 "ast_index_timeout: %x ", 1987 mpdu_info->rx_reo_queue_desc_addr_39_32, 1988 mpdu_info->receive_queue_number, 1989 mpdu_info->pre_delim_err_warning, 1990 mpdu_info->first_delim_err, 1991 mpdu_info->key_id_octet, 1992 mpdu_info->new_peer_entry, 1993 mpdu_info->decrypt_needed, 1994 mpdu_info->decap_type, 1995 mpdu_info->rx_insert_vlan_c_tag_padding, 1996 mpdu_info->rx_insert_vlan_s_tag_padding, 1997 mpdu_info->strip_vlan_c_tag_decap, 1998 mpdu_info->strip_vlan_s_tag_decap, 1999 mpdu_info->pre_delim_count, 2000 mpdu_info->ampdu_flag, 2001 mpdu_info->bar_frame, 2002 mpdu_info->mpdu_length, 2003 mpdu_info->first_mpdu, 2004 mpdu_info->mcast_bcast, 2005 mpdu_info->ast_index_not_found, 2006 mpdu_info->ast_index_timeout); 2007 2008 hal_verbose_debug( 2009 "rx_mpdu_start tlv (4/5) - " 2010 "power_mgmt: %x " 2011 "non_qos: %x " 2012 "null_data: %x " 2013 "mgmt_type: %x " 2014 "ctrl_type: %x " 2015 "more_data: %x " 2016 "eosp: %x " 2017 "fragment_flag: %x " 2018 "order: %x " 2019 "u_apsd_trigger: %x " 2020 "encrypt_required: %x " 2021 "directed: %x " 2022 "mpdu_frame_control_field: %x " 2023 "mpdu_duration_field: %x " 2024 "mac_addr_ad1_31_0: %x " 2025 "mac_addr_ad1_47_32: %x " 2026 "mac_addr_ad2_15_0: %x " 2027 "mac_addr_ad2_47_16: %x " 2028 "mac_addr_ad3_31_0: %x " 2029 "mac_addr_ad3_47_32: %x ", 2030 mpdu_info->power_mgmt, 2031 mpdu_info->non_qos, 2032 mpdu_info->null_data, 2033 mpdu_info->mgmt_type, 2034 mpdu_info->ctrl_type, 2035 mpdu_info->more_data, 2036 mpdu_info->eosp, 2037 mpdu_info->fragment_flag, 2038 mpdu_info->order, 2039 mpdu_info->u_apsd_trigger, 2040 mpdu_info->encrypt_required, 2041 mpdu_info->directed, 2042 mpdu_info->mpdu_frame_control_field, 2043 mpdu_info->mpdu_duration_field, 2044 mpdu_info->mac_addr_ad1_31_0, 2045 mpdu_info->mac_addr_ad1_47_32, 2046 mpdu_info->mac_addr_ad2_15_0, 2047 mpdu_info->mac_addr_ad2_47_16, 2048 mpdu_info->mac_addr_ad3_31_0, 2049 mpdu_info->mac_addr_ad3_47_32); 2050 2051 hal_verbose_debug( 2052 "rx_mpdu_start tlv (5/5) - " 2053 "mpdu_sequence_control_field: %x " 2054 "mac_addr_ad4_31_0: %x " 2055 "mac_addr_ad4_47_32: %x " 2056 "mpdu_qos_control_field: %x " 2057 "mpdu_ht_control_field: %x ", 2058 mpdu_info->mpdu_sequence_control_field, 2059 mpdu_info->mac_addr_ad4_31_0, 2060 mpdu_info->mac_addr_ad4_47_32, 2061 mpdu_info->mpdu_qos_control_field, 2062 mpdu_info->mpdu_ht_control_field); 2063 } 2064 2065 /** 2066 * hal_tx_desc_set_search_type - Set the search type value 2067 * @desc: Handle to Tx Descriptor 2068 * @search_type: search type 2069 * 0 – Normal search 2070 * 1 – Index based address search 2071 * 2 – Index based flow search 2072 * 2073 * Return: void 2074 */ 2075 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2076 static void hal_tx_desc_set_search_type_generic(void *desc, 2077 uint8_t search_type) 2078 { 2079 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2080 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2081 } 2082 #else 2083 static void hal_tx_desc_set_search_type_generic(void *desc, 2084 uint8_t search_type) 2085 { 2086 } 2087 2088 #endif 2089 2090 /** 2091 * hal_tx_desc_set_search_index - Set the search index value 2092 * @desc: Handle to Tx Descriptor 2093 * @search_index: The index that will be used for index based address or 2094 * flow search. The field is valid when 'search_type' is 2095 * 1 0r 2 2096 * 2097 * Return: void 2098 */ 2099 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2100 static void hal_tx_desc_set_search_index_generic(void *desc, 2101 uint32_t search_index) 2102 { 2103 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2104 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2105 } 2106 #else 2107 static void hal_tx_desc_set_search_index_generic(void *desc, 2108 uint32_t search_index) 2109 { 2110 } 2111 #endif 2112 2113 /** 2114 * hal_tx_desc_set_cache_set_num_generic - Set the cache-set-num value 2115 * @desc: Handle to Tx Descriptor 2116 * @cache_num: Cache set number that should be used to cache the index 2117 * based search results, for address and flow search. 2118 * This value should be equal to LSB four bits of the hash value 2119 * of match data, in case of search index points to an entry 2120 * which may be used in content based search also. The value can 2121 * be anything when the entry pointed by search index will not be 2122 * used for content based search. 2123 * 2124 * Return: void 2125 */ 2126 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2127 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2128 uint8_t cache_num) 2129 { 2130 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2131 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2132 } 2133 #else 2134 static void hal_tx_desc_set_cache_set_num_generic(void *desc, 2135 uint8_t cache_num) 2136 { 2137 } 2138 #endif 2139 2140 /** 2141 * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table 2142 * @soc: HAL SoC context 2143 * @map: PCP-TID mapping table 2144 * 2145 * PCP are mapped to 8 TID values using TID values programmed 2146 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2147 * The mapping register has TID mapping for 8 PCP values 2148 * 2149 * Return: none 2150 */ 2151 static void hal_tx_set_pcp_tid_map_generic(struct hal_soc *soc, uint8_t *map) 2152 { 2153 uint32_t addr, value; 2154 2155 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2156 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2157 2158 value = (map[0] | 2159 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2160 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2161 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2162 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2163 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2164 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2165 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2166 2167 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2168 } 2169 2170 /** 2171 * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with 2172 * value received from user-space 2173 * @soc: HAL SoC context 2174 * @pcp: pcp value 2175 * @tid : tid value 2176 * 2177 * Return: void 2178 */ 2179 static 2180 void hal_tx_update_pcp_tid_generic(struct hal_soc *soc, 2181 uint8_t pcp, uint8_t tid) 2182 { 2183 uint32_t addr, value, regval; 2184 2185 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2186 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2187 2188 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2189 2190 /* Read back previous PCP TID config and update 2191 * with new config. 2192 */ 2193 regval = HAL_REG_READ(soc, addr); 2194 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2195 regval |= value; 2196 2197 HAL_REG_WRITE(soc, addr, 2198 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2199 } 2200 2201 /** 2202 * hal_tx_update_tidmap_prty_generic() - Update the tid map priority 2203 * @soc: HAL SoC context 2204 * @val: priority value 2205 * 2206 * Return: void 2207 */ 2208 static 2209 void hal_tx_update_tidmap_prty_generic(struct hal_soc *soc, uint8_t value) 2210 { 2211 uint32_t addr; 2212 2213 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2214 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2215 2216 HAL_REG_WRITE(soc, addr, 2217 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2218 } 2219 2220 #endif /* _HAL_GENERIC_API_H_ */ 2221