1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #ifndef _HAL_GENERIC_API_H_ 19 #define _HAL_GENERIC_API_H_ 20 21 #include <hal_rx.h> 22 #include "hal_api_mon.h" 23 24 /** 25 * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value 26 * from stats enum to radiotap enum 27 * @he_gi: HE GI value used in stats 28 * @he_ltf: HE LTF value used in stats 29 * 30 * Return: void 31 */ 32 static inline void hal_get_radiotap_he_gi_ltf(uint16_t *he_gi, uint16_t *he_ltf) 33 { 34 switch (*he_gi) { 35 case HE_GI_0_8: 36 *he_gi = HE_GI_RADIOTAP_0_8; 37 break; 38 case HE_GI_1_6: 39 *he_gi = HE_GI_RADIOTAP_1_6; 40 break; 41 case HE_GI_3_2: 42 *he_gi = HE_GI_RADIOTAP_3_2; 43 break; 44 default: 45 *he_gi = HE_GI_RADIOTAP_RESERVED; 46 } 47 48 switch (*he_ltf) { 49 case HE_LTF_1_X: 50 *he_ltf = HE_LTF_RADIOTAP_1_X; 51 break; 52 case HE_LTF_2_X: 53 *he_ltf = HE_LTF_RADIOTAP_2_X; 54 break; 55 case HE_LTF_4_X: 56 *he_ltf = HE_LTF_RADIOTAP_4_X; 57 break; 58 default: 59 *he_ltf = HE_LTF_RADIOTAP_UNKNOWN; 60 } 61 } 62 63 /* channel number to freq conversion */ 64 #define CHANNEL_NUM_14 14 65 #define CHANNEL_NUM_15 15 66 #define CHANNEL_NUM_27 27 67 #define CHANNEL_NUM_35 35 68 #define CHANNEL_NUM_182 182 69 #define CHANNEL_NUM_197 197 70 #define CHANNEL_FREQ_2484 2484 71 #define CHANNEL_FREQ_2407 2407 72 #define CHANNEL_FREQ_2512 2512 73 #define CHANNEL_FREQ_5000 5000 74 #define CHANNEL_FREQ_5950 5950 75 #define CHANNEL_FREQ_4000 4000 76 #define CHANNEL_FREQ_5150 5150 77 #define CHANNEL_FREQ_5920 5920 78 #define CHANNEL_FREQ_5935 5935 79 #define FREQ_MULTIPLIER_CONST_5MHZ 5 80 #define FREQ_MULTIPLIER_CONST_20MHZ 20 81 /** 82 * hal_rx_radiotap_num_to_freq() - Get frequency from chan number 83 * @chan_num - Input channel number 84 * @center_freq - Input Channel Center frequency 85 * 86 * Return - Channel frequency in Mhz 87 */ 88 static uint16_t 89 hal_rx_radiotap_num_to_freq(uint16_t chan_num, qdf_freq_t center_freq) 90 { 91 if (center_freq > CHANNEL_FREQ_5920 && center_freq < CHANNEL_FREQ_5950) 92 return CHANNEL_FREQ_5935; 93 94 if (center_freq < CHANNEL_FREQ_5950) { 95 if (chan_num == CHANNEL_NUM_14) 96 return CHANNEL_FREQ_2484; 97 if (chan_num < CHANNEL_NUM_14) 98 return CHANNEL_FREQ_2407 + 99 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 100 101 if (chan_num < CHANNEL_NUM_27) 102 return CHANNEL_FREQ_2512 + 103 ((chan_num - CHANNEL_NUM_15) * 104 FREQ_MULTIPLIER_CONST_20MHZ); 105 106 if (chan_num > CHANNEL_NUM_182 && 107 chan_num < CHANNEL_NUM_197) 108 return ((chan_num * FREQ_MULTIPLIER_CONST_5MHZ) + 109 CHANNEL_FREQ_4000); 110 111 return CHANNEL_FREQ_5000 + 112 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 113 } else { 114 return CHANNEL_FREQ_5950 + 115 (chan_num * FREQ_MULTIPLIER_CONST_5MHZ); 116 } 117 } 118 119 /** 120 * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring 121 * @hal_soc: Opaque HAL SOC handle 122 * @hal_ring: Source ring pointer 123 * @headp: Head Pointer 124 * @tailp: Tail Pointer 125 * @ring: Ring type 126 * 127 * Return: Update tail pointer and head pointer in arguments. 128 */ 129 static inline 130 void hal_get_hw_hptp_generic(struct hal_soc *hal_soc, 131 hal_ring_handle_t hal_ring_hdl, 132 uint32_t *headp, uint32_t *tailp, 133 uint8_t ring) 134 { 135 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 136 struct hal_hw_srng_config *ring_config; 137 enum hal_ring_type ring_type = (enum hal_ring_type)ring; 138 139 if (!hal_soc || !srng) { 140 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, 141 "%s: Context is Null", __func__); 142 return; 143 } 144 145 ring_config = HAL_SRNG_CONFIG(hal_soc, ring_type); 146 if (!ring_config->lmac_ring) { 147 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 148 *headp = SRNG_SRC_REG_READ(srng, HP); 149 *tailp = SRNG_SRC_REG_READ(srng, TP); 150 } else { 151 *headp = SRNG_DST_REG_READ(srng, HP); 152 *tailp = SRNG_DST_REG_READ(srng, TP); 153 } 154 } 155 } 156 157 #if defined(WBM_IDLE_LSB_WRITE_CONFIRM_WAR) 158 /** 159 * hal_wbm_idle_lsb_write_confirm() - Check and update WBM_IDLE_LINK ring LSB 160 * @srng: srng handle 161 * 162 * Return: None 163 */ 164 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 165 { 166 if (srng->ring_id == HAL_SRNG_WBM_IDLE_LINK) { 167 while (SRNG_SRC_REG_READ(srng, BASE_LSB) != 168 ((unsigned int)srng->ring_base_paddr & 0xffffffff)) 169 SRNG_SRC_REG_WRITE(srng, BASE_LSB, 170 srng->ring_base_paddr & 171 0xffffffff); 172 } 173 } 174 #else 175 static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng) 176 { 177 } 178 #endif 179 180 /** 181 * hal_srng_src_hw_init - Private function to initialize SRNG 182 * source ring HW 183 * @hal_soc: HAL SOC handle 184 * @srng: SRNG ring pointer 185 */ 186 static inline 187 void hal_srng_src_hw_init_generic(struct hal_soc *hal, 188 struct hal_srng *srng) 189 { 190 uint32_t reg_val = 0; 191 uint64_t tp_addr = 0; 192 193 hal_debug("hw_init srng %d", srng->ring_id); 194 195 if (srng->flags & HAL_SRNG_MSI_INTR) { 196 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, 197 srng->msi_addr & 0xffffffff); 198 reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), 199 (uint64_t)(srng->msi_addr) >> 32) | 200 SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, 201 MSI1_ENABLE), 1); 202 SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 203 SRNG_SRC_REG_WRITE(srng, MSI1_DATA, 204 qdf_cpu_to_le32(srng->msi_data)); 205 } 206 207 SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 208 hal_wbm_idle_lsb_write_confirm(srng); 209 210 reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 211 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 212 SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 213 srng->entry_size * srng->num_entries); 214 SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); 215 216 reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); 217 SRNG_SRC_REG_WRITE(srng, ID, reg_val); 218 219 /** 220 * Interrupt setup: 221 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 222 * if level mode is required 223 */ 224 reg_val = 0; 225 226 /* 227 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be 228 * programmed in terms of 1us resolution instead of 8us resolution as 229 * given in MLD. 230 */ 231 if (srng->intr_timer_thres_us) { 232 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 233 INTERRUPT_TIMER_THRESHOLD), 234 srng->intr_timer_thres_us); 235 /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ 236 } 237 238 if (srng->intr_batch_cntr_thres_entries) { 239 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, 240 BATCH_COUNTER_THRESHOLD), 241 srng->intr_batch_cntr_thres_entries * 242 srng->entry_size); 243 } 244 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); 245 246 reg_val = 0; 247 if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { 248 reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, 249 LOW_THRESHOLD), srng->u.src_ring.low_threshold); 250 } 251 252 SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); 253 254 /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should 255 * remain 0 to avoid some WBM stability issues. Remote head/tail 256 * pointers are not required since this ring is completely managed 257 * by WBM HW 258 */ 259 reg_val = 0; 260 if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { 261 tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 262 ((unsigned long)(srng->u.src_ring.tp_addr) - 263 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 264 SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); 265 SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); 266 } else { 267 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); 268 } 269 270 /* Initilaize head and tail pointers to indicate ring is empty */ 271 SRNG_SRC_REG_WRITE(srng, HP, 0); 272 SRNG_SRC_REG_WRITE(srng, TP, 0); 273 *(srng->u.src_ring.tp_addr) = 0; 274 275 reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 276 SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 277 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 278 SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 279 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 280 SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 281 282 /* Loop count is not used for SRC rings */ 283 reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); 284 285 /* 286 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 287 * todo: update fw_api and replace with above line 288 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 289 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 290 */ 291 reg_val |= 0x40; 292 293 SRNG_SRC_REG_WRITE(srng, MISC, reg_val); 294 } 295 296 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 297 /** 298 * hal_srng_dst_msi2_setup() - Configure MSI2 register for a SRNG 299 * @srng: SRNG handle 300 * 301 * Return: None 302 */ 303 static inline void hal_srng_dst_msi2_setup(struct hal_srng *srng) 304 { 305 uint32_t reg_val = 0; 306 307 if (srng->u.dst_ring.nf_irq_support) { 308 SRNG_DST_REG_WRITE(srng, MSI2_BASE_LSB, 309 srng->msi2_addr & 0xffffffff); 310 reg_val = SRNG_SM(SRNG_DST_FLD(MSI2_BASE_MSB, ADDR), 311 (uint64_t)(srng->msi2_addr) >> 32) | 312 SRNG_SM(SRNG_DST_FLD(MSI2_BASE_MSB, 313 MSI2_ENABLE), 1); 314 SRNG_DST_REG_WRITE(srng, MSI2_BASE_MSB, reg_val); 315 SRNG_DST_REG_WRITE(srng, MSI2_DATA, 316 qdf_cpu_to_le32(srng->msi2_data)); 317 } 318 } 319 320 /** 321 * hal_srng_dst_near_full_int_setup() - Configure near-full params for SRNG 322 * @srng: SRNG handle 323 * 324 * Return: None 325 */ 326 static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng) 327 { 328 uint32_t reg_val = 0; 329 330 if (srng->u.dst_ring.nf_irq_support) { 331 if (srng->intr_timer_thres_us) { 332 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT2_SETUP, 333 INTERRUPT2_TIMER_THRESHOLD), 334 srng->intr_timer_thres_us >> 3); 335 } 336 337 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT2_SETUP, 338 HIGH_THRESHOLD), 339 srng->u.dst_ring.high_thresh * 340 srng->entry_size); 341 } 342 343 SRNG_DST_REG_WRITE(srng, PRODUCER_INT2_SETUP, reg_val); 344 } 345 #else 346 static inline void hal_srng_dst_msi2_setup(struct hal_srng *srng) 347 { 348 } 349 350 static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng) 351 { 352 } 353 #endif 354 355 /** 356 * hal_srng_dst_hw_init - Private function to initialize SRNG 357 * destination ring HW 358 * @hal_soc: HAL SOC handle 359 * @srng: SRNG ring pointer 360 */ 361 static inline 362 void hal_srng_dst_hw_init_generic(struct hal_soc *hal, 363 struct hal_srng *srng) 364 { 365 uint32_t reg_val = 0; 366 uint64_t hp_addr = 0; 367 368 hal_debug("hw_init srng %d", srng->ring_id); 369 370 if (srng->flags & HAL_SRNG_MSI_INTR) { 371 SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, 372 srng->msi_addr & 0xffffffff); 373 reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), 374 (uint64_t)(srng->msi_addr) >> 32) | 375 SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, 376 MSI1_ENABLE), 1); 377 SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); 378 SRNG_DST_REG_WRITE(srng, MSI1_DATA, 379 qdf_cpu_to_le32(srng->msi_data)); 380 381 hal_srng_dst_msi2_setup(srng); 382 } 383 384 SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); 385 reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), 386 ((uint64_t)(srng->ring_base_paddr) >> 32)) | 387 SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), 388 srng->entry_size * srng->num_entries); 389 SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); 390 391 reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | 392 SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); 393 SRNG_DST_REG_WRITE(srng, ID, reg_val); 394 395 396 /** 397 * Interrupt setup: 398 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 399 * if level mode is required 400 */ 401 reg_val = 0; 402 if (srng->intr_timer_thres_us) { 403 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 404 INTERRUPT_TIMER_THRESHOLD), 405 srng->intr_timer_thres_us >> 3); 406 } 407 408 if (srng->intr_batch_cntr_thres_entries) { 409 reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, 410 BATCH_COUNTER_THRESHOLD), 411 srng->intr_batch_cntr_thres_entries * 412 srng->entry_size); 413 } 414 415 SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); 416 417 /** 418 * Near-Full Interrupt setup: 419 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE 420 * if level mode is required 421 */ 422 hal_srng_dst_near_full_int_setup(srng); 423 424 hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + 425 ((unsigned long)(srng->u.dst_ring.hp_addr) - 426 (unsigned long)(hal->shadow_rdptr_mem_vaddr))); 427 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); 428 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); 429 430 /* Initilaize head and tail pointers to indicate ring is empty */ 431 SRNG_DST_REG_WRITE(srng, HP, 0); 432 SRNG_DST_REG_WRITE(srng, TP, 0); 433 *(srng->u.dst_ring.hp_addr) = 0; 434 435 reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? 436 SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | 437 ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? 438 SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | 439 ((srng->flags & HAL_SRNG_MSI_SWAP) ? 440 SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); 441 442 /* 443 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); 444 * todo: update fw_api and replace with above line 445 * (when SRNG_ENABLE field for the MISC register is available in fw_api) 446 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) 447 */ 448 reg_val |= 0x40; 449 450 SRNG_DST_REG_WRITE(srng, MISC, reg_val); 451 452 } 453 454 /** 455 * hal_srng_hw_reg_offset_init_generic() - Initialize the HW srng reg offset 456 * @hal_soc: HAL Soc handle 457 * 458 * Return: None 459 */ 460 static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc) 461 { 462 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 463 464 /* dst */ 465 hw_reg_offset[DST_HP] = REG_OFFSET(DST, HP); 466 hw_reg_offset[DST_TP] = REG_OFFSET(DST, TP); 467 hw_reg_offset[DST_ID] = REG_OFFSET(DST, ID); 468 hw_reg_offset[DST_MISC] = REG_OFFSET(DST, MISC); 469 hw_reg_offset[DST_HP_ADDR_LSB] = REG_OFFSET(DST, HP_ADDR_LSB); 470 hw_reg_offset[DST_HP_ADDR_MSB] = REG_OFFSET(DST, HP_ADDR_MSB); 471 hw_reg_offset[DST_MSI1_BASE_LSB] = REG_OFFSET(DST, MSI1_BASE_LSB); 472 hw_reg_offset[DST_MSI1_BASE_MSB] = REG_OFFSET(DST, MSI1_BASE_MSB); 473 hw_reg_offset[DST_MSI1_DATA] = REG_OFFSET(DST, MSI1_DATA); 474 hw_reg_offset[DST_BASE_LSB] = REG_OFFSET(DST, BASE_LSB); 475 hw_reg_offset[DST_BASE_MSB] = REG_OFFSET(DST, BASE_MSB); 476 hw_reg_offset[DST_PRODUCER_INT_SETUP] = 477 REG_OFFSET(DST, PRODUCER_INT_SETUP); 478 479 /* src */ 480 hw_reg_offset[SRC_HP] = REG_OFFSET(SRC, HP); 481 hw_reg_offset[SRC_TP] = REG_OFFSET(SRC, TP); 482 hw_reg_offset[SRC_ID] = REG_OFFSET(SRC, ID); 483 hw_reg_offset[SRC_MISC] = REG_OFFSET(SRC, MISC); 484 hw_reg_offset[SRC_TP_ADDR_LSB] = REG_OFFSET(SRC, TP_ADDR_LSB); 485 hw_reg_offset[SRC_TP_ADDR_MSB] = REG_OFFSET(SRC, TP_ADDR_MSB); 486 hw_reg_offset[SRC_MSI1_BASE_LSB] = REG_OFFSET(SRC, MSI1_BASE_LSB); 487 hw_reg_offset[SRC_MSI1_BASE_MSB] = REG_OFFSET(SRC, MSI1_BASE_MSB); 488 hw_reg_offset[SRC_MSI1_DATA] = REG_OFFSET(SRC, MSI1_DATA); 489 hw_reg_offset[SRC_BASE_LSB] = REG_OFFSET(SRC, BASE_LSB); 490 hw_reg_offset[SRC_BASE_MSB] = REG_OFFSET(SRC, BASE_MSB); 491 hw_reg_offset[SRC_CONSUMER_INT_SETUP_IX0] = 492 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0); 493 hw_reg_offset[SRC_CONSUMER_INT_SETUP_IX1] = 494 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1); 495 } 496 497 #endif /* HAL_GENERIC_API_H_ */ 498